tjh.dev / kernel
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Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

Pull powerpc fixes from Ben Herrenschmidt:
"Here is a series of powerpc fixes. It's a bit big, mostly because of
the series of 11 "EEH" patches from Gavin. The EEH (Our IBM specific
PCI/PCIe Enhanced Error Handling) code had been rotting for a while
and this merge window saw a significant rework & fixing of it by Gavin
Shan.

However, that wasn't complete and left some open issues. There were
still a few corner cases that didn't work properly, for example in
relation to hotplug and devices without explicit error handlers. We
had some patches but they weren't quite good enough yet so I left them
off the 3.11 merge window.

Gavin since then fixed it all up, we ran quite a few rounds of testing
and it seems fairly solid (at least probably more than it has ever
been). This should probably have made -rc1 but both Gavin and I took
some vacation so it had to wait for -rc2.

The rest is more bug fixes, mostly to new features recently added, for
example, we missed the cpu table entry for one of the two models of P8
(we didn't realize they had different PVR [Processor Version Register]
values), some module CRC issues, etc..."

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (23 commits)
powerpc/perf: BHRB filter configuration should follow the task
powerpc/perf: Ignore separate BHRB privilege state filter request
powerpc/powernv: Mark pnv_pci_init_ioda2_phb() as __init
powerpc/mm: Use the correct SLB(LLP) encoding in tlbie instruction
powerpc/mm: Fix fallthrough bug in hpte_decode
powerpc/pseries: Fix a typo in pSeries_lpar_hpte_insert()
powerpc/eeh: Introdce flag to protect sysfs
powerpc/eeh: Fix unbalanced enable for IRQ
powerpc/eeh: Don't use pci_dev during BAR restore
powerpc/eeh: Use partial hotplug for EEH unaware drivers
powerpc/pci: Partial tree hotplug support
powerpc/eeh: Use safe list traversal when walking EEH devices
powerpc/eeh: Keep PE during hotplug
powerpc/pci/hotplug: Don't need to remove from EEH cache twice
powerpc/pci: Override pcibios_release_device()
powerpc/eeh: Export functions for hotplug
powerpc/eeh: Remove reference to PCI device
powerpc: Fix the corrupt r3 error during MCE handling.
powerpc/perf: Set PPC_FEATURE2_EBB when we register the power8 PMU
powerpc/pseries: Drop "select HOTPLUG"
...

Linus Torvalds 07bc9dc1 b48a97be

+394 -173
+24 -6
arch/powerpc/include/asm/eeh.h
··· 55 55 #define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */ 56 56 #define EEH_PE_PHB_DEAD (1 << 2) /* Dead PHB */ 57 57 58 + #define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */ 59 + 58 60 struct eeh_pe { 59 61 int type; /* PE type: PHB/Bus/Device */ 60 62 int state; /* PE EEH dependent mode */ ··· 74 72 struct list_head child; /* Child PEs */ 75 73 }; 76 74 77 - #define eeh_pe_for_each_dev(pe, edev) \ 78 - list_for_each_entry(edev, &pe->edevs, list) 75 + #define eeh_pe_for_each_dev(pe, edev, tmp) \ 76 + list_for_each_entry_safe(edev, tmp, &pe->edevs, list) 79 77 80 78 /* 81 79 * The struct is used to trace EEH state for the associated ··· 84 82 * another tree except the currently existing tree of PCI 85 83 * buses and PCI devices 86 84 */ 87 - #define EEH_DEV_IRQ_DISABLED (1<<0) /* Interrupt disabled */ 85 + #define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */ 86 + #define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */ 87 + #define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */ 88 + #define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */ 89 + #define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */ 90 + 91 + #define EEH_DEV_SYSFS (1 << 8) /* Sysfs created */ 88 92 89 93 struct eeh_dev { 90 94 int mode; /* EEH mode */ ··· 98 90 int config_addr; /* Config address */ 99 91 int pe_config_addr; /* PE config address */ 100 92 u32 config_space[16]; /* Saved PCI config space */ 93 + u8 pcie_cap; /* Saved PCIe capability */ 101 94 struct eeh_pe *pe; /* Associated PE */ 102 95 struct list_head list; /* Form link list in the PE */ 103 96 struct pci_controller *phb; /* Associated PHB */ 104 97 struct device_node *dn; /* Associated device node */ 105 98 struct pci_dev *pdev; /* Associated PCI device */ 99 + struct pci_bus *bus; /* PCI bus for partial hotplug */ 106 100 }; 107 101 108 102 static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev) ··· 203 193 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb); 204 194 struct eeh_pe *eeh_pe_get(struct eeh_dev *edev); 205 195 int eeh_add_to_parent_pe(struct eeh_dev *edev); 206 - int eeh_rmv_from_parent_pe(struct eeh_dev *edev, int purge_pe); 196 + int eeh_rmv_from_parent_pe(struct eeh_dev *edev); 207 197 void eeh_pe_update_time_stamp(struct eeh_pe *pe); 198 + void *eeh_pe_traverse(struct eeh_pe *root, 199 + eeh_traverse_func fn, void *flag); 208 200 void *eeh_pe_dev_traverse(struct eeh_pe *root, 209 201 eeh_traverse_func fn, void *flag); 210 202 void eeh_pe_restore_bars(struct eeh_pe *pe); ··· 221 209 unsigned long val); 222 210 int eeh_dev_check_failure(struct eeh_dev *edev); 223 211 void eeh_addr_cache_build(void); 212 + void eeh_add_device_early(struct device_node *); 224 213 void eeh_add_device_tree_early(struct device_node *); 214 + void eeh_add_device_late(struct pci_dev *); 225 215 void eeh_add_device_tree_late(struct pci_bus *); 226 216 void eeh_add_sysfs_files(struct pci_bus *); 227 - void eeh_remove_bus_device(struct pci_dev *, int); 217 + void eeh_remove_device(struct pci_dev *); 228 218 229 219 /** 230 220 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure. ··· 266 252 267 253 static inline void eeh_addr_cache_build(void) { } 268 254 255 + static inline void eeh_add_device_early(struct device_node *dn) { } 256 + 269 257 static inline void eeh_add_device_tree_early(struct device_node *dn) { } 258 + 259 + static inline void eeh_add_device_late(struct pci_dev *dev) { } 270 260 271 261 static inline void eeh_add_device_tree_late(struct pci_bus *bus) { } 272 262 273 263 static inline void eeh_add_sysfs_files(struct pci_bus *bus) { } 274 264 275 - static inline void eeh_remove_bus_device(struct pci_dev *dev, int purge_pe) { } 265 + static inline void eeh_remove_device(struct pci_dev *dev) { } 276 266 277 267 #define EEH_POSSIBLE_ERROR(val, type) (0) 278 268 #define EEH_IO_ERROR_VALUE(size) (-1UL)
+4 -3
arch/powerpc/include/asm/hw_irq.h
··· 96 96 #endif 97 97 98 98 #define hard_irq_disable() do { \ 99 - u8 _was_enabled = get_paca()->soft_enabled; \ 99 + u8 _was_enabled; \ 100 100 __hard_irq_disable(); \ 101 - get_paca()->soft_enabled = 0; \ 102 - get_paca()->irq_happened |= PACA_IRQ_HARD_DIS; \ 101 + _was_enabled = local_paca->soft_enabled; \ 102 + local_paca->soft_enabled = 0; \ 103 + local_paca->irq_happened |= PACA_IRQ_HARD_DIS; \ 103 104 if (_was_enabled) \ 104 105 trace_hardirqs_off(); \ 105 106 } while(0)
+2 -3
arch/powerpc/include/asm/module.h
··· 82 82 void sort_ex_table(struct exception_table_entry *start, 83 83 struct exception_table_entry *finish); 84 84 85 - #ifdef CONFIG_MODVERSIONS 85 + #if defined(CONFIG_MODVERSIONS) && defined(CONFIG_PPC64) 86 86 #define ARCH_RELOCATES_KCRCTAB 87 - 88 - extern const unsigned long reloc_start[]; 87 + #define reloc_start PHYSICAL_START 89 88 #endif 90 89 #endif /* __KERNEL__ */ 91 90 #endif /* _ASM_POWERPC_MODULE_H */
-1
arch/powerpc/include/asm/pci-bridge.h
··· 209 209 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn); 210 210 211 211 /** Remove all of the PCI devices under this bus */ 212 - extern void __pcibios_remove_pci_devices(struct pci_bus *bus, int purge_pe); 213 212 extern void pcibios_remove_pci_devices(struct pci_bus *bus); 214 213 215 214 /** Discover new pci devices under this bus, and add them */
+2 -1
arch/powerpc/include/asm/reg.h
··· 1088 1088 #define PVR_970MP 0x0044 1089 1089 #define PVR_970GX 0x0045 1090 1090 #define PVR_POWER7p 0x004A 1091 - #define PVR_POWER8 0x004B 1091 + #define PVR_POWER8E 0x004B 1092 + #define PVR_POWER8 0x004D 1092 1093 #define PVR_BE 0x0070 1093 1094 #define PVR_PA6T 0x0090 1094 1095
+19 -1
arch/powerpc/kernel/cputable.c
··· 494 494 .cpu_restore = __restore_cpu_power7, 495 495 .platform = "power7+", 496 496 }, 497 - { /* Power8 */ 497 + { /* Power8E */ 498 498 .pvr_mask = 0xffff0000, 499 499 .pvr_value = 0x004b0000, 500 + .cpu_name = "POWER8E (raw)", 501 + .cpu_features = CPU_FTRS_POWER8, 502 + .cpu_user_features = COMMON_USER_POWER8, 503 + .cpu_user_features2 = COMMON_USER2_POWER8, 504 + .mmu_features = MMU_FTRS_POWER8, 505 + .icache_bsize = 128, 506 + .dcache_bsize = 128, 507 + .num_pmcs = 6, 508 + .pmc_type = PPC_PMC_IBM, 509 + .oprofile_cpu_type = "ppc64/power8", 510 + .oprofile_type = PPC_OPROFILE_INVALID, 511 + .cpu_setup = __setup_cpu_power8, 512 + .cpu_restore = __restore_cpu_power8, 513 + .platform = "power8", 514 + }, 515 + { /* Power8 */ 516 + .pvr_mask = 0xffff0000, 517 + .pvr_value = 0x004d0000, 500 518 .cpu_name = "POWER8 (raw)", 501 519 .cpu_features = CPU_FTRS_POWER8, 502 520 .cpu_user_features = COMMON_USER_POWER8,
+34 -36
arch/powerpc/kernel/eeh.c
··· 231 231 void eeh_slot_error_detail(struct eeh_pe *pe, int severity) 232 232 { 233 233 size_t loglen = 0; 234 - struct eeh_dev *edev; 234 + struct eeh_dev *edev, *tmp; 235 235 bool valid_cfg_log = true; 236 236 237 237 /* ··· 251 251 eeh_pe_restore_bars(pe); 252 252 253 253 pci_regs_buf[0] = 0; 254 - eeh_pe_for_each_dev(pe, edev) { 254 + eeh_pe_for_each_dev(pe, edev, tmp) { 255 255 loglen += eeh_gather_pci_data(edev, pci_regs_buf + loglen, 256 256 EEH_PCI_REGS_LOG_LEN - loglen); 257 257 } ··· 499 499 } 500 500 501 501 eeh_dev_check_failure(edev); 502 - 503 - pci_dev_put(eeh_dev_to_pci_dev(edev)); 504 502 return val; 505 503 } 506 504 ··· 836 838 * on the CEC architecture, type of the device, on earlier boot 837 839 * command-line arguments & etc. 838 840 */ 839 - static void eeh_add_device_early(struct device_node *dn) 841 + void eeh_add_device_early(struct device_node *dn) 840 842 { 841 843 struct pci_controller *phb; 842 844 ··· 884 886 * This routine must be used to complete EEH initialization for PCI 885 887 * devices that were added after system boot (e.g. hotplug, dlpar). 886 888 */ 887 - static void eeh_add_device_late(struct pci_dev *dev) 889 + void eeh_add_device_late(struct pci_dev *dev) 888 890 { 889 891 struct device_node *dn; 890 892 struct eeh_dev *edev; ··· 900 902 pr_debug("EEH: Already referenced !\n"); 901 903 return; 902 904 } 903 - WARN_ON(edev->pdev); 904 905 905 - pci_dev_get(dev); 906 + /* 907 + * The EEH cache might not be removed correctly because of 908 + * unbalanced kref to the device during unplug time, which 909 + * relies on pcibios_release_device(). So we have to remove 910 + * that here explicitly. 911 + */ 912 + if (edev->pdev) { 913 + eeh_rmv_from_parent_pe(edev); 914 + eeh_addr_cache_rmv_dev(edev->pdev); 915 + eeh_sysfs_remove_device(edev->pdev); 916 + edev->mode &= ~EEH_DEV_SYSFS; 917 + 918 + edev->pdev = NULL; 919 + dev->dev.archdata.edev = NULL; 920 + } 921 + 906 922 edev->pdev = dev; 907 923 dev->dev.archdata.edev = edev; 908 924 ··· 979 967 /** 980 968 * eeh_remove_device - Undo EEH setup for the indicated pci device 981 969 * @dev: pci device to be removed 982 - * @purge_pe: remove the PE or not 983 970 * 984 971 * This routine should be called when a device is removed from 985 972 * a running system (e.g. by hotplug or dlpar). It unregisters ··· 986 975 * this device will no longer be detected after this call; thus, 987 976 * i/o errors affecting this slot may leave this device unusable. 988 977 */ 989 - static void eeh_remove_device(struct pci_dev *dev, int purge_pe) 978 + void eeh_remove_device(struct pci_dev *dev) 990 979 { 991 980 struct eeh_dev *edev; 992 981 ··· 997 986 /* Unregister the device with the EEH/PCI address search system */ 998 987 pr_debug("EEH: Removing device %s\n", pci_name(dev)); 999 988 1000 - if (!edev || !edev->pdev) { 989 + if (!edev || !edev->pdev || !edev->pe) { 1001 990 pr_debug("EEH: Not referenced !\n"); 1002 991 return; 1003 992 } 993 + 994 + /* 995 + * During the hotplug for EEH error recovery, we need the EEH 996 + * device attached to the parent PE in order for BAR restore 997 + * a bit later. So we keep it for BAR restore and remove it 998 + * from the parent PE during the BAR resotre. 999 + */ 1004 1000 edev->pdev = NULL; 1005 1001 dev->dev.archdata.edev = NULL; 1006 - pci_dev_put(dev); 1002 + if (!(edev->pe->state & EEH_PE_KEEP)) 1003 + eeh_rmv_from_parent_pe(edev); 1004 + else 1005 + edev->mode |= EEH_DEV_DISCONNECTED; 1007 1006 1008 - eeh_rmv_from_parent_pe(edev, purge_pe); 1009 1007 eeh_addr_cache_rmv_dev(dev); 1010 1008 eeh_sysfs_remove_device(dev); 1009 + edev->mode &= ~EEH_DEV_SYSFS; 1011 1010 } 1012 - 1013 - /** 1014 - * eeh_remove_bus_device - Undo EEH setup for the indicated PCI device 1015 - * @dev: PCI device 1016 - * @purge_pe: remove the corresponding PE or not 1017 - * 1018 - * This routine must be called when a device is removed from the 1019 - * running system through hotplug or dlpar. The corresponding 1020 - * PCI address cache will be removed. 1021 - */ 1022 - void eeh_remove_bus_device(struct pci_dev *dev, int purge_pe) 1023 - { 1024 - struct pci_bus *bus = dev->subordinate; 1025 - struct pci_dev *child, *tmp; 1026 - 1027 - eeh_remove_device(dev, purge_pe); 1028 - 1029 - if (bus && dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 1030 - list_for_each_entry_safe(child, tmp, &bus->devices, bus_list) 1031 - eeh_remove_bus_device(child, purge_pe); 1032 - } 1033 - } 1034 - EXPORT_SYMBOL_GPL(eeh_remove_bus_device); 1035 1011 1036 1012 static int proc_eeh_show(struct seq_file *m, void *v) 1037 1013 {
+5 -13
arch/powerpc/kernel/eeh_cache.c
··· 68 68 struct pci_io_addr_range *piar; 69 69 piar = rb_entry(n, struct pci_io_addr_range, rb_node); 70 70 71 - if (addr < piar->addr_lo) { 71 + if (addr < piar->addr_lo) 72 72 n = n->rb_left; 73 - } else { 74 - if (addr > piar->addr_hi) { 75 - n = n->rb_right; 76 - } else { 77 - pci_dev_get(piar->pcidev); 78 - return piar->edev; 79 - } 80 - } 73 + else if (addr > piar->addr_hi) 74 + n = n->rb_right; 75 + else 76 + return piar->edev; 81 77 } 82 78 83 79 return NULL; ··· 152 156 if (!piar) 153 157 return NULL; 154 158 155 - pci_dev_get(dev); 156 159 piar->addr_lo = alo; 157 160 piar->addr_hi = ahi; 158 161 piar->edev = pci_dev_to_eeh_dev(dev); ··· 245 250 246 251 if (piar->pcidev == dev) { 247 252 rb_erase(n, &pci_io_addr_cache_root.rb_root); 248 - pci_dev_put(piar->pcidev); 249 253 kfree(piar); 250 254 goto restart; 251 255 } ··· 296 302 if (!edev) 297 303 continue; 298 304 299 - pci_dev_get(dev); /* matching put is in eeh_remove_device() */ 300 305 dev->dev.archdata.edev = edev; 301 306 edev->pdev = dev; 302 307 303 308 eeh_addr_cache_insert_dev(dev); 304 - 305 309 eeh_sysfs_add_device(dev); 306 310 } 307 311
+74 -3
arch/powerpc/kernel/eeh_driver.c
··· 143 143 static void eeh_enable_irq(struct pci_dev *dev) 144 144 { 145 145 struct eeh_dev *edev = pci_dev_to_eeh_dev(dev); 146 + struct irq_desc *desc; 146 147 147 148 if ((edev->mode) & EEH_DEV_IRQ_DISABLED) { 148 149 edev->mode &= ~EEH_DEV_IRQ_DISABLED; 149 - enable_irq(dev->irq); 150 + 151 + desc = irq_to_desc(dev->irq); 152 + if (desc && desc->depth > 0) 153 + enable_irq(dev->irq); 150 154 } 151 155 } 152 156 ··· 342 338 return NULL; 343 339 } 344 340 341 + static void *eeh_rmv_device(void *data, void *userdata) 342 + { 343 + struct pci_driver *driver; 344 + struct eeh_dev *edev = (struct eeh_dev *)data; 345 + struct pci_dev *dev = eeh_dev_to_pci_dev(edev); 346 + int *removed = (int *)userdata; 347 + 348 + /* 349 + * Actually, we should remove the PCI bridges as well. 350 + * However, that's lots of complexity to do that, 351 + * particularly some of devices under the bridge might 352 + * support EEH. So we just care about PCI devices for 353 + * simplicity here. 354 + */ 355 + if (!dev || (dev->hdr_type & PCI_HEADER_TYPE_BRIDGE)) 356 + return NULL; 357 + driver = eeh_pcid_get(dev); 358 + if (driver && driver->err_handler) 359 + return NULL; 360 + 361 + /* Remove it from PCI subsystem */ 362 + pr_debug("EEH: Removing %s without EEH sensitive driver\n", 363 + pci_name(dev)); 364 + edev->bus = dev->bus; 365 + edev->mode |= EEH_DEV_DISCONNECTED; 366 + (*removed)++; 367 + 368 + pci_stop_and_remove_bus_device(dev); 369 + 370 + return NULL; 371 + } 372 + 373 + static void *eeh_pe_detach_dev(void *data, void *userdata) 374 + { 375 + struct eeh_pe *pe = (struct eeh_pe *)data; 376 + struct eeh_dev *edev, *tmp; 377 + 378 + eeh_pe_for_each_dev(pe, edev, tmp) { 379 + if (!(edev->mode & EEH_DEV_DISCONNECTED)) 380 + continue; 381 + 382 + edev->mode &= ~(EEH_DEV_DISCONNECTED | EEH_DEV_IRQ_DISABLED); 383 + eeh_rmv_from_parent_pe(edev); 384 + } 385 + 386 + return NULL; 387 + } 388 + 345 389 /** 346 390 * eeh_reset_device - Perform actual reset of a pci slot 347 391 * @pe: EEH PE ··· 401 349 */ 402 350 static int eeh_reset_device(struct eeh_pe *pe, struct pci_bus *bus) 403 351 { 352 + struct pci_bus *frozen_bus = eeh_pe_bus_get(pe); 404 353 struct timeval tstamp; 405 - int cnt, rc; 354 + int cnt, rc, removed = 0; 406 355 407 356 /* pcibios will clear the counter; save the value */ 408 357 cnt = pe->freeze_count; ··· 415 362 * devices are expected to be attached soon when calling 416 363 * into pcibios_add_pci_devices(). 417 364 */ 365 + eeh_pe_state_mark(pe, EEH_PE_KEEP); 418 366 if (bus) 419 - __pcibios_remove_pci_devices(bus, 0); 367 + pcibios_remove_pci_devices(bus); 368 + else if (frozen_bus) 369 + eeh_pe_dev_traverse(pe, eeh_rmv_device, &removed); 420 370 421 371 /* Reset the pci controller. (Asserts RST#; resets config space). 422 372 * Reconfigure bridges and devices. Don't try to bring the system ··· 440 384 * potentially weird things happen. 441 385 */ 442 386 if (bus) { 387 + pr_info("EEH: Sleep 5s ahead of complete hotplug\n"); 443 388 ssleep(5); 389 + 390 + /* 391 + * The EEH device is still connected with its parent 392 + * PE. We should disconnect it so the binding can be 393 + * rebuilt when adding PCI devices. 394 + */ 395 + eeh_pe_traverse(pe, eeh_pe_detach_dev, NULL); 444 396 pcibios_add_pci_devices(bus); 397 + } else if (frozen_bus && removed) { 398 + pr_info("EEH: Sleep 5s ahead of partial hotplug\n"); 399 + ssleep(5); 400 + 401 + eeh_pe_traverse(pe, eeh_pe_detach_dev, NULL); 402 + pcibios_add_pci_devices(frozen_bus); 445 403 } 404 + eeh_pe_state_clear(pe, EEH_PE_KEEP); 446 405 447 406 pe->tstamp = tstamp; 448 407 pe->freeze_count = cnt;
+25 -33
arch/powerpc/kernel/eeh_pe.c
··· 149 149 * callback returns something other than NULL, or no more PEs 150 150 * to be traversed. 151 151 */ 152 - static void *eeh_pe_traverse(struct eeh_pe *root, 153 - eeh_traverse_func fn, void *flag) 152 + void *eeh_pe_traverse(struct eeh_pe *root, 153 + eeh_traverse_func fn, void *flag) 154 154 { 155 155 struct eeh_pe *pe; 156 156 void *ret; ··· 176 176 eeh_traverse_func fn, void *flag) 177 177 { 178 178 struct eeh_pe *pe; 179 - struct eeh_dev *edev; 179 + struct eeh_dev *edev, *tmp; 180 180 void *ret; 181 181 182 182 if (!root) { ··· 186 186 187 187 /* Traverse root PE */ 188 188 for (pe = root; pe; pe = eeh_pe_next(pe, root)) { 189 - eeh_pe_for_each_dev(pe, edev) { 189 + eeh_pe_for_each_dev(pe, edev, tmp) { 190 190 ret = fn(edev, flag); 191 191 if (ret) 192 192 return ret; ··· 333 333 while (parent) { 334 334 if (!(parent->type & EEH_PE_INVALID)) 335 335 break; 336 - parent->type &= ~EEH_PE_INVALID; 336 + parent->type &= ~(EEH_PE_INVALID | EEH_PE_KEEP); 337 337 parent = parent->parent; 338 338 } 339 339 pr_debug("EEH: Add %s to Device PE#%x, Parent PE#%x\n", ··· 397 397 /** 398 398 * eeh_rmv_from_parent_pe - Remove one EEH device from the associated PE 399 399 * @edev: EEH device 400 - * @purge_pe: remove PE or not 401 400 * 402 401 * The PE hierarchy tree might be changed when doing PCI hotplug. 403 402 * Also, the PCI devices or buses could be removed from the system 404 403 * during EEH recovery. So we have to call the function remove the 405 404 * corresponding PE accordingly if necessary. 406 405 */ 407 - int eeh_rmv_from_parent_pe(struct eeh_dev *edev, int purge_pe) 406 + int eeh_rmv_from_parent_pe(struct eeh_dev *edev) 408 407 { 409 408 struct eeh_pe *pe, *parent, *child; 410 409 int cnt; 411 410 412 411 if (!edev->pe) { 413 - pr_warning("%s: No PE found for EEH device %s\n", 414 - __func__, edev->dn->full_name); 412 + pr_debug("%s: No PE found for EEH device %s\n", 413 + __func__, edev->dn->full_name); 415 414 return -EEXIST; 416 415 } 417 416 ··· 430 431 if (pe->type & EEH_PE_PHB) 431 432 break; 432 433 433 - if (purge_pe) { 434 + if (!(pe->state & EEH_PE_KEEP)) { 434 435 if (list_empty(&pe->edevs) && 435 436 list_empty(&pe->child_list)) { 436 437 list_del(&pe->child); ··· 501 502 { 502 503 struct eeh_pe *pe = (struct eeh_pe *)data; 503 504 int state = *((int *)flag); 504 - struct eeh_dev *tmp; 505 + struct eeh_dev *edev, *tmp; 505 506 struct pci_dev *pdev; 506 507 507 508 /* ··· 511 512 * the PCI device driver. 512 513 */ 513 514 pe->state |= state; 514 - eeh_pe_for_each_dev(pe, tmp) { 515 - pdev = eeh_dev_to_pci_dev(tmp); 515 + eeh_pe_for_each_dev(pe, edev, tmp) { 516 + pdev = eeh_dev_to_pci_dev(edev); 516 517 if (pdev) 517 518 pdev->error_state = pci_channel_io_frozen; 518 519 } ··· 578 579 * blocked on normal path during the stage. So we need utilize 579 580 * eeh operations, which is always permitted. 580 581 */ 581 - static void eeh_bridge_check_link(struct pci_dev *pdev, 582 + static void eeh_bridge_check_link(struct eeh_dev *edev, 582 583 struct device_node *dn) 583 584 { 584 585 int cap; ··· 589 590 * We only check root port and downstream ports of 590 591 * PCIe switches 591 592 */ 592 - if (!pci_is_pcie(pdev) || 593 - (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT && 594 - pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM)) 593 + if (!(edev->mode & (EEH_DEV_ROOT_PORT | EEH_DEV_DS_PORT))) 595 594 return; 596 595 597 - pr_debug("%s: Check PCIe link for %s ...\n", 598 - __func__, pci_name(pdev)); 596 + pr_debug("%s: Check PCIe link for %04x:%02x:%02x.%01x ...\n", 597 + __func__, edev->phb->global_number, 598 + edev->config_addr >> 8, 599 + PCI_SLOT(edev->config_addr & 0xFF), 600 + PCI_FUNC(edev->config_addr & 0xFF)); 599 601 600 602 /* Check slot status */ 601 - cap = pdev->pcie_cap; 603 + cap = edev->pcie_cap; 602 604 eeh_ops->read_config(dn, cap + PCI_EXP_SLTSTA, 2, &val); 603 605 if (!(val & PCI_EXP_SLTSTA_PDS)) { 604 606 pr_debug(" No card in the slot (0x%04x) !\n", val); ··· 653 653 #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF)) 654 654 #define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)]) 655 655 656 - static void eeh_restore_bridge_bars(struct pci_dev *pdev, 657 - struct eeh_dev *edev, 656 + static void eeh_restore_bridge_bars(struct eeh_dev *edev, 658 657 struct device_node *dn) 659 658 { 660 659 int i; ··· 679 680 eeh_ops->write_config(dn, PCI_COMMAND, 4, edev->config_space[1]); 680 681 681 682 /* Check the PCIe link is ready */ 682 - eeh_bridge_check_link(pdev, dn); 683 + eeh_bridge_check_link(edev, dn); 683 684 } 684 685 685 686 static void eeh_restore_device_bars(struct eeh_dev *edev, ··· 728 729 */ 729 730 static void *eeh_restore_one_device_bars(void *data, void *flag) 730 731 { 731 - struct pci_dev *pdev = NULL; 732 732 struct eeh_dev *edev = (struct eeh_dev *)data; 733 733 struct device_node *dn = eeh_dev_to_of_node(edev); 734 734 735 - /* Trace the PCI bridge */ 736 - if (eeh_probe_mode_dev()) { 737 - pdev = eeh_dev_to_pci_dev(edev); 738 - if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) 739 - pdev = NULL; 740 - } 741 - 742 - if (pdev) 743 - eeh_restore_bridge_bars(pdev, edev, dn); 735 + /* Do special restore for bridges */ 736 + if (edev->mode & EEH_DEV_BRIDGE) 737 + eeh_restore_bridge_bars(edev, dn); 744 738 else 745 739 eeh_restore_device_bars(edev, dn); 746 740
+21
arch/powerpc/kernel/eeh_sysfs.c
··· 56 56 57 57 void eeh_sysfs_add_device(struct pci_dev *pdev) 58 58 { 59 + struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev); 59 60 int rc=0; 61 + 62 + if (edev && (edev->mode & EEH_DEV_SYSFS)) 63 + return; 60 64 61 65 rc += device_create_file(&pdev->dev, &dev_attr_eeh_mode); 62 66 rc += device_create_file(&pdev->dev, &dev_attr_eeh_config_addr); ··· 68 64 69 65 if (rc) 70 66 printk(KERN_WARNING "EEH: Unable to create sysfs entries\n"); 67 + else if (edev) 68 + edev->mode |= EEH_DEV_SYSFS; 71 69 } 72 70 73 71 void eeh_sysfs_remove_device(struct pci_dev *pdev) 74 72 { 73 + struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev); 74 + 75 + /* 76 + * The parent directory might have been removed. We needn't 77 + * continue for that case. 78 + */ 79 + if (!pdev->dev.kobj.sd) { 80 + if (edev) 81 + edev->mode &= ~EEH_DEV_SYSFS; 82 + return; 83 + } 84 + 75 85 device_remove_file(&pdev->dev, &dev_attr_eeh_mode); 76 86 device_remove_file(&pdev->dev, &dev_attr_eeh_config_addr); 77 87 device_remove_file(&pdev->dev, &dev_attr_eeh_pe_config_addr); 88 + 89 + if (edev) 90 + edev->mode &= ~EEH_DEV_SYSFS; 78 91 }
+2
arch/powerpc/kernel/pci-common.c
··· 1462 1462 /* Allocate bus and devices resources */ 1463 1463 pcibios_allocate_bus_resources(bus); 1464 1464 pcibios_claim_one_bus(bus); 1465 + if (!pci_has_flag(PCI_PROBE_ONLY)) 1466 + pci_assign_unassigned_bus_resources(bus); 1465 1467 1466 1468 /* Fixup EEH */ 1467 1469 eeh_add_device_tree_late(bus);
+28 -29
arch/powerpc/kernel/pci-hotplug.c
··· 22 22 #include <asm/eeh.h> 23 23 24 24 /** 25 - * __pcibios_remove_pci_devices - remove all devices under this bus 26 - * @bus: the indicated PCI bus 27 - * @purge_pe: destroy the PE on removal of PCI devices 25 + * pcibios_release_device - release PCI device 26 + * @dev: PCI device 28 27 * 29 - * Remove all of the PCI devices under this bus both from the 30 - * linux pci device tree, and from the powerpc EEH address cache. 31 - * By default, the corresponding PE will be destroied during the 32 - * normal PCI hotplug path. For PCI hotplug during EEH recovery, 33 - * the corresponding PE won't be destroied and deallocated. 28 + * The function is called before releasing the indicated PCI device. 34 29 */ 35 - void __pcibios_remove_pci_devices(struct pci_bus *bus, int purge_pe) 30 + void pcibios_release_device(struct pci_dev *dev) 36 31 { 37 - struct pci_dev *dev, *tmp; 38 - struct pci_bus *child_bus; 39 - 40 - /* First go down child busses */ 41 - list_for_each_entry(child_bus, &bus->children, node) 42 - __pcibios_remove_pci_devices(child_bus, purge_pe); 43 - 44 - pr_debug("PCI: Removing devices on bus %04x:%02x\n", 45 - pci_domain_nr(bus), bus->number); 46 - list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) { 47 - pr_debug(" * Removing %s...\n", pci_name(dev)); 48 - eeh_remove_bus_device(dev, purge_pe); 49 - pci_stop_and_remove_bus_device(dev); 50 - } 32 + eeh_remove_device(dev); 51 33 } 52 34 53 35 /** ··· 41 59 */ 42 60 void pcibios_remove_pci_devices(struct pci_bus *bus) 43 61 { 44 - __pcibios_remove_pci_devices(bus, 1); 62 + struct pci_dev *dev, *tmp; 63 + struct pci_bus *child_bus; 64 + 65 + /* First go down child busses */ 66 + list_for_each_entry(child_bus, &bus->children, node) 67 + pcibios_remove_pci_devices(child_bus); 68 + 69 + pr_debug("PCI: Removing devices on bus %04x:%02x\n", 70 + pci_domain_nr(bus), bus->number); 71 + list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) { 72 + pr_debug(" Removing %s...\n", pci_name(dev)); 73 + pci_stop_and_remove_bus_device(dev); 74 + } 45 75 } 76 + 46 77 EXPORT_SYMBOL_GPL(pcibios_remove_pci_devices); 47 78 48 79 /** ··· 71 76 */ 72 77 void pcibios_add_pci_devices(struct pci_bus * bus) 73 78 { 74 - int slotno, num, mode, pass, max; 79 + int slotno, mode, pass, max; 75 80 struct pci_dev *dev; 76 81 struct device_node *dn = pci_bus_to_OF_node(bus); 77 82 ··· 85 90 /* use ofdt-based probe */ 86 91 of_rescan_bus(dn, bus); 87 92 } else if (mode == PCI_PROBE_NORMAL) { 88 - /* use legacy probe */ 93 + /* 94 + * Use legacy probe. In the partial hotplug case, we 95 + * probably have grandchildren devices unplugged. So 96 + * we don't check the return value from pci_scan_slot() in 97 + * order for fully rescan all the way down to pick them up. 98 + * They can have been removed during partial hotplug. 99 + */ 89 100 slotno = PCI_SLOT(PCI_DN(dn->child)->devfn); 90 - num = pci_scan_slot(bus, PCI_DEVFN(slotno, 0)); 91 - if (!num) 92 - return; 101 + pci_scan_slot(bus, PCI_DEVFN(slotno, 0)); 93 102 pcibios_setup_bus_devices(bus); 94 103 max = bus->busn_res.start; 95 104 for (pass = 0; pass < 2; pass++) {
+40 -16
arch/powerpc/kernel/pci_of_scan.c
··· 230 230 return; 231 231 } 232 232 233 - bus = pci_add_new_bus(dev->bus, dev, busrange[0]); 233 + bus = pci_find_bus(pci_domain_nr(dev->bus), busrange[0]); 234 234 if (!bus) { 235 - printk(KERN_ERR "Failed to create pci bus for %s\n", 236 - node->full_name); 237 - return; 235 + bus = pci_add_new_bus(dev->bus, dev, busrange[0]); 236 + if (!bus) { 237 + printk(KERN_ERR "Failed to create pci bus for %s\n", 238 + node->full_name); 239 + return; 240 + } 238 241 } 239 242 240 243 bus->primary = dev->bus->number; ··· 295 292 } 296 293 EXPORT_SYMBOL(of_scan_pci_bridge); 297 294 295 + static struct pci_dev *of_scan_pci_dev(struct pci_bus *bus, 296 + struct device_node *dn) 297 + { 298 + struct pci_dev *dev = NULL; 299 + const u32 *reg; 300 + int reglen, devfn; 301 + 302 + pr_debug(" * %s\n", dn->full_name); 303 + if (!of_device_is_available(dn)) 304 + return NULL; 305 + 306 + reg = of_get_property(dn, "reg", &reglen); 307 + if (reg == NULL || reglen < 20) 308 + return NULL; 309 + devfn = (reg[0] >> 8) & 0xff; 310 + 311 + /* Check if the PCI device is already there */ 312 + dev = pci_get_slot(bus, devfn); 313 + if (dev) { 314 + pci_dev_put(dev); 315 + return dev; 316 + } 317 + 318 + /* create a new pci_dev for this device */ 319 + dev = of_create_pci_dev(dn, bus, devfn); 320 + if (!dev) 321 + return NULL; 322 + 323 + pr_debug(" dev header type: %x\n", dev->hdr_type); 324 + return dev; 325 + } 326 + 298 327 /** 299 328 * __of_scan_bus - given a PCI bus node, setup bus and scan for child devices 300 329 * @node: device tree node for the PCI bus ··· 337 302 int rescan_existing) 338 303 { 339 304 struct device_node *child; 340 - const u32 *reg; 341 - int reglen, devfn; 342 305 struct pci_dev *dev; 343 306 344 307 pr_debug("of_scan_bus(%s) bus no %d...\n", ··· 344 311 345 312 /* Scan direct children */ 346 313 for_each_child_of_node(node, child) { 347 - pr_debug(" * %s\n", child->full_name); 348 - if (!of_device_is_available(child)) 349 - continue; 350 - reg = of_get_property(child, "reg", &reglen); 351 - if (reg == NULL || reglen < 20) 352 - continue; 353 - devfn = (reg[0] >> 8) & 0xff; 354 - 355 - /* create a new pci_dev for this device */ 356 - dev = of_create_pci_dev(child, bus, devfn); 314 + dev = of_scan_pci_dev(bus, child); 357 315 if (!dev) 358 316 continue; 359 317 pr_debug(" dev header type: %x\n", dev->hdr_type);
+3 -2
arch/powerpc/kernel/prom_init.c
··· 644 644 W(0xfffe0000), W(0x003a0000), /* POWER5/POWER5+ */ 645 645 W(0xffff0000), W(0x003e0000), /* POWER6 */ 646 646 W(0xffff0000), W(0x003f0000), /* POWER7 */ 647 - W(0xffff0000), W(0x004b0000), /* POWER8 */ 647 + W(0xffff0000), W(0x004b0000), /* POWER8E */ 648 + W(0xffff0000), W(0x004d0000), /* POWER8 */ 648 649 W(0xffffffff), W(0x0f000004), /* all 2.07-compliant */ 649 650 W(0xffffffff), W(0x0f000003), /* all 2.06-compliant */ 650 651 W(0xffffffff), W(0x0f000002), /* all 2.05-compliant */ ··· 707 706 * must match by the macro below. Update the definition if 708 707 * the structure layout changes. 709 708 */ 710 - #define IBM_ARCH_VEC_NRCORES_OFFSET 117 709 + #define IBM_ARCH_VEC_NRCORES_OFFSET 125 711 710 W(NR_CPUS), /* number of cores supported */ 712 711 0, 713 712 0,
-3
arch/powerpc/kernel/vmlinux.lds.S
··· 38 38 #endif 39 39 SECTIONS 40 40 { 41 - . = 0; 42 - reloc_start = .; 43 - 44 41 . = KERNELBASE; 45 42 46 43 /*
+10 -2
arch/powerpc/mm/hash_native_64.c
··· 43 43 { 44 44 unsigned long va; 45 45 unsigned int penc; 46 + unsigned long sllp; 46 47 47 48 /* 48 49 * We need 14 to 65 bits of va for a tlibe of 4K page ··· 65 64 /* clear out bits after (52) [0....52.....63] */ 66 65 va &= ~((1ul << (64 - 52)) - 1); 67 66 va |= ssize << 8; 68 - va |= mmu_psize_defs[apsize].sllp << 6; 67 + sllp = ((mmu_psize_defs[apsize].sllp & SLB_VSID_L) >> 6) | 68 + ((mmu_psize_defs[apsize].sllp & SLB_VSID_LP) >> 4); 69 + va |= sllp << 5; 69 70 asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2) 70 71 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) 71 72 : "memory"); ··· 101 98 { 102 99 unsigned long va; 103 100 unsigned int penc; 101 + unsigned long sllp; 104 102 105 103 /* VPN_SHIFT can be atmost 12 */ 106 104 va = vpn << VPN_SHIFT; ··· 117 113 /* clear out bits after(52) [0....52.....63] */ 118 114 va &= ~((1ul << (64 - 52)) - 1); 119 115 va |= ssize << 8; 120 - va |= mmu_psize_defs[apsize].sllp << 6; 116 + sllp = ((mmu_psize_defs[apsize].sllp & SLB_VSID_L) >> 6) | 117 + ((mmu_psize_defs[apsize].sllp & SLB_VSID_LP) >> 4); 118 + va |= sllp << 5; 121 119 asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)" 122 120 : : "r"(va) : "memory"); 123 121 break; ··· 560 554 seg_off |= vpi << shift; 561 555 } 562 556 *vpn = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT; 557 + break; 563 558 case MMU_SEGSIZE_1T: 564 559 /* We only have 40 - 23 bits of seg_off in avpn */ 565 560 seg_off = (avpn & 0x1ffff) << 23; ··· 570 563 seg_off |= vpi << shift; 571 564 } 572 565 *vpn = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT; 566 + break; 573 567 default: 574 568 *vpn = size = 0; 575 569 }
+4 -1
arch/powerpc/perf/core-book3s.c
··· 1252 1252 1253 1253 ret = 0; 1254 1254 out: 1255 - if (has_branch_stack(event)) 1255 + if (has_branch_stack(event)) { 1256 1256 power_pmu_bhrb_enable(event); 1257 + cpuhw->bhrb_filter = ppmu->bhrb_filter_map( 1258 + event->attr.branch_sample_type); 1259 + } 1257 1260 1258 1261 perf_pmu_enable(event->pmu); 1259 1262 local_irq_restore(flags);
+14 -10
arch/powerpc/perf/power8-pmu.c
··· 561 561 static u64 power8_bhrb_filter_map(u64 branch_sample_type) 562 562 { 563 563 u64 pmu_bhrb_filter = 0; 564 - u64 br_privilege = branch_sample_type & ONLY_PLM; 565 564 566 - /* BHRB and regular PMU events share the same prvillege state 565 + /* BHRB and regular PMU events share the same privilege state 567 566 * filter configuration. BHRB is always recorded along with a 568 - * regular PMU event. So privilege state filter criteria for BHRB 569 - * and the companion PMU events has to be the same. As a default 570 - * "perf record" tool sets all privillege bits ON when no filter 571 - * criteria is provided in the command line. So as along as all 572 - * privillege bits are ON or they are OFF, we are good to go. 567 + * regular PMU event. As the privilege state filter is handled 568 + * in the basic PMC configuration of the accompanying regular 569 + * PMU event, we ignore any separate BHRB specific request. 573 570 */ 574 - if ((br_privilege != 7) && (br_privilege != 0)) 575 - return -1; 576 571 577 572 /* No branch filter requested */ 578 573 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY) ··· 616 621 617 622 static int __init init_power8_pmu(void) 618 623 { 624 + int rc; 625 + 619 626 if (!cur_cpu_spec->oprofile_cpu_type || 620 627 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power8")) 621 628 return -ENODEV; 622 629 623 - return register_power_pmu(&power8_pmu); 630 + rc = register_power_pmu(&power8_pmu); 631 + if (rc) 632 + return rc; 633 + 634 + /* Tell userspace that EBB is supported */ 635 + cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB; 636 + 637 + return 0; 624 638 } 625 639 early_initcall(init_power8_pmu);
+14 -3
arch/powerpc/platforms/powernv/eeh-powernv.c
··· 114 114 * the root bridge. So it's not reasonable to continue 115 115 * the probing. 116 116 */ 117 - if (!dn || !edev) 117 + if (!dn || !edev || edev->pe) 118 118 return 0; 119 119 120 120 /* Skip for PCI-ISA bridge */ ··· 122 122 return 0; 123 123 124 124 /* Initialize eeh device */ 125 - edev->class_code = dev->class; 126 - edev->mode = 0; 125 + edev->class_code = dev->class; 126 + edev->mode &= 0xFFFFFF00; 127 + if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) 128 + edev->mode |= EEH_DEV_BRIDGE; 129 + if (pci_is_pcie(dev)) { 130 + edev->pcie_cap = pci_pcie_cap(dev); 131 + 132 + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 133 + edev->mode |= EEH_DEV_ROOT_PORT; 134 + else if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) 135 + edev->mode |= EEH_DEV_DS_PORT; 136 + } 137 + 127 138 edev->config_addr = ((dev->bus->number << 8) | dev->devfn); 128 139 edev->pe_config_addr = phb->bdfn_to_pe(phb, dev->bus, dev->devfn & 0xff); 129 140
+1 -1
arch/powerpc/platforms/powernv/pci-ioda.c
··· 1266 1266 opal_pci_set_pe(phb_id, 0, 0, 7, 1, 1 , OPAL_MAP_PE); 1267 1267 } 1268 1268 1269 - void pnv_pci_init_ioda2_phb(struct device_node *np) 1269 + void __init pnv_pci_init_ioda2_phb(struct device_node *np) 1270 1270 { 1271 1271 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); 1272 1272 }
-1
arch/powerpc/platforms/pseries/Kconfig
··· 19 19 select ZLIB_DEFLATE 20 20 select PPC_DOORBELL 21 21 select HAVE_CONTEXT_TRACKING 22 - select HOTPLUG if SMP 23 22 select HOTPLUG_CPU if SMP 24 23 default y 25 24
+64 -3
arch/powerpc/platforms/pseries/eeh_pseries.c
··· 133 133 return 0; 134 134 } 135 135 136 + static int pseries_eeh_cap_start(struct device_node *dn) 137 + { 138 + struct pci_dn *pdn = PCI_DN(dn); 139 + u32 status; 140 + 141 + if (!pdn) 142 + return 0; 143 + 144 + rtas_read_config(pdn, PCI_STATUS, 2, &status); 145 + if (!(status & PCI_STATUS_CAP_LIST)) 146 + return 0; 147 + 148 + return PCI_CAPABILITY_LIST; 149 + } 150 + 151 + 152 + static int pseries_eeh_find_cap(struct device_node *dn, int cap) 153 + { 154 + struct pci_dn *pdn = PCI_DN(dn); 155 + int pos = pseries_eeh_cap_start(dn); 156 + int cnt = 48; /* Maximal number of capabilities */ 157 + u32 id; 158 + 159 + if (!pos) 160 + return 0; 161 + 162 + while (cnt--) { 163 + rtas_read_config(pdn, pos, 1, &pos); 164 + if (pos < 0x40) 165 + break; 166 + pos &= ~3; 167 + rtas_read_config(pdn, pos + PCI_CAP_LIST_ID, 1, &id); 168 + if (id == 0xff) 169 + break; 170 + if (id == cap) 171 + return pos; 172 + pos += PCI_CAP_LIST_NEXT; 173 + } 174 + 175 + return 0; 176 + } 177 + 136 178 /** 137 179 * pseries_eeh_of_probe - EEH probe on the given device 138 180 * @dn: OF node ··· 188 146 { 189 147 struct eeh_dev *edev; 190 148 struct eeh_pe pe; 149 + struct pci_dn *pdn = PCI_DN(dn); 191 150 const u32 *class_code, *vendor_id, *device_id; 192 151 const u32 *regs; 152 + u32 pcie_flags; 193 153 int enable = 0; 194 154 int ret; 195 155 196 156 /* Retrieve OF node and eeh device */ 197 157 edev = of_node_to_eeh_dev(dn); 198 - if (!of_device_is_available(dn)) 158 + if (edev->pe || !of_device_is_available(dn)) 199 159 return NULL; 200 160 201 161 /* Retrieve class/vendor/device IDs */ ··· 211 167 if (dn->type && !strcmp(dn->type, "isa")) 212 168 return NULL; 213 169 214 - /* Update class code and mode of eeh device */ 170 + /* 171 + * Update class code and mode of eeh device. We need 172 + * correctly reflects that current device is root port 173 + * or PCIe switch downstream port. 174 + */ 215 175 edev->class_code = *class_code; 216 - edev->mode = 0; 176 + edev->pcie_cap = pseries_eeh_find_cap(dn, PCI_CAP_ID_EXP); 177 + edev->mode &= 0xFFFFFF00; 178 + if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { 179 + edev->mode |= EEH_DEV_BRIDGE; 180 + if (edev->pcie_cap) { 181 + rtas_read_config(pdn, edev->pcie_cap + PCI_EXP_FLAGS, 182 + 2, &pcie_flags); 183 + pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; 184 + if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) 185 + edev->mode |= EEH_DEV_ROOT_PORT; 186 + else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) 187 + edev->mode |= EEH_DEV_DS_PORT; 188 + } 189 + } 217 190 218 191 /* Retrieve the device address */ 219 192 regs = of_get_property(dn, "reg", NULL);
+1 -1
arch/powerpc/platforms/pseries/lpar.c
··· 146 146 flags = 0; 147 147 148 148 /* Make pHyp happy */ 149 - if ((rflags & _PAGE_NO_CACHE) & !(rflags & _PAGE_WRITETHRU)) 149 + if ((rflags & _PAGE_NO_CACHE) && !(rflags & _PAGE_WRITETHRU)) 150 150 hpte_r &= ~_PAGE_COHERENT; 151 151 if (firmware_has_feature(FW_FEATURE_XCMO) && !(hpte_r & HPTE_R_N)) 152 152 flags |= H_COALESCE_CAND;
+3
arch/powerpc/platforms/pseries/ras.c
··· 287 287 unsigned long *savep; 288 288 struct rtas_error_log *h, *errhdr = NULL; 289 289 290 + /* Mask top two bits */ 291 + regs->gpr[3] &= ~(0x3UL << 62); 292 + 290 293 if (!VALID_FWNMI_BUFFER(regs->gpr[3])) { 291 294 printk(KERN_ERR "FWNMI: corrupt r3 0x%016lx\n", regs->gpr[3]); 292 295 return NULL;
-1
drivers/pci/hotplug/rpadlpar_core.c
··· 388 388 /* Remove the EADS bridge device itself */ 389 389 BUG_ON(!bus->self); 390 390 pr_debug("PCI: Now removing bridge device %s\n", pci_name(bus->self)); 391 - eeh_remove_bus_device(bus->self, true); 392 391 pci_stop_and_remove_bus_device(bus->self); 393 392 394 393 return 0;