Merge git://www.linux-watchdog.org/linux-watchdog

+23

Documentation/devicetree/bindings/watchdog/da9062-wdt.txt

··· 1 + * Dialog Semiconductor DA9062/61 Watchdog Timer 2 + 3 + Required properties: 4 + 5 + - compatible: should be one of the following valid compatible string lines: 6 + "dlg,da9061-watchdog", "dlg,da9062-watchdog" 7 + "dlg,da9062-watchdog" 8 + 9 + Example: DA9062 10 + 11 + pmic0: da9062@58 { 12 + watchdog { 13 + compatible = "dlg,da9062-watchdog"; 14 + }; 15 + }; 16 + 17 + Example: DA9061 using a fall-back compatible for the DA9062 watchdog driver 18 + 19 + pmic0: da9061@58 { 20 + watchdog { 21 + compatible = "dlg,da9061-watchdog", "dlg,da9062-watchdog"; 22 + }; 23 + };

+3

Documentation/devicetree/bindings/watchdog/dw_wdt.txt

··· 10 10 Optional Properties: 11 11 12 12 - interrupts : The interrupt used for the watchdog timeout warning. 13 + - resets : phandle pointing to the system reset controller with 14 + line index for the watchdog. 13 15 14 16 Example: 15 17 ··· 20 18 reg = <0xffd02000 0x1000>; 21 19 interrupts = <0 171 4>; 22 20 clocks = <&per_base_clk>; 21 + resets = <&rst WDT0_RESET>; 23 22 };

+3 -1

Documentation/devicetree/bindings/watchdog/renesas-wdt.txt

··· 2 2 3 3 Required properties: 4 4 - compatible : Should be "renesas,<soctype>-wdt", and 5 - "renesas,rcar-gen3-wdt" as fallback. 5 + "renesas,rcar-gen3-wdt" or "renesas,rza-wdt" as fallback. 6 6 Examples with soctypes are: 7 7 - "renesas,r8a7795-wdt" (R-Car H3) 8 8 - "renesas,r8a7796-wdt" (R-Car M3-W) 9 + - "renesas,r7s72100-wdt" (RZ/A1) 9 10 10 11 When compatible with the generic version, nodes must list the SoC-specific 11 12 version corresponding to the platform first, followed by the generic ··· 18 17 Optional properties: 19 18 - timeout-sec : Contains the watchdog timeout in seconds 20 19 - power-domains : the power domain the WDT belongs to 20 + - interrupts: Some WDTs have an interrupt when used in interval timer mode 21 21 22 22 Examples: 23 23

+19

Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.txt

··· 1 + STM32 Independent WatchDoG (IWDG) 2 + --------------------------------- 3 + 4 + Required properties: 5 + - compatible: "st,stm32-iwdg" 6 + - reg: physical base address and length of the registers set for the device 7 + - clocks: must contain a single entry describing the clock input 8 + 9 + Optional Properties: 10 + - timeout-sec: Watchdog timeout value in seconds. 11 + 12 + Example: 13 + 14 + iwdg: watchdog@40003000 { 15 + compatible = "st,stm32-iwdg"; 16 + reg = <0x40003000 0x400>; 17 + clocks = <&clk_lsi>; 18 + timeout-sec = <32>; 19 + };

+20

Documentation/devicetree/bindings/watchdog/uniphier-wdt.txt

··· 1 + UniPhier watchdog timer controller 2 + 3 + This UniPhier watchdog timer controller must be under sysctrl node. 4 + 5 + Required properties: 6 + - compatible: should be "socionext,uniphier-wdt" 7 + 8 + Example: 9 + 10 + sysctrl@61840000 { 11 + compatible = "socionext,uniphier-ld11-sysctrl", 12 + "simple-mfd", "syscon"; 13 + reg = <0x61840000 0x4000>; 14 + 15 + watchdog { 16 + compatible = "socionext,uniphier-wdt"; 17 + } 18 + 19 + other nodes ... 20 + };

+6

Documentation/watchdog/watchdog-parameters.txt

··· 369 369 nowayout: Watchdog cannot be stopped once started 370 370 (default=kernel config parameter) 371 371 ------------------------------------------------- 372 + uniphier_wdt: 373 + timeout: Watchdog timeout in power of two seconds. 374 + (1 <= timeout <= 128, default=64) 375 + nowayout: Watchdog cannot be stopped once started 376 + (default=kernel config parameter) 377 + ------------------------------------------------- 372 378 w83627hf_wdt: 373 379 wdt_io: w83627hf/thf WDT io port (default 0x2E) 374 380 timeout: Watchdog timeout in seconds. 1 <= timeout <= 255, default=60.

+52 -9

drivers/watchdog/Kconfig

··· 46 46 get killed. If you say Y here, the watchdog cannot be stopped once 47 47 it has been started. 48 48 49 + config WATCHDOG_HANDLE_BOOT_ENABLED 50 + bool "Update boot-enabled watchdog until userspace takes over" 51 + default y 52 + help 53 + The default watchdog behaviour (which you get if you say Y here) is 54 + to ping watchdog devices that were enabled before the driver has 55 + been loaded until control is taken over from userspace using the 56 + /dev/watchdog file. If you say N here, the kernel will not update 57 + the watchdog on its own. Thus if your userspace does not start fast 58 + enough your device will reboot. 59 + 49 60 config WATCHDOG_SYSFS 50 61 bool "Read different watchdog information through sysfs" 51 62 help ··· 732 721 This driver adds watchdog support for the integrated watchdogs in the 733 722 Renesas R-Car and other SH-Mobile SoCs (usually named RWDT or SWDT). 734 723 724 + config RENESAS_RZAWDT 725 + tristate "Renesas RZ/A WDT Watchdog" 726 + depends on ARCH_RENESAS || COMPILE_TEST 727 + select WATCHDOG_CORE 728 + help 729 + This driver adds watchdog support for the integrated watchdogs in the 730 + Renesas RZ/A SoCs. These watchdogs can be used to reset a system. 731 + 735 732 config ASPEED_WATCHDOG 736 733 tristate "Aspeed 2400 watchdog support" 737 734 depends on ARCH_ASPEED || COMPILE_TEST ··· 762 743 in ZTE zx2967 SoCs. 763 744 To compile this driver as a module, choose M here: the 764 745 module will be called zx2967_wdt. 746 + 747 + config STM32_WATCHDOG 748 + tristate "STM32 Independent WatchDoG (IWDG) support" 749 + depends on ARCH_STM32 750 + select WATCHDOG_CORE 751 + default y 752 + help 753 + Say Y here to include support for the watchdog timer 754 + in stm32 SoCs. 755 + 756 + To compile this driver as a module, choose M here: the 757 + module will be called stm32_iwdg. 758 + 759 + config UNIPHIER_WATCHDOG 760 + tristate "UniPhier watchdog support" 761 + depends on ARCH_UNIPHIER || COMPILE_TEST 762 + depends on OF && MFD_SYSCON 763 + select WATCHDOG_CORE 764 + help 765 + Say Y here to include support watchdog timer embedded 766 + into the UniPhier system. 767 + 768 + To compile this driver as a module, choose M here: the 769 + module will be called uniphier_wdt. 765 770 766 771 # AVR32 Architecture 767 772 ··· 872 829 the timeout module parameter. 873 830 874 831 config F71808E_WDT 875 - tristate "Fintek F71808E, F71862FG, F71869, F71882FG and F71889FG Watchdog" 832 + tristate "Fintek F718xx, F818xx Super I/O Watchdog" 876 833 depends on X86 877 834 help 878 - This is the driver for the hardware watchdog on the Fintek 879 - F71808E, F71862FG, F71869, F71882FG and F71889FG Super I/O controllers. 835 + This is the driver for the hardware watchdog on the Fintek F71808E, 836 + F71862FG, F71868, F71869, F71882FG, F71889FG, F81865 and F81866 837 + Super I/O controllers. 880 838 881 839 You can compile this driver directly into the kernel, or use 882 840 it as a module. The module will be called f71808e_wdt. ··· 1081 1037 config IT87_WDT 1082 1038 tristate "IT87 Watchdog Timer" 1083 1039 depends on X86 1040 + select WATCHDOG_CORE 1084 1041 ---help--- 1085 - This is the driver for the hardware watchdog on the ITE IT8620, 1086 - IT8702, IT8712, IT8716, IT8718, IT8720, IT8721, IT8726 and IT8728 1087 - Super I/O chips. 1088 - 1089 - If the driver does not work, then make sure that the game port in 1090 - the BIOS is enabled. 1042 + This is the driver for the hardware watchdog on the ITE IT8607, 1043 + IT8620, IT8622, IT8625, IT8628, IT8655, IT8665, IT8686, IT8702, 1044 + IT8712, IT8716, IT8718, IT8720, IT8721, IT8726, IT8728, and 1045 + IT8783 Super I/O chips. 1091 1046 1092 1047 This watchdog simply watches your kernel to make sure it doesn't 1093 1048 freeze, and if it does, it reboots your computer after a certain

+3

drivers/watchdog/Makefile

··· 82 82 obj-$(CONFIG_BCM7038_WDT) += bcm7038_wdt.o 83 83 obj-$(CONFIG_ATLAS7_WATCHDOG) += atlas7_wdt.o 84 84 obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o 85 + obj-$(CONFIG_RENESAS_RZAWDT) += rza_wdt.o 85 86 obj-$(CONFIG_ASPEED_WATCHDOG) += aspeed_wdt.o 86 87 obj-$(CONFIG_ZX2967_WATCHDOG) += zx2967_wdt.o 88 + obj-$(CONFIG_STM32_WATCHDOG) += stm32_iwdg.o 89 + obj-$(CONFIG_UNIPHIER_WATCHDOG) += uniphier_wdt.o 87 90 88 91 # AVR32 Architecture 89 92 obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o

+2 -2

drivers/watchdog/bcm47xx_wdt.c

··· 97 97 return 0; 98 98 } 99 99 100 - static struct watchdog_ops bcm47xx_wdt_hard_ops = { 100 + static const struct watchdog_ops bcm47xx_wdt_hard_ops = { 101 101 .owner = THIS_MODULE, 102 102 .start = bcm47xx_wdt_hard_start, 103 103 .stop = bcm47xx_wdt_hard_stop, ··· 168 168 WDIOF_MAGICCLOSE, 169 169 }; 170 170 171 - static struct watchdog_ops bcm47xx_wdt_soft_ops = { 171 + static const struct watchdog_ops bcm47xx_wdt_soft_ops = { 172 172 .owner = THIS_MODULE, 173 173 .start = bcm47xx_wdt_soft_start, 174 174 .stop = bcm47xx_wdt_soft_stop,

+1 -1

drivers/watchdog/cadence_wdt.c

··· 458 458 459 459 static SIMPLE_DEV_PM_OPS(cdns_wdt_pm_ops, cdns_wdt_suspend, cdns_wdt_resume); 460 460 461 - static struct of_device_id cdns_wdt_of_match[] = { 461 + static const struct of_device_id cdns_wdt_of_match[] = { 462 462 { .compatible = "cdns,wdt-r1p2", }, 463 463 { /* end of table */ } 464 464 };

+8 -2

drivers/watchdog/davinci_wdt.c

··· 173 173 return PTR_ERR(davinci_wdt->clk); 174 174 } 175 175 176 - clk_prepare_enable(davinci_wdt->clk); 176 + ret = clk_prepare_enable(davinci_wdt->clk); 177 + if (ret) { 178 + dev_err(&pdev->dev, "failed to prepare clock\n"); 179 + return ret; 180 + } 177 181 178 182 platform_set_drvdata(pdev, davinci_wdt); 179 183 ··· 202 198 return PTR_ERR(davinci_wdt->base); 203 199 204 200 ret = watchdog_register_device(wdd); 205 - if (ret < 0) 201 + if (ret < 0) { 202 + clk_disable_unprepare(davinci_wdt->clk); 206 203 dev_err(dev, "cannot register watchdog device\n"); 204 + } 207 205 208 206 return ret; 209 207 }

+11

drivers/watchdog/dw_wdt.c

··· 29 29 #include <linux/of.h> 30 30 #include <linux/pm.h> 31 31 #include <linux/platform_device.h> 32 + #include <linux/reset.h> 32 33 #include <linux/watchdog.h> 33 34 34 35 #define WDOG_CONTROL_REG_OFFSET 0x00 ··· 55 54 struct clk *clk; 56 55 unsigned long rate; 57 56 struct watchdog_device wdd; 57 + struct reset_control *rst; 58 58 }; 59 59 60 60 #define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd) ··· 236 234 goto out_disable_clk; 237 235 } 238 236 237 + dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); 238 + if (IS_ERR(dw_wdt->rst)) { 239 + ret = PTR_ERR(dw_wdt->rst); 240 + goto out_disable_clk; 241 + } 242 + 243 + reset_control_deassert(dw_wdt->rst); 244 + 239 245 wdd = &dw_wdt->wdd; 240 246 wdd->info = &dw_wdt_ident; 241 247 wdd->ops = &dw_wdt_ops; ··· 289 279 struct dw_wdt *dw_wdt = platform_get_drvdata(pdev); 290 280 291 281 watchdog_unregister_device(&dw_wdt->wdd); 282 + reset_control_assert(dw_wdt->rst); 292 283 clk_disable_unprepare(dw_wdt->clk); 293 284 294 285 return 0;

+20 -7

drivers/watchdog/f71808e_wdt.c

··· 57 57 #define SIO_F71808_ID 0x0901 /* Chipset ID */ 58 58 #define SIO_F71858_ID 0x0507 /* Chipset ID */ 59 59 #define SIO_F71862_ID 0x0601 /* Chipset ID */ 60 + #define SIO_F71868_ID 0x1106 /* Chipset ID */ 60 61 #define SIO_F71869_ID 0x0814 /* Chipset ID */ 61 62 #define SIO_F71869A_ID 0x1007 /* Chipset ID */ 62 63 #define SIO_F71882_ID 0x0541 /* Chipset ID */ ··· 102 101 static unsigned int pulse_width = WATCHDOG_PULSE_WIDTH; 103 102 module_param(pulse_width, uint, 0); 104 103 MODULE_PARM_DESC(pulse_width, 105 - "Watchdog signal pulse width. 0(=level), 1 ms, 25 ms, 125 ms or 5000 ms" 104 + "Watchdog signal pulse width. 0(=level), 1, 25, 30, 125, 150, 5000 or 6000 ms" 106 105 " (default=" __MODULE_STRING(WATCHDOG_PULSE_WIDTH) ")"); 107 106 108 107 static unsigned int f71862fg_pin = WATCHDOG_F71862FG_PIN; ··· 120 119 MODULE_PARM_DESC(start_withtimeout, "Start watchdog timer on module load with" 121 120 " given initial timeout. Zero (default) disables this feature."); 122 121 123 - enum chips { f71808fg, f71858fg, f71862fg, f71869, f71882fg, f71889fg, f81865, 124 - f81866}; 122 + enum chips { f71808fg, f71858fg, f71862fg, f71868, f71869, f71882fg, f71889fg, 123 + f81865, f81866}; 125 124 126 125 static const char *f71808e_names[] = { 127 126 "f71808fg", 128 127 "f71858fg", 129 128 "f71862fg", 129 + "f71868", 130 130 "f71869", 131 131 "f71882fg", 132 132 "f71889fg", ··· 254 252 static int watchdog_set_pulse_width(unsigned int pw) 255 253 { 256 254 int err = 0; 255 + unsigned int t1 = 25, t2 = 125, t3 = 5000; 256 + 257 + if (watchdog.type == f71868) { 258 + t1 = 30; 259 + t2 = 150; 260 + t3 = 6000; 261 + } 257 262 258 263 mutex_lock(&watchdog.lock); 259 264 260 - if (pw <= 1) { 265 + if (pw <= 1) { 261 266 watchdog.pulse_val = 0; 262 - } else if (pw <= 25) { 267 + } else if (pw <= t1) { 263 268 watchdog.pulse_val = 1; 264 - } else if (pw <= 125) { 269 + } else if (pw <= t2) { 265 270 watchdog.pulse_val = 2; 266 - } else if (pw <= 5000) { 271 + } else if (pw <= t3) { 267 272 watchdog.pulse_val = 3; 268 273 } else { 269 274 pr_err("pulse width out of range\n"); ··· 363 354 goto exit_superio; 364 355 break; 365 356 357 + case f71868: 366 358 case f71869: 367 359 /* GPIO14 --> WDTRST# */ 368 360 superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT1, 4); ··· 801 791 case SIO_F71862_ID: 802 792 watchdog.type = f71862fg; 803 793 err = f71862fg_pin_configure(0); /* validate module parameter */ 794 + break; 795 + case SIO_F71868_ID: 796 + watchdog.type = f71868; 804 797 break; 805 798 case SIO_F71869_ID: 806 799 case SIO_F71869A_ID:

+13 -60

drivers/watchdog/gpio_wdt.c

··· 18 18 19 19 #define SOFT_TIMEOUT_MIN 1 20 20 #define SOFT_TIMEOUT_DEF 60 21 - #define SOFT_TIMEOUT_MAX 0xffff 22 21 23 22 enum { 24 23 HW_ALGO_TOGGLE, ··· 29 30 bool active_low; 30 31 bool state; 31 32 bool always_running; 32 - bool armed; 33 33 unsigned int hw_algo; 34 - unsigned int hw_margin; 35 - unsigned long last_jiffies; 36 - struct timer_list timer; 37 34 struct watchdog_device wdd; 38 35 }; 39 36 ··· 42 47 gpio_direction_input(priv->gpio); 43 48 } 44 49 45 - static void gpio_wdt_hwping(unsigned long data) 50 + static int gpio_wdt_ping(struct watchdog_device *wdd) 46 51 { 47 - struct watchdog_device *wdd = (struct watchdog_device *)data; 48 52 struct gpio_wdt_priv *priv = watchdog_get_drvdata(wdd); 49 - 50 - if (priv->armed && time_after(jiffies, priv->last_jiffies + 51 - msecs_to_jiffies(wdd->timeout * 1000))) { 52 - dev_crit(wdd->parent, 53 - "Timer expired. System will reboot soon!\n"); 54 - return; 55 - } 56 - 57 - /* Restart timer */ 58 - mod_timer(&priv->timer, jiffies + priv->hw_margin); 59 53 60 54 switch (priv->hw_algo) { 61 55 case HW_ALGO_TOGGLE: ··· 59 75 gpio_set_value_cansleep(priv->gpio, priv->active_low); 60 76 break; 61 77 } 62 - } 63 - 64 - static void gpio_wdt_start_impl(struct gpio_wdt_priv *priv) 65 - { 66 - priv->state = priv->active_low; 67 - gpio_direction_output(priv->gpio, priv->state); 68 - priv->last_jiffies = jiffies; 69 - gpio_wdt_hwping((unsigned long)&priv->wdd); 78 + return 0; 70 79 } 71 80 72 81 static int gpio_wdt_start(struct watchdog_device *wdd) 73 82 { 74 83 struct gpio_wdt_priv *priv = watchdog_get_drvdata(wdd); 75 84 76 - gpio_wdt_start_impl(priv); 77 - priv->armed = true; 85 + priv->state = priv->active_low; 86 + gpio_direction_output(priv->gpio, priv->state); 78 87 79 - return 0; 88 + set_bit(WDOG_HW_RUNNING, &wdd->status); 89 + 90 + return gpio_wdt_ping(wdd); 80 91 } 81 92 82 93 static int gpio_wdt_stop(struct watchdog_device *wdd) 83 94 { 84 95 struct gpio_wdt_priv *priv = watchdog_get_drvdata(wdd); 85 96 86 - priv->armed = false; 87 97 if (!priv->always_running) { 88 - mod_timer(&priv->timer, 0); 89 98 gpio_wdt_disable(priv); 99 + clear_bit(WDOG_HW_RUNNING, &wdd->status); 90 100 } 91 101 92 102 return 0; 93 - } 94 - 95 - static int gpio_wdt_ping(struct watchdog_device *wdd) 96 - { 97 - struct gpio_wdt_priv *priv = watchdog_get_drvdata(wdd); 98 - 99 - priv->last_jiffies = jiffies; 100 - 101 - return 0; 102 - } 103 - 104 - static int gpio_wdt_set_timeout(struct watchdog_device *wdd, unsigned int t) 105 - { 106 - wdd->timeout = t; 107 - 108 - return gpio_wdt_ping(wdd); 109 103 } 110 104 111 105 static const struct watchdog_info gpio_wdt_ident = { ··· 97 135 .start = gpio_wdt_start, 98 136 .stop = gpio_wdt_stop, 99 137 .ping = gpio_wdt_ping, 100 - .set_timeout = gpio_wdt_set_timeout, 101 138 }; 102 139 103 140 static int gpio_wdt_probe(struct platform_device *pdev) ··· 146 185 if (hw_margin < 2 || hw_margin > 65535) 147 186 return -EINVAL; 148 187 149 - /* Use safe value (1/2 of real timeout) */ 150 - priv->hw_margin = msecs_to_jiffies(hw_margin / 2); 151 - 152 188 priv->always_running = of_property_read_bool(pdev->dev.of_node, 153 189 "always-running"); 154 190 ··· 154 196 priv->wdd.info = &gpio_wdt_ident; 155 197 priv->wdd.ops = &gpio_wdt_ops; 156 198 priv->wdd.min_timeout = SOFT_TIMEOUT_MIN; 157 - priv->wdd.max_timeout = SOFT_TIMEOUT_MAX; 199 + priv->wdd.max_hw_heartbeat_ms = hw_margin; 158 200 priv->wdd.parent = &pdev->dev; 159 201 160 202 if (watchdog_init_timeout(&priv->wdd, 0, &pdev->dev) < 0) 161 203 priv->wdd.timeout = SOFT_TIMEOUT_DEF; 162 204 163 - setup_timer(&priv->timer, gpio_wdt_hwping, (unsigned long)&priv->wdd); 164 - 165 205 watchdog_stop_on_reboot(&priv->wdd); 166 206 167 - ret = watchdog_register_device(&priv->wdd); 168 - if (ret) 169 - return ret; 170 - 171 207 if (priv->always_running) 172 - gpio_wdt_start_impl(priv); 208 + gpio_wdt_start(&priv->wdd); 173 209 174 - return 0; 210 + ret = watchdog_register_device(&priv->wdd); 211 + 212 + return ret; 175 213 } 176 214 177 215 static int gpio_wdt_remove(struct platform_device *pdev) 178 216 { 179 217 struct gpio_wdt_priv *priv = platform_get_drvdata(pdev); 180 218 181 - del_timer_sync(&priv->timer); 182 219 watchdog_unregister_device(&priv->wdd); 183 220 184 221 return 0;

+15 -2

drivers/watchdog/intel-mid_wdt.c

··· 147 147 return ret; 148 148 } 149 149 150 - /* Make sure the watchdog is not running */ 151 - wdt_stop(wdt_dev); 150 + /* 151 + * The firmware followed by U-Boot leaves the watchdog running 152 + * with the default threshold which may vary. When we get here 153 + * we should make a decision to prevent any side effects before 154 + * user space daemon will take care of it. The best option, 155 + * taking into consideration that there is no way to read values 156 + * back from hardware, is to enforce watchdog being run with 157 + * deterministic values. 158 + */ 159 + ret = wdt_start(wdt_dev); 160 + if (ret) 161 + return ret; 162 + 163 + /* Make sure the watchdog is serviced */ 164 + set_bit(WDOG_HW_RUNNING, &wdt_dev->status); 152 165 153 166 ret = devm_watchdog_register_device(&pdev->dev, wdt_dev); 154 167 if (ret) {

+77 -511

drivers/watchdog/it87_wdt.c

··· 12 12 * http://www.ite.com.tw/ 13 13 * 14 14 * Support of the watchdog timers, which are available on 15 - * IT8620, IT8702, IT8712, IT8716, IT8718, IT8720, IT8721, IT8726, 16 - * IT8728 and IT8783. 15 + * IT8607, IT8620, IT8622, IT8625, IT8628, IT8655, IT8665, IT8686, 16 + * IT8702, IT8712, IT8716, IT8718, IT8720, IT8721, IT8726, IT8728, 17 + * and IT8783. 17 18 * 18 19 * This program is free software; you can redistribute it and/or 19 20 * modify it under the terms of the GNU General Public License ··· 25 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 26 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 27 26 * GNU General Public License for more details. 28 - * 29 - * You should have received a copy of the GNU General Public License 30 - * along with this program; if not, write to the Free Software 31 - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 32 27 */ 33 28 34 29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 35 30 31 + #include <linux/init.h> 32 + #include <linux/io.h> 33 + #include <linux/kernel.h> 36 34 #include <linux/module.h> 37 35 #include <linux/moduleparam.h> 38 36 #include <linux/types.h> 39 - #include <linux/kernel.h> 40 - #include <linux/fs.h> 41 - #include <linux/miscdevice.h> 42 - #include <linux/init.h> 43 - #include <linux/ioport.h> 44 37 #include <linux/watchdog.h> 45 - #include <linux/notifier.h> 46 - #include <linux/reboot.h> 47 - #include <linux/uaccess.h> 48 - #include <linux/io.h> 49 38 50 - 51 - #define WATCHDOG_VERSION "1.14" 52 39 #define WATCHDOG_NAME "IT87 WDT" 53 - #define DRIVER_VERSION WATCHDOG_NAME " driver, v" WATCHDOG_VERSION "\n" 54 - #define WD_MAGIC 'V' 55 40 56 41 /* Defaults for Module Parameter */ 57 - #define DEFAULT_NOGAMEPORT 0 58 - #define DEFAULT_NOCIR 0 59 - #define DEFAULT_EXCLUSIVE 1 60 42 #define DEFAULT_TIMEOUT 60 61 43 #define DEFAULT_TESTMODE 0 62 44 #define DEFAULT_NOWAYOUT WATCHDOG_NOWAYOUT ··· 50 66 51 67 /* Logical device Numbers LDN */ 52 68 #define GPIO 0x07 53 - #define GAMEPORT 0x09 54 - #define CIR 0x0a 55 69 56 70 /* Configuration Registers and Functions */ 57 71 #define LDNREG 0x07 58 72 #define CHIPID 0x20 59 73 #define CHIPREV 0x22 60 - #define ACTREG 0x30 61 - #define BASEREG 0x60 62 74 63 75 /* Chip Id numbers */ 64 76 #define NO_DEV_ID 0xffff 77 + #define IT8607_ID 0x8607 65 78 #define IT8620_ID 0x8620 79 + #define IT8622_ID 0x8622 80 + #define IT8625_ID 0x8625 81 + #define IT8628_ID 0x8628 82 + #define IT8655_ID 0x8655 83 + #define IT8665_ID 0x8665 84 + #define IT8686_ID 0x8686 66 85 #define IT8702_ID 0x8702 67 86 #define IT8705_ID 0x8705 68 87 #define IT8712_ID 0x8712 ··· 83 96 #define WDTVALLSB 0x73 84 97 #define WDTVALMSB 0x74 85 98 86 - /* GPIO Bits WDTCTRL */ 87 - #define WDT_CIRINT 0x80 88 - #define WDT_MOUSEINT 0x40 89 - #define WDT_KYBINT 0x20 90 - #define WDT_GAMEPORT 0x10 /* not in it8718, it8720, it8721, it8728 */ 91 - #define WDT_FORCE 0x02 92 - #define WDT_ZERO 0x01 93 - 94 99 /* GPIO Bits WDTCFG */ 95 100 #define WDT_TOV1 0x80 96 101 #define WDT_KRST 0x40 ··· 90 111 #define WDT_PWROK 0x10 /* not in it8721 */ 91 112 #define WDT_INT_MASK 0x0f 92 113 93 - /* CIR Configuration Register LDN=0x0a */ 94 - #define CIR_ILS 0x70 114 + static unsigned int max_units, chip_type; 95 115 96 - /* The default Base address is not always available, we use this */ 97 - #define CIR_BASE 0x0208 116 + static unsigned int timeout = DEFAULT_TIMEOUT; 117 + static int testmode = DEFAULT_TESTMODE; 118 + static bool nowayout = DEFAULT_NOWAYOUT; 98 119 99 - /* CIR Controller */ 100 - #define CIR_DR(b) (b) 101 - #define CIR_IER(b) (b + 1) 102 - #define CIR_RCR(b) (b + 2) 103 - #define CIR_TCR1(b) (b + 3) 104 - #define CIR_TCR2(b) (b + 4) 105 - #define CIR_TSR(b) (b + 5) 106 - #define CIR_RSR(b) (b + 6) 107 - #define CIR_BDLR(b) (b + 5) 108 - #define CIR_BDHR(b) (b + 6) 109 - #define CIR_IIR(b) (b + 7) 110 - 111 - /* Default Base address of Game port */ 112 - #define GP_BASE_DEFAULT 0x0201 113 - 114 - /* wdt_status */ 115 - #define WDTS_TIMER_RUN 0 116 - #define WDTS_DEV_OPEN 1 117 - #define WDTS_KEEPALIVE 2 118 - #define WDTS_LOCKED 3 119 - #define WDTS_USE_GP 4 120 - #define WDTS_EXPECTED 5 121 - #define WDTS_USE_CIR 6 122 - 123 - static unsigned int base, gpact, ciract, max_units, chip_type; 124 - static unsigned long wdt_status; 125 - 126 - static int nogameport = DEFAULT_NOGAMEPORT; 127 - static int nocir = DEFAULT_NOCIR; 128 - static int exclusive = DEFAULT_EXCLUSIVE; 129 - static int timeout = DEFAULT_TIMEOUT; 130 - static int testmode = DEFAULT_TESTMODE; 131 - static bool nowayout = DEFAULT_NOWAYOUT; 132 - 133 - module_param(nogameport, int, 0); 134 - MODULE_PARM_DESC(nogameport, "Forbid the activation of game port, default=" 135 - __MODULE_STRING(DEFAULT_NOGAMEPORT)); 136 - module_param(nocir, int, 0); 137 - MODULE_PARM_DESC(nocir, "Forbid the use of Consumer IR interrupts to reset timer, default=" 138 - __MODULE_STRING(DEFAULT_NOCIR)); 139 - module_param(exclusive, int, 0); 140 - MODULE_PARM_DESC(exclusive, "Watchdog exclusive device open, default=" 141 - __MODULE_STRING(DEFAULT_EXCLUSIVE)); 142 120 module_param(timeout, int, 0); 143 121 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds, default=" 144 122 __MODULE_STRING(DEFAULT_TIMEOUT)); ··· 167 231 } 168 232 169 233 /* Internal function, should be called after superio_select(GPIO) */ 170 - static void wdt_update_timeout(void) 234 + static void _wdt_update_timeout(unsigned int t) 171 235 { 172 236 unsigned char cfg = WDT_KRST; 173 - int tm = timeout; 174 237 175 238 if (testmode) 176 239 cfg = 0; 177 240 178 - if (tm <= max_units) 241 + if (t <= max_units) 179 242 cfg |= WDT_TOV1; 180 243 else 181 - tm /= 60; 244 + t /= 60; 182 245 183 246 if (chip_type != IT8721_ID) 184 247 cfg |= WDT_PWROK; 185 248 186 249 superio_outb(cfg, WDTCFG); 187 - superio_outb(tm, WDTVALLSB); 250 + superio_outb(t, WDTVALLSB); 188 251 if (max_units > 255) 189 - superio_outb(tm>>8, WDTVALMSB); 252 + superio_outb(t >> 8, WDTVALMSB); 253 + } 254 + 255 + static int wdt_update_timeout(unsigned int t) 256 + { 257 + int ret; 258 + 259 + ret = superio_enter(); 260 + if (ret) 261 + return ret; 262 + 263 + superio_select(GPIO); 264 + _wdt_update_timeout(t); 265 + superio_exit(); 266 + 267 + return 0; 190 268 } 191 269 192 270 static int wdt_round_time(int t) ··· 212 262 213 263 /* watchdog timer handling */ 214 264 215 - static void wdt_keepalive(void) 265 + static int wdt_start(struct watchdog_device *wdd) 216 266 { 217 - if (test_bit(WDTS_USE_GP, &wdt_status)) 218 - inb(base); 219 - else if (test_bit(WDTS_USE_CIR, &wdt_status)) 220 - /* The timer reloads with around 5 msec delay */ 221 - outb(0x55, CIR_DR(base)); 222 - else { 223 - if (superio_enter()) 224 - return; 225 - 226 - superio_select(GPIO); 227 - wdt_update_timeout(); 228 - superio_exit(); 229 - } 230 - set_bit(WDTS_KEEPALIVE, &wdt_status); 267 + return wdt_update_timeout(wdd->timeout); 231 268 } 232 269 233 - static int wdt_start(void) 270 + static int wdt_stop(struct watchdog_device *wdd) 234 271 { 235 - int ret = superio_enter(); 236 - if (ret) 237 - return ret; 238 - 239 - superio_select(GPIO); 240 - if (test_bit(WDTS_USE_GP, &wdt_status)) 241 - superio_outb(WDT_GAMEPORT, WDTCTRL); 242 - else if (test_bit(WDTS_USE_CIR, &wdt_status)) 243 - superio_outb(WDT_CIRINT, WDTCTRL); 244 - wdt_update_timeout(); 245 - 246 - superio_exit(); 247 - 248 - return 0; 249 - } 250 - 251 - static int wdt_stop(void) 252 - { 253 - int ret = superio_enter(); 254 - if (ret) 255 - return ret; 256 - 257 - superio_select(GPIO); 258 - superio_outb(0x00, WDTCTRL); 259 - superio_outb(WDT_TOV1, WDTCFG); 260 - superio_outb(0x00, WDTVALLSB); 261 - if (max_units > 255) 262 - superio_outb(0x00, WDTVALMSB); 263 - 264 - superio_exit(); 265 - return 0; 272 + return wdt_update_timeout(0); 266 273 } 267 274 268 275 /** ··· 232 325 * Used within WDIOC_SETTIMEOUT watchdog device ioctl. 233 326 */ 234 327 235 - static int wdt_set_timeout(int t) 328 + static int wdt_set_timeout(struct watchdog_device *wdd, unsigned int t) 236 329 { 237 - if (t < 1 || t > max_units * 60) 238 - return -EINVAL; 330 + int ret = 0; 239 331 240 332 if (t > max_units) 241 - timeout = wdt_round_time(t); 242 - else 243 - timeout = t; 333 + t = wdt_round_time(t); 244 334 245 - if (test_bit(WDTS_TIMER_RUN, &wdt_status)) { 246 - int ret = superio_enter(); 247 - if (ret) 248 - return ret; 335 + wdd->timeout = t; 249 336 250 - superio_select(GPIO); 251 - wdt_update_timeout(); 252 - superio_exit(); 253 - } 254 - return 0; 255 - } 337 + if (watchdog_hw_running(wdd)) 338 + ret = wdt_update_timeout(t); 256 339 257 - /** 258 - * wdt_get_status - determines the status supported by watchdog ioctl 259 - * @status: status returned to user space 260 - * 261 - * The status bit of the device does not allow to distinguish 262 - * between a regular system reset and a watchdog forced reset. 263 - * But, in test mode it is useful, so it is supported through 264 - * WDIOC_GETSTATUS watchdog ioctl. Additionally the driver 265 - * reports the keepalive signal and the acception of the magic. 266 - * 267 - * Used within WDIOC_GETSTATUS watchdog device ioctl. 268 - */ 269 - 270 - static int wdt_get_status(int *status) 271 - { 272 - *status = 0; 273 - if (testmode) { 274 - int ret = superio_enter(); 275 - if (ret) 276 - return ret; 277 - 278 - superio_select(GPIO); 279 - if (superio_inb(WDTCTRL) & WDT_ZERO) { 280 - superio_outb(0x00, WDTCTRL); 281 - clear_bit(WDTS_TIMER_RUN, &wdt_status); 282 - *status |= WDIOF_CARDRESET; 283 - } 284 - 285 - superio_exit(); 286 - } 287 - if (test_and_clear_bit(WDTS_KEEPALIVE, &wdt_status)) 288 - *status |= WDIOF_KEEPALIVEPING; 289 - if (test_bit(WDTS_EXPECTED, &wdt_status)) 290 - *status |= WDIOF_MAGICCLOSE; 291 - return 0; 292 - } 293 - 294 - /* /dev/watchdog handling */ 295 - 296 - /** 297 - * wdt_open - watchdog file_operations .open 298 - * @inode: inode of the device 299 - * @file: file handle to the device 300 - * 301 - * The watchdog timer starts by opening the device. 302 - * 303 - * Used within the file operation of the watchdog device. 304 - */ 305 - 306 - static int wdt_open(struct inode *inode, struct file *file) 307 - { 308 - if (exclusive && test_and_set_bit(WDTS_DEV_OPEN, &wdt_status)) 309 - return -EBUSY; 310 - if (!test_and_set_bit(WDTS_TIMER_RUN, &wdt_status)) { 311 - int ret; 312 - if (nowayout && !test_and_set_bit(WDTS_LOCKED, &wdt_status)) 313 - __module_get(THIS_MODULE); 314 - 315 - ret = wdt_start(); 316 - if (ret) { 317 - clear_bit(WDTS_LOCKED, &wdt_status); 318 - clear_bit(WDTS_TIMER_RUN, &wdt_status); 319 - clear_bit(WDTS_DEV_OPEN, &wdt_status); 320 - return ret; 321 - } 322 - } 323 - return nonseekable_open(inode, file); 324 - } 325 - 326 - /** 327 - * wdt_release - watchdog file_operations .release 328 - * @inode: inode of the device 329 - * @file: file handle to the device 330 - * 331 - * Closing the watchdog device either stops the watchdog timer 332 - * or in the case, that nowayout is set or the magic character 333 - * wasn't written, a critical warning about an running watchdog 334 - * timer is given. 335 - * 336 - * Used within the file operation of the watchdog device. 337 - */ 338 - 339 - static int wdt_release(struct inode *inode, struct file *file) 340 - { 341 - if (test_bit(WDTS_TIMER_RUN, &wdt_status)) { 342 - if (test_and_clear_bit(WDTS_EXPECTED, &wdt_status)) { 343 - int ret = wdt_stop(); 344 - if (ret) { 345 - /* 346 - * Stop failed. Just keep the watchdog alive 347 - * and hope nothing bad happens. 348 - */ 349 - set_bit(WDTS_EXPECTED, &wdt_status); 350 - wdt_keepalive(); 351 - return ret; 352 - } 353 - clear_bit(WDTS_TIMER_RUN, &wdt_status); 354 - } else { 355 - wdt_keepalive(); 356 - pr_crit("unexpected close, not stopping watchdog!\n"); 357 - } 358 - } 359 - clear_bit(WDTS_DEV_OPEN, &wdt_status); 360 - return 0; 361 - } 362 - 363 - /** 364 - * wdt_write - watchdog file_operations .write 365 - * @file: file handle to the watchdog 366 - * @buf: buffer to write 367 - * @count: count of bytes 368 - * @ppos: pointer to the position to write. No seeks allowed 369 - * 370 - * A write to a watchdog device is defined as a keepalive signal. Any 371 - * write of data will do, as we don't define content meaning. 372 - * 373 - * Used within the file operation of the watchdog device. 374 - */ 375 - 376 - static ssize_t wdt_write(struct file *file, const char __user *buf, 377 - size_t count, loff_t *ppos) 378 - { 379 - if (count) { 380 - clear_bit(WDTS_EXPECTED, &wdt_status); 381 - wdt_keepalive(); 382 - } 383 - if (!nowayout) { 384 - size_t ofs; 385 - 386 - /* note: just in case someone wrote the magic character long ago */ 387 - for (ofs = 0; ofs != count; ofs++) { 388 - char c; 389 - if (get_user(c, buf + ofs)) 390 - return -EFAULT; 391 - if (c == WD_MAGIC) 392 - set_bit(WDTS_EXPECTED, &wdt_status); 393 - } 394 - } 395 - return count; 340 + return ret; 396 341 } 397 342 398 343 static const struct watchdog_info ident = { 399 344 .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, 400 - .firmware_version = 1, 345 + .firmware_version = 1, 401 346 .identity = WATCHDOG_NAME, 402 347 }; 403 348 404 - /** 405 - * wdt_ioctl - watchdog file_operations .unlocked_ioctl 406 - * @file: file handle to the device 407 - * @cmd: watchdog command 408 - * @arg: argument pointer 409 - * 410 - * The watchdog API defines a common set of functions for all watchdogs 411 - * according to their available features. 412 - * 413 - * Used within the file operation of the watchdog device. 414 - */ 415 - 416 - static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 417 - { 418 - int rc = 0, status, new_options, new_timeout; 419 - union { 420 - struct watchdog_info __user *ident; 421 - int __user *i; 422 - } uarg; 423 - 424 - uarg.i = (int __user *)arg; 425 - 426 - switch (cmd) { 427 - case WDIOC_GETSUPPORT: 428 - return copy_to_user(uarg.ident, 429 - &ident, sizeof(ident)) ? -EFAULT : 0; 430 - 431 - case WDIOC_GETSTATUS: 432 - rc = wdt_get_status(&status); 433 - if (rc) 434 - return rc; 435 - return put_user(status, uarg.i); 436 - 437 - case WDIOC_GETBOOTSTATUS: 438 - return put_user(0, uarg.i); 439 - 440 - case WDIOC_KEEPALIVE: 441 - wdt_keepalive(); 442 - return 0; 443 - 444 - case WDIOC_SETOPTIONS: 445 - if (get_user(new_options, uarg.i)) 446 - return -EFAULT; 447 - 448 - switch (new_options) { 449 - case WDIOS_DISABLECARD: 450 - if (test_bit(WDTS_TIMER_RUN, &wdt_status)) { 451 - rc = wdt_stop(); 452 - if (rc) 453 - return rc; 454 - } 455 - clear_bit(WDTS_TIMER_RUN, &wdt_status); 456 - return 0; 457 - 458 - case WDIOS_ENABLECARD: 459 - if (!test_and_set_bit(WDTS_TIMER_RUN, &wdt_status)) { 460 - rc = wdt_start(); 461 - if (rc) { 462 - clear_bit(WDTS_TIMER_RUN, &wdt_status); 463 - return rc; 464 - } 465 - } 466 - return 0; 467 - 468 - default: 469 - return -EFAULT; 470 - } 471 - 472 - case WDIOC_SETTIMEOUT: 473 - if (get_user(new_timeout, uarg.i)) 474 - return -EFAULT; 475 - rc = wdt_set_timeout(new_timeout); 476 - case WDIOC_GETTIMEOUT: 477 - if (put_user(timeout, uarg.i)) 478 - return -EFAULT; 479 - return rc; 480 - 481 - default: 482 - return -ENOTTY; 483 - } 484 - } 485 - 486 - static int wdt_notify_sys(struct notifier_block *this, unsigned long code, 487 - void *unused) 488 - { 489 - if (code == SYS_DOWN || code == SYS_HALT) 490 - wdt_stop(); 491 - return NOTIFY_DONE; 492 - } 493 - 494 - static const struct file_operations wdt_fops = { 495 - .owner = THIS_MODULE, 496 - .llseek = no_llseek, 497 - .write = wdt_write, 498 - .unlocked_ioctl = wdt_ioctl, 499 - .open = wdt_open, 500 - .release = wdt_release, 349 + static struct watchdog_ops wdt_ops = { 350 + .owner = THIS_MODULE, 351 + .start = wdt_start, 352 + .stop = wdt_stop, 353 + .set_timeout = wdt_set_timeout, 501 354 }; 502 355 503 - static struct miscdevice wdt_miscdev = { 504 - .minor = WATCHDOG_MINOR, 505 - .name = "watchdog", 506 - .fops = &wdt_fops, 507 - }; 508 - 509 - static struct notifier_block wdt_notifier = { 510 - .notifier_call = wdt_notify_sys, 356 + static struct watchdog_device wdt_dev = { 357 + .info = &ident, 358 + .ops = &wdt_ops, 359 + .min_timeout = 1, 511 360 }; 512 361 513 362 static int __init it87_wdt_init(void) 514 363 { 515 - int rc = 0; 516 - int try_gameport = !nogameport; 517 364 u8 chip_rev; 518 - int gp_rreq_fail = 0; 519 - 520 - wdt_status = 0; 365 + int rc; 521 366 522 367 rc = superio_enter(); 523 368 if (rc) ··· 290 631 case IT8726_ID: 291 632 max_units = 65535; 292 633 break; 634 + case IT8607_ID: 293 635 case IT8620_ID: 636 + case IT8622_ID: 637 + case IT8625_ID: 638 + case IT8628_ID: 639 + case IT8655_ID: 640 + case IT8665_ID: 641 + case IT8686_ID: 294 642 case IT8718_ID: 295 643 case IT8720_ID: 296 644 case IT8721_ID: 297 645 case IT8728_ID: 298 646 case IT8783_ID: 299 647 max_units = 65535; 300 - try_gameport = 0; 301 648 break; 302 649 case IT8705_ID: 303 650 pr_err("Unsupported Chip found, Chip %04x Revision %02x\n", ··· 325 660 superio_select(GPIO); 326 661 superio_outb(WDT_TOV1, WDTCFG); 327 662 superio_outb(0x00, WDTCTRL); 328 - 329 - /* First try to get Gameport support */ 330 - if (try_gameport) { 331 - superio_select(GAMEPORT); 332 - base = superio_inw(BASEREG); 333 - if (!base) { 334 - base = GP_BASE_DEFAULT; 335 - superio_outw(base, BASEREG); 336 - } 337 - gpact = superio_inb(ACTREG); 338 - superio_outb(0x01, ACTREG); 339 - if (request_region(base, 1, WATCHDOG_NAME)) 340 - set_bit(WDTS_USE_GP, &wdt_status); 341 - else 342 - gp_rreq_fail = 1; 343 - } 344 - 345 - /* If we haven't Gameport support, try to get CIR support */ 346 - if (!nocir && !test_bit(WDTS_USE_GP, &wdt_status)) { 347 - if (!request_region(CIR_BASE, 8, WATCHDOG_NAME)) { 348 - if (gp_rreq_fail) 349 - pr_err("I/O Address 0x%04x and 0x%04x already in use\n", 350 - base, CIR_BASE); 351 - else 352 - pr_err("I/O Address 0x%04x already in use\n", 353 - CIR_BASE); 354 - rc = -EIO; 355 - goto err_out; 356 - } 357 - base = CIR_BASE; 358 - 359 - superio_select(CIR); 360 - superio_outw(base, BASEREG); 361 - superio_outb(0x00, CIR_ILS); 362 - ciract = superio_inb(ACTREG); 363 - superio_outb(0x01, ACTREG); 364 - if (gp_rreq_fail) { 365 - superio_select(GAMEPORT); 366 - superio_outb(gpact, ACTREG); 367 - } 368 - set_bit(WDTS_USE_CIR, &wdt_status); 369 - } 663 + superio_exit(); 370 664 371 665 if (timeout < 1 || timeout > max_units * 60) { 372 666 timeout = DEFAULT_TIMEOUT; ··· 336 712 if (timeout > max_units) 337 713 timeout = wdt_round_time(timeout); 338 714 339 - rc = register_reboot_notifier(&wdt_notifier); 715 + wdt_dev.timeout = timeout; 716 + wdt_dev.max_timeout = max_units * 60; 717 + 718 + watchdog_stop_on_reboot(&wdt_dev); 719 + rc = watchdog_register_device(&wdt_dev); 340 720 if (rc) { 341 - pr_err("Cannot register reboot notifier (err=%d)\n", rc); 342 - goto err_out_region; 721 + pr_err("Cannot register watchdog device (err=%d)\n", rc); 722 + return rc; 343 723 } 344 724 345 - rc = misc_register(&wdt_miscdev); 346 - if (rc) { 347 - pr_err("Cannot register miscdev on minor=%d (err=%d)\n", 348 - wdt_miscdev.minor, rc); 349 - goto err_out_reboot; 350 - } 725 + pr_info("Chip IT%04x revision %d initialized. timeout=%d sec (nowayout=%d testmode=%d)\n", 726 + chip_type, chip_rev, timeout, nowayout, testmode); 351 727 352 - /* Initialize CIR to use it as keepalive source */ 353 - if (test_bit(WDTS_USE_CIR, &wdt_status)) { 354 - outb(0x00, CIR_RCR(base)); 355 - outb(0xc0, CIR_TCR1(base)); 356 - outb(0x5c, CIR_TCR2(base)); 357 - outb(0x10, CIR_IER(base)); 358 - outb(0x00, CIR_BDHR(base)); 359 - outb(0x01, CIR_BDLR(base)); 360 - outb(0x09, CIR_IER(base)); 361 - } 362 - 363 - pr_info("Chip IT%04x revision %d initialized. timeout=%d sec (nowayout=%d testmode=%d exclusive=%d nogameport=%d nocir=%d)\n", 364 - chip_type, chip_rev, timeout, 365 - nowayout, testmode, exclusive, nogameport, nocir); 366 - 367 - superio_exit(); 368 728 return 0; 369 - 370 - err_out_reboot: 371 - unregister_reboot_notifier(&wdt_notifier); 372 - err_out_region: 373 - if (test_bit(WDTS_USE_GP, &wdt_status)) 374 - release_region(base, 1); 375 - else if (test_bit(WDTS_USE_CIR, &wdt_status)) { 376 - release_region(base, 8); 377 - superio_select(CIR); 378 - superio_outb(ciract, ACTREG); 379 - } 380 - err_out: 381 - if (try_gameport) { 382 - superio_select(GAMEPORT); 383 - superio_outb(gpact, ACTREG); 384 - } 385 - 386 - superio_exit(); 387 - return rc; 388 729 } 389 730 390 731 static void __exit it87_wdt_exit(void) 391 732 { 392 - if (superio_enter() == 0) { 393 - superio_select(GPIO); 394 - superio_outb(0x00, WDTCTRL); 395 - superio_outb(0x00, WDTCFG); 396 - superio_outb(0x00, WDTVALLSB); 397 - if (max_units > 255) 398 - superio_outb(0x00, WDTVALMSB); 399 - if (test_bit(WDTS_USE_GP, &wdt_status)) { 400 - superio_select(GAMEPORT); 401 - superio_outb(gpact, ACTREG); 402 - } else if (test_bit(WDTS_USE_CIR, &wdt_status)) { 403 - superio_select(CIR); 404 - superio_outb(ciract, ACTREG); 405 - } 406 - superio_exit(); 407 - } 408 - 409 - misc_deregister(&wdt_miscdev); 410 - unregister_reboot_notifier(&wdt_notifier); 411 - 412 - if (test_bit(WDTS_USE_GP, &wdt_status)) 413 - release_region(base, 1); 414 - else if (test_bit(WDTS_USE_CIR, &wdt_status)) 415 - release_region(base, 8); 733 + watchdog_unregister_device(&wdt_dev); 416 734 } 417 735 418 736 module_init(it87_wdt_init);

+3 -1

drivers/watchdog/meson_gxbb_wdt.c

··· 203 203 if (IS_ERR(data->clk)) 204 204 return PTR_ERR(data->clk); 205 205 206 - clk_prepare_enable(data->clk); 206 + ret = clk_prepare_enable(data->clk); 207 + if (ret) 208 + return ret; 207 209 208 210 platform_set_drvdata(pdev, data); 209 211

+1 -1

drivers/watchdog/orion_wdt.c

··· 651 651 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" 652 652 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 653 653 654 - MODULE_LICENSE("GPL"); 654 + MODULE_LICENSE("GPL v2"); 655 655 MODULE_ALIAS("platform:orion_wdt");

+199

drivers/watchdog/rza_wdt.c

··· 1 + /* 2 + * Renesas RZ/A Series WDT Driver 3 + * 4 + * Copyright (C) 2017 Renesas Electronics America, Inc. 5 + * Copyright (C) 2017 Chris Brandt 6 + * 7 + * This file is subject to the terms and conditions of the GNU General Public 8 + * License. See the file "COPYING" in the main directory of this archive 9 + * for more details. 10 + */ 11 + 12 + #include <linux/bitops.h> 13 + #include <linux/clk.h> 14 + #include <linux/delay.h> 15 + #include <linux/module.h> 16 + #include <linux/of_address.h> 17 + #include <linux/platform_device.h> 18 + #include <linux/watchdog.h> 19 + 20 + #define DEFAULT_TIMEOUT 30 21 + 22 + /* Watchdog Timer Registers */ 23 + #define WTCSR 0 24 + #define WTCSR_MAGIC 0xA500 25 + #define WTSCR_WT BIT(6) 26 + #define WTSCR_TME BIT(5) 27 + #define WTSCR_CKS(i) (i) 28 + 29 + #define WTCNT 2 30 + #define WTCNT_MAGIC 0x5A00 31 + 32 + #define WRCSR 4 33 + #define WRCSR_MAGIC 0x5A00 34 + #define WRCSR_RSTE BIT(6) 35 + #define WRCSR_CLEAR_WOVF 0xA500 /* special value */ 36 + 37 + struct rza_wdt { 38 + struct watchdog_device wdev; 39 + void __iomem *base; 40 + struct clk *clk; 41 + }; 42 + 43 + static int rza_wdt_start(struct watchdog_device *wdev) 44 + { 45 + struct rza_wdt *priv = watchdog_get_drvdata(wdev); 46 + 47 + /* Stop timer */ 48 + writew(WTCSR_MAGIC | 0, priv->base + WTCSR); 49 + 50 + /* Must dummy read WRCSR:WOVF at least once before clearing */ 51 + readb(priv->base + WRCSR); 52 + writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR); 53 + 54 + /* 55 + * Start timer with slowest clock source and reset option enabled. 56 + */ 57 + writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR); 58 + writew(WTCNT_MAGIC | 0, priv->base + WTCNT); 59 + writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME | WTSCR_CKS(7), 60 + priv->base + WTCSR); 61 + 62 + return 0; 63 + } 64 + 65 + static int rza_wdt_stop(struct watchdog_device *wdev) 66 + { 67 + struct rza_wdt *priv = watchdog_get_drvdata(wdev); 68 + 69 + writew(WTCSR_MAGIC | 0, priv->base + WTCSR); 70 + 71 + return 0; 72 + } 73 + 74 + static int rza_wdt_ping(struct watchdog_device *wdev) 75 + { 76 + struct rza_wdt *priv = watchdog_get_drvdata(wdev); 77 + 78 + writew(WTCNT_MAGIC | 0, priv->base + WTCNT); 79 + 80 + return 0; 81 + } 82 + 83 + static int rza_wdt_restart(struct watchdog_device *wdev, unsigned long action, 84 + void *data) 85 + { 86 + struct rza_wdt *priv = watchdog_get_drvdata(wdev); 87 + 88 + /* Stop timer */ 89 + writew(WTCSR_MAGIC | 0, priv->base + WTCSR); 90 + 91 + /* Must dummy read WRCSR:WOVF at least once before clearing */ 92 + readb(priv->base + WRCSR); 93 + writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR); 94 + 95 + /* 96 + * Start timer with fastest clock source and only 1 clock left before 97 + * overflow with reset option enabled. 98 + */ 99 + writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR); 100 + writew(WTCNT_MAGIC | 255, priv->base + WTCNT); 101 + writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME, priv->base + WTCSR); 102 + 103 + /* 104 + * Actually make sure the above sequence hits hardware before sleeping. 105 + */ 106 + wmb(); 107 + 108 + /* Wait for WDT overflow (reset) */ 109 + udelay(20); 110 + 111 + return 0; 112 + } 113 + 114 + static const struct watchdog_info rza_wdt_ident = { 115 + .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, 116 + .identity = "Renesas RZ/A WDT Watchdog", 117 + }; 118 + 119 + static const struct watchdog_ops rza_wdt_ops = { 120 + .owner = THIS_MODULE, 121 + .start = rza_wdt_start, 122 + .stop = rza_wdt_stop, 123 + .ping = rza_wdt_ping, 124 + .restart = rza_wdt_restart, 125 + }; 126 + 127 + static int rza_wdt_probe(struct platform_device *pdev) 128 + { 129 + struct rza_wdt *priv; 130 + struct resource *res; 131 + unsigned long rate; 132 + int ret; 133 + 134 + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 135 + if (!priv) 136 + return -ENOMEM; 137 + 138 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 139 + priv->base = devm_ioremap_resource(&pdev->dev, res); 140 + if (IS_ERR(priv->base)) 141 + return PTR_ERR(priv->base); 142 + 143 + priv->clk = devm_clk_get(&pdev->dev, NULL); 144 + if (IS_ERR(priv->clk)) 145 + return PTR_ERR(priv->clk); 146 + 147 + rate = clk_get_rate(priv->clk); 148 + if (rate < 16384) { 149 + dev_err(&pdev->dev, "invalid clock rate (%ld)\n", rate); 150 + return -ENOENT; 151 + } 152 + 153 + /* Assume slowest clock rate possible (CKS=7) */ 154 + rate /= 16384; 155 + 156 + priv->wdev.info = &rza_wdt_ident, 157 + priv->wdev.ops = &rza_wdt_ops, 158 + priv->wdev.parent = &pdev->dev; 159 + 160 + /* 161 + * Since the max possible timeout of our 8-bit count register is less 162 + * than a second, we must use max_hw_heartbeat_ms. 163 + */ 164 + priv->wdev.max_hw_heartbeat_ms = (1000 * U8_MAX) / rate; 165 + dev_dbg(&pdev->dev, "max hw timeout of %dms\n", 166 + priv->wdev.max_hw_heartbeat_ms); 167 + 168 + priv->wdev.min_timeout = 1; 169 + priv->wdev.timeout = DEFAULT_TIMEOUT; 170 + 171 + watchdog_init_timeout(&priv->wdev, 0, &pdev->dev); 172 + watchdog_set_drvdata(&priv->wdev, priv); 173 + 174 + ret = devm_watchdog_register_device(&pdev->dev, &priv->wdev); 175 + if (ret) 176 + dev_err(&pdev->dev, "Cannot register watchdog device\n"); 177 + 178 + return ret; 179 + } 180 + 181 + static const struct of_device_id rza_wdt_of_match[] = { 182 + { .compatible = "renesas,rza-wdt", }, 183 + { /* sentinel */ } 184 + }; 185 + MODULE_DEVICE_TABLE(of, rza_wdt_of_match); 186 + 187 + static struct platform_driver rza_wdt_driver = { 188 + .probe = rza_wdt_probe, 189 + .driver = { 190 + .name = "rza_wdt", 191 + .of_match_table = rza_wdt_of_match, 192 + }, 193 + }; 194 + 195 + module_platform_driver(rza_wdt_driver); 196 + 197 + MODULE_DESCRIPTION("Renesas RZ/A WDT Driver"); 198 + MODULE_AUTHOR("Chris Brandt <chris.brandt@renesas.com>"); 199 + MODULE_LICENSE("GPL v2");

+26 -32

drivers/watchdog/s3c2410_wdt.c

··· 1 - /* linux/drivers/char/watchdog/s3c2410_wdt.c 2 - * 1 + /* 3 2 * Copyright (c) 2004 Simtec Electronics 4 3 * Ben Dooks <ben@simtec.co.uk> 5 4 * ··· 16 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 19 * GNU General Public License for more details. 19 - * 20 - * You should have received a copy of the GNU General Public License 21 - * along with this program; if not, write to the Free Software 22 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 - */ 20 + */ 24 21 25 22 #include <linux/module.h> 26 23 #include <linux/moduleparam.h> ··· 32 37 #include <linux/slab.h> 33 38 #include <linux/err.h> 34 39 #include <linux/of.h> 40 + #include <linux/of_device.h> 35 41 #include <linux/mfd/syscon.h> 36 42 #include <linux/regmap.h> 37 43 #include <linux/delay.h> ··· 90 94 __MODULE_STRING(S3C2410_WATCHDOG_ATBOOT)); 91 95 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" 92 96 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 93 - MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, " 94 - "0 to reboot (default 0)"); 97 + MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default 0)"); 95 98 96 99 /** 97 100 * struct s3c2410_wdt_variant - Per-variant config data ··· 126 131 unsigned long wtdat_save; 127 132 struct watchdog_device wdt_device; 128 133 struct notifier_block freq_transition; 129 - struct s3c2410_wdt_variant *drv_data; 134 + const struct s3c2410_wdt_variant *drv_data; 130 135 struct regmap *pmureg; 131 136 }; 132 137 ··· 305 310 return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE; 306 311 } 307 312 308 - static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout) 313 + static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, 314 + unsigned int timeout) 309 315 { 310 316 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); 311 317 unsigned long freq = clk_get_rate(wdt->clock); ··· 397 401 .restart = s3c2410wdt_restart, 398 402 }; 399 403 400 - static struct watchdog_device s3c2410_wdd = { 404 + static const struct watchdog_device s3c2410_wdd = { 401 405 .info = &s3c2410_wdt_ident, 402 406 .ops = &s3c2410wdt_ops, 403 407 .timeout = S3C2410_WATCHDOG_DEFAULT_TIME, ··· 503 507 return 0; 504 508 } 505 509 506 - static inline struct s3c2410_wdt_variant * 510 + static inline const struct s3c2410_wdt_variant * 507 511 s3c2410_get_wdt_drv_data(struct platform_device *pdev) 508 512 { 509 - if (pdev->dev.of_node) { 510 - const struct of_device_id *match; 511 - match = of_match_node(s3c2410_wdt_match, pdev->dev.of_node); 512 - return (struct s3c2410_wdt_variant *)match->data; 513 - } else { 514 - return (struct s3c2410_wdt_variant *) 515 - platform_get_device_id(pdev)->driver_data; 513 + const struct s3c2410_wdt_variant *variant; 514 + 515 + variant = of_device_get_match_data(&pdev->dev); 516 + if (!variant) { 517 + /* Device matched by platform_device_id */ 518 + variant = (struct s3c2410_wdt_variant *) 519 + platform_get_device_id(pdev)->driver_data; 516 520 } 521 + 522 + return variant; 517 523 } 518 524 519 525 static int s3c2410wdt_probe(struct platform_device *pdev) 520 526 { 521 - struct device *dev; 527 + struct device *dev = &pdev->dev; 522 528 struct s3c2410_wdt *wdt; 523 529 struct resource *wdt_mem; 524 530 struct resource *wdt_irq; ··· 528 530 int started = 0; 529 531 int ret; 530 532 531 - dev = &pdev->dev; 532 - 533 533 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); 534 534 if (!wdt) 535 535 return -ENOMEM; 536 536 537 - wdt->dev = &pdev->dev; 537 + wdt->dev = dev; 538 538 spin_lock_init(&wdt->lock); 539 539 wdt->wdt_device = s3c2410_wdd; 540 540 ··· 588 592 /* see if we can actually set the requested timer margin, and if 589 593 * not, try the default value */ 590 594 591 - watchdog_init_timeout(&wdt->wdt_device, tmr_margin, &pdev->dev); 595 + watchdog_init_timeout(&wdt->wdt_device, tmr_margin, dev); 592 596 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, 593 597 wdt->wdt_device.timeout); 594 598 if (ret) { ··· 597 601 598 602 if (started == 0) 599 603 dev_info(dev, 600 - "tmr_margin value out of range, default %d used\n", 601 - S3C2410_WATCHDOG_DEFAULT_TIME); 604 + "tmr_margin value out of range, default %d used\n", 605 + S3C2410_WATCHDOG_DEFAULT_TIME); 602 606 else 603 - dev_info(dev, "default timer value is out of range, " 604 - "cannot start\n"); 607 + dev_info(dev, "default timer value is out of range, cannot start\n"); 605 608 } 606 609 607 610 ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0, ··· 614 619 watchdog_set_restart_priority(&wdt->wdt_device, 128); 615 620 616 621 wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); 617 - wdt->wdt_device.parent = &pdev->dev; 622 + wdt->wdt_device.parent = dev; 618 623 619 624 ret = watchdog_register_device(&wdt->wdt_device); 620 625 if (ret) { ··· 749 754 750 755 module_platform_driver(s3c2410wdt_driver); 751 756 752 - MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, " 753 - "Dimitry Andric <dimitry.andric@tomtom.com>"); 757 + MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Dimitry Andric <dimitry.andric@tomtom.com>"); 754 758 MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver"); 755 759 MODULE_LICENSE("GPL");

+11 -8

drivers/watchdog/sama5d4_wdt.c

··· 228 228 229 229 wdt->reg_base = regs; 230 230 231 - if (pdev->dev.of_node) { 232 - irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 233 - if (!irq) 234 - dev_warn(&pdev->dev, "failed to get IRQ from DT\n"); 231 + irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 232 + if (!irq) 233 + dev_warn(&pdev->dev, "failed to get IRQ from DT\n"); 235 234 236 - ret = of_sama5d4_wdt_init(pdev->dev.of_node, wdt); 237 - if (ret) 238 - return ret; 239 - } 235 + ret = of_sama5d4_wdt_init(pdev->dev.of_node, wdt); 236 + if (ret) 237 + return ret; 240 238 241 239 if ((wdt->mr & AT91_WDT_WDFIEN) && irq) { 242 240 ret = devm_request_irq(&pdev->dev, irq, sama5d4_wdt_irq_handler, ··· 300 302 { 301 303 struct sama5d4_wdt *wdt = dev_get_drvdata(dev); 302 304 305 + /* 306 + * FIXME: writing MR also pings the watchdog which may not be desired. 307 + * This should only be done when the registers are lost on suspend but 308 + * there is no way to get this information right now. 309 + */ 303 310 sama5d4_wdt_init(wdt); 304 311 305 312 return 0;

+253

drivers/watchdog/stm32_iwdg.c

··· 1 + /* 2 + * Driver for STM32 Independent Watchdog 3 + * 4 + * Copyright (C) Yannick Fertre 2017 5 + * Author: Yannick Fertre <yannick.fertre@st.com> 6 + * 7 + * This driver is based on tegra_wdt.c 8 + * 9 + * License terms: GNU General Public License (GPL), version 2 10 + */ 11 + 12 + #include <linux/clk.h> 13 + #include <linux/delay.h> 14 + #include <linux/kernel.h> 15 + #include <linux/module.h> 16 + #include <linux/interrupt.h> 17 + #include <linux/io.h> 18 + #include <linux/iopoll.h> 19 + #include <linux/of.h> 20 + #include <linux/platform_device.h> 21 + #include <linux/watchdog.h> 22 + 23 + /* IWDG registers */ 24 + #define IWDG_KR 0x00 /* Key register */ 25 + #define IWDG_PR 0x04 /* Prescaler Register */ 26 + #define IWDG_RLR 0x08 /* ReLoad Register */ 27 + #define IWDG_SR 0x0C /* Status Register */ 28 + #define IWDG_WINR 0x10 /* Windows Register */ 29 + 30 + /* IWDG_KR register bit mask */ 31 + #define KR_KEY_RELOAD 0xAAAA /* reload counter enable */ 32 + #define KR_KEY_ENABLE 0xCCCC /* peripheral enable */ 33 + #define KR_KEY_EWA 0x5555 /* write access enable */ 34 + #define KR_KEY_DWA 0x0000 /* write access disable */ 35 + 36 + /* IWDG_PR register bit values */ 37 + #define PR_4 0x00 /* prescaler set to 4 */ 38 + #define PR_8 0x01 /* prescaler set to 8 */ 39 + #define PR_16 0x02 /* prescaler set to 16 */ 40 + #define PR_32 0x03 /* prescaler set to 32 */ 41 + #define PR_64 0x04 /* prescaler set to 64 */ 42 + #define PR_128 0x05 /* prescaler set to 128 */ 43 + #define PR_256 0x06 /* prescaler set to 256 */ 44 + 45 + /* IWDG_RLR register values */ 46 + #define RLR_MIN 0x07C /* min value supported by reload register */ 47 + #define RLR_MAX 0xFFF /* max value supported by reload register */ 48 + 49 + /* IWDG_SR register bit mask */ 50 + #define FLAG_PVU BIT(0) /* Watchdog prescaler value update */ 51 + #define FLAG_RVU BIT(1) /* Watchdog counter reload value update */ 52 + 53 + /* set timeout to 100000 us */ 54 + #define TIMEOUT_US 100000 55 + #define SLEEP_US 1000 56 + 57 + struct stm32_iwdg { 58 + struct watchdog_device wdd; 59 + void __iomem *regs; 60 + struct clk *clk; 61 + unsigned int rate; 62 + }; 63 + 64 + static inline u32 reg_read(void __iomem *base, u32 reg) 65 + { 66 + return readl_relaxed(base + reg); 67 + } 68 + 69 + static inline void reg_write(void __iomem *base, u32 reg, u32 val) 70 + { 71 + writel_relaxed(val, base + reg); 72 + } 73 + 74 + static int stm32_iwdg_start(struct watchdog_device *wdd) 75 + { 76 + struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd); 77 + u32 val = FLAG_PVU | FLAG_RVU; 78 + u32 reload; 79 + int ret; 80 + 81 + dev_dbg(wdd->parent, "%s\n", __func__); 82 + 83 + /* prescaler fixed to 256 */ 84 + reload = clamp_t(unsigned int, ((wdd->timeout * wdt->rate) / 256) - 1, 85 + RLR_MIN, RLR_MAX); 86 + 87 + /* enable write access */ 88 + reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA); 89 + 90 + /* set prescaler & reload registers */ 91 + reg_write(wdt->regs, IWDG_PR, PR_256); /* prescaler fix to 256 */ 92 + reg_write(wdt->regs, IWDG_RLR, reload); 93 + reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE); 94 + 95 + /* wait for the registers to be updated (max 100ms) */ 96 + ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, val, 97 + !(val & (FLAG_PVU | FLAG_RVU)), 98 + SLEEP_US, TIMEOUT_US); 99 + if (ret) { 100 + dev_err(wdd->parent, 101 + "Fail to set prescaler or reload registers\n"); 102 + return ret; 103 + } 104 + 105 + /* reload watchdog */ 106 + reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD); 107 + 108 + return 0; 109 + } 110 + 111 + static int stm32_iwdg_ping(struct watchdog_device *wdd) 112 + { 113 + struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd); 114 + 115 + dev_dbg(wdd->parent, "%s\n", __func__); 116 + 117 + /* reload watchdog */ 118 + reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD); 119 + 120 + return 0; 121 + } 122 + 123 + static int stm32_iwdg_set_timeout(struct watchdog_device *wdd, 124 + unsigned int timeout) 125 + { 126 + dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout); 127 + 128 + wdd->timeout = timeout; 129 + 130 + if (watchdog_active(wdd)) 131 + return stm32_iwdg_start(wdd); 132 + 133 + return 0; 134 + } 135 + 136 + static const struct watchdog_info stm32_iwdg_info = { 137 + .options = WDIOF_SETTIMEOUT | 138 + WDIOF_MAGICCLOSE | 139 + WDIOF_KEEPALIVEPING, 140 + .identity = "STM32 Independent Watchdog", 141 + }; 142 + 143 + static struct watchdog_ops stm32_iwdg_ops = { 144 + .owner = THIS_MODULE, 145 + .start = stm32_iwdg_start, 146 + .ping = stm32_iwdg_ping, 147 + .set_timeout = stm32_iwdg_set_timeout, 148 + }; 149 + 150 + static int stm32_iwdg_probe(struct platform_device *pdev) 151 + { 152 + struct watchdog_device *wdd; 153 + struct stm32_iwdg *wdt; 154 + struct resource *res; 155 + void __iomem *regs; 156 + struct clk *clk; 157 + int ret; 158 + 159 + /* This is the timer base. */ 160 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 161 + regs = devm_ioremap_resource(&pdev->dev, res); 162 + if (IS_ERR(regs)) { 163 + dev_err(&pdev->dev, "Could not get resource\n"); 164 + return PTR_ERR(regs); 165 + } 166 + 167 + clk = devm_clk_get(&pdev->dev, NULL); 168 + if (IS_ERR(clk)) { 169 + dev_err(&pdev->dev, "Unable to get clock\n"); 170 + return PTR_ERR(clk); 171 + } 172 + 173 + ret = clk_prepare_enable(clk); 174 + if (ret) { 175 + dev_err(&pdev->dev, "Unable to prepare clock %p\n", clk); 176 + return ret; 177 + } 178 + 179 + /* 180 + * Allocate our watchdog driver data, which has the 181 + * struct watchdog_device nested within it. 182 + */ 183 + wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL); 184 + if (!wdt) { 185 + ret = -ENOMEM; 186 + goto err; 187 + } 188 + 189 + /* Initialize struct stm32_iwdg. */ 190 + wdt->regs = regs; 191 + wdt->clk = clk; 192 + wdt->rate = clk_get_rate(clk); 193 + 194 + /* Initialize struct watchdog_device. */ 195 + wdd = &wdt->wdd; 196 + wdd->info = &stm32_iwdg_info; 197 + wdd->ops = &stm32_iwdg_ops; 198 + wdd->min_timeout = ((RLR_MIN + 1) * 256) / wdt->rate; 199 + wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * 256 * 1000) / wdt->rate; 200 + wdd->parent = &pdev->dev; 201 + 202 + watchdog_set_drvdata(wdd, wdt); 203 + watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT); 204 + 205 + ret = watchdog_init_timeout(wdd, 0, &pdev->dev); 206 + if (ret) 207 + dev_warn(&pdev->dev, 208 + "unable to set timeout value, using default\n"); 209 + 210 + ret = watchdog_register_device(wdd); 211 + if (ret) { 212 + dev_err(&pdev->dev, "failed to register watchdog device\n"); 213 + goto err; 214 + } 215 + 216 + platform_set_drvdata(pdev, wdt); 217 + 218 + return 0; 219 + err: 220 + clk_disable_unprepare(clk); 221 + 222 + return ret; 223 + } 224 + 225 + static int stm32_iwdg_remove(struct platform_device *pdev) 226 + { 227 + struct stm32_iwdg *wdt = platform_get_drvdata(pdev); 228 + 229 + watchdog_unregister_device(&wdt->wdd); 230 + clk_disable_unprepare(wdt->clk); 231 + 232 + return 0; 233 + } 234 + 235 + static const struct of_device_id stm32_iwdg_of_match[] = { 236 + { .compatible = "st,stm32-iwdg" }, 237 + { /* end node */ } 238 + }; 239 + MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match); 240 + 241 + static struct platform_driver stm32_iwdg_driver = { 242 + .probe = stm32_iwdg_probe, 243 + .remove = stm32_iwdg_remove, 244 + .driver = { 245 + .name = "iwdg", 246 + .of_match_table = stm32_iwdg_of_match, 247 + }, 248 + }; 249 + module_platform_driver(stm32_iwdg_driver); 250 + 251 + MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 252 + MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver"); 253 + MODULE_LICENSE("GPL v2");

+268

drivers/watchdog/uniphier_wdt.c

··· 1 + /* 2 + * Watchdog driver for the UniPhier watchdog timer 3 + * 4 + * (c) Copyright 2014 Panasonic Corporation 5 + * (c) Copyright 2016 Socionext Inc. 6 + * All rights reserved. 7 + * 8 + * This program is free software; you can redistribute it and/or modify 9 + * it under the terms of the GNU General Public License version 2 as 10 + * published by the Free Software Foundation. 11 + * 12 + * This program is distributed in the hope that it will be useful, 13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 + * GNU General Public License for more details. 16 + */ 17 + 18 + #include <linux/bitops.h> 19 + #include <linux/mfd/syscon.h> 20 + #include <linux/module.h> 21 + #include <linux/of.h> 22 + #include <linux/platform_device.h> 23 + #include <linux/regmap.h> 24 + #include <linux/watchdog.h> 25 + 26 + /* WDT timer setting register */ 27 + #define WDTTIMSET 0x3004 28 + #define WDTTIMSET_PERIOD_MASK (0xf << 0) 29 + #define WDTTIMSET_PERIOD_1_SEC (0x3 << 0) 30 + 31 + /* WDT reset selection register */ 32 + #define WDTRSTSEL 0x3008 33 + #define WDTRSTSEL_RSTSEL_MASK (0x3 << 0) 34 + #define WDTRSTSEL_RSTSEL_BOTH (0x0 << 0) 35 + #define WDTRSTSEL_RSTSEL_IRQ_ONLY (0x2 << 0) 36 + 37 + /* WDT control register */ 38 + #define WDTCTRL 0x300c 39 + #define WDTCTRL_STATUS BIT(8) 40 + #define WDTCTRL_CLEAR BIT(1) 41 + #define WDTCTRL_ENABLE BIT(0) 42 + 43 + #define SEC_TO_WDTTIMSET_PRD(sec) \ 44 + (ilog2(sec) + WDTTIMSET_PERIOD_1_SEC) 45 + 46 + #define WDTST_TIMEOUT 1000 /* usec */ 47 + 48 + #define WDT_DEFAULT_TIMEOUT 64 /* Default is 64 seconds */ 49 + #define WDT_PERIOD_MIN 1 50 + #define WDT_PERIOD_MAX 128 51 + 52 + static unsigned int timeout = 0; 53 + static bool nowayout = WATCHDOG_NOWAYOUT; 54 + 55 + struct uniphier_wdt_dev { 56 + struct watchdog_device wdt_dev; 57 + struct regmap *regmap; 58 + }; 59 + 60 + /* 61 + * UniPhier Watchdog operations 62 + */ 63 + static int uniphier_watchdog_ping(struct watchdog_device *w) 64 + { 65 + struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(w); 66 + unsigned int val; 67 + int ret; 68 + 69 + /* Clear counter */ 70 + ret = regmap_write_bits(wdev->regmap, WDTCTRL, 71 + WDTCTRL_CLEAR, WDTCTRL_CLEAR); 72 + if (!ret) 73 + /* 74 + * As SoC specification, after clear counter, 75 + * it needs to wait until counter status is 1. 76 + */ 77 + ret = regmap_read_poll_timeout(wdev->regmap, WDTCTRL, val, 78 + (val & WDTCTRL_STATUS), 79 + 0, WDTST_TIMEOUT); 80 + 81 + return ret; 82 + } 83 + 84 + static int __uniphier_watchdog_start(struct regmap *regmap, unsigned int sec) 85 + { 86 + unsigned int val; 87 + int ret; 88 + 89 + ret = regmap_read_poll_timeout(regmap, WDTCTRL, val, 90 + !(val & WDTCTRL_STATUS), 91 + 0, WDTST_TIMEOUT); 92 + if (ret) 93 + return ret; 94 + 95 + /* Setup period */ 96 + ret = regmap_write(regmap, WDTTIMSET, 97 + SEC_TO_WDTTIMSET_PRD(sec)); 98 + if (ret) 99 + return ret; 100 + 101 + /* Enable and clear watchdog */ 102 + ret = regmap_write(regmap, WDTCTRL, WDTCTRL_ENABLE | WDTCTRL_CLEAR); 103 + if (!ret) 104 + /* 105 + * As SoC specification, after clear counter, 106 + * it needs to wait until counter status is 1. 107 + */ 108 + ret = regmap_read_poll_timeout(regmap, WDTCTRL, val, 109 + (val & WDTCTRL_STATUS), 110 + 0, WDTST_TIMEOUT); 111 + 112 + return ret; 113 + } 114 + 115 + static int __uniphier_watchdog_stop(struct regmap *regmap) 116 + { 117 + /* Disable and stop watchdog */ 118 + return regmap_write_bits(regmap, WDTCTRL, WDTCTRL_ENABLE, 0); 119 + } 120 + 121 + static int __uniphier_watchdog_restart(struct regmap *regmap, unsigned int sec) 122 + { 123 + int ret; 124 + 125 + ret = __uniphier_watchdog_stop(regmap); 126 + if (ret) 127 + return ret; 128 + 129 + return __uniphier_watchdog_start(regmap, sec); 130 + } 131 + 132 + static int uniphier_watchdog_start(struct watchdog_device *w) 133 + { 134 + struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(w); 135 + unsigned int tmp_timeout; 136 + 137 + tmp_timeout = roundup_pow_of_two(w->timeout); 138 + 139 + return __uniphier_watchdog_start(wdev->regmap, tmp_timeout); 140 + } 141 + 142 + static int uniphier_watchdog_stop(struct watchdog_device *w) 143 + { 144 + struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(w); 145 + 146 + return __uniphier_watchdog_stop(wdev->regmap); 147 + } 148 + 149 + static int uniphier_watchdog_set_timeout(struct watchdog_device *w, 150 + unsigned int t) 151 + { 152 + struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(w); 153 + unsigned int tmp_timeout; 154 + int ret; 155 + 156 + tmp_timeout = roundup_pow_of_two(t); 157 + if (tmp_timeout == w->timeout) 158 + return 0; 159 + 160 + if (watchdog_active(w)) { 161 + ret = __uniphier_watchdog_restart(wdev->regmap, tmp_timeout); 162 + if (ret) 163 + return ret; 164 + } 165 + 166 + w->timeout = tmp_timeout; 167 + 168 + return 0; 169 + } 170 + 171 + /* 172 + * Kernel Interfaces 173 + */ 174 + static const struct watchdog_info uniphier_wdt_info = { 175 + .identity = "uniphier-wdt", 176 + .options = WDIOF_SETTIMEOUT | 177 + WDIOF_KEEPALIVEPING | 178 + WDIOF_MAGICCLOSE | 179 + WDIOF_OVERHEAT, 180 + }; 181 + 182 + static const struct watchdog_ops uniphier_wdt_ops = { 183 + .owner = THIS_MODULE, 184 + .start = uniphier_watchdog_start, 185 + .stop = uniphier_watchdog_stop, 186 + .ping = uniphier_watchdog_ping, 187 + .set_timeout = uniphier_watchdog_set_timeout, 188 + }; 189 + 190 + static int uniphier_wdt_probe(struct platform_device *pdev) 191 + { 192 + struct device *dev = &pdev->dev; 193 + struct uniphier_wdt_dev *wdev; 194 + struct regmap *regmap; 195 + struct device_node *parent; 196 + int ret; 197 + 198 + wdev = devm_kzalloc(dev, sizeof(*wdev), GFP_KERNEL); 199 + if (!wdev) 200 + return -ENOMEM; 201 + 202 + platform_set_drvdata(pdev, wdev); 203 + 204 + parent = of_get_parent(dev->of_node); /* parent should be syscon node */ 205 + regmap = syscon_node_to_regmap(parent); 206 + of_node_put(parent); 207 + if (IS_ERR(regmap)) 208 + return PTR_ERR(regmap); 209 + 210 + wdev->regmap = regmap; 211 + wdev->wdt_dev.info = &uniphier_wdt_info; 212 + wdev->wdt_dev.ops = &uniphier_wdt_ops; 213 + wdev->wdt_dev.max_timeout = WDT_PERIOD_MAX; 214 + wdev->wdt_dev.min_timeout = WDT_PERIOD_MIN; 215 + wdev->wdt_dev.parent = dev; 216 + 217 + if (watchdog_init_timeout(&wdev->wdt_dev, timeout, dev) < 0) { 218 + wdev->wdt_dev.timeout = WDT_DEFAULT_TIMEOUT; 219 + } 220 + watchdog_set_nowayout(&wdev->wdt_dev, nowayout); 221 + watchdog_stop_on_reboot(&wdev->wdt_dev); 222 + 223 + watchdog_set_drvdata(&wdev->wdt_dev, wdev); 224 + 225 + uniphier_watchdog_stop(&wdev->wdt_dev); 226 + ret = regmap_write(wdev->regmap, WDTRSTSEL, WDTRSTSEL_RSTSEL_BOTH); 227 + if (ret) 228 + return ret; 229 + 230 + ret = devm_watchdog_register_device(dev, &wdev->wdt_dev); 231 + if (ret) 232 + return ret; 233 + 234 + dev_info(dev, "watchdog driver (timeout=%d sec, nowayout=%d)\n", 235 + wdev->wdt_dev.timeout, nowayout); 236 + 237 + return 0; 238 + } 239 + 240 + static const struct of_device_id uniphier_wdt_dt_ids[] = { 241 + { .compatible = "socionext,uniphier-wdt" }, 242 + { /* sentinel */ } 243 + }; 244 + MODULE_DEVICE_TABLE(of, uniphier_wdt_dt_ids); 245 + 246 + static struct platform_driver uniphier_wdt_driver = { 247 + .probe = uniphier_wdt_probe, 248 + .driver = { 249 + .name = "uniphier-wdt", 250 + .of_match_table = uniphier_wdt_dt_ids, 251 + }, 252 + }; 253 + 254 + module_platform_driver(uniphier_wdt_driver); 255 + 256 + module_param(timeout, uint, 0000); 257 + MODULE_PARM_DESC(timeout, 258 + "Watchdog timeout seconds in power of 2. (0 < timeout < 128, default=" 259 + __MODULE_STRING(WDT_DEFAULT_TIMEOUT) ")"); 260 + 261 + module_param(nowayout, bool, 0000); 262 + MODULE_PARM_DESC(nowayout, 263 + "Watchdog cannot be stopped once started (default=" 264 + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); 265 + 266 + MODULE_AUTHOR("Keiji Hayashibara <hayashibara.keiji@socionext.com>"); 267 + MODULE_DESCRIPTION("UniPhier Watchdog Device Driver"); 268 + MODULE_LICENSE("GPL v2");

+14 -1

drivers/watchdog/w83627hf_wdt.c

··· 49 49 50 50 enum chips { w83627hf, w83627s, w83697hf, w83697ug, w83637hf, w83627thf, 51 51 w83687thf, w83627ehf, w83627dhg, w83627uhg, w83667hg, w83627dhg_p, 52 - w83667hg_b, nct6775, nct6776, nct6779, nct6791, nct6792, nct6102 }; 52 + w83667hg_b, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793, 53 + nct6795, nct6102 }; 53 54 54 55 static int timeout; /* in seconds */ 55 56 module_param(timeout, int, 0); ··· 98 97 #define NCT6779_ID 0xc5 99 98 #define NCT6791_ID 0xc8 100 99 #define NCT6792_ID 0xc9 100 + #define NCT6793_ID 0xd1 101 + #define NCT6795_ID 0xd3 101 102 102 103 #define W83627HF_WDT_TIMEOUT 0xf6 103 104 #define W83697HF_WDT_TIMEOUT 0xf4 ··· 207 204 case nct6779: 208 205 case nct6791: 209 206 case nct6792: 207 + case nct6793: 208 + case nct6795: 210 209 case nct6102: 211 210 /* 212 211 * These chips have a fixed WDTO# output pin (W83627UHG), ··· 401 396 case NCT6792_ID: 402 397 ret = nct6792; 403 398 break; 399 + case NCT6793_ID: 400 + ret = nct6793; 401 + break; 402 + case NCT6795_ID: 403 + ret = nct6795; 404 + break; 404 405 case NCT6102_ID: 405 406 ret = nct6102; 406 407 cr_wdt_timeout = NCT6102D_WDT_TIMEOUT; ··· 448 437 "NCT6779", 449 438 "NCT6791", 450 439 "NCT6792", 440 + "NCT6793", 441 + "NCT6795", 451 442 "NCT6102", 452 443 }; 453 444

+25 -7

drivers/watchdog/watchdog_dev.c

··· 80 80 81 81 static struct workqueue_struct *watchdog_wq; 82 82 83 + static bool handle_boot_enabled = 84 + IS_ENABLED(CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED); 85 + 83 86 static inline bool watchdog_need_worker(struct watchdog_device *wdd) 84 87 { 85 88 /* All variables in milli-seconds */ ··· 195 192 return __watchdog_ping(wdd); 196 193 } 197 194 195 + static bool watchdog_worker_should_ping(struct watchdog_core_data *wd_data) 196 + { 197 + struct watchdog_device *wdd = wd_data->wdd; 198 + 199 + return wdd && (watchdog_active(wdd) || watchdog_hw_running(wdd)); 200 + } 201 + 198 202 static void watchdog_ping_work(struct work_struct *work) 199 203 { 200 204 struct watchdog_core_data *wd_data; 201 - struct watchdog_device *wdd; 202 205 203 206 wd_data = container_of(to_delayed_work(work), struct watchdog_core_data, 204 207 work); 205 208 206 209 mutex_lock(&wd_data->lock); 207 - wdd = wd_data->wdd; 208 - if (wdd && (watchdog_active(wdd) || watchdog_hw_running(wdd))) 209 - __watchdog_ping(wdd); 210 + if (watchdog_worker_should_ping(wd_data)) 211 + __watchdog_ping(wd_data->wdd); 210 212 mutex_unlock(&wd_data->lock); 211 213 } 212 214 ··· 964 956 * and schedule an immediate ping. 965 957 */ 966 958 if (watchdog_hw_running(wdd)) { 967 - __module_get(wdd->ops->owner); 968 - kref_get(&wd_data->kref); 969 - queue_delayed_work(watchdog_wq, &wd_data->work, 0); 959 + if (handle_boot_enabled) { 960 + __module_get(wdd->ops->owner); 961 + kref_get(&wd_data->kref); 962 + queue_delayed_work(watchdog_wq, &wd_data->work, 0); 963 + } else { 964 + pr_info("watchdog%d running and kernel based pre-userspace handler disabled\n", 965 + wdd->id); 966 + } 970 967 } 971 968 972 969 return 0; ··· 1119 1106 class_unregister(&watchdog_class); 1120 1107 destroy_workqueue(watchdog_wq); 1121 1108 } 1109 + 1110 + module_param(handle_boot_enabled, bool, 0444); 1111 + MODULE_PARM_DESC(handle_boot_enabled, 1112 + "Watchdog core auto-updates boot enabled watchdogs before userspace takes over (default=" 1113 + __MODULE_STRING(IS_ENABLED(CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED)) ")");

+1 -1

drivers/watchdog/zx2967_wdt.c

··· 154 154 .identity = "zx2967 watchdog", 155 155 }; 156 156 157 - static struct watchdog_ops zx2967_wdt_ops = { 157 + static const struct watchdog_ops zx2967_wdt_ops = { 158 158 .owner = THIS_MODULE, 159 159 .start = zx2967_wdt_start, 160 160 .stop = zx2967_wdt_stop,

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