tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/xe/guc: Skip access counter queue init for unsupported platforms

Add a has_access_counter feature flag to the graphics IP descriptor
and skip writing parameters for the access counter queue in
guc_um_init_params(), leaving queue_params[2] zero-initialized
to signal unavailability to the GuC.

The queue_params[] array layout is fixed by firmware ABI, so we
maintain the structure with queues 0 and 1 (page fault request/response)
always configured, and queue 2 conditionally skipped based on the
has_access_counter flag.

Bspec: 59323
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Suggested-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: Varun Gupta <varun.gupta1@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20260225164748.2302380-1-varun.gupta@intel.com
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>

authored by

Himal Prasad Ghimiray and committed by
Tejas Upadhyay 07eb8b54 6bc6fec7

+18
+2
drivers/gpu/drm/xe/xe_device_types.h
··· 153 153 154 154 /** @info.force_execlist: Forced execlist submission */ 155 155 u8 force_execlist:1; 156 + /** @info.has_access_counter: Device supports access counter */ 157 + u8 has_access_counter:1; 156 158 /** @info.has_asid: Has address space ID */ 157 159 u8 has_asid:1; 158 160 /** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */
+11
drivers/gpu/drm/xe/xe_guc_ads.c
··· 819 819 { 820 820 u32 um_queue_offset = guc_ads_um_queues_offset(ads); 821 821 struct xe_guc *guc = ads_to_guc(ads); 822 + struct xe_device *xe = ads_to_xe(ads); 822 823 u64 base_dpa; 823 824 u32 base_ggtt; 824 825 bool with_dpa; ··· 831 830 base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset; 832 831 833 832 for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) { 833 + /* 834 + * Some platforms support USM but not access counters. 835 + * Skip ACCESS_COUNTER queue initialization for such 836 + * platforms, leaving queue_params[2] zero-initialized 837 + * to signal unavailability to the GuC. 838 + */ 839 + if (i == GUC_UM_HW_QUEUE_ACCESS_COUNTER && 840 + !xe->info.has_access_counter) 841 + continue; 842 + 834 843 ads_blob_write(ads, um_init_params.queue_params[i].base_dpa, 835 844 with_dpa ? (base_dpa + (i * GUC_UM_QUEUE_SIZE)) : 0); 836 845 ads_blob_write(ads, um_init_params.queue_params[i].base_ggtt_address,
+4
drivers/gpu/drm/xe/xe_pci.c
··· 81 81 82 82 XE_HP_FEATURES, 83 83 84 + .has_access_counter = 1, 84 85 .has_asid = 1, 85 86 .has_atomic_enable_pte_bit = 1, 86 87 .has_usm = 1, ··· 99 98 }; 100 99 101 100 #define XE2_GFX_FEATURES \ 101 + .has_access_counter = 1, \ 102 102 .has_asid = 1, \ 103 103 .has_atomic_enable_pte_bit = 1, \ 104 104 .has_range_tlb_inval = 1, \ ··· 125 123 126 124 static const struct xe_graphics_desc graphics_xe3p_xpc = { 127 125 XE2_GFX_FEATURES, 126 + .has_access_counter = 0, 128 127 .has_indirect_ring_state = 1, 129 128 .hw_engine_mask = 130 129 GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) | ··· 947 944 media_desc = NULL; 948 945 } 949 946 947 + xe->info.has_access_counter = graphics_desc->has_access_counter; 950 948 xe->info.has_asid = graphics_desc->has_asid; 951 949 xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit; 952 950 if (xe->info.platform != XE_PVC)
+1
drivers/gpu/drm/xe/xe_pci_types.h
··· 70 70 u8 num_geometry_xecore_fuse_regs; 71 71 u8 num_compute_xecore_fuse_regs; 72 72 73 + u8 has_access_counter:1; 73 74 u8 has_asid:1; 74 75 u8 has_atomic_enable_pte_bit:1; 75 76 u8 has_indirect_ring_state:1;