+16

drivers/media/platform/renesas/rzg2l-cru/Kconfig

reviewed

··· 15 15 16 16 To compile this driver as a module, choose M here: the 17 17 module will be called rzg2l-csi2. 18 18 + 19 19 + config VIDEO_RZG2L_CRU 20 20 + tristate "RZ/G2L Camera Receiving Unit (CRU) Driver" 21 21 + depends on ARCH_RENESAS || COMPILE_TEST 22 22 + depends on V4L_PLATFORM_DRIVERS 23 23 + depends on VIDEO_DEV && OF 24 24 + select MEDIA_CONTROLLER 25 25 + select V4L2_FWNODE 26 26 + select VIDEOBUF2_DMA_CONTIG 27 27 + select VIDEO_V4L2_SUBDEV_API 28 28 + help 29 29 + Support for Renesas RZ/G2L (and alike SoC's) Camera Receiving 30 30 + Unit (CRU) driver. 31 31 + 32 32 + To compile this driver as a module, choose M here: the 33 33 + module will be called rzg2l-cru.

+3

drivers/media/platform/renesas/rzg2l-cru/Makefile

reviewed

··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 2 3 3 obj-$(CONFIG_VIDEO_RZG2L_CSI2) += rzg2l-csi2.o 4 4 + 5 5 + rzg2l-cru-objs = rzg2l-core.o rzg2l-ip.o rzg2l-video.o 6 6 + obj-$(CONFIG_VIDEO_RZG2L_CRU) += rzg2l-cru.o

+338

drivers/media/platform/renesas/rzg2l-cru/rzg2l-core.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0+ 2 2 + /* 3 3 + * Driver for Renesas RZ/G2L CRU 4 4 + * 5 5 + * Copyright (C) 2022 Renesas Electronics Corp. 6 6 + * 7 7 + * Based on Renesas R-Car VIN 8 8 + * Copyright (C) 2011-2013 Renesas Solutions Corp. 9 9 + * Copyright (C) 2013 Cogent Embedded, Inc., <source@cogentembedded.com> 10 10 + * Copyright (C) 2008 Magnus Damm 11 11 + */ 12 12 + 13 13 + #include <linux/clk.h> 14 14 + #include <linux/module.h> 15 15 + #include <linux/mod_devicetable.h> 16 16 + #include <linux/of.h> 17 17 + #include <linux/of_device.h> 18 18 + #include <linux/of_graph.h> 19 19 + #include <linux/platform_device.h> 20 20 + #include <linux/pm_runtime.h> 21 21 + 22 22 + #include <media/v4l2-fwnode.h> 23 23 + #include <media/v4l2-mc.h> 24 24 + 25 25 + #include "rzg2l-cru.h" 26 26 + 27 27 + static inline struct rzg2l_cru_dev *notifier_to_cru(struct v4l2_async_notifier *n) 28 28 + { 29 29 + return container_of(n, struct rzg2l_cru_dev, notifier); 30 30 + } 31 31 + 32 32 + static const struct media_device_ops rzg2l_cru_media_ops = { 33 33 + .link_notify = v4l2_pipeline_link_notify, 34 34 + }; 35 35 + 36 36 + /* ----------------------------------------------------------------------------- 37 37 + * Group async notifier 38 38 + */ 39 39 + 40 40 + static int rzg2l_cru_group_notify_complete(struct v4l2_async_notifier *notifier) 41 41 + { 42 42 + struct rzg2l_cru_dev *cru = notifier_to_cru(notifier); 43 43 + struct media_entity *source, *sink; 44 44 + int ret; 45 45 + 46 46 + ret = rzg2l_cru_ip_subdev_register(cru); 47 47 + if (ret) 48 48 + return ret; 49 49 + 50 50 + ret = v4l2_device_register_subdev_nodes(&cru->v4l2_dev); 51 51 + if (ret) { 52 52 + dev_err(cru->dev, "Failed to register subdev nodes\n"); 53 53 + return ret; 54 54 + } 55 55 + 56 56 + ret = rzg2l_cru_video_register(cru); 57 57 + if (ret) 58 58 + return ret; 59 59 + 60 60 + /* 61 61 + * CRU can be connected either to CSI2 or PARALLEL device 62 62 + * For now we are only supporting CSI2 63 63 + * 64 64 + * Create media device link between CSI-2 <-> CRU IP 65 65 + */ 66 66 + source = &cru->csi.subdev->entity; 67 67 + sink = &cru->ip.subdev.entity; 68 68 + ret = media_create_pad_link(source, 1, sink, 0, 69 69 + MEDIA_LNK_FL_ENABLED | 70 70 + MEDIA_LNK_FL_IMMUTABLE); 71 71 + if (ret) { 72 72 + dev_err(cru->dev, "Error creating link from %s to %s\n", 73 73 + source->name, sink->name); 74 74 + return ret; 75 75 + } 76 76 + cru->csi.channel = 0; 77 77 + cru->ip.remote = cru->csi.subdev; 78 78 + 79 79 + /* Create media device link between CRU IP <-> CRU OUTPUT */ 80 80 + source = &cru->ip.subdev.entity; 81 81 + sink = &cru->vdev.entity; 82 82 + ret = media_create_pad_link(source, 1, sink, 0, 83 83 + MEDIA_LNK_FL_ENABLED | 84 84 + MEDIA_LNK_FL_IMMUTABLE); 85 85 + if (ret) { 86 86 + dev_err(cru->dev, "Error creating link from %s to %s\n", 87 87 + source->name, sink->name); 88 88 + return ret; 89 89 + } 90 90 + 91 91 + return 0; 92 92 + } 93 93 + 94 94 + static void rzg2l_cru_group_notify_unbind(struct v4l2_async_notifier *notifier, 95 95 + struct v4l2_subdev *subdev, 96 96 + struct v4l2_async_subdev *asd) 97 97 + { 98 98 + struct rzg2l_cru_dev *cru = notifier_to_cru(notifier); 99 99 + 100 100 + rzg2l_cru_ip_subdev_unregister(cru); 101 101 + 102 102 + mutex_lock(&cru->mdev_lock); 103 103 + 104 104 + if (cru->csi.asd == asd) { 105 105 + cru->csi.subdev = NULL; 106 106 + dev_dbg(cru->dev, "Unbind CSI-2 %s\n", subdev->name); 107 107 + } 108 108 + 109 109 + mutex_unlock(&cru->mdev_lock); 110 110 + } 111 111 + 112 112 + static int rzg2l_cru_group_notify_bound(struct v4l2_async_notifier *notifier, 113 113 + struct v4l2_subdev *subdev, 114 114 + struct v4l2_async_subdev *asd) 115 115 + { 116 116 + struct rzg2l_cru_dev *cru = notifier_to_cru(notifier); 117 117 + 118 118 + mutex_lock(&cru->mdev_lock); 119 119 + 120 120 + if (cru->csi.asd == asd) { 121 121 + cru->csi.subdev = subdev; 122 122 + dev_dbg(cru->dev, "Bound CSI-2 %s\n", subdev->name); 123 123 + } 124 124 + 125 125 + mutex_unlock(&cru->mdev_lock); 126 126 + 127 127 + return 0; 128 128 + } 129 129 + 130 130 + static const struct v4l2_async_notifier_operations rzg2l_cru_async_ops = { 131 131 + .bound = rzg2l_cru_group_notify_bound, 132 132 + .unbind = rzg2l_cru_group_notify_unbind, 133 133 + .complete = rzg2l_cru_group_notify_complete, 134 134 + }; 135 135 + 136 136 + static int rzg2l_cru_mc_parse_of(struct rzg2l_cru_dev *cru) 137 137 + { 138 138 + struct v4l2_fwnode_endpoint vep = { 139 139 + .bus_type = V4L2_MBUS_CSI2_DPHY, 140 140 + }; 141 141 + struct fwnode_handle *ep, *fwnode; 142 142 + struct v4l2_async_subdev *asd; 143 143 + int ret; 144 144 + 145 145 + ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(cru->dev), 1, 0, 0); 146 146 + if (!ep) 147 147 + return 0; 148 148 + 149 149 + fwnode = fwnode_graph_get_remote_endpoint(ep); 150 150 + ret = v4l2_fwnode_endpoint_parse(ep, &vep); 151 151 + fwnode_handle_put(ep); 152 152 + if (ret) { 153 153 + dev_err(cru->dev, "Failed to parse %pOF\n", to_of_node(fwnode)); 154 154 + ret = -EINVAL; 155 155 + goto out; 156 156 + } 157 157 + 158 158 + if (!of_device_is_available(to_of_node(fwnode))) { 159 159 + dev_dbg(cru->dev, "OF device %pOF disabled, ignoring\n", 160 160 + to_of_node(fwnode)); 161 161 + ret = -ENOTCONN; 162 162 + goto out; 163 163 + } 164 164 + 165 165 + asd = v4l2_async_nf_add_fwnode(&cru->notifier, fwnode, 166 166 + struct v4l2_async_subdev); 167 167 + if (IS_ERR(asd)) { 168 168 + ret = PTR_ERR(asd); 169 169 + goto out; 170 170 + } 171 171 + 172 172 + cru->csi.asd = asd; 173 173 + 174 174 + dev_dbg(cru->dev, "Added OF device %pOF to slot %u\n", 175 175 + to_of_node(fwnode), vep.base.id); 176 176 + out: 177 177 + fwnode_handle_put(fwnode); 178 178 + 179 179 + return ret; 180 180 + } 181 181 + 182 182 + static int rzg2l_cru_mc_parse_of_graph(struct rzg2l_cru_dev *cru) 183 183 + { 184 184 + int ret; 185 185 + 186 186 + v4l2_async_nf_init(&cru->notifier); 187 187 + 188 188 + ret = rzg2l_cru_mc_parse_of(cru); 189 189 + if (ret) 190 190 + return ret; 191 191 + 192 192 + cru->notifier.ops = &rzg2l_cru_async_ops; 193 193 + 194 194 + if (list_empty(&cru->notifier.asd_list)) 195 195 + return 0; 196 196 + 197 197 + ret = v4l2_async_nf_register(&cru->v4l2_dev, &cru->notifier); 198 198 + if (ret < 0) { 199 199 + dev_err(cru->dev, "Notifier registration failed\n"); 200 200 + v4l2_async_nf_cleanup(&cru->notifier); 201 201 + return ret; 202 202 + } 203 203 + 204 204 + return 0; 205 205 + } 206 206 + 207 207 + static int rzg2l_cru_media_init(struct rzg2l_cru_dev *cru) 208 208 + { 209 209 + struct media_device *mdev = NULL; 210 210 + const struct of_device_id *match; 211 211 + int ret; 212 212 + 213 213 + cru->pad.flags = MEDIA_PAD_FL_SINK; 214 214 + ret = media_entity_pads_init(&cru->vdev.entity, 1, &cru->pad); 215 215 + if (ret) 216 216 + return ret; 217 217 + 218 218 + mutex_init(&cru->mdev_lock); 219 219 + mdev = &cru->mdev; 220 220 + mdev->dev = cru->dev; 221 221 + mdev->ops = &rzg2l_cru_media_ops; 222 222 + 223 223 + match = of_match_node(cru->dev->driver->of_match_table, 224 224 + cru->dev->of_node); 225 225 + 226 226 + strscpy(mdev->driver_name, KBUILD_MODNAME, sizeof(mdev->driver_name)); 227 227 + strscpy(mdev->model, match->compatible, sizeof(mdev->model)); 228 228 + 229 229 + cru->v4l2_dev.mdev = &cru->mdev; 230 230 + 231 231 + media_device_init(mdev); 232 232 + 233 233 + ret = rzg2l_cru_mc_parse_of_graph(cru); 234 234 + if (ret) { 235 235 + mutex_lock(&cru->mdev_lock); 236 236 + cru->v4l2_dev.mdev = NULL; 237 237 + mutex_unlock(&cru->mdev_lock); 238 238 + } 239 239 + 240 240 + return 0; 241 241 + } 242 242 + 243 243 + static int rzg2l_cru_probe(struct platform_device *pdev) 244 244 + { 245 245 + struct rzg2l_cru_dev *cru; 246 246 + int ret; 247 247 + 248 248 + cru = devm_kzalloc(&pdev->dev, sizeof(*cru), GFP_KERNEL); 249 249 + if (!cru) 250 250 + return -ENOMEM; 251 251 + 252 252 + cru->base = devm_platform_ioremap_resource(pdev, 0); 253 253 + if (IS_ERR(cru->base)) 254 254 + return PTR_ERR(cru->base); 255 255 + 256 256 + cru->presetn = devm_reset_control_get_shared(&pdev->dev, "presetn"); 257 257 + if (IS_ERR(cru->presetn)) 258 258 + return dev_err_probe(&pdev->dev, PTR_ERR(cru->presetn), 259 259 + "Failed to get cpg presetn\n"); 260 260 + 261 261 + cru->aresetn = devm_reset_control_get_exclusive(&pdev->dev, "aresetn"); 262 262 + if (IS_ERR(cru->aresetn)) 263 263 + return dev_err_probe(&pdev->dev, PTR_ERR(cru->aresetn), 264 264 + "Failed to get cpg aresetn\n"); 265 265 + 266 266 + cru->vclk = devm_clk_get(&pdev->dev, "video"); 267 267 + if (IS_ERR(cru->vclk)) 268 268 + return dev_err_probe(&pdev->dev, PTR_ERR(cru->vclk), 269 269 + "Failed to get video clock\n"); 270 270 + 271 271 + cru->dev = &pdev->dev; 272 272 + cru->info = of_device_get_match_data(&pdev->dev); 273 273 + 274 274 + cru->image_conv_irq = platform_get_irq(pdev, 0); 275 275 + if (cru->image_conv_irq < 0) 276 276 + return cru->image_conv_irq; 277 277 + 278 278 + platform_set_drvdata(pdev, cru); 279 279 + 280 280 + ret = rzg2l_cru_dma_register(cru); 281 281 + if (ret) 282 282 + return ret; 283 283 + 284 284 + cru->num_buf = RZG2L_CRU_HW_BUFFER_DEFAULT; 285 285 + pm_suspend_ignore_children(&pdev->dev, true); 286 286 + pm_runtime_enable(&pdev->dev); 287 287 + 288 288 + ret = rzg2l_cru_media_init(cru); 289 289 + if (ret) 290 290 + goto error_dma_unregister; 291 291 + 292 292 + return 0; 293 293 + 294 294 + error_dma_unregister: 295 295 + rzg2l_cru_dma_unregister(cru); 296 296 + pm_runtime_disable(&pdev->dev); 297 297 + 298 298 + return ret; 299 299 + } 300 300 + 301 301 + static int rzg2l_cru_remove(struct platform_device *pdev) 302 302 + { 303 303 + struct rzg2l_cru_dev *cru = platform_get_drvdata(pdev); 304 304 + 305 305 + pm_runtime_disable(&pdev->dev); 306 306 + 307 307 + v4l2_async_nf_unregister(&cru->notifier); 308 308 + v4l2_async_nf_cleanup(&cru->notifier); 309 309 + 310 310 + rzg2l_cru_video_unregister(cru); 311 311 + media_device_cleanup(&cru->mdev); 312 312 + mutex_destroy(&cru->mdev_lock); 313 313 + 314 314 + rzg2l_cru_dma_unregister(cru); 315 315 + 316 316 + return 0; 317 317 + } 318 318 + 319 319 + static const struct of_device_id rzg2l_cru_of_id_table[] = { 320 320 + { .compatible = "renesas,rzg2l-cru", }, 321 321 + { /* sentinel */ } 322 322 + }; 323 323 + MODULE_DEVICE_TABLE(of, rzg2l_cru_of_id_table); 324 324 + 325 325 + static struct platform_driver rzg2l_cru_driver = { 326 326 + .driver = { 327 327 + .name = "rzg2l-cru", 328 328 + .of_match_table = rzg2l_cru_of_id_table, 329 329 + }, 330 330 + .probe = rzg2l_cru_probe, 331 331 + .remove = rzg2l_cru_remove, 332 332 + }; 333 333 + 334 334 + module_platform_driver(rzg2l_cru_driver); 335 335 + 336 336 + MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 337 337 + MODULE_DESCRIPTION("Renesas RZ/G2L CRU driver"); 338 338 + MODULE_LICENSE("GPL");

+152

drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0+ */ 2 2 + /* 3 3 + * Driver for Renesas RZ/G2L CRU 4 4 + * 5 5 + * Copyright (C) 2022 Renesas Electronics Corp. 6 6 + */ 7 7 + 8 8 + #ifndef __RZG2L_CRU__ 9 9 + #define __RZG2L_CRU__ 10 10 + 11 11 + #include <linux/reset.h> 12 12 + 13 13 + #include <media/v4l2-async.h> 14 14 + #include <media/v4l2-dev.h> 15 15 + #include <media/v4l2-device.h> 16 16 + #include <media/videobuf2-v4l2.h> 17 17 + 18 18 + /* Number of HW buffers */ 19 19 + #define RZG2L_CRU_HW_BUFFER_MAX 8 20 20 + #define RZG2L_CRU_HW_BUFFER_DEFAULT 3 21 21 + 22 22 + /* Address alignment mask for HW buffers */ 23 23 + #define RZG2L_CRU_HW_BUFFER_MASK 0x1ff 24 24 + 25 25 + /* Maximum number of CSI2 virtual channels */ 26 26 + #define RZG2L_CRU_CSI2_VCHANNEL 4 27 27 + 28 28 + #define RZG2L_CRU_MIN_INPUT_WIDTH 320 29 29 + #define RZG2L_CRU_MAX_INPUT_WIDTH 2800 30 30 + #define RZG2L_CRU_MIN_INPUT_HEIGHT 240 31 31 + #define RZG2L_CRU_MAX_INPUT_HEIGHT 4095 32 32 + 33 33 + /** 34 34 + * enum rzg2l_cru_dma_state - DMA states 35 35 + * @RZG2L_CRU_DMA_STOPPED: No operation in progress 36 36 + * @RZG2L_CRU_DMA_STARTING: Capture starting up 37 37 + * @RZG2L_CRU_DMA_RUNNING: Operation in progress have buffers 38 38 + * @RZG2L_CRU_DMA_STOPPING: Stopping operation 39 39 + */ 40 40 + enum rzg2l_cru_dma_state { 41 41 + RZG2L_CRU_DMA_STOPPED = 0, 42 42 + RZG2L_CRU_DMA_STARTING, 43 43 + RZG2L_CRU_DMA_RUNNING, 44 44 + RZG2L_CRU_DMA_STOPPING, 45 45 + }; 46 46 + 47 47 + struct rzg2l_cru_csi { 48 48 + struct v4l2_async_subdev *asd; 49 49 + struct v4l2_subdev *subdev; 50 50 + u32 channel; 51 51 + }; 52 52 + 53 53 + struct rzg2l_cru_ip { 54 54 + struct v4l2_subdev subdev; 55 55 + struct media_pad pads[2]; 56 56 + struct v4l2_async_notifier notifier; 57 57 + struct v4l2_subdev *remote; 58 58 + }; 59 59 + 60 60 + /** 61 61 + * struct rzg2l_cru_dev - Renesas CRU device structure 62 62 + * @dev: (OF) device 63 63 + * @base: device I/O register space remapped to virtual memory 64 64 + * @info: info about CRU instance 65 65 + * 66 66 + * @presetn: CRU_PRESETN reset line 67 67 + * @aresetn: CRU_ARESETN reset line 68 68 + * 69 69 + * @vclk: CRU Main clock 70 70 + * 71 71 + * @vdev: V4L2 video device associated with CRU 72 72 + * @v4l2_dev: V4L2 device 73 73 + * @num_buf: Holds the current number of buffers enabled 74 74 + * @notifier: V4L2 asynchronous subdevs notifier 75 75 + * 76 76 + * @ip: Image processing subdev info 77 77 + * @csi: CSI info 78 78 + * @mdev: media device 79 79 + * @mdev_lock: protects the count, notifier and csi members 80 80 + * @pad: media pad for the video device entity 81 81 + * 82 82 + * @lock: protects @queue 83 83 + * @queue: vb2 buffers queue 84 84 + * @scratch: cpu address for scratch buffer 85 85 + * @scratch_phys: physical address of the scratch buffer 86 86 + * 87 87 + * @qlock: protects @queue_buf, @buf_list, @sequence 88 88 + * @state 89 89 + * @queue_buf: Keeps track of buffers given to HW slot 90 90 + * @buf_list: list of queued buffers 91 91 + * @sequence: V4L2 buffers sequence number 92 92 + * @state: keeps track of operation state 93 93 + * 94 94 + * @format: active V4L2 pixel format 95 95 + */ 96 96 + struct rzg2l_cru_dev { 97 97 + struct device *dev; 98 98 + void __iomem *base; 99 99 + const struct rzg2l_cru_info *info; 100 100 + 101 101 + struct reset_control *presetn; 102 102 + struct reset_control *aresetn; 103 103 + 104 104 + struct clk *vclk; 105 105 + 106 106 + int image_conv_irq; 107 107 + 108 108 + struct video_device vdev; 109 109 + struct v4l2_device v4l2_dev; 110 110 + u8 num_buf; 111 111 + 112 112 + struct v4l2_async_notifier notifier; 113 113 + 114 114 + struct rzg2l_cru_ip ip; 115 115 + struct rzg2l_cru_csi csi; 116 116 + struct media_device mdev; 117 117 + struct mutex mdev_lock; 118 118 + struct media_pad pad; 119 119 + 120 120 + struct mutex lock; 121 121 + struct vb2_queue queue; 122 122 + void *scratch; 123 123 + dma_addr_t scratch_phys; 124 124 + 125 125 + spinlock_t qlock; 126 126 + struct vb2_v4l2_buffer *queue_buf[RZG2L_CRU_HW_BUFFER_MAX]; 127 127 + struct list_head buf_list; 128 128 + unsigned int sequence; 129 129 + enum rzg2l_cru_dma_state state; 130 130 + 131 131 + struct v4l2_pix_format format; 132 132 + }; 133 133 + 134 134 + void rzg2l_cru_vclk_unprepare(struct rzg2l_cru_dev *cru); 135 135 + int rzg2l_cru_vclk_prepare(struct rzg2l_cru_dev *cru); 136 136 + 137 137 + int rzg2l_cru_start_image_processing(struct rzg2l_cru_dev *cru); 138 138 + void rzg2l_cru_stop_image_processing(struct rzg2l_cru_dev *cru); 139 139 + 140 140 + int rzg2l_cru_dma_register(struct rzg2l_cru_dev *cru); 141 141 + void rzg2l_cru_dma_unregister(struct rzg2l_cru_dev *cru); 142 142 + 143 143 + int rzg2l_cru_video_register(struct rzg2l_cru_dev *cru); 144 144 + void rzg2l_cru_video_unregister(struct rzg2l_cru_dev *cru); 145 145 + 146 146 + const struct v4l2_format_info *rzg2l_cru_format_from_pixel(u32 format); 147 147 + 148 148 + int rzg2l_cru_ip_subdev_register(struct rzg2l_cru_dev *cru); 149 149 + void rzg2l_cru_ip_subdev_unregister(struct rzg2l_cru_dev *cru); 150 150 + struct v4l2_mbus_framefmt *rzg2l_cru_ip_get_src_fmt(struct rzg2l_cru_dev *cru); 151 151 + 152 152 + #endif

+255

drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Driver for Renesas RZ/G2L CRU 4 4 + * 5 5 + * Copyright (C) 2022 Renesas Electronics Corp. 6 6 + */ 7 7 + 8 8 + #include "rzg2l-cru.h" 9 9 + 10 10 + struct rzg2l_cru_ip_format { 11 11 + u32 code; 12 12 + unsigned int datatype; 13 13 + unsigned int bpp; 14 14 + }; 15 15 + 16 16 + static const struct rzg2l_cru_ip_format rzg2l_cru_ip_formats[] = { 17 17 + { .code = MEDIA_BUS_FMT_UYVY8_1X16, .datatype = 0x1e, .bpp = 16 }, 18 18 + }; 19 19 + 20 20 + enum rzg2l_csi2_pads { 21 21 + RZG2L_CRU_IP_SINK = 0, 22 22 + RZG2L_CRU_IP_SOURCE, 23 23 + }; 24 24 + 25 25 + static const struct rzg2l_cru_ip_format *rzg2l_cru_ip_code_to_fmt(unsigned int code) 26 26 + { 27 27 + unsigned int i; 28 28 + 29 29 + for (i = 0; i < ARRAY_SIZE(rzg2l_cru_ip_formats); i++) 30 30 + if (rzg2l_cru_ip_formats[i].code == code) 31 31 + return &rzg2l_cru_ip_formats[i]; 32 32 + 33 33 + return NULL; 34 34 + } 35 35 + 36 36 + struct v4l2_mbus_framefmt *rzg2l_cru_ip_get_src_fmt(struct rzg2l_cru_dev *cru) 37 37 + { 38 38 + struct v4l2_subdev_state *state; 39 39 + struct v4l2_mbus_framefmt *fmt; 40 40 + 41 41 + state = v4l2_subdev_lock_and_get_active_state(&cru->ip.subdev); 42 42 + fmt = v4l2_subdev_get_pad_format(&cru->ip.subdev, state, 1); 43 43 + v4l2_subdev_unlock_state(state); 44 44 + 45 45 + return fmt; 46 46 + } 47 47 + 48 48 + static int rzg2l_cru_ip_s_stream(struct v4l2_subdev *sd, int enable) 49 49 + { 50 50 + struct rzg2l_cru_dev *cru; 51 51 + int s_stream_ret = 0; 52 52 + int ret; 53 53 + 54 54 + cru = v4l2_get_subdevdata(sd); 55 55 + 56 56 + if (!enable) { 57 57 + ret = v4l2_subdev_call(cru->ip.remote, video, s_stream, enable); 58 58 + if (ret) 59 59 + s_stream_ret = ret; 60 60 + 61 61 + ret = v4l2_subdev_call(cru->ip.remote, video, post_streamoff); 62 62 + if (ret == -ENOIOCTLCMD) 63 63 + ret = 0; 64 64 + if (ret && !s_stream_ret) 65 65 + s_stream_ret = ret; 66 66 + rzg2l_cru_stop_image_processing(cru); 67 67 + } else { 68 68 + ret = v4l2_subdev_call(cru->ip.remote, video, pre_streamon, 0); 69 69 + if (ret == -ENOIOCTLCMD) 70 70 + ret = 0; 71 71 + if (ret) 72 72 + return ret; 73 73 + 74 74 + ret = rzg2l_cru_start_image_processing(cru); 75 75 + if (ret) { 76 76 + v4l2_subdev_call(cru->ip.remote, video, post_streamoff); 77 77 + return ret; 78 78 + } 79 79 + 80 80 + rzg2l_cru_vclk_unprepare(cru); 81 81 + 82 82 + ret = v4l2_subdev_call(cru->ip.remote, video, s_stream, enable); 83 83 + if (ret == -ENOIOCTLCMD) 84 84 + ret = 0; 85 85 + if (!ret) { 86 86 + ret = rzg2l_cru_vclk_prepare(cru); 87 87 + if (!ret) 88 88 + return 0; 89 89 + } else { 90 90 + /* enable back vclk so that s_stream in error path disables it */ 91 91 + if (rzg2l_cru_vclk_prepare(cru)) 92 92 + dev_err(cru->dev, "Failed to enable vclk\n"); 93 93 + } 94 94 + 95 95 + s_stream_ret = ret; 96 96 + 97 97 + v4l2_subdev_call(cru->ip.remote, video, post_streamoff); 98 98 + rzg2l_cru_stop_image_processing(cru); 99 99 + } 100 100 + 101 101 + return s_stream_ret; 102 102 + } 103 103 + 104 104 + static int rzg2l_cru_ip_set_format(struct v4l2_subdev *sd, 105 105 + struct v4l2_subdev_state *state, 106 106 + struct v4l2_subdev_format *fmt) 107 107 + { 108 108 + struct v4l2_mbus_framefmt *src_format; 109 109 + struct v4l2_mbus_framefmt *sink_format; 110 110 + 111 111 + src_format = v4l2_subdev_get_pad_format(sd, state, RZG2L_CRU_IP_SOURCE); 112 112 + if (fmt->pad == RZG2L_CRU_IP_SOURCE) { 113 113 + fmt->format = *src_format; 114 114 + return 0; 115 115 + } 116 116 + 117 117 + sink_format = v4l2_subdev_get_pad_format(sd, state, fmt->pad); 118 118 + 119 119 + if (!rzg2l_cru_ip_code_to_fmt(fmt->format.code)) 120 120 + sink_format->code = rzg2l_cru_ip_formats[0].code; 121 121 + else 122 122 + sink_format->code = fmt->format.code; 123 123 + 124 124 + sink_format->field = V4L2_FIELD_NONE; 125 125 + sink_format->colorspace = fmt->format.colorspace; 126 126 + sink_format->xfer_func = fmt->format.xfer_func; 127 127 + sink_format->ycbcr_enc = fmt->format.ycbcr_enc; 128 128 + sink_format->quantization = fmt->format.quantization; 129 129 + sink_format->width = clamp_t(u32, fmt->format.width, 130 130 + RZG2L_CRU_MIN_INPUT_WIDTH, RZG2L_CRU_MAX_INPUT_WIDTH); 131 131 + sink_format->height = clamp_t(u32, fmt->format.height, 132 132 + RZG2L_CRU_MIN_INPUT_HEIGHT, RZG2L_CRU_MAX_INPUT_HEIGHT); 133 133 + 134 134 + fmt->format = *sink_format; 135 135 + 136 136 + /* propagate format to source pad */ 137 137 + *src_format = *sink_format; 138 138 + 139 139 + return 0; 140 140 + } 141 141 + 142 142 + static int rzg2l_cru_ip_enum_mbus_code(struct v4l2_subdev *sd, 143 143 + struct v4l2_subdev_state *state, 144 144 + struct v4l2_subdev_mbus_code_enum *code) 145 145 + { 146 146 + if (code->index >= ARRAY_SIZE(rzg2l_cru_ip_formats)) 147 147 + return -EINVAL; 148 148 + 149 149 + code->code = rzg2l_cru_ip_formats[code->index].code; 150 150 + return 0; 151 151 + } 152 152 + 153 153 + static int rzg2l_cru_ip_enum_frame_size(struct v4l2_subdev *sd, 154 154 + struct v4l2_subdev_state *state, 155 155 + struct v4l2_subdev_frame_size_enum *fse) 156 156 + { 157 157 + if (fse->index != 0) 158 158 + return -EINVAL; 159 159 + 160 160 + if (fse->code != MEDIA_BUS_FMT_UYVY8_1X16) 161 161 + return -EINVAL; 162 162 + 163 163 + fse->min_width = RZG2L_CRU_MIN_INPUT_WIDTH; 164 164 + fse->min_height = RZG2L_CRU_MIN_INPUT_HEIGHT; 165 165 + fse->max_width = RZG2L_CRU_MAX_INPUT_WIDTH; 166 166 + fse->max_height = RZG2L_CRU_MAX_INPUT_HEIGHT; 167 167 + 168 168 + return 0; 169 169 + } 170 170 + 171 171 + static int rzg2l_cru_ip_init_config(struct v4l2_subdev *sd, 172 172 + struct v4l2_subdev_state *sd_state) 173 173 + { 174 174 + struct v4l2_subdev_format fmt = { .pad = RZG2L_CRU_IP_SINK, }; 175 175 + 176 176 + fmt.format.width = RZG2L_CRU_MIN_INPUT_WIDTH; 177 177 + fmt.format.height = RZG2L_CRU_MIN_INPUT_HEIGHT; 178 178 + fmt.format.field = V4L2_FIELD_NONE; 179 179 + fmt.format.code = MEDIA_BUS_FMT_UYVY8_1X16; 180 180 + fmt.format.colorspace = V4L2_COLORSPACE_SRGB; 181 181 + fmt.format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 182 182 + fmt.format.quantization = V4L2_QUANTIZATION_DEFAULT; 183 183 + fmt.format.xfer_func = V4L2_XFER_FUNC_DEFAULT; 184 184 + 185 185 + return rzg2l_cru_ip_set_format(sd, sd_state, &fmt); 186 186 + } 187 187 + 188 188 + static const struct v4l2_subdev_video_ops rzg2l_cru_ip_video_ops = { 189 189 + .s_stream = rzg2l_cru_ip_s_stream, 190 190 + }; 191 191 + 192 192 + static const struct v4l2_subdev_pad_ops rzg2l_cru_ip_pad_ops = { 193 193 + .enum_mbus_code = rzg2l_cru_ip_enum_mbus_code, 194 194 + .enum_frame_size = rzg2l_cru_ip_enum_frame_size, 195 195 + .init_cfg = rzg2l_cru_ip_init_config, 196 196 + .get_fmt = v4l2_subdev_get_fmt, 197 197 + .set_fmt = rzg2l_cru_ip_set_format, 198 198 + }; 199 199 + 200 200 + static const struct v4l2_subdev_ops rzg2l_cru_ip_subdev_ops = { 201 201 + .video = &rzg2l_cru_ip_video_ops, 202 202 + .pad = &rzg2l_cru_ip_pad_ops, 203 203 + }; 204 204 + 205 205 + static const struct media_entity_operations rzg2l_cru_ip_entity_ops = { 206 206 + .link_validate = v4l2_subdev_link_validate, 207 207 + }; 208 208 + 209 209 + int rzg2l_cru_ip_subdev_register(struct rzg2l_cru_dev *cru) 210 210 + { 211 211 + struct rzg2l_cru_ip *ip = &cru->ip; 212 212 + int ret; 213 213 + 214 214 + ip->subdev.dev = cru->dev; 215 215 + v4l2_subdev_init(&ip->subdev, &rzg2l_cru_ip_subdev_ops); 216 216 + v4l2_set_subdevdata(&ip->subdev, cru); 217 217 + snprintf(ip->subdev.name, sizeof(ip->subdev.name), 218 218 + "cru-ip-%s", dev_name(cru->dev)); 219 219 + ip->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE; 220 220 + 221 221 + ip->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; 222 222 + ip->subdev.entity.ops = &rzg2l_cru_ip_entity_ops; 223 223 + 224 224 + ip->pads[0].flags = MEDIA_PAD_FL_SINK; 225 225 + ip->pads[1].flags = MEDIA_PAD_FL_SOURCE; 226 226 + 227 227 + ret = media_entity_pads_init(&ip->subdev.entity, 2, ip->pads); 228 228 + if (ret) 229 229 + return ret; 230 230 + 231 231 + ret = v4l2_subdev_init_finalize(&ip->subdev); 232 232 + if (ret < 0) 233 233 + goto entity_cleanup; 234 234 + 235 235 + ret = v4l2_device_register_subdev(&cru->v4l2_dev, &ip->subdev); 236 236 + if (ret < 0) 237 237 + goto error_subdev; 238 238 + 239 239 + return 0; 240 240 + error_subdev: 241 241 + v4l2_subdev_cleanup(&ip->subdev); 242 242 + entity_cleanup: 243 243 + media_entity_cleanup(&ip->subdev.entity); 244 244 + 245 245 + return ret; 246 246 + } 247 247 + 248 248 + void rzg2l_cru_ip_subdev_unregister(struct rzg2l_cru_dev *cru) 249 249 + { 250 250 + struct rzg2l_cru_ip *ip = &cru->ip; 251 251 + 252 252 + media_entity_cleanup(&ip->subdev.entity); 253 253 + v4l2_subdev_cleanup(&ip->subdev); 254 254 + v4l2_device_unregister_subdev(&ip->subdev); 255 255 + }

+1057

drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0+ 2 2 + /* 3 3 + * Driver for Renesas RZ/G2L CRU 4 4 + * 5 5 + * Copyright (C) 2022 Renesas Electronics Corp. 6 6 + * 7 7 + * Based on Renesas R-Car VIN 8 8 + * Copyright (C) 2016 Renesas Electronics Corp. 9 9 + * Copyright (C) 2011-2013 Renesas Solutions Corp. 10 10 + * Copyright (C) 2013 Cogent Embedded, Inc., <source@cogentembedded.com> 11 11 + * Copyright (C) 2008 Magnus Damm 12 12 + */ 13 13 + 14 14 + #include <linux/clk.h> 15 15 + #include <linux/delay.h> 16 16 + #include <linux/pm_runtime.h> 17 17 + 18 18 + #include <media/v4l2-ioctl.h> 19 19 + #include <media/videobuf2-dma-contig.h> 20 20 + 21 21 + #include "rzg2l-cru.h" 22 22 + 23 23 + /* HW CRU Registers Definition */ 24 24 + 25 25 + /* CRU Control Register */ 26 26 + #define CRUnCTRL 0x0 27 27 + #define CRUnCTRL_VINSEL(x) ((x) << 0) 28 28 + 29 29 + /* CRU Interrupt Enable Register */ 30 30 + #define CRUnIE 0x4 31 31 + #define CRUnIE_EFE BIT(17) 32 32 + 33 33 + /* CRU Interrupt Status Register */ 34 34 + #define CRUnINTS 0x8 35 35 + #define CRUnINTS_SFS BIT(16) 36 36 + 37 37 + /* CRU Reset Register */ 38 38 + #define CRUnRST 0xc 39 39 + #define CRUnRST_VRESETN BIT(0) 40 40 + 41 41 + /* Memory Bank Base Address (Lower) Register for CRU Image Data */ 42 42 + #define AMnMBxADDRL(x) (0x100 + ((x) * 8)) 43 43 + 44 44 + /* Memory Bank Base Address (Higher) Register for CRU Image Data */ 45 45 + #define AMnMBxADDRH(x) (0x104 + ((x) * 8)) 46 46 + 47 47 + /* Memory Bank Enable Register for CRU Image Data */ 48 48 + #define AMnMBVALID 0x148 49 49 + #define AMnMBVALID_MBVALID(x) GENMASK(x, 0) 50 50 + 51 51 + /* Memory Bank Status Register for CRU Image Data */ 52 52 + #define AMnMBS 0x14c 53 53 + #define AMnMBS_MBSTS 0x7 54 54 + 55 55 + /* AXI Master FIFO Pointer Register for CRU Image Data */ 56 56 + #define AMnFIFOPNTR 0x168 57 57 + #define AMnFIFOPNTR_FIFOWPNTR GENMASK(7, 0) 58 58 + #define AMnFIFOPNTR_FIFORPNTR_Y GENMASK(23, 16) 59 59 + 60 60 + /* AXI Master Transfer Stop Register for CRU Image Data */ 61 61 + #define AMnAXISTP 0x174 62 62 + #define AMnAXISTP_AXI_STOP BIT(0) 63 63 + 64 64 + /* AXI Master Transfer Stop Status Register for CRU Image Data */ 65 65 + #define AMnAXISTPACK 0x178 66 66 + #define AMnAXISTPACK_AXI_STOP_ACK BIT(0) 67 67 + 68 68 + /* CRU Image Processing Enable Register */ 69 69 + #define ICnEN 0x200 70 70 + #define ICnEN_ICEN BIT(0) 71 71 + 72 72 + /* CRU Image Processing Main Control Register */ 73 73 + #define ICnMC 0x208 74 74 + #define ICnMC_CSCTHR BIT(5) 75 75 + #define ICnMC_INF_YUV8_422 (0x1e << 16) 76 76 + #define ICnMC_INF_USER (0x30 << 16) 77 77 + #define ICnMC_VCSEL(x) ((x) << 22) 78 78 + #define ICnMC_INF_MASK GENMASK(21, 16) 79 79 + 80 80 + /* CRU Module Status Register */ 81 81 + #define ICnMS 0x254 82 82 + #define ICnMS_IA BIT(2) 83 83 + 84 84 + /* CRU Data Output Mode Register */ 85 85 + #define ICnDMR 0x26c 86 86 + #define ICnDMR_YCMODE_UYVY (1 << 4) 87 87 + 88 88 + #define RZG2L_TIMEOUT_MS 100 89 89 + #define RZG2L_RETRIES 10 90 90 + 91 91 + #define RZG2L_CRU_DEFAULT_FORMAT V4L2_PIX_FMT_UYVY 92 92 + #define RZG2L_CRU_DEFAULT_WIDTH RZG2L_CRU_MIN_INPUT_WIDTH 93 93 + #define RZG2L_CRU_DEFAULT_HEIGHT RZG2L_CRU_MIN_INPUT_HEIGHT 94 94 + #define RZG2L_CRU_DEFAULT_FIELD V4L2_FIELD_NONE 95 95 + #define RZG2L_CRU_DEFAULT_COLORSPACE V4L2_COLORSPACE_SRGB 96 96 + 97 97 + struct rzg2l_cru_buffer { 98 98 + struct vb2_v4l2_buffer vb; 99 99 + struct list_head list; 100 100 + }; 101 101 + 102 102 + #define to_buf_list(vb2_buffer) \ 103 103 + (&container_of(vb2_buffer, struct rzg2l_cru_buffer, vb)->list) 104 104 + 105 105 + /* ----------------------------------------------------------------------------- 106 106 + * DMA operations 107 107 + */ 108 108 + static void rzg2l_cru_write(struct rzg2l_cru_dev *cru, u32 offset, u32 value) 109 109 + { 110 110 + iowrite32(value, cru->base + offset); 111 111 + } 112 112 + 113 113 + static u32 rzg2l_cru_read(struct rzg2l_cru_dev *cru, u32 offset) 114 114 + { 115 115 + return ioread32(cru->base + offset); 116 116 + } 117 117 + 118 118 + /* Need to hold qlock before calling */ 119 119 + static void return_unused_buffers(struct rzg2l_cru_dev *cru, 120 120 + enum vb2_buffer_state state) 121 121 + { 122 122 + struct rzg2l_cru_buffer *buf, *node; 123 123 + unsigned long flags; 124 124 + unsigned int i; 125 125 + 126 126 + spin_lock_irqsave(&cru->qlock, flags); 127 127 + for (i = 0; i < cru->num_buf; i++) { 128 128 + if (cru->queue_buf[i]) { 129 129 + vb2_buffer_done(&cru->queue_buf[i]->vb2_buf, 130 130 + state); 131 131 + cru->queue_buf[i] = NULL; 132 132 + } 133 133 + } 134 134 + 135 135 + list_for_each_entry_safe(buf, node, &cru->buf_list, list) { 136 136 + vb2_buffer_done(&buf->vb.vb2_buf, state); 137 137 + list_del(&buf->list); 138 138 + } 139 139 + spin_unlock_irqrestore(&cru->qlock, flags); 140 140 + } 141 141 + 142 142 + static int rzg2l_cru_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers, 143 143 + unsigned int *nplanes, unsigned int sizes[], 144 144 + struct device *alloc_devs[]) 145 145 + { 146 146 + struct rzg2l_cru_dev *cru = vb2_get_drv_priv(vq); 147 147 + 148 148 + /* Make sure the image size is large enough. */ 149 149 + if (*nplanes) 150 150 + return sizes[0] < cru->format.sizeimage ? -EINVAL : 0; 151 151 + 152 152 + *nplanes = 1; 153 153 + sizes[0] = cru->format.sizeimage; 154 154 + 155 155 + return 0; 156 156 + }; 157 157 + 158 158 + static int rzg2l_cru_buffer_prepare(struct vb2_buffer *vb) 159 159 + { 160 160 + struct rzg2l_cru_dev *cru = vb2_get_drv_priv(vb->vb2_queue); 161 161 + unsigned long size = cru->format.sizeimage; 162 162 + 163 163 + if (vb2_plane_size(vb, 0) < size) { 164 164 + dev_err(cru->dev, "buffer too small (%lu < %lu)\n", 165 165 + vb2_plane_size(vb, 0), size); 166 166 + return -EINVAL; 167 167 + } 168 168 + 169 169 + vb2_set_plane_payload(vb, 0, size); 170 170 + 171 171 + return 0; 172 172 + } 173 173 + 174 174 + static void rzg2l_cru_buffer_queue(struct vb2_buffer *vb) 175 175 + { 176 176 + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 177 177 + struct rzg2l_cru_dev *cru = vb2_get_drv_priv(vb->vb2_queue); 178 178 + unsigned long flags; 179 179 + 180 180 + spin_lock_irqsave(&cru->qlock, flags); 181 181 + 182 182 + list_add_tail(to_buf_list(vbuf), &cru->buf_list); 183 183 + 184 184 + spin_unlock_irqrestore(&cru->qlock, flags); 185 185 + } 186 186 + 187 187 + static int rzg2l_cru_mc_validate_format(struct rzg2l_cru_dev *cru, 188 188 + struct v4l2_subdev *sd, 189 189 + struct media_pad *pad) 190 190 + { 191 191 + struct v4l2_subdev_format fmt = { 192 192 + .which = V4L2_SUBDEV_FORMAT_ACTIVE, 193 193 + }; 194 194 + 195 195 + fmt.pad = pad->index; 196 196 + if (v4l2_subdev_call_state_active(sd, pad, get_fmt, &fmt)) 197 197 + return -EPIPE; 198 198 + 199 199 + switch (fmt.format.code) { 200 200 + case MEDIA_BUS_FMT_UYVY8_1X16: 201 201 + break; 202 202 + default: 203 203 + return -EPIPE; 204 204 + } 205 205 + 206 206 + switch (fmt.format.field) { 207 207 + case V4L2_FIELD_TOP: 208 208 + case V4L2_FIELD_BOTTOM: 209 209 + case V4L2_FIELD_NONE: 210 210 + case V4L2_FIELD_INTERLACED_TB: 211 211 + case V4L2_FIELD_INTERLACED_BT: 212 212 + case V4L2_FIELD_INTERLACED: 213 213 + case V4L2_FIELD_SEQ_TB: 214 214 + case V4L2_FIELD_SEQ_BT: 215 215 + break; 216 216 + default: 217 217 + return -EPIPE; 218 218 + } 219 219 + 220 220 + if (fmt.format.width != cru->format.width || 221 221 + fmt.format.height != cru->format.height) 222 222 + return -EPIPE; 223 223 + 224 224 + return 0; 225 225 + } 226 226 + 227 227 + static void rzg2l_cru_set_slot_addr(struct rzg2l_cru_dev *cru, 228 228 + int slot, dma_addr_t addr) 229 229 + { 230 230 + /* 231 231 + * The address needs to be 512 bytes aligned. Driver should never accept 232 232 + * settings that do not satisfy this in the first place... 233 233 + */ 234 234 + if (WARN_ON((addr) & RZG2L_CRU_HW_BUFFER_MASK)) 235 235 + return; 236 236 + 237 237 + /* Currently, we just use the buffer in 32 bits address */ 238 238 + rzg2l_cru_write(cru, AMnMBxADDRL(slot), addr); 239 239 + rzg2l_cru_write(cru, AMnMBxADDRH(slot), 0); 240 240 + } 241 241 + 242 242 + /* 243 243 + * Moves a buffer from the queue to the HW slot. If no buffer is 244 244 + * available use the scratch buffer. The scratch buffer is never 245 245 + * returned to userspace, its only function is to enable the capture 246 246 + * loop to keep running. 247 247 + */ 248 248 + static void rzg2l_cru_fill_hw_slot(struct rzg2l_cru_dev *cru, int slot) 249 249 + { 250 250 + struct vb2_v4l2_buffer *vbuf; 251 251 + struct rzg2l_cru_buffer *buf; 252 252 + dma_addr_t phys_addr; 253 253 + 254 254 + /* A already populated slot shall never be overwritten. */ 255 255 + if (WARN_ON(cru->queue_buf[slot])) 256 256 + return; 257 257 + 258 258 + dev_dbg(cru->dev, "Filling HW slot: %d\n", slot); 259 259 + 260 260 + if (list_empty(&cru->buf_list)) { 261 261 + cru->queue_buf[slot] = NULL; 262 262 + phys_addr = cru->scratch_phys; 263 263 + } else { 264 264 + /* Keep track of buffer we give to HW */ 265 265 + buf = list_entry(cru->buf_list.next, 266 266 + struct rzg2l_cru_buffer, list); 267 267 + vbuf = &buf->vb; 268 268 + list_del_init(to_buf_list(vbuf)); 269 269 + cru->queue_buf[slot] = vbuf; 270 270 + 271 271 + /* Setup DMA */ 272 272 + phys_addr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); 273 273 + } 274 274 + 275 275 + rzg2l_cru_set_slot_addr(cru, slot, phys_addr); 276 276 + } 277 277 + 278 278 + static void rzg2l_cru_initialize_axi(struct rzg2l_cru_dev *cru) 279 279 + { 280 280 + unsigned int slot; 281 281 + 282 282 + /* 283 283 + * Set image data memory banks. 284 284 + * Currently, we will use maximum address. 285 285 + */ 286 286 + rzg2l_cru_write(cru, AMnMBVALID, AMnMBVALID_MBVALID(cru->num_buf - 1)); 287 287 + 288 288 + for (slot = 0; slot < cru->num_buf; slot++) 289 289 + rzg2l_cru_fill_hw_slot(cru, slot); 290 290 + } 291 291 + 292 292 + static void rzg2l_cru_csi2_setup(struct rzg2l_cru_dev *cru, bool *input_is_yuv, 293 293 + struct v4l2_mbus_framefmt *ip_sd_fmt) 294 294 + { 295 295 + u32 icnmc; 296 296 + 297 297 + switch (ip_sd_fmt->code) { 298 298 + case MEDIA_BUS_FMT_UYVY8_1X16: 299 299 + icnmc = ICnMC_INF_YUV8_422; 300 300 + *input_is_yuv = true; 301 301 + break; 302 302 + default: 303 303 + *input_is_yuv = false; 304 304 + icnmc = ICnMC_INF_USER; 305 305 + break; 306 306 + } 307 307 + 308 308 + icnmc |= (rzg2l_cru_read(cru, ICnMC) & ~ICnMC_INF_MASK); 309 309 + 310 310 + /* Set virtual channel CSI2 */ 311 311 + icnmc |= ICnMC_VCSEL(cru->csi.channel); 312 312 + 313 313 + rzg2l_cru_write(cru, ICnMC, icnmc); 314 314 + } 315 315 + 316 316 + static int rzg2l_cru_initialize_image_conv(struct rzg2l_cru_dev *cru, 317 317 + struct v4l2_mbus_framefmt *ip_sd_fmt) 318 318 + { 319 319 + bool output_is_yuv = false; 320 320 + bool input_is_yuv = false; 321 321 + u32 icndmr; 322 322 + 323 323 + rzg2l_cru_csi2_setup(cru, &input_is_yuv, ip_sd_fmt); 324 324 + 325 325 + /* Output format */ 326 326 + switch (cru->format.pixelformat) { 327 327 + case V4L2_PIX_FMT_UYVY: 328 328 + icndmr = ICnDMR_YCMODE_UYVY; 329 329 + output_is_yuv = true; 330 330 + break; 331 331 + default: 332 332 + dev_err(cru->dev, "Invalid pixelformat (0x%x)\n", 333 333 + cru->format.pixelformat); 334 334 + return -EINVAL; 335 335 + } 336 336 + 337 337 + /* If input and output use same colorspace, do bypass mode */ 338 338 + if (output_is_yuv == input_is_yuv) 339 339 + rzg2l_cru_write(cru, ICnMC, 340 340 + rzg2l_cru_read(cru, ICnMC) | ICnMC_CSCTHR); 341 341 + else 342 342 + rzg2l_cru_write(cru, ICnMC, 343 343 + rzg2l_cru_read(cru, ICnMC) & (~ICnMC_CSCTHR)); 344 344 + 345 345 + /* Set output data format */ 346 346 + rzg2l_cru_write(cru, ICnDMR, icndmr); 347 347 + 348 348 + return 0; 349 349 + } 350 350 + 351 351 + void rzg2l_cru_stop_image_processing(struct rzg2l_cru_dev *cru) 352 352 + { 353 353 + u32 amnfifopntr, amnfifopntr_w, amnfifopntr_r_y; 354 354 + unsigned int retries = 0; 355 355 + unsigned long flags; 356 356 + u32 icnms; 357 357 + 358 358 + spin_lock_irqsave(&cru->qlock, flags); 359 359 + 360 360 + /* Disable and clear the interrupt */ 361 361 + rzg2l_cru_write(cru, CRUnIE, 0); 362 362 + rzg2l_cru_write(cru, CRUnINTS, 0x001F0F0F); 363 363 + 364 364 + /* Stop the operation of image conversion */ 365 365 + rzg2l_cru_write(cru, ICnEN, 0); 366 366 + 367 367 + /* Wait for streaming to stop */ 368 368 + while ((rzg2l_cru_read(cru, ICnMS) & ICnMS_IA) && retries++ < RZG2L_RETRIES) { 369 369 + spin_unlock_irqrestore(&cru->qlock, flags); 370 370 + msleep(RZG2L_TIMEOUT_MS); 371 371 + spin_lock_irqsave(&cru->qlock, flags); 372 372 + } 373 373 + 374 374 + icnms = rzg2l_cru_read(cru, ICnMS) & ICnMS_IA; 375 375 + if (icnms) 376 376 + dev_err(cru->dev, "Failed stop HW, something is seriously broken\n"); 377 377 + 378 378 + cru->state = RZG2L_CRU_DMA_STOPPED; 379 379 + 380 380 + /* Wait until the FIFO becomes empty */ 381 381 + for (retries = 5; retries > 0; retries--) { 382 382 + amnfifopntr = rzg2l_cru_read(cru, AMnFIFOPNTR); 383 383 + 384 384 + amnfifopntr_w = amnfifopntr & AMnFIFOPNTR_FIFOWPNTR; 385 385 + amnfifopntr_r_y = 386 386 + (amnfifopntr & AMnFIFOPNTR_FIFORPNTR_Y) >> 16; 387 387 + if (amnfifopntr_w == amnfifopntr_r_y) 388 388 + break; 389 389 + 390 390 + usleep_range(10, 20); 391 391 + } 392 392 + 393 393 + /* Notify that FIFO is not empty here */ 394 394 + if (!retries) 395 395 + dev_err(cru->dev, "Failed to empty FIFO\n"); 396 396 + 397 397 + /* Stop AXI bus */ 398 398 + rzg2l_cru_write(cru, AMnAXISTP, AMnAXISTP_AXI_STOP); 399 399 + 400 400 + /* Wait until the AXI bus stop */ 401 401 + for (retries = 5; retries > 0; retries--) { 402 402 + if (rzg2l_cru_read(cru, AMnAXISTPACK) & 403 403 + AMnAXISTPACK_AXI_STOP_ACK) 404 404 + break; 405 405 + 406 406 + usleep_range(10, 20); 407 407 + }; 408 408 + 409 409 + /* Notify that AXI bus can not stop here */ 410 410 + if (!retries) 411 411 + dev_err(cru->dev, "Failed to stop AXI bus\n"); 412 412 + 413 413 + /* Cancel the AXI bus stop request */ 414 414 + rzg2l_cru_write(cru, AMnAXISTP, 0); 415 415 + 416 416 + /* Reset the CRU (AXI-master) */ 417 417 + reset_control_assert(cru->aresetn); 418 418 + 419 419 + /* Resets the image processing module */ 420 420 + rzg2l_cru_write(cru, CRUnRST, 0); 421 421 + 422 422 + spin_unlock_irqrestore(&cru->qlock, flags); 423 423 + } 424 424 + 425 425 + int rzg2l_cru_start_image_processing(struct rzg2l_cru_dev *cru) 426 426 + { 427 427 + struct v4l2_mbus_framefmt *fmt = rzg2l_cru_ip_get_src_fmt(cru); 428 428 + unsigned long flags; 429 429 + int ret; 430 430 + 431 431 + spin_lock_irqsave(&cru->qlock, flags); 432 432 + 433 433 + /* Initialize image convert */ 434 434 + ret = rzg2l_cru_initialize_image_conv(cru, fmt); 435 435 + if (ret) { 436 436 + spin_unlock_irqrestore(&cru->qlock, flags); 437 437 + return ret; 438 438 + } 439 439 + 440 440 + /* Select a video input */ 441 441 + rzg2l_cru_write(cru, CRUnCTRL, CRUnCTRL_VINSEL(0)); 442 442 + 443 443 + /* Cancel the software reset for image processing block */ 444 444 + rzg2l_cru_write(cru, CRUnRST, CRUnRST_VRESETN); 445 445 + 446 446 + /* Disable and clear the interrupt before using */ 447 447 + rzg2l_cru_write(cru, CRUnIE, 0); 448 448 + rzg2l_cru_write(cru, CRUnINTS, 0x001f000f); 449 449 + 450 450 + /* Initialize the AXI master */ 451 451 + rzg2l_cru_initialize_axi(cru); 452 452 + 453 453 + /* Enable interrupt */ 454 454 + rzg2l_cru_write(cru, CRUnIE, CRUnIE_EFE); 455 455 + 456 456 + /* Enable image processing reception */ 457 457 + rzg2l_cru_write(cru, ICnEN, ICnEN_ICEN); 458 458 + 459 459 + spin_unlock_irqrestore(&cru->qlock, flags); 460 460 + 461 461 + return 0; 462 462 + } 463 463 + 464 464 + void rzg2l_cru_vclk_unprepare(struct rzg2l_cru_dev *cru) 465 465 + { 466 466 + clk_disable_unprepare(cru->vclk); 467 467 + } 468 468 + 469 469 + int rzg2l_cru_vclk_prepare(struct rzg2l_cru_dev *cru) 470 470 + { 471 471 + return clk_prepare_enable(cru->vclk); 472 472 + } 473 473 + 474 474 + static int rzg2l_cru_set_stream(struct rzg2l_cru_dev *cru, int on) 475 475 + { 476 476 + struct media_pipeline *pipe; 477 477 + struct v4l2_subdev *sd; 478 478 + struct media_pad *pad; 479 479 + int ret; 480 480 + 481 481 + pad = media_pad_remote_pad_first(&cru->pad); 482 482 + if (!pad) 483 483 + return -EPIPE; 484 484 + 485 485 + sd = media_entity_to_v4l2_subdev(pad->entity); 486 486 + 487 487 + if (!on) { 488 488 + int stream_off_ret = 0; 489 489 + 490 490 + ret = v4l2_subdev_call(sd, video, s_stream, 0); 491 491 + if (ret) 492 492 + stream_off_ret = ret; 493 493 + 494 494 + ret = v4l2_subdev_call(sd, video, post_streamoff); 495 495 + if (ret == -ENOIOCTLCMD) 496 496 + ret = 0; 497 497 + if (ret && !stream_off_ret) 498 498 + stream_off_ret = ret; 499 499 + 500 500 + video_device_pipeline_stop(&cru->vdev); 501 501 + 502 502 + pm_runtime_put_sync(cru->dev); 503 503 + clk_disable_unprepare(cru->vclk); 504 504 + 505 505 + return stream_off_ret; 506 506 + } 507 507 + 508 508 + ret = pm_runtime_resume_and_get(cru->dev); 509 509 + if (ret) 510 510 + return ret; 511 511 + 512 512 + ret = clk_prepare_enable(cru->vclk); 513 513 + if (ret) 514 514 + goto err_pm_put; 515 515 + 516 516 + ret = rzg2l_cru_mc_validate_format(cru, sd, pad); 517 517 + if (ret) 518 518 + goto err_vclk_disable; 519 519 + 520 520 + pipe = media_entity_pipeline(&sd->entity) ? : &cru->vdev.pipe; 521 521 + ret = video_device_pipeline_start(&cru->vdev, pipe); 522 522 + if (ret) 523 523 + goto err_vclk_disable; 524 524 + 525 525 + ret = v4l2_subdev_call(sd, video, pre_streamon, 0); 526 526 + if (ret == -ENOIOCTLCMD) 527 527 + ret = 0; 528 528 + if (ret) 529 529 + goto pipe_line_stop; 530 530 + 531 531 + ret = v4l2_subdev_call(sd, video, s_stream, 1); 532 532 + if (ret == -ENOIOCTLCMD) 533 533 + ret = 0; 534 534 + if (ret) 535 535 + goto err_s_stream; 536 536 + 537 537 + return 0; 538 538 + 539 539 + err_s_stream: 540 540 + v4l2_subdev_call(sd, video, post_streamoff); 541 541 + 542 542 + pipe_line_stop: 543 543 + video_device_pipeline_stop(&cru->vdev); 544 544 + 545 545 + err_vclk_disable: 546 546 + clk_disable_unprepare(cru->vclk); 547 547 + 548 548 + err_pm_put: 549 549 + pm_runtime_put_sync(cru->dev); 550 550 + 551 551 + return ret; 552 552 + } 553 553 + 554 554 + static void rzg2l_cru_stop_streaming(struct rzg2l_cru_dev *cru) 555 555 + { 556 556 + cru->state = RZG2L_CRU_DMA_STOPPING; 557 557 + 558 558 + rzg2l_cru_set_stream(cru, 0); 559 559 + } 560 560 + 561 561 + static irqreturn_t rzg2l_cru_irq(int irq, void *data) 562 562 + { 563 563 + struct rzg2l_cru_dev *cru = data; 564 564 + unsigned int handled = 0; 565 565 + unsigned long flags; 566 566 + u32 irq_status; 567 567 + u32 amnmbs; 568 568 + int slot; 569 569 + 570 570 + spin_lock_irqsave(&cru->qlock, flags); 571 571 + 572 572 + irq_status = rzg2l_cru_read(cru, CRUnINTS); 573 573 + if (!irq_status) 574 574 + goto done; 575 575 + 576 576 + handled = 1; 577 577 + 578 578 + rzg2l_cru_write(cru, CRUnINTS, rzg2l_cru_read(cru, CRUnINTS)); 579 579 + 580 580 + /* Nothing to do if capture status is 'RZG2L_CRU_DMA_STOPPED' */ 581 581 + if (cru->state == RZG2L_CRU_DMA_STOPPED) { 582 582 + dev_dbg(cru->dev, "IRQ while state stopped\n"); 583 583 + goto done; 584 584 + } 585 585 + 586 586 + /* Increase stop retries if capture status is 'RZG2L_CRU_DMA_STOPPING' */ 587 587 + if (cru->state == RZG2L_CRU_DMA_STOPPING) { 588 588 + if (irq_status & CRUnINTS_SFS) 589 589 + dev_dbg(cru->dev, "IRQ while state stopping\n"); 590 590 + goto done; 591 591 + } 592 592 + 593 593 + /* Prepare for capture and update state */ 594 594 + amnmbs = rzg2l_cru_read(cru, AMnMBS); 595 595 + slot = amnmbs & AMnMBS_MBSTS; 596 596 + 597 597 + /* 598 598 + * AMnMBS.MBSTS indicates the destination of Memory Bank (MB). 599 599 + * Recalculate to get the current transfer complete MB. 600 600 + */ 601 601 + if (slot == 0) 602 602 + slot = cru->num_buf - 1; 603 603 + else 604 604 + slot--; 605 605 + 606 606 + /* 607 607 + * To hand buffers back in a known order to userspace start 608 608 + * to capture first from slot 0. 609 609 + */ 610 610 + if (cru->state == RZG2L_CRU_DMA_STARTING) { 611 611 + if (slot != 0) { 612 612 + dev_dbg(cru->dev, "Starting sync slot: %d\n", slot); 613 613 + goto done; 614 614 + } 615 615 + 616 616 + dev_dbg(cru->dev, "Capture start synced!\n"); 617 617 + cru->state = RZG2L_CRU_DMA_RUNNING; 618 618 + } 619 619 + 620 620 + /* Capture frame */ 621 621 + if (cru->queue_buf[slot]) { 622 622 + cru->queue_buf[slot]->field = cru->format.field; 623 623 + cru->queue_buf[slot]->sequence = cru->sequence; 624 624 + cru->queue_buf[slot]->vb2_buf.timestamp = ktime_get_ns(); 625 625 + vb2_buffer_done(&cru->queue_buf[slot]->vb2_buf, 626 626 + VB2_BUF_STATE_DONE); 627 627 + cru->queue_buf[slot] = NULL; 628 628 + } else { 629 629 + /* Scratch buffer was used, dropping frame. */ 630 630 + dev_dbg(cru->dev, "Dropping frame %u\n", cru->sequence); 631 631 + } 632 632 + 633 633 + cru->sequence++; 634 634 + 635 635 + /* Prepare for next frame */ 636 636 + rzg2l_cru_fill_hw_slot(cru, slot); 637 637 + 638 638 + done: 639 639 + spin_unlock_irqrestore(&cru->qlock, flags); 640 640 + 641 641 + return IRQ_RETVAL(handled); 642 642 + } 643 643 + 644 644 + static int rzg2l_cru_start_streaming_vq(struct vb2_queue *vq, unsigned int count) 645 645 + { 646 646 + struct rzg2l_cru_dev *cru = vb2_get_drv_priv(vq); 647 647 + int ret; 648 648 + 649 649 + /* Release reset state */ 650 650 + ret = reset_control_deassert(cru->aresetn); 651 651 + if (ret) { 652 652 + dev_err(cru->dev, "failed to deassert aresetn\n"); 653 653 + return ret; 654 654 + } 655 655 + 656 656 + ret = reset_control_deassert(cru->presetn); 657 657 + if (ret) { 658 658 + reset_control_assert(cru->aresetn); 659 659 + dev_err(cru->dev, "failed to deassert presetn\n"); 660 660 + return ret; 661 661 + } 662 662 + 663 663 + ret = request_irq(cru->image_conv_irq, rzg2l_cru_irq, 664 664 + IRQF_SHARED, KBUILD_MODNAME, cru); 665 665 + if (ret) { 666 666 + dev_err(cru->dev, "failed to request irq\n"); 667 667 + goto assert_resets; 668 668 + } 669 669 + 670 670 + /* Allocate scratch buffer. */ 671 671 + cru->scratch = dma_alloc_coherent(cru->dev, cru->format.sizeimage, 672 672 + &cru->scratch_phys, GFP_KERNEL); 673 673 + if (!cru->scratch) { 674 674 + return_unused_buffers(cru, VB2_BUF_STATE_QUEUED); 675 675 + dev_err(cru->dev, "Failed to allocate scratch buffer\n"); 676 676 + goto free_image_conv_irq; 677 677 + } 678 678 + 679 679 + cru->sequence = 0; 680 680 + 681 681 + ret = rzg2l_cru_set_stream(cru, 1); 682 682 + if (ret) { 683 683 + return_unused_buffers(cru, VB2_BUF_STATE_QUEUED); 684 684 + goto out; 685 685 + } 686 686 + 687 687 + cru->state = RZG2L_CRU_DMA_STARTING; 688 688 + dev_dbg(cru->dev, "Starting to capture\n"); 689 689 + return 0; 690 690 + 691 691 + out: 692 692 + if (ret) 693 693 + dma_free_coherent(cru->dev, cru->format.sizeimage, cru->scratch, 694 694 + cru->scratch_phys); 695 695 + free_image_conv_irq: 696 696 + free_irq(cru->image_conv_irq, cru); 697 697 + 698 698 + assert_resets: 699 699 + reset_control_assert(cru->presetn); 700 700 + reset_control_assert(cru->aresetn); 701 701 + 702 702 + return ret; 703 703 + } 704 704 + 705 705 + static void rzg2l_cru_stop_streaming_vq(struct vb2_queue *vq) 706 706 + { 707 707 + struct rzg2l_cru_dev *cru = vb2_get_drv_priv(vq); 708 708 + 709 709 + rzg2l_cru_stop_streaming(cru); 710 710 + 711 711 + /* Free scratch buffer */ 712 712 + dma_free_coherent(cru->dev, cru->format.sizeimage, 713 713 + cru->scratch, cru->scratch_phys); 714 714 + 715 715 + free_irq(cru->image_conv_irq, cru); 716 716 + reset_control_assert(cru->presetn); 717 717 + 718 718 + return_unused_buffers(cru, VB2_BUF_STATE_ERROR); 719 719 + } 720 720 + 721 721 + static const struct vb2_ops rzg2l_cru_qops = { 722 722 + .queue_setup = rzg2l_cru_queue_setup, 723 723 + .buf_prepare = rzg2l_cru_buffer_prepare, 724 724 + .buf_queue = rzg2l_cru_buffer_queue, 725 725 + .start_streaming = rzg2l_cru_start_streaming_vq, 726 726 + .stop_streaming = rzg2l_cru_stop_streaming_vq, 727 727 + .wait_prepare = vb2_ops_wait_prepare, 728 728 + .wait_finish = vb2_ops_wait_finish, 729 729 + }; 730 730 + 731 731 + void rzg2l_cru_dma_unregister(struct rzg2l_cru_dev *cru) 732 732 + { 733 733 + mutex_destroy(&cru->lock); 734 734 + 735 735 + v4l2_device_unregister(&cru->v4l2_dev); 736 736 + vb2_queue_release(&cru->queue); 737 737 + } 738 738 + 739 739 + int rzg2l_cru_dma_register(struct rzg2l_cru_dev *cru) 740 740 + { 741 741 + struct vb2_queue *q = &cru->queue; 742 742 + unsigned int i; 743 743 + int ret; 744 744 + 745 745 + /* Initialize the top-level structure */ 746 746 + ret = v4l2_device_register(cru->dev, &cru->v4l2_dev); 747 747 + if (ret) 748 748 + return ret; 749 749 + 750 750 + mutex_init(&cru->lock); 751 751 + INIT_LIST_HEAD(&cru->buf_list); 752 752 + 753 753 + spin_lock_init(&cru->qlock); 754 754 + 755 755 + cru->state = RZG2L_CRU_DMA_STOPPED; 756 756 + 757 757 + for (i = 0; i < RZG2L_CRU_HW_BUFFER_MAX; i++) 758 758 + cru->queue_buf[i] = NULL; 759 759 + 760 760 + /* buffer queue */ 761 761 + q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 762 762 + q->io_modes = VB2_MMAP | VB2_DMABUF; 763 763 + q->lock = &cru->lock; 764 764 + q->drv_priv = cru; 765 765 + q->buf_struct_size = sizeof(struct rzg2l_cru_buffer); 766 766 + q->ops = &rzg2l_cru_qops; 767 767 + q->mem_ops = &vb2_dma_contig_memops; 768 768 + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 769 769 + q->min_buffers_needed = 4; 770 770 + q->dev = cru->dev; 771 771 + 772 772 + ret = vb2_queue_init(q); 773 773 + if (ret < 0) { 774 774 + dev_err(cru->dev, "failed to initialize VB2 queue\n"); 775 775 + goto error; 776 776 + } 777 777 + 778 778 + return 0; 779 779 + 780 780 + error: 781 781 + mutex_destroy(&cru->lock); 782 782 + v4l2_device_unregister(&cru->v4l2_dev); 783 783 + return ret; 784 784 + } 785 785 + 786 786 + /* ----------------------------------------------------------------------------- 787 787 + * V4L2 stuff 788 788 + */ 789 789 + 790 790 + static const struct v4l2_format_info rzg2l_cru_formats[] = { 791 791 + { 792 792 + .format = V4L2_PIX_FMT_UYVY, 793 793 + .bpp[0] = 2, 794 794 + }, 795 795 + }; 796 796 + 797 797 + const struct v4l2_format_info *rzg2l_cru_format_from_pixel(u32 format) 798 798 + { 799 799 + unsigned int i; 800 800 + 801 801 + for (i = 0; i < ARRAY_SIZE(rzg2l_cru_formats); i++) 802 802 + if (rzg2l_cru_formats[i].format == format) 803 803 + return rzg2l_cru_formats + i; 804 804 + 805 805 + return NULL; 806 806 + } 807 807 + 808 808 + static u32 rzg2l_cru_format_bytesperline(struct v4l2_pix_format *pix) 809 809 + { 810 810 + const struct v4l2_format_info *fmt; 811 811 + 812 812 + fmt = rzg2l_cru_format_from_pixel(pix->pixelformat); 813 813 + 814 814 + if (WARN_ON(!fmt)) 815 815 + return -EINVAL; 816 816 + 817 817 + return pix->width * fmt->bpp[0]; 818 818 + } 819 819 + 820 820 + static u32 rzg2l_cru_format_sizeimage(struct v4l2_pix_format *pix) 821 821 + { 822 822 + return pix->bytesperline * pix->height; 823 823 + } 824 824 + 825 825 + static void rzg2l_cru_format_align(struct rzg2l_cru_dev *cru, 826 826 + struct v4l2_pix_format *pix) 827 827 + { 828 828 + if (!rzg2l_cru_format_from_pixel(pix->pixelformat)) 829 829 + pix->pixelformat = RZG2L_CRU_DEFAULT_FORMAT; 830 830 + 831 831 + switch (pix->field) { 832 832 + case V4L2_FIELD_TOP: 833 833 + case V4L2_FIELD_BOTTOM: 834 834 + case V4L2_FIELD_NONE: 835 835 + case V4L2_FIELD_INTERLACED_TB: 836 836 + case V4L2_FIELD_INTERLACED_BT: 837 837 + case V4L2_FIELD_INTERLACED: 838 838 + break; 839 839 + default: 840 840 + pix->field = RZG2L_CRU_DEFAULT_FIELD; 841 841 + break; 842 842 + } 843 843 + 844 844 + /* Limit to CRU capabilities */ 845 845 + v4l_bound_align_image(&pix->width, 320, RZG2L_CRU_MAX_INPUT_WIDTH, 1, 846 846 + &pix->height, 240, RZG2L_CRU_MAX_INPUT_HEIGHT, 2, 0); 847 847 + 848 848 + pix->bytesperline = rzg2l_cru_format_bytesperline(pix); 849 849 + pix->sizeimage = rzg2l_cru_format_sizeimage(pix); 850 850 + 851 851 + dev_dbg(cru->dev, "Format %ux%u bpl: %u size: %u\n", 852 852 + pix->width, pix->height, pix->bytesperline, pix->sizeimage); 853 853 + } 854 854 + 855 855 + static void rzg2l_cru_try_format(struct rzg2l_cru_dev *cru, 856 856 + struct v4l2_pix_format *pix) 857 857 + { 858 858 + /* 859 859 + * The V4L2 specification clearly documents the colorspace fields 860 860 + * as being set by drivers for capture devices. Using the values 861 861 + * supplied by userspace thus wouldn't comply with the API. Until 862 862 + * the API is updated force fixed values. 863 863 + */ 864 864 + pix->colorspace = RZG2L_CRU_DEFAULT_COLORSPACE; 865 865 + pix->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(pix->colorspace); 866 866 + pix->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(pix->colorspace); 867 867 + pix->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true, pix->colorspace, 868 868 + pix->ycbcr_enc); 869 869 + 870 870 + rzg2l_cru_format_align(cru, pix); 871 871 + } 872 872 + 873 873 + static int rzg2l_cru_querycap(struct file *file, void *priv, 874 874 + struct v4l2_capability *cap) 875 875 + { 876 876 + strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver)); 877 877 + strscpy(cap->card, "RZG2L_CRU", sizeof(cap->card)); 878 878 + 879 879 + return 0; 880 880 + } 881 881 + 882 882 + static int rzg2l_cru_try_fmt_vid_cap(struct file *file, void *priv, 883 883 + struct v4l2_format *f) 884 884 + { 885 885 + struct rzg2l_cru_dev *cru = video_drvdata(file); 886 886 + 887 887 + rzg2l_cru_try_format(cru, &f->fmt.pix); 888 888 + 889 889 + return 0; 890 890 + } 891 891 + 892 892 + static int rzg2l_cru_s_fmt_vid_cap(struct file *file, void *priv, 893 893 + struct v4l2_format *f) 894 894 + { 895 895 + struct rzg2l_cru_dev *cru = video_drvdata(file); 896 896 + 897 897 + if (vb2_is_busy(&cru->queue)) 898 898 + return -EBUSY; 899 899 + 900 900 + rzg2l_cru_try_format(cru, &f->fmt.pix); 901 901 + 902 902 + cru->format = f->fmt.pix; 903 903 + 904 904 + return 0; 905 905 + } 906 906 + 907 907 + static int rzg2l_cru_g_fmt_vid_cap(struct file *file, void *priv, 908 908 + struct v4l2_format *f) 909 909 + { 910 910 + struct rzg2l_cru_dev *cru = video_drvdata(file); 911 911 + 912 912 + f->fmt.pix = cru->format; 913 913 + 914 914 + return 0; 915 915 + } 916 916 + 917 917 + static int rzg2l_cru_enum_fmt_vid_cap(struct file *file, void *priv, 918 918 + struct v4l2_fmtdesc *f) 919 919 + { 920 920 + if (f->index >= ARRAY_SIZE(rzg2l_cru_formats)) 921 921 + return -EINVAL; 922 922 + 923 923 + f->pixelformat = rzg2l_cru_formats[f->index].format; 924 924 + 925 925 + return 0; 926 926 + } 927 927 + 928 928 + static const struct v4l2_ioctl_ops rzg2l_cru_ioctl_ops = { 929 929 + .vidioc_querycap = rzg2l_cru_querycap, 930 930 + .vidioc_try_fmt_vid_cap = rzg2l_cru_try_fmt_vid_cap, 931 931 + .vidioc_g_fmt_vid_cap = rzg2l_cru_g_fmt_vid_cap, 932 932 + .vidioc_s_fmt_vid_cap = rzg2l_cru_s_fmt_vid_cap, 933 933 + .vidioc_enum_fmt_vid_cap = rzg2l_cru_enum_fmt_vid_cap, 934 934 + 935 935 + .vidioc_reqbufs = vb2_ioctl_reqbufs, 936 936 + .vidioc_create_bufs = vb2_ioctl_create_bufs, 937 937 + .vidioc_querybuf = vb2_ioctl_querybuf, 938 938 + .vidioc_qbuf = vb2_ioctl_qbuf, 939 939 + .vidioc_dqbuf = vb2_ioctl_dqbuf, 940 940 + .vidioc_expbuf = vb2_ioctl_expbuf, 941 941 + .vidioc_prepare_buf = vb2_ioctl_prepare_buf, 942 942 + .vidioc_streamon = vb2_ioctl_streamon, 943 943 + .vidioc_streamoff = vb2_ioctl_streamoff, 944 944 + }; 945 945 + 946 946 + /* ----------------------------------------------------------------------------- 947 947 + * Media controller file operations 948 948 + */ 949 949 + 950 950 + static int rzg2l_cru_open(struct file *file) 951 951 + { 952 952 + struct rzg2l_cru_dev *cru = video_drvdata(file); 953 953 + int ret; 954 954 + 955 955 + ret = mutex_lock_interruptible(&cru->lock); 956 956 + if (ret) 957 957 + return ret; 958 958 + 959 959 + file->private_data = cru; 960 960 + ret = v4l2_fh_open(file); 961 961 + if (ret) 962 962 + goto err_unlock; 963 963 + 964 964 + mutex_unlock(&cru->lock); 965 965 + 966 966 + return 0; 967 967 + 968 968 + err_unlock: 969 969 + mutex_unlock(&cru->lock); 970 970 + 971 971 + return ret; 972 972 + } 973 973 + 974 974 + static int rzg2l_cru_release(struct file *file) 975 975 + { 976 976 + struct rzg2l_cru_dev *cru = video_drvdata(file); 977 977 + int ret; 978 978 + 979 979 + mutex_lock(&cru->lock); 980 980 + 981 981 + /* the release helper will cleanup any on-going streaming. */ 982 982 + ret = _vb2_fop_release(file, NULL); 983 983 + 984 984 + mutex_unlock(&cru->lock); 985 985 + 986 986 + return ret; 987 987 + } 988 988 + 989 989 + static const struct v4l2_file_operations rzg2l_cru_fops = { 990 990 + .owner = THIS_MODULE, 991 991 + .unlocked_ioctl = video_ioctl2, 992 992 + .open = rzg2l_cru_open, 993 993 + .release = rzg2l_cru_release, 994 994 + .poll = vb2_fop_poll, 995 995 + .mmap = vb2_fop_mmap, 996 996 + .read = vb2_fop_read, 997 997 + }; 998 998 + 999 999 + static void rzg2l_cru_v4l2_init(struct rzg2l_cru_dev *cru) 1000 1000 + { 1001 1001 + struct video_device *vdev = &cru->vdev; 1002 1002 + 1003 1003 + vdev->v4l2_dev = &cru->v4l2_dev; 1004 1004 + vdev->queue = &cru->queue; 1005 1005 + snprintf(vdev->name, sizeof(vdev->name), "CRU output"); 1006 1006 + vdev->release = video_device_release_empty; 1007 1007 + vdev->lock = &cru->lock; 1008 1008 + vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; 1009 1009 + vdev->device_caps |= V4L2_CAP_IO_MC; 1010 1010 + vdev->fops = &rzg2l_cru_fops; 1011 1011 + vdev->ioctl_ops = &rzg2l_cru_ioctl_ops; 1012 1012 + 1013 1013 + /* Set a default format */ 1014 1014 + cru->format.pixelformat = RZG2L_CRU_DEFAULT_FORMAT; 1015 1015 + cru->format.width = RZG2L_CRU_DEFAULT_WIDTH; 1016 1016 + cru->format.height = RZG2L_CRU_DEFAULT_HEIGHT; 1017 1017 + cru->format.field = RZG2L_CRU_DEFAULT_FIELD; 1018 1018 + cru->format.colorspace = RZG2L_CRU_DEFAULT_COLORSPACE; 1019 1019 + rzg2l_cru_format_align(cru, &cru->format); 1020 1020 + } 1021 1021 + 1022 1022 + void rzg2l_cru_video_unregister(struct rzg2l_cru_dev *cru) 1023 1023 + { 1024 1024 + media_device_unregister(&cru->mdev); 1025 1025 + video_unregister_device(&cru->vdev); 1026 1026 + } 1027 1027 + 1028 1028 + int rzg2l_cru_video_register(struct rzg2l_cru_dev *cru) 1029 1029 + { 1030 1030 + struct video_device *vdev = &cru->vdev; 1031 1031 + int ret; 1032 1032 + 1033 1033 + if (video_is_registered(&cru->vdev)) { 1034 1034 + struct media_entity *entity; 1035 1035 + 1036 1036 + entity = &cru->vdev.entity; 1037 1037 + if (!entity->graph_obj.mdev) 1038 1038 + entity->graph_obj.mdev = &cru->mdev; 1039 1039 + return 0; 1040 1040 + } 1041 1041 + 1042 1042 + rzg2l_cru_v4l2_init(cru); 1043 1043 + video_set_drvdata(vdev, cru); 1044 1044 + ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); 1045 1045 + if (ret) { 1046 1046 + dev_err(cru->dev, "Failed to register video device\n"); 1047 1047 + return ret; 1048 1048 + } 1049 1049 + 1050 1050 + ret = media_device_register(&cru->mdev); 1051 1051 + if (ret) { 1052 1052 + video_unregister_device(&cru->vdev); 1053 1053 + return ret; 1054 1054 + } 1055 1055 + 1056 1056 + return 0; 1057 1057 + }