Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'powerpc-4.13-4' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc fixes from Michael Ellerman:
"The highlight is Ben's patch to work around a host killing bug when
running KVM guests with the Radix MMU on Power9. See the long change
log of that commit for more detail.
And then three fairly minor fixes:
- fix of_node_put() underflow during reconfig remove, using old DLPAR
tools.
- fix recently introduced ld version check with 64-bit LE-only
toolchain.
- free the subpage_prot_table correctly, avoiding a memory leak.
Thanks to: Aneesh Kumar K.V, Benjamin Herrenschmidt, Laurent Vivier"
* tag 'powerpc-4.13-4' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
powerpc/mm/hash: Free the subpage_prot_table correctly
powerpc/Makefile: Fix ld version check with 64-bit LE-only toolchain
powerpc/pseries: Fix of_node_put() underflow during reconfig remove
powerpc/mm/radix: Workaround prefetch issue with KVM
+168
-36
+13
-12
arch/powerpc/Makefile
+13
-12
arch/powerpc/Makefile
···
59
59
machine-$(CONFIG_CPU_LITTLE_ENDIAN) += le
60
60
UTS_MACHINE := $(subst $(space),,$(machine-y))
61
61
62
+
# XXX This needs to be before we override LD below
63
+
ifdef CONFIG_PPC32
64
+
KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
65
+
else
66
+
ifeq ($(call ld-ifversion, -ge, 225000000, y),y)
67
+
# Have the linker provide sfpr if possible.
68
+
# There is a corresponding test in arch/powerpc/lib/Makefile
69
+
KBUILD_LDFLAGS_MODULE += --save-restore-funcs
70
+
else
71
+
KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
72
+
endif
73
+
endif
74
+
62
75
ifeq ($(CONFIG_CPU_LITTLE_ENDIAN),y)
63
76
override LD += -EL
64
77
LDEMULATION := lppc
···
201
188
CHECKFLAGS += -D__BIG_ENDIAN__
202
189
else
203
190
CHECKFLAGS += -D__LITTLE_ENDIAN__
204
-
endif
205
-
206
-
ifdef CONFIG_PPC32
207
-
KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
208
-
else
209
-
ifeq ($(call ld-ifversion, -ge, 225000000, y),y)
210
-
# Have the linker provide sfpr if possible.
211
-
# There is a corresponding test in arch/powerpc/lib/Makefile
212
-
KBUILD_LDFLAGS_MODULE += --save-restore-funcs
213
-
else
214
-
KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
215
-
endif
216
191
endif
217
192
218
193
ifeq ($(CONFIG_476FPE_ERR46),y)
+8
-7
arch/powerpc/include/asm/book3s/64/mmu.h
+8
-7
arch/powerpc/include/asm/book3s/64/mmu.h
···
59
59
#define PRTS_MASK 0x1f /* process table size field */
60
60
#define PRTB_MASK 0x0ffffffffffff000UL
61
61
62
-
/*
63
-
* Limit process table to PAGE_SIZE table. This
64
-
* also limit the max pid we can support.
65
-
* MAX_USER_CONTEXT * 16 bytes of space.
66
-
*/
67
-
#define PRTB_SIZE_SHIFT (CONTEXT_BITS + 4)
68
-
#define PRTB_ENTRIES (1ul << CONTEXT_BITS)
62
+
/* Number of supported PID bits */
63
+
extern unsigned int mmu_pid_bits;
64
+
65
+
/* Base PID to allocate from */
66
+
extern unsigned int mmu_base_pid;
67
+
68
+
#define PRTB_SIZE_SHIFT (mmu_pid_bits + 4)
69
+
#define PRTB_ENTRIES (1ul << mmu_pid_bits)
69
70
70
71
/*
71
72
* Power9 currently only support 64K partition table size.
+16
-2
arch/powerpc/include/asm/mmu_context.h
+16
-2
arch/powerpc/include/asm/mmu_context.h
···
45
45
46
46
#ifdef CONFIG_PPC_BOOK3S_64
47
47
extern void radix__switch_mmu_context(struct mm_struct *prev,
48
-
struct mm_struct *next);
48
+
struct mm_struct *next);
49
49
static inline void switch_mmu_context(struct mm_struct *prev,
50
50
struct mm_struct *next,
51
51
struct task_struct *tsk)
···
67
67
extern void mmu_context_init(void);
68
68
#endif
69
69
70
+
#if defined(CONFIG_KVM_BOOK3S_HV_POSSIBLE) && defined(CONFIG_PPC_RADIX_MMU)
71
+
extern void radix_kvm_prefetch_workaround(struct mm_struct *mm);
72
+
#else
73
+
static inline void radix_kvm_prefetch_workaround(struct mm_struct *mm) { }
74
+
#endif
75
+
70
76
extern void switch_cop(struct mm_struct *next);
71
77
extern int use_cop(unsigned long acop, struct mm_struct *mm);
72
78
extern void drop_cop(unsigned long acop, struct mm_struct *mm);
···
85
79
struct mm_struct *next,
86
80
struct task_struct *tsk)
87
81
{
82
+
bool new_on_cpu = false;
83
+
88
84
/* Mark this context has been used on the new CPU */
89
-
if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(next)))
85
+
if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(next))) {
90
86
cpumask_set_cpu(smp_processor_id(), mm_cpumask(next));
87
+
new_on_cpu = true;
88
+
}
91
89
92
90
/* 32-bit keeps track of the current PGDIR in the thread struct */
93
91
#ifdef CONFIG_PPC32
···
119
109
if (cpu_has_feature(CPU_FTR_ALTIVEC))
120
110
asm volatile ("dssall");
121
111
#endif /* CONFIG_ALTIVEC */
112
+
113
+
if (new_on_cpu)
114
+
radix_kvm_prefetch_workaround(next);
115
+
122
116
/*
123
117
* The actual HW switching method differs between the various
124
118
* sub architectures. Out of line for now
+51
-8
arch/powerpc/kvm/book3s_hv_rmhandlers.S
+51
-8
arch/powerpc/kvm/book3s_hv_rmhandlers.S
···
1443
1443
ori r6,r6,1
1444
1444
mtspr SPRN_CTRLT,r6
1445
1445
4:
1446
-
/* Read the guest SLB and save it away */
1446
+
/* Check if we are running hash or radix and store it in cr2 */
1447
1447
ld r5, VCPU_KVM(r9)
1448
1448
lbz r0, KVM_RADIX(r5)
1449
-
cmpwi r0, 0
1449
+
cmpwi cr2,r0,0
1450
+
1451
+
/* Read the guest SLB and save it away */
1450
1452
li r5, 0
1451
-
bne 3f /* for radix, save 0 entries */
1453
+
bne cr2, 3f /* for radix, save 0 entries */
1452
1454
lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1453
1455
mtctr r0
1454
1456
li r6,0
···
1714
1712
END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
1715
1713
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1716
1714
22:
1717
-
/* Clear out SLB */
1718
-
li r5,0
1719
-
slbmte r5,r5
1720
-
slbia
1721
-
ptesync
1722
1715
1723
1716
/* Restore host values of some registers */
1724
1717
BEGIN_FTR_SECTION
···
1734
1737
mtspr SPRN_PID, r7
1735
1738
mtspr SPRN_IAMR, r8
1736
1739
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1740
+
1741
+
#ifdef CONFIG_PPC_RADIX_MMU
1742
+
/*
1743
+
* Are we running hash or radix ?
1744
+
*/
1745
+
beq cr2,3f
1746
+
1747
+
/* Radix: Handle the case where the guest used an illegal PID */
1748
+
LOAD_REG_ADDR(r4, mmu_base_pid)
1749
+
lwz r3, VCPU_GUEST_PID(r9)
1750
+
lwz r5, 0(r4)
1751
+
cmpw cr0,r3,r5
1752
+
blt 2f
1753
+
1754
+
/*
1755
+
* Illegal PID, the HW might have prefetched and cached in the TLB
1756
+
* some translations for the LPID 0 / guest PID combination which
1757
+
* Linux doesn't know about, so we need to flush that PID out of
1758
+
* the TLB. First we need to set LPIDR to 0 so tlbiel applies to
1759
+
* the right context.
1760
+
*/
1761
+
li r0,0
1762
+
mtspr SPRN_LPID,r0
1763
+
isync
1764
+
1765
+
/* Then do a congruence class local flush */
1766
+
ld r6,VCPU_KVM(r9)
1767
+
lwz r0,KVM_TLB_SETS(r6)
1768
+
mtctr r0
1769
+
li r7,0x400 /* IS field = 0b01 */
1770
+
ptesync
1771
+
sldi r0,r3,32 /* RS has PID */
1772
+
1: PPC_TLBIEL(7,0,2,1,1) /* RIC=2, PRS=1, R=1 */
1773
+
addi r7,r7,0x1000
1774
+
bdnz 1b
1775
+
ptesync
1776
+
1777
+
2: /* Flush the ERAT on radix P9 DD1 guest exit */
1737
1778
BEGIN_FTR_SECTION
1738
1779
PPC_INVALIDATE_ERAT
1739
1780
END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
1781
+
b 4f
1782
+
#endif /* CONFIG_PPC_RADIX_MMU */
1740
1783
1784
+
/* Hash: clear out SLB */
1785
+
3: li r5,0
1786
+
slbmte r5,r5
1787
+
slbia
1788
+
ptesync
1789
+
4:
1741
1790
/*
1742
1791
* POWER7/POWER8 guest -> host partition switch code.
1743
1792
* We don't have to lock against tlbies but we do
+3
-2
arch/powerpc/mm/mmu_context_book3s64.c
+3
-2
arch/powerpc/mm/mmu_context_book3s64.c
···
126
126
static int radix__init_new_context(struct mm_struct *mm)
127
127
{
128
128
unsigned long rts_field;
129
-
int index;
129
+
int index, max_id;
130
130
131
-
index = alloc_context_id(1, PRTB_ENTRIES - 1);
131
+
max_id = (1 << mmu_pid_bits) - 1;
132
+
index = alloc_context_id(mmu_base_pid, max_id);
132
133
if (index < 0)
133
134
return index;
134
135
+33
-1
arch/powerpc/mm/pgtable-radix.c
+33
-1
arch/powerpc/mm/pgtable-radix.c
···
25
25
26
26
#include <trace/events/thp.h>
27
27
28
+
unsigned int mmu_pid_bits;
29
+
unsigned int mmu_base_pid;
30
+
28
31
static int native_register_process_table(unsigned long base, unsigned long pg_sz,
29
32
unsigned long table_size)
30
33
{
···
264
261
for_each_memblock(memory, reg)
265
262
WARN_ON(create_physical_mapping(reg->base,
266
263
reg->base + reg->size));
264
+
265
+
/* Find out how many PID bits are supported */
266
+
if (cpu_has_feature(CPU_FTR_HVMODE)) {
267
+
if (!mmu_pid_bits)
268
+
mmu_pid_bits = 20;
269
+
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
270
+
/*
271
+
* When KVM is possible, we only use the top half of the
272
+
* PID space to avoid collisions between host and guest PIDs
273
+
* which can cause problems due to prefetch when exiting the
274
+
* guest with AIL=3
275
+
*/
276
+
mmu_base_pid = 1 << (mmu_pid_bits - 1);
277
+
#else
278
+
mmu_base_pid = 1;
279
+
#endif
280
+
} else {
281
+
/* The guest uses the bottom half of the PID space */
282
+
if (!mmu_pid_bits)
283
+
mmu_pid_bits = 19;
284
+
mmu_base_pid = 1;
285
+
}
286
+
267
287
/*
268
288
* Allocate Partition table and process table for the
269
289
* host.
270
290
*/
271
-
BUILD_BUG_ON_MSG((PRTB_SIZE_SHIFT > 36), "Process table size too large.");
291
+
BUG_ON(PRTB_SIZE_SHIFT > 36);
272
292
process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT);
273
293
/*
274
294
* Fill in the process table.
···
365
339
if (type == NULL || strcmp(type, "cpu") != 0)
366
340
return 0;
367
341
342
+
/* Find MMU PID size */
343
+
prop = of_get_flat_dt_prop(node, "ibm,mmu-pid-bits", &size);
344
+
if (prop && size == 4)
345
+
mmu_pid_bits = be32_to_cpup(prop);
346
+
347
+
/* Grab page size encodings */
368
348
prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
369
349
if (!prop)
370
350
return 0;
+1
-1
arch/powerpc/mm/subpage-prot.c
+1
-1
arch/powerpc/mm/subpage-prot.c
+43
-2
arch/powerpc/mm/tlb-radix.c
+43
-2
arch/powerpc/mm/tlb-radix.c
···
12
12
#include <linux/mm.h>
13
13
#include <linux/hugetlb.h>
14
14
#include <linux/memblock.h>
15
-
#include <asm/ppc-opcode.h>
16
15
16
+
#include <asm/ppc-opcode.h>
17
17
#include <asm/tlb.h>
18
18
#include <asm/tlbflush.h>
19
19
#include <asm/trace.h>
20
-
20
+
#include <asm/cputhreads.h>
21
21
22
22
#define RIC_FLUSH_TLB 0
23
23
#define RIC_FLUSH_PWC 1
···
454
454
else
455
455
radix__flush_tlb_page_psize(mm, address, mmu_virtual_psize);
456
456
}
457
+
458
+
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
459
+
extern void radix_kvm_prefetch_workaround(struct mm_struct *mm)
460
+
{
461
+
unsigned int pid = mm->context.id;
462
+
463
+
if (unlikely(pid == MMU_NO_CONTEXT))
464
+
return;
465
+
466
+
/*
467
+
* If this context hasn't run on that CPU before and KVM is
468
+
* around, there's a slim chance that the guest on another
469
+
* CPU just brought in obsolete translation into the TLB of
470
+
* this CPU due to a bad prefetch using the guest PID on
471
+
* the way into the hypervisor.
472
+
*
473
+
* We work around this here. If KVM is possible, we check if
474
+
* any sibling thread is in KVM. If it is, the window may exist
475
+
* and thus we flush that PID from the core.
476
+
*
477
+
* A potential future improvement would be to mark which PIDs
478
+
* have never been used on the system and avoid it if the PID
479
+
* is new and the process has no other cpumask bit set.
480
+
*/
481
+
if (cpu_has_feature(CPU_FTR_HVMODE) && radix_enabled()) {
482
+
int cpu = smp_processor_id();
483
+
int sib = cpu_first_thread_sibling(cpu);
484
+
bool flush = false;
485
+
486
+
for (; sib <= cpu_last_thread_sibling(cpu) && !flush; sib++) {
487
+
if (sib == cpu)
488
+
continue;
489
+
if (paca[sib].kvm_hstate.kvm_vcpu)
490
+
flush = true;
491
+
}
492
+
if (flush)
493
+
_tlbiel_pid(pid, RIC_FLUSH_ALL);
494
+
}
495
+
}
496
+
EXPORT_SYMBOL_GPL(radix_kvm_prefetch_workaround);
497
+
#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */