Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'edac_urgent_for_v6.15_rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras
Pull EDAC fixes from Borislav Petkov:
- Test the correct structure member when handling correctable errors
and avoid spurious interrupts, in altera_edac
* tag 'edac_urgent_for_v6.15_rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras:
EDAC/altera: Set DDR and SDMMC interrupt mask before registration
EDAC/altera: Test the correct error reg offset
+7
-4
+5
-4
drivers/edac/altera_edac.c
+5
-4
drivers/edac/altera_edac.c
···
99
99
if (status & priv->ecc_stat_ce_mask) {
100
100
regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
101
101
&err_addr);
102
-
if (priv->ecc_uecnt_offset)
102
+
if (priv->ecc_cecnt_offset)
103
103
regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset,
104
104
&err_count);
105
105
edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
···
1005
1005
}
1006
1006
}
1007
1007
1008
-
/* Interrupt mode set to every SBERR */
1009
-
regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
1010
-
ALTR_A10_ECC_INTMODE);
1011
1008
/* Enable ECC */
1012
1009
ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
1013
1010
ALTR_A10_ECC_CTRL_OFST));
···
2123
2126
"Unable to get syscon altr,sysmgr-syscon\n");
2124
2127
return PTR_ERR(edac->ecc_mgr_map);
2125
2128
}
2129
+
2130
+
/* Set irq mask for DDR SBE to avoid any pending irq before registration */
2131
+
regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
2132
+
(A10_SYSMGR_ECC_INTMASK_SDMMCB | A10_SYSMGR_ECC_INTMASK_DDR0));
2126
2133
2127
2134
edac->irq_chip.name = pdev->dev.of_node->name;
2128
2135
edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
+2
drivers/edac/altera_edac.h
+2
drivers/edac/altera_edac.h
···
249
249
#define A10_SYSMGR_ECC_INTMASK_SET_OFST 0x94
250
250
#define A10_SYSMGR_ECC_INTMASK_CLR_OFST 0x98
251
251
#define A10_SYSMGR_ECC_INTMASK_OCRAM BIT(1)
252
+
#define A10_SYSMGR_ECC_INTMASK_SDMMCB BIT(16)
253
+
#define A10_SYSMGR_ECC_INTMASK_DDR0 BIT(17)
252
254
253
255
#define A10_SYSMGR_ECC_INTSTAT_SERR_OFST 0x9C
254
256
#define A10_SYSMGR_ECC_INTSTAT_DERR_OFST 0xA0