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iio: adc: ad9467: support write/read offset via _calibbias

Support configuring output calibration value. Among the devices
currently supported by this driver, this setting is specific to
ad9434. The offset can be used to calibrate the output against
a known input. The register is called offset, but the procedure
is best mapped internally with calibbias operation.

Reviewed-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
Reviewed-by: Nuno Sá <nuno.sa@analog.com>
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

authored by

Tomas Melin and committed by
Jonathan Cameron
0820dd9f c7f9c36b

+59 -1
+59 -1
drivers/iio/adc/ad9467.c
··· 145 145 unsigned int num_lanes; 146 146 unsigned int dco_en; 147 147 unsigned int test_points; 148 + const int *offset_range; 148 149 /* data clock output */ 149 150 bool has_dco; 150 151 bool has_dco_invert; ··· 235 234 return 0; 236 235 } 237 236 237 + static const int ad9434_offset_range[] = { 238 + -128, 1, 127, 239 + }; 240 + 238 241 static const unsigned int ad9265_scale_table[][2] = { 239 242 {1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0}, 240 243 }; ··· 303 298 } 304 299 305 300 static const struct iio_chan_spec ad9434_channels[] = { 306 - AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 12, 's'), 301 + { 302 + .type = IIO_VOLTAGE, 303 + .indexed = 1, 304 + .channel = 0, 305 + .info_mask_shared_by_type = 306 + BIT(IIO_CHAN_INFO_SCALE) | 307 + BIT(IIO_CHAN_INFO_SAMP_FREQ) | 308 + BIT(IIO_CHAN_INFO_CALIBBIAS), 309 + .info_mask_shared_by_type_available = 310 + BIT(IIO_CHAN_INFO_SCALE) | 311 + BIT(IIO_CHAN_INFO_CALIBBIAS), 312 + .scan_index = 0, 313 + .scan_type = { 314 + .sign = 's', 315 + .realbits = 12, 316 + .storagebits = 16, 317 + }, 318 + }, 307 319 }; 308 320 309 321 static const struct iio_chan_spec ad9467_channels[] = { ··· 389 367 .default_output_mode = AD9434_DEF_OUTPUT_MODE, 390 368 .vref_mask = AD9434_REG_VREF_MASK, 391 369 .num_lanes = 6, 370 + .offset_range = ad9434_offset_range, 392 371 }; 393 372 394 373 static const struct ad9467_chip_info ad9265_chip_tbl = { ··· 520 497 } 521 498 522 499 return -EINVAL; 500 + } 501 + 502 + static int ad9467_get_offset(struct ad9467_state *st, int *val) 503 + { 504 + int ret; 505 + 506 + ret = ad9467_spi_read(st, AN877_ADC_REG_OFFSET); 507 + if (ret < 0) 508 + return ret; 509 + *val = ret; 510 + 511 + return IIO_VAL_INT; 512 + } 513 + 514 + static int ad9467_set_offset(struct ad9467_state *st, int val) 515 + { 516 + int ret; 517 + 518 + if (val < st->info->offset_range[0] || val > st->info->offset_range[2]) 519 + return -EINVAL; 520 + 521 + ret = ad9467_spi_write(st, AN877_ADC_REG_OFFSET, val); 522 + if (ret < 0) 523 + return ret; 524 + 525 + return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 526 + AN877_ADC_TRANSFER_SYNC); 523 527 } 524 528 525 529 static int ad9467_outputmode_set(struct ad9467_state *st, unsigned int mode) ··· 852 802 struct ad9467_state *st = iio_priv(indio_dev); 853 803 854 804 switch (m) { 805 + case IIO_CHAN_INFO_CALIBBIAS: 806 + return ad9467_get_offset(st, val); 855 807 case IIO_CHAN_INFO_SCALE: 856 808 return ad9467_get_scale(st, val, val2); 857 809 case IIO_CHAN_INFO_SAMP_FREQ: ··· 888 836 int ret; 889 837 890 838 switch (mask) { 839 + case IIO_CHAN_INFO_CALIBBIAS: 840 + return ad9467_set_offset(st, val); 891 841 case IIO_CHAN_INFO_SCALE: 892 842 return ad9467_set_scale(st, val, val2); 893 843 case IIO_CHAN_INFO_SAMP_FREQ: ··· 928 874 const struct ad9467_chip_info *info = st->info; 929 875 930 876 switch (mask) { 877 + case IIO_CHAN_INFO_CALIBBIAS: 878 + *type = IIO_VAL_INT; 879 + *vals = info->offset_range; 880 + return IIO_AVAIL_RANGE; 931 881 case IIO_CHAN_INFO_SCALE: 932 882 *vals = (const int *)st->scales; 933 883 *type = IIO_VAL_INT_PLUS_MICRO;