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Merge branch '20230608125315.11454-2-srinivas.kandagatla@linaro.org' into arm64-for-6.5

Merge the SC8280XP LPASSCC DeviceTree bindings in order to get access
to the newly added reset defines.

+77
+60
Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/qcom,sc8280xp-lpasscc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm LPASS Core & Audio Clock Controller on SC8280XP 8 + 9 + maintainers: 10 + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> 11 + 12 + description: | 13 + Qualcomm LPASS core and audio clock control module provides the clocks, 14 + and reset on SC8280XP. 15 + 16 + See also:: 17 + include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h 18 + 19 + properties: 20 + compatible: 21 + enum: 22 + - qcom,sc8280xp-lpassaudiocc 23 + - qcom,sc8280xp-lpasscc 24 + 25 + reg: 26 + maxItems: 1 27 + 28 + '#clock-cells': 29 + const: 1 30 + 31 + '#reset-cells': 32 + const: 1 33 + 34 + required: 35 + - compatible 36 + - reg 37 + - '#clock-cells' 38 + - '#reset-cells' 39 + 40 + additionalProperties: false 41 + 42 + examples: 43 + - | 44 + #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 45 + lpass_audiocc: clock-controller@32a9000 { 46 + compatible = "qcom,sc8280xp-lpassaudiocc"; 47 + reg = <0x032a9000 0x1000>; 48 + #clock-cells = <1>; 49 + #reset-cells = <1>; 50 + }; 51 + 52 + - | 53 + #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 54 + lpasscc: clock-controller@33e0000 { 55 + compatible = "qcom,sc8280xp-lpasscc"; 56 + reg = <0x033e0000 0x12000>; 57 + #clock-cells = <1>; 58 + #reset-cells = <1>; 59 + }; 60 + ...
+17
include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2023, Linaro Ltd. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H 7 + #define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H 8 + 9 + /* LPASS AUDIO CC CSR */ 10 + #define LPASS_AUDIO_SWR_RX_CGCR 0 11 + #define LPASS_AUDIO_SWR_WSA_CGCR 1 12 + #define LPASS_AUDIO_SWR_WSA2_CGCR 2 13 + 14 + /* LPASS TCSR */ 15 + #define LPASS_AUDIO_SWR_TX_CGCR 0 16 + 17 + #endif