Merge tag 'drm-next-2023-05-05' of git://anongit.freedesktop.org/drm/drm

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Pull more drm fixes from Dave Airlie:
"This is the fixes for the last couple of weeks for i915 and last 3
weeks for amdgpu, lots of them but pretty scattered around and all
pretty small.

amdgpu:
- SR-IOV fixes
- DCN 3.2 fixes
- DC mclk handling fixes
- eDP fixes
- SubVP fixes
- HDCP regression fix
- DSC fixes
- DC FP fixes
- DCN 3.x fixes
- Display flickering fix when switching between vram and gtt
- Z8 power saving fix
- Fix hang when skipping modeset
- GPU reset fixes
- Doorbell fix when resizing BARs
- Fix spurious warnings in gmc
- Locking fix for AMDGPU_SCHED IOCTL
- SR-IOV fix
- DCN 3.1.4 fix
- DCN 3.2 fix
- Fix job cleanup when CS is aborted

i915:
- skl pipe source size check
- mtl transcoder mask fix
- DSI power on sequence fix
- GuC versioning corner case fix"

* tag 'drm-next-2023-05-05' of git://anongit.freedesktop.org/drm/drm: (48 commits)
drm/amdgpu: drop redundant sched job cleanup when cs is aborted
drm/amd/display: filter out invalid bits in pipe_fuses
drm/amd/display: Change default Z8 watermark values
drm/amdgpu: disable SDMA WPTR_POLL_ENABLE for SR-IOV
drm/amdgpu: add a missing lock for AMDGPU_SCHED
drm/amdgpu: fix an amdgpu_irq_put() issue in gmc_v9_0_hw_fini()
drm/amdgpu: fix amdgpu_irq_put call trace in gmc_v10_0_hw_fini
drm/amdgpu: fix amdgpu_irq_put call trace in gmc_v11_0_hw_fini
drm/amdgpu: Enable doorbell selfring after resize FB BAR
drm/amdgpu: Use the default reset when loading or reloading the driver
drm/amdgpu: Fix mode2 reset for sienna cichlid
drm/i915/dsi: Use unconditional msleep() instead of intel_dsi_msleep()
drm/i915/mtl: Add the missing CPU transcoder mask in intel_device_info
drm/i915/guc: Actually return an error if GuC version range check fails
drm/amd/display: Lowering min Z8 residency time
drm/amd/display: fix flickering caused by S/G mode
drm/amd/display: Set min_width and min_height capability for DCN30
drm/amd/display: Isolate remaining FPU code in DCN32
drm/amd/display: Update bounding box values for DCN321
drm/amd/display: Do not clear GPINT register when releasing DMUB from reset
...

Linus Torvalds 3 years ago 084f51d4 78b421b6

+413 -261

50 changed files

expand all

drivers

gpu

drm

amd

amdgpu

amdgpu_cs.c

amdgpu_device.c

amdgpu_sched.c

gmc_v10_0.c

gmc_v11_0.c

gmc_v9_0.c

jpeg_v4_0.c

nv.c

sdma_v6_0.c

sienna_cichlid.c

soc15.c

soc21.c

display

amdgpu_dm

amdgpu_dm.c

amdgpu_dm_helpers.c

amdgpu_dm_mst_types.c

dc_fpu.c

clk_mgr

dcn32

dcn32_clk_mgr.c

core

dc_resource.c

dc.h

dc_stream.h

dce110

dce110_hw_sequencer.c

dcn20

dcn20_hwseq.c

dcn30

dcn30_hwseq.c

dcn30_resource.c

dcn31

dcn31_hwseq.c

dcn314

dcn314_dccg.c

dcn314_resource.c

dcn32

dcn32_hwseq.c

dcn32_resource.c

dcn321

dcn321_resource.c

dml

dcn20

dcn20_fpu.c

dcn30

dcn30_fpu.c

dcn314

dcn314_fpu.c

dcn32

dcn32_fpu.c

dcn32_fpu.h

dcn321

dcn321_fpu.c

link

link_dpms.c

protocols

link_dp_training.c

link_edp_panel_control.c

dmub

src

dmub_dcn32.c

include

signal_types.h

swsmu

inc

smu_v13_0.h

smu13

smu_v13_0.c

i915

display

icl_dsi.c

intel_dsi_vbt.c

intel_dsi_vbt.h

skl_scaler.c

vlv_dsi.c

intel_uc_fw.c

i915_pci.c

+3 -10

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

··· 1276 1276 r = drm_sched_job_add_dependency(&leader->base, fence); 1277 1277 if (r) { 1278 1278 dma_fence_put(fence); 1279 - goto error_cleanup; 1279 + return r; 1280 1280 } 1281 1281 } 1282 1282 ··· 1303 1303 } 1304 1304 if (r) { 1305 1305 r = -EAGAIN; 1306 - goto error_unlock; 1306 + mutex_unlock(&p->adev->notifier_lock); 1307 + return r; 1307 1308 } 1308 1309 1309 1310 p->fence = dma_fence_get(&leader->base.s_fence->finished); ··· 1351 1350 mutex_unlock(&p->adev->notifier_lock); 1352 1351 mutex_unlock(&p->bo_list->bo_list_mutex); 1353 1352 return 0; 1354 - 1355 - error_unlock: 1356 - mutex_unlock(&p->adev->notifier_lock); 1357 - 1358 - error_cleanup: 1359 - for (i = 0; i < p->gang_size; ++i) 1360 - drm_sched_job_cleanup(&p->jobs[i]->base); 1361 - return r; 1362 1353 } 1363 1354 1364 1355 /* Cleanup the parser structure */

+24 -15

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

··· 2539 2539 amdgpu_fru_get_product_info(adev); 2540 2540 2541 2541 init_failed: 2542 - if (amdgpu_sriov_vf(adev)) 2543 - amdgpu_virt_release_full_gpu(adev, true); 2544 2542 2545 2543 return r; 2546 2544 } ··· 3578 3580 int r, i; 3579 3581 bool px = false; 3580 3582 u32 max_MBps; 3583 + int tmp; 3581 3584 3582 3585 adev->shutdown = false; 3583 3586 adev->flags = flags; ··· 3800 3801 } 3801 3802 } 3802 3803 } else { 3804 + tmp = amdgpu_reset_method; 3805 + /* It should do a default reset when loading or reloading the driver, 3806 + * regardless of the module parameter reset_method. 3807 + */ 3808 + amdgpu_reset_method = AMD_RESET_METHOD_NONE; 3803 3809 r = amdgpu_asic_reset(adev); 3810 + amdgpu_reset_method = tmp; 3804 3811 if (r) { 3805 3812 dev_err(adev->dev, "asic reset on init failed\n"); 3806 3813 goto failed; ··· 3864 3859 3865 3860 r = amdgpu_device_ip_init(adev); 3866 3861 if (r) { 3867 - /* failed in exclusive mode due to timeout */ 3868 - if (amdgpu_sriov_vf(adev) && 3869 - !amdgpu_sriov_runtime(adev) && 3870 - amdgpu_virt_mmio_blocked(adev) && 3871 - !amdgpu_virt_wait_reset(adev)) { 3872 - dev_err(adev->dev, "VF exclusive mode timeout\n"); 3873 - /* Don't send request since VF is inactive. */ 3874 - adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 3875 - adev->virt.ops = NULL; 3876 - r = -EAGAIN; 3877 - goto release_ras_con; 3878 - } 3879 3862 dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); 3880 3863 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); 3881 3864 goto release_ras_con; ··· 3932 3939 msecs_to_jiffies(AMDGPU_RESUME_MS)); 3933 3940 } 3934 3941 3935 - if (amdgpu_sriov_vf(adev)) 3942 + if (amdgpu_sriov_vf(adev)) { 3943 + amdgpu_virt_release_full_gpu(adev, true); 3936 3944 flush_delayed_work(&adev->delayed_init_work); 3945 + } 3937 3946 3938 3947 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes); 3939 3948 if (r) ··· 3975 3980 return 0; 3976 3981 3977 3982 release_ras_con: 3983 + if (amdgpu_sriov_vf(adev)) 3984 + amdgpu_virt_release_full_gpu(adev, true); 3985 + 3986 + /* failed in exclusive mode due to timeout */ 3987 + if (amdgpu_sriov_vf(adev) && 3988 + !amdgpu_sriov_runtime(adev) && 3989 + amdgpu_virt_mmio_blocked(adev) && 3990 + !amdgpu_virt_wait_reset(adev)) { 3991 + dev_err(adev->dev, "VF exclusive mode timeout\n"); 3992 + /* Don't send request since VF is inactive. */ 3993 + adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 3994 + adev->virt.ops = NULL; 3995 + r = -EAGAIN; 3996 + } 3978 3997 amdgpu_release_ras_context(adev); 3979 3998 3980 3999 failed:

+5 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c

··· 38 38 { 39 39 struct fd f = fdget(fd); 40 40 struct amdgpu_fpriv *fpriv; 41 + struct amdgpu_ctx_mgr *mgr; 41 42 struct amdgpu_ctx *ctx; 42 43 uint32_t id; 43 44 int r; ··· 52 51 return r; 53 52 } 54 53 55 - idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id) 54 + mgr = &fpriv->ctx_mgr; 55 + mutex_lock(&mgr->lock); 56 + idr_for_each_entry(&mgr->ctx_handles, ctx, id) 56 57 amdgpu_ctx_priority_override(ctx, priority); 58 + mutex_unlock(&mgr->lock); 57 59 58 60 fdput(f); 59 61 return 0;

-1

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

··· 1143 1143 return 0; 1144 1144 } 1145 1145 1146 - amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1147 1146 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1148 1147 1149 1148 return 0;

-1

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

··· 951 951 return 0; 952 952 } 953 953 954 - amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 955 954 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 956 955 gmc_v11_0_gart_disable(adev); 957 956

-1

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

··· 1999 1999 if (adev->mmhub.funcs->update_power_gating) 2000 2000 adev->mmhub.funcs->update_power_gating(adev, false); 2001 2001 2002 - amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 2003 2002 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 2004 2003 2005 2004 return 0;

+1 -1

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

··· 430 430 MMSCH_COMMAND__END; 431 431 432 432 header.version = MMSCH_VERSION; 433 - header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2; 433 + header.total_size = RREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE); 434 434 435 435 header.jpegdec.init_status = 0; 436 436 header.jpegdec.table_offset = 0;

+13 -10

drivers/gpu/drm/amd/amdgpu/nv.c

··· 531 531 532 532 } 533 533 534 - static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 535 - bool enable) 536 - { 537 - adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 538 - adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 539 - } 540 - 541 534 const struct amdgpu_ip_block_version nv_common_ip_block = 542 535 { 543 536 .type = AMD_IP_BLOCK_TYPE_COMMON, ··· 992 999 } 993 1000 } 994 1001 1002 + /* Enable selfring doorbell aperture late because doorbell BAR 1003 + * aperture will change if resize BAR successfully in gmc sw_init. 1004 + */ 1005 + adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 1006 + 995 1007 return 0; 996 1008 } 997 1009 ··· 1036 1038 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 1037 1039 adev->nbio.funcs->remap_hdp_registers(adev); 1038 1040 /* enable the doorbell aperture */ 1039 - nv_enable_doorbell_aperture(adev, true); 1041 + adev->nbio.funcs->enable_doorbell_aperture(adev, true); 1040 1042 1041 1043 return 0; 1042 1044 } ··· 1045 1047 { 1046 1048 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1047 1049 1048 - /* disable the doorbell aperture */ 1049 - nv_enable_doorbell_aperture(adev, false); 1050 + /* Disable the doorbell aperture and selfring doorbell aperture 1051 + * separately in hw_fini because nv_enable_doorbell_aperture 1052 + * has been removed and there is no need to delay disabling 1053 + * selfring doorbell. 1054 + */ 1055 + adev->nbio.funcs->enable_doorbell_aperture(adev, false); 1056 + adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 1050 1057 1051 1058 return 0; 1052 1059 }

+1 -4

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

··· 510 510 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 511 511 512 512 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 513 - if (amdgpu_sriov_vf(adev)) 514 - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1); 515 - else 516 - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); 513 + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); 517 514 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1); 518 515 519 516 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);

+1 -1

drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c

··· 40 40 adev->pm.fw_version >= 0x3a5500 && !amdgpu_sriov_vf(adev)) 41 41 return true; 42 42 #endif 43 - return false; 43 + return amdgpu_reset_method == AMD_RESET_METHOD_MODE2; 44 44 } 45 45 46 46 static struct amdgpu_reset_handler *

+15 -10

drivers/gpu/drm/amd/amdgpu/soc15.c

··· 619 619 adev->nbio.funcs->program_aspm(adev); 620 620 } 621 621 622 - static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, 623 - bool enable) 624 - { 625 - adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 626 - adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 627 - } 628 - 629 622 const struct amdgpu_ip_block_version vega10_common_ip_block = 630 623 { 631 624 .type = AMD_IP_BLOCK_TYPE_COMMON, ··· 1118 1125 if (amdgpu_sriov_vf(adev)) 1119 1126 xgpu_ai_mailbox_get_irq(adev); 1120 1127 1128 + /* Enable selfring doorbell aperture late because doorbell BAR 1129 + * aperture will change if resize BAR successfully in gmc sw_init. 1130 + */ 1131 + adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 1132 + 1121 1133 return 0; 1122 1134 } 1123 1135 ··· 1180 1182 adev->nbio.funcs->remap_hdp_registers(adev); 1181 1183 1182 1184 /* enable the doorbell aperture */ 1183 - soc15_enable_doorbell_aperture(adev, true); 1185 + adev->nbio.funcs->enable_doorbell_aperture(adev, true); 1186 + 1184 1187 /* HW doorbell routing policy: doorbell writing not 1185 1188 * in SDMA/IH/MM/ACV range will be routed to CP. So 1186 1189 * we need to init SDMA doorbell range prior ··· 1197 1198 { 1198 1199 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1199 1200 1200 - /* disable the doorbell aperture */ 1201 - soc15_enable_doorbell_aperture(adev, false); 1201 + /* Disable the doorbell aperture and selfring doorbell aperture 1202 + * separately in hw_fini because soc15_enable_doorbell_aperture 1203 + * has been removed and there is no need to delay disabling 1204 + * selfring doorbell. 1205 + */ 1206 + adev->nbio.funcs->enable_doorbell_aperture(adev, false); 1207 + adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 1208 + 1202 1209 if (amdgpu_sriov_vf(adev)) 1203 1210 xgpu_ai_mailbox_put_irq(adev); 1204 1211

+13 -10

drivers/gpu/drm/amd/amdgpu/soc21.c

··· 450 450 adev->nbio.funcs->program_aspm(adev); 451 451 } 452 452 453 - static void soc21_enable_doorbell_aperture(struct amdgpu_device *adev, 454 - bool enable) 455 - { 456 - adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 457 - adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 458 - } 459 - 460 453 const struct amdgpu_ip_block_version soc21_common_ip_block = 461 454 { 462 455 .type = AMD_IP_BLOCK_TYPE_COMMON, ··· 757 764 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); 758 765 } 759 766 767 + /* Enable selfring doorbell aperture late because doorbell BAR 768 + * aperture will change if resize BAR successfully in gmc sw_init. 769 + */ 770 + adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 771 + 760 772 return 0; 761 773 } 762 774 ··· 795 797 if (adev->nbio.funcs->remap_hdp_registers) 796 798 adev->nbio.funcs->remap_hdp_registers(adev); 797 799 /* enable the doorbell aperture */ 798 - soc21_enable_doorbell_aperture(adev, true); 800 + adev->nbio.funcs->enable_doorbell_aperture(adev, true); 799 801 800 802 return 0; 801 803 } ··· 804 806 { 805 807 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 806 808 807 - /* disable the doorbell aperture */ 808 - soc21_enable_doorbell_aperture(adev, false); 809 + /* Disable the doorbell aperture and selfring doorbell aperture 810 + * separately in hw_fini because soc21_enable_doorbell_aperture 811 + * has been removed and there is no need to delay disabling 812 + * selfring doorbell. 813 + */ 814 + adev->nbio.funcs->enable_doorbell_aperture(adev, false); 815 + adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 809 816 810 817 if (amdgpu_sriov_vf(adev)) { 811 818 xgpu_nv_mailbox_put_irq(adev);

+28 -6

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

··· 3128 3128 aconnector->edid); 3129 3129 } 3130 3130 3131 - aconnector->timing_requested = kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL); 3132 - if (!aconnector->timing_requested) 3133 - dm_error("%s: failed to create aconnector->requested_timing\n", __func__); 3131 + if (!aconnector->timing_requested) { 3132 + aconnector->timing_requested = 3133 + kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL); 3134 + if (!aconnector->timing_requested) 3135 + dm_error("failed to create aconnector->requested_timing\n"); 3136 + } 3134 3137 3135 3138 drm_connector_update_edid_property(connector, aconnector->edid); 3136 3139 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); ··· 7897 7894 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); 7898 7895 } 7899 7896 7897 + static inline uint32_t get_mem_type(struct drm_framebuffer *fb) 7898 + { 7899 + struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); 7900 + 7901 + return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; 7902 + } 7903 + 7900 7904 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 7901 7905 struct dc_state *dc_state, 7902 7906 struct drm_device *dev, ··· 7978 7968 continue; 7979 7969 7980 7970 dc_plane = dm_new_plane_state->dc_state; 7971 + if (!dc_plane) 7972 + continue; 7981 7973 7982 7974 bundle->surface_updates[planes_count].surface = dc_plane; 7983 7975 if (new_pcrtc_state->color_mgmt_changed) { ··· 8046 8034 8047 8035 /* 8048 8036 * Only allow immediate flips for fast updates that don't 8049 - * change FB pitch, DCC state, rotation or mirroing. 8037 + * change memory domain, FB pitch, DCC state, rotation or 8038 + * mirroring. 8050 8039 */ 8051 8040 bundle->flip_addrs[planes_count].flip_immediate = 8052 8041 crtc->state->async_flip && 8053 - acrtc_state->update_type == UPDATE_TYPE_FAST; 8042 + acrtc_state->update_type == UPDATE_TYPE_FAST && 8043 + get_mem_type(old_plane_state->fb) == get_mem_type(fb); 8054 8044 8055 8045 timestamp_ns = ktime_get_ns(); 8056 8046 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); ··· 8564 8550 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 8565 8551 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 8566 8552 8553 + if (!adev->dm.hdcp_workqueue) 8554 + continue; 8555 + 8567 8556 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i); 8568 8557 8569 8558 if (!connector) ··· 8614 8597 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 8615 8598 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 8616 8599 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 8600 + 8601 + if (!adev->dm.hdcp_workqueue) 8602 + continue; 8617 8603 8618 8604 new_crtc_state = NULL; 8619 8605 old_crtc_state = NULL; ··· 9636 9616 return -EINVAL; 9637 9617 } 9638 9618 9619 + if (dm_old_plane_state->dc_state) 9620 + dc_plane_state_release(dm_old_plane_state->dc_state); 9639 9621 9640 - dc_plane_state_release(dm_old_plane_state->dc_state); 9641 9622 dm_new_plane_state->dc_state = NULL; 9642 9623 9643 9624 *lock_and_validation_needed = true; ··· 10175 10154 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); 10176 10155 if (ret) { 10177 10156 DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n"); 10157 + ret = -EINVAL; 10178 10158 goto fail; 10179 10159 } 10180 10160

-1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

··· 687 687 return; 688 688 689 689 data[0] |= (1 << 1); // set bit 1 to 1 690 - return; 691 690 692 691 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 693 692 return;

+11 -6

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

··· 379 379 if (aconnector->dc_sink && connector->state) { 380 380 struct drm_device *dev = connector->dev; 381 381 struct amdgpu_device *adev = drm_to_adev(dev); 382 - struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 383 - struct hdcp_workqueue *hdcp_w = &hdcp_work[aconnector->dc_link->link_index]; 384 382 385 - connector->state->hdcp_content_type = 386 - hdcp_w->hdcp_content_type[connector->index]; 387 - connector->state->content_protection = 388 - hdcp_w->content_protection[connector->index]; 383 + if (adev->dm.hdcp_workqueue) { 384 + struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 385 + struct hdcp_workqueue *hdcp_w = 386 + &hdcp_work[aconnector->dc_link->link_index]; 387 + 388 + connector->state->hdcp_content_type = 389 + hdcp_w->hdcp_content_type[connector->index]; 390 + connector->state->content_protection = 391 + hdcp_w->content_protection[connector->index]; 392 + } 389 393 } 390 394 391 395 if (aconnector->dc_sink) { ··· 1410 1406 ret = pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars); 1411 1407 if (ret != 0) { 1412 1408 DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state() failed\n"); 1409 + ret = -EINVAL; 1413 1410 goto clean_exit; 1414 1411 } 1415 1412

drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c

··· 89 89 90 90 if (*pcpu == 1) { 91 91 #if defined(CONFIG_X86) 92 + migrate_disable(); 92 93 kernel_fpu_begin(); 93 94 #elif defined(CONFIG_PPC64) 94 95 if (cpu_has_feature(CPU_FTR_VSX_COMP)) { ··· 130 129 if (*pcpu <= 0) { 131 130 #if defined(CONFIG_X86) 132 131 kernel_fpu_end(); 132 + migrate_enable(); 133 133 #elif defined(CONFIG_PPC64) 134 134 if (cpu_has_feature(CPU_FTR_VSX_COMP)) { 135 135 disable_kernel_vsx();

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

··· 878 878 struct pp_smu_funcs *pp_smu, 879 879 struct dccg *dccg) 880 880 { 881 + struct clk_log_info log_info = {0}; 882 + 881 883 clk_mgr->base.ctx = ctx; 882 884 clk_mgr->base.funcs = &dcn32_funcs; 883 885 if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) { ··· 913 911 clk_mgr->base.clks.ref_dtbclk_khz = 268750; 914 912 } 915 913 914 + 916 915 /* integer part is now VCO frequency in kHz */ 917 916 clk_mgr->base.dentist_vco_freq_khz = dcn32_get_vco_frequency_from_reg(clk_mgr); 918 917 919 918 /* in case we don't get a value from the register, use default */ 920 919 if (clk_mgr->base.dentist_vco_freq_khz == 0) 921 920 clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */ 921 + 922 + dcn32_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info); 922 923 923 924 if (ctx->dc->debug.disable_dtb_ref_clk_switch && 924 925 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

··· 1707 1707 struct dc_stream_status *stream_status = NULL; 1708 1708 struct resource_pool *pool = dc->res_pool; 1709 1709 1710 + if (!plane_state) 1711 + return true; 1712 + 1710 1713 for (i = 0; i < context->stream_count; i++) 1711 1714 if (context->streams[i] == stream) { 1712 1715 stream_status = &context->stream_status[i];

drivers/gpu/drm/amd/display/dc/dc.h

··· 1454 1454 1455 1455 struct ddc_service *ddc; 1456 1456 1457 + enum dp_panel_mode panel_mode; 1457 1458 bool aux_mode; 1458 1459 1459 1460 /* Private to DC core */

+1 -1

drivers/gpu/drm/amd/display/dc/dc_stream.h

··· 144 144 unsigned int cust_pattern_size; 145 145 }; 146 146 147 - #define SUBVP_DRR_MARGIN_US 600 // 600us for DRR margin (SubVP + DRR) 147 + #define SUBVP_DRR_MARGIN_US 100 // 100us for DRR margin (SubVP + DRR) 148 148 149 149 enum mall_stream_type { 150 150 SUBVP_NONE, // subvp not in use

+11 -8

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

··· 3031 3031 const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 3032 3032 unsigned int i; 3033 3033 3034 - 3034 + /* 3035 + * Add the logic to extract BOTH power up and power down sequences 3036 + * from enable/disable link output and only call edp panel control 3037 + * in enable_link_dp and disable_link_dp once. 3038 + */ 3035 3039 if (link->connector_signal == SIGNAL_TYPE_EDP) { 3036 - if (!link->dc->config.edp_no_power_sequencing) 3037 - link->dc->hwss.edp_power_control(link, true); 3038 3040 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 3039 3041 } 3040 3042 ··· 3098 3096 3099 3097 link_hwss->disable_link_output(link, link_res, signal); 3100 3098 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 3101 - 3102 - if (signal == SIGNAL_TYPE_EDP && 3103 - link->dc->hwss.edp_backlight_control) 3104 - link->dc->hwss.edp_power_control(link, false); 3105 - else if (dmcu != NULL && dmcu->funcs->lock_phy) 3099 + /* 3100 + * Add the logic to extract BOTH power up and power down sequences 3101 + * from enable/disable link output and only call edp panel control 3102 + * in enable_link_dp and disable_link_dp once. 3103 + */ 3104 + if (dmcu != NULL && dmcu->funcs->lock_phy) 3106 3105 dmcu->funcs->unlock_phy(dmcu); 3107 3106 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); 3108 3107 }

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

··· 2113 2113 if (hubbub->funcs->program_compbuf_size) 2114 2114 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); 2115 2115 2116 + if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { 2117 + dc_dmub_srv_p_state_delegate(dc, 2118 + true, context); 2119 + context->bw_ctx.bw.dcn.clk.p_state_change_support = true; 2120 + dc->clk_mgr->clks.fw_based_mclk_switching = true; 2121 + } else { 2122 + dc->clk_mgr->clks.fw_based_mclk_switching = false; 2123 + } 2124 + 2116 2125 dc->clk_mgr->funcs->update_clocks( 2117 2126 dc->clk_mgr, 2118 2127 context,

+24 -1

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c

··· 983 983 } 984 984 985 985 void dcn30_prepare_bandwidth(struct dc *dc, 986 - struct dc_state *context) 986 + struct dc_state *context) 987 987 { 988 + bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support; 989 + /* Any transition into an FPO config should disable MCLK switching first to avoid 990 + * driver and FW P-State synchronization issues. 991 + */ 992 + if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) { 993 + dc->optimized_required = true; 994 + context->bw_ctx.bw.dcn.clk.p_state_change_support = false; 995 + } 996 + 988 997 if (dc->clk_mgr->dc_mode_softmax_enabled) 989 998 if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && 990 999 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) 991 1000 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz); 992 1001 993 1002 dcn20_prepare_bandwidth(dc, context); 1003 + /* 1004 + * enabled -> enabled: do not disable 1005 + * enabled -> disabled: disable 1006 + * disabled -> enabled: don't care 1007 + * disabled -> disabled: don't care 1008 + */ 1009 + if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) 1010 + dc_dmub_srv_p_state_delegate(dc, false, context); 1011 + 1012 + if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) { 1013 + /* After disabling P-State, restore the original value to ensure we get the correct P-State 1014 + * on the next optimize. */ 1015 + context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support; 1016 + } 994 1017 } 995 1018

+3 -1

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c

··· 701 701 .argb8888 = 167, 702 702 .nv12 = 167, 703 703 .fp16 = 167 704 - } 704 + }, 705 + 16, 706 + 16 705 707 }; 706 708 707 709 static const struct dc_debug_options debug_defaults_drv = {

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c

··· 295 295 if (dc->res_pool->hubbub->funcs->init_crb) 296 296 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 297 297 #endif 298 + 299 + // Get DMCUB capabilities 300 + dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub); 301 + dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; 298 302 } 299 303 300 304 void dcn31_dsc_pg_control(

+1 -1

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c

··· 274 274 } 275 275 } 276 276 277 - void dccg314_init(struct dccg *dccg) 277 + static void dccg314_init(struct dccg *dccg) 278 278 { 279 279 int otg_inst; 280 280

+1 -1

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c

··· 885 885 static const struct dc_debug_options debug_defaults_drv = { 886 886 .disable_z10 = false, 887 887 .enable_z9_disable_interface = true, 888 - .minimum_z8_residency_time = 3080, 888 + .minimum_z8_residency_time = 2000, 889 889 .psr_skip_crtc_disable = true, 890 890 .disable_dmcu = true, 891 891 .force_abm_enable = false,

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

··· 948 948 if (dc->ctx->dmub_srv) { 949 949 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub); 950 950 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; 951 + dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch; 951 952 } 952 953 } 953 954

+30 -22

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

··· 324 324 325 325 static const struct dcn10_link_enc_mask le_mask = { 326 326 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \ 327 - 328 327 //DPCS_DCN31_MASK_SH_LIST(_MASK) 329 328 }; 330 329 ··· 2023 2024 // In general cases we want to keep the dram clock change requirement 2024 2025 // (prefer configs that support MCLK switch). Only override to false 2025 2026 // for SubVP 2026 - if (subvp_in_use) 2027 + if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || subvp_in_use) 2027 2028 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false; 2028 2029 else 2029 2030 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true; ··· 2079 2080 .restore_mall_state = dcn32_restore_mall_state, 2080 2081 }; 2081 2082 2083 + static uint32_t read_pipe_fuses(struct dc_context *ctx) 2084 + { 2085 + uint32_t value = REG_READ(CC_DC_PIPE_DIS); 2086 + /* DCN32 support max 4 pipes */ 2087 + value = value & 0xf; 2088 + return value; 2089 + } 2090 + 2082 2091 2083 2092 static bool dcn32_resource_construct( 2084 2093 uint8_t num_virtual_links, ··· 2100 2093 uint32_t pipe_fuses = 0; 2101 2094 uint32_t num_pipes = 4; 2102 2095 2103 - #undef REG_STRUCT 2104 - #define REG_STRUCT bios_regs 2105 - bios_regs_init(); 2096 + #undef REG_STRUCT 2097 + #define REG_STRUCT bios_regs 2098 + bios_regs_init(); 2106 2099 2107 - #undef REG_STRUCT 2108 - #define REG_STRUCT clk_src_regs 2109 - clk_src_regs_init(0, A), 2110 - clk_src_regs_init(1, B), 2111 - clk_src_regs_init(2, C), 2112 - clk_src_regs_init(3, D), 2113 - clk_src_regs_init(4, E); 2114 - #undef REG_STRUCT 2115 - #define REG_STRUCT abm_regs 2116 - abm_regs_init(0), 2117 - abm_regs_init(1), 2118 - abm_regs_init(2), 2119 - abm_regs_init(3); 2100 + #undef REG_STRUCT 2101 + #define REG_STRUCT clk_src_regs 2102 + clk_src_regs_init(0, A), 2103 + clk_src_regs_init(1, B), 2104 + clk_src_regs_init(2, C), 2105 + clk_src_regs_init(3, D), 2106 + clk_src_regs_init(4, E); 2120 2107 2121 - #undef REG_STRUCT 2122 - #define REG_STRUCT dccg_regs 2123 - dccg_regs_init(); 2108 + #undef REG_STRUCT 2109 + #define REG_STRUCT abm_regs 2110 + abm_regs_init(0), 2111 + abm_regs_init(1), 2112 + abm_regs_init(2), 2113 + abm_regs_init(3); 2114 + 2115 + #undef REG_STRUCT 2116 + #define REG_STRUCT dccg_regs 2117 + dccg_regs_init(); 2124 2118 2125 2119 DC_FP_START(); 2126 2120 ··· 2130 2122 pool->base.res_cap = &res_cap_dcn32; 2131 2123 /* max number of pipes for ASIC before checking for pipe fuses */ 2132 2124 num_pipes = pool->base.res_cap->num_timing_generator; 2133 - pipe_fuses = REG_READ(CC_DC_PIPE_DIS); 2125 + pipe_fuses = read_pipe_fuses(ctx); 2134 2126 2135 2127 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 2136 2128 if (pipe_fuses & 1 << i)

+9 -1

drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c

··· 1632 1632 .restore_mall_state = dcn32_restore_mall_state, 1633 1633 }; 1634 1634 1635 + static uint32_t read_pipe_fuses(struct dc_context *ctx) 1636 + { 1637 + uint32_t value = REG_READ(CC_DC_PIPE_DIS); 1638 + /* DCN321 support max 4 pipes */ 1639 + value = value & 0xf; 1640 + return value; 1641 + } 1642 + 1635 1643 1636 1644 static bool dcn321_resource_construct( 1637 1645 uint8_t num_virtual_links, ··· 1682 1674 pool->base.res_cap = &res_cap_dcn321; 1683 1675 /* max number of pipes for ASIC before checking for pipe fuses */ 1684 1676 num_pipes = pool->base.res_cap->num_timing_generator; 1685 - pipe_fuses = REG_READ(CC_DC_PIPE_DIS); 1677 + pipe_fuses = read_pipe_fuses(ctx); 1686 1678 1687 1679 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 1688 1680 if (pipe_fuses & 1 << i)

+91 -87

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

··· 917 917 } 918 918 919 919 void dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params, 920 - struct dc_state *context, 921 - display_e2e_pipe_params_st *pipes, 922 - int pipe_cnt, int i) 920 + struct dc_state *context, 921 + display_e2e_pipe_params_st *pipes, 922 + int pipe_cnt, int i) 923 923 { 924 - int k; 924 + int k; 925 925 926 - dc_assert_fp_enabled(); 926 + dc_assert_fp_enabled(); 927 927 928 - for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) { 929 - wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 930 - wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 931 - } 932 - wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */ 928 + for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) { 929 + wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 930 + wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 931 + } 932 + wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */ 933 933 } 934 934 935 935 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) ··· 1037 1037 *vstartup_start = ((newVstartup > *vstartup_start) ? newVstartup : *vstartup_start); 1038 1038 } 1039 1039 1040 - void dcn20_calculate_dlg_params( 1041 - struct dc *dc, struct dc_state *context, 1042 - display_e2e_pipe_params_st *pipes, 1043 - int pipe_cnt, 1044 - int vlevel) 1040 + void dcn20_calculate_dlg_params(struct dc *dc, 1041 + struct dc_state *context, 1042 + display_e2e_pipe_params_st *pipes, 1043 + int pipe_cnt, 1044 + int vlevel) 1045 1045 { 1046 1046 int i, pipe_idx; 1047 1047 ··· 1083 1083 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 1084 1084 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 1085 1085 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 1086 + 1086 1087 if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { 1087 1088 // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests 1088 1089 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0; ··· 1092 1091 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes; 1093 1092 context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode; 1094 1093 } 1094 + 1095 1095 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 1096 1096 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 1097 1097 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = ··· 1120 1118 if (!context->res_ctx.pipe_ctx[i].stream) 1121 1119 continue; 1122 1120 1121 + /* cstate disabled on 201 */ 1123 1122 if (dc->ctx->dce_version == DCN_VERSION_2_01) 1124 1123 cstate_en = false; 1125 1124 ··· 1204 1201 } 1205 1202 } 1206 1203 1207 - int dcn20_populate_dml_pipes_from_context( 1208 - struct dc *dc, 1209 - struct dc_state *context, 1210 - display_e2e_pipe_params_st *pipes, 1211 - bool fast_validate) 1204 + int dcn20_populate_dml_pipes_from_context(struct dc *dc, 1205 + struct dc_state *context, 1206 + display_e2e_pipe_params_st *pipes, 1207 + bool fast_validate) 1212 1208 { 1213 1209 int pipe_cnt, i; 1214 1210 bool synchronized_vblank = true; ··· 1259 1257 1260 1258 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; 1261 1259 1260 + pipes[pipe_cnt].pipe.dest.use_maximum_vstartup = dc->ctx->dce_version == DCN_VERSION_2_01; 1261 + 1262 1262 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC; 1263 1263 /* todo: rotation?*/ 1264 1264 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; ··· 1300 1296 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2; 1301 1297 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst; 1302 1298 pipes[pipe_cnt].dout.dp_lanes = 4; 1303 - if (res_ctx->pipe_ctx[i].stream->link) 1304 - pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na; 1299 + pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na; 1305 1300 pipes[pipe_cnt].dout.is_virtual = 0; 1306 1301 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min; 1307 1302 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max; ··· 1360 1357 pipes[pipe_cnt].dout.is_virtual = 1; 1361 1358 pipes[pipe_cnt].dout.output_type = dm_dp; 1362 1359 pipes[pipe_cnt].dout.dp_lanes = 4; 1363 - pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_hbr2; 1364 1360 } 1365 1361 1366 1362 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) { ··· 1509 1507 default: 1510 1508 break; 1511 1509 } 1510 + 1512 1511 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y; 1513 1512 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y; 1514 1513 pipes[pipe_cnt].pipe.src.viewport_x_y = scl->viewport.x; ··· 1618 1615 return pipe_cnt; 1619 1616 } 1620 1617 1621 - void dcn20_calculate_wm( 1622 - struct dc *dc, struct dc_state *context, 1623 - display_e2e_pipe_params_st *pipes, 1624 - int *out_pipe_cnt, 1625 - int *pipe_split_from, 1626 - int vlevel, 1627 - bool fast_validate) 1618 + void dcn20_calculate_wm(struct dc *dc, struct dc_state *context, 1619 + display_e2e_pipe_params_st *pipes, 1620 + int *out_pipe_cnt, 1621 + int *pipe_split_from, 1622 + int vlevel, 1623 + bool fast_validate) 1628 1624 { 1629 1625 int pipe_cnt, i, pipe_idx; 1630 1626 ··· 1735 1733 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 1736 1734 } 1737 1735 1738 - void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb, 1739 - struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) 1736 + void dcn20_update_bounding_box(struct dc *dc, 1737 + struct _vcs_dpi_soc_bounding_box_st *bb, 1738 + struct pp_smu_nv_clock_table *max_clocks, 1739 + unsigned int *uclk_states, 1740 + unsigned int num_states) 1740 1741 { 1741 1742 int num_calculated_states = 0; 1742 1743 int min_dcfclk = 0; ··· 1801 1796 bb->clock_limits[num_calculated_states].state = bb->num_states; 1802 1797 } 1803 1798 1804 - void dcn20_cap_soc_clocks( 1805 - struct _vcs_dpi_soc_bounding_box_st *bb, 1806 - struct pp_smu_nv_clock_table max_clocks) 1799 + void dcn20_cap_soc_clocks(struct _vcs_dpi_soc_bounding_box_st *bb, 1800 + struct pp_smu_nv_clock_table max_clocks) 1807 1801 { 1808 1802 int i; 1809 1803 ··· 1958 1954 } 1959 1955 1960 1956 bool dcn20_validate_bandwidth_fp(struct dc *dc, 1961 - struct dc_state *context, 1962 - bool fast_validate) 1957 + struct dc_state *context, 1958 + bool fast_validate) 1963 1959 { 1964 - bool voltage_supported = false; 1965 - bool full_pstate_supported = false; 1966 - bool dummy_pstate_supported = false; 1967 - double p_state_latency_us; 1960 + bool voltage_supported = false; 1961 + bool full_pstate_supported = false; 1962 + bool dummy_pstate_supported = false; 1963 + double p_state_latency_us; 1968 1964 1969 - dc_assert_fp_enabled(); 1965 + dc_assert_fp_enabled(); 1970 1966 1971 - p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us; 1972 - context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support = 1973 - dc->debug.disable_dram_clock_change_vactive_support; 1974 - context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive = 1975 - dc->debug.enable_dram_clock_change_one_display_vactive; 1967 + p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us; 1968 + context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support = 1969 + dc->debug.disable_dram_clock_change_vactive_support; 1970 + context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive = 1971 + dc->debug.enable_dram_clock_change_one_display_vactive; 1976 1972 1977 - /*Unsafe due to current pipe merge and split logic*/ 1978 - ASSERT(context != dc->current_state); 1973 + /*Unsafe due to current pipe merge and split logic*/ 1974 + ASSERT(context != dc->current_state); 1979 1975 1980 - if (fast_validate) { 1981 - return dcn20_validate_bandwidth_internal(dc, context, true); 1982 - } 1976 + if (fast_validate) { 1977 + return dcn20_validate_bandwidth_internal(dc, context, true); 1978 + } 1983 1979 1984 - // Best case, we support full UCLK switch latency 1985 - voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 1986 - full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 1980 + // Best case, we support full UCLK switch latency 1981 + voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 1982 + full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 1987 1983 1988 - if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 || 1989 - (voltage_supported && full_pstate_supported)) { 1990 - context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported; 1991 - goto restore_dml_state; 1992 - } 1984 + if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 || 1985 + (voltage_supported && full_pstate_supported)) { 1986 + context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported; 1987 + goto restore_dml_state; 1988 + } 1993 1989 1994 - // Fallback: Try to only support G6 temperature read latency 1995 - context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; 1990 + // Fallback: Try to only support G6 temperature read latency 1991 + context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; 1996 1992 1997 - voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 1998 - dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 1993 + voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false); 1994 + dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; 1999 1995 2000 - if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) { 2001 - context->bw_ctx.bw.dcn.clk.p_state_change_support = false; 2002 - goto restore_dml_state; 2003 - } 1996 + if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) { 1997 + context->bw_ctx.bw.dcn.clk.p_state_change_support = false; 1998 + goto restore_dml_state; 1999 + } 2004 2000 2005 - // ERROR: fallback is supposed to always work. 2006 - ASSERT(false); 2001 + // ERROR: fallback is supposed to always work. 2002 + ASSERT(false); 2007 2003 2008 2004 restore_dml_state: 2009 - context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us; 2010 - return voltage_supported; 2005 + context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us; 2006 + return voltage_supported; 2011 2007 } 2012 2008 2013 2009 void dcn20_fpu_set_wm_ranges(int i, 2014 - struct pp_smu_wm_range_sets *ranges, 2015 - struct _vcs_dpi_soc_bounding_box_st *loaded_bb) 2010 + struct pp_smu_wm_range_sets *ranges, 2011 + struct _vcs_dpi_soc_bounding_box_st *loaded_bb) 2016 2012 { 2017 - dc_assert_fp_enabled(); 2013 + dc_assert_fp_enabled(); 2018 2014 2019 - ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; 2020 - ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; 2015 + ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; 2016 + ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; 2021 2017 } 2022 2018 2023 2019 void dcn20_fpu_adjust_dppclk(struct vba_vars_st *v, 2024 - int vlevel, 2025 - int max_mpc_comb, 2026 - int pipe_idx, 2027 - bool is_validating_bw) 2020 + int vlevel, 2021 + int max_mpc_comb, 2022 + int pipe_idx, 2023 + bool is_validating_bw) 2028 2024 { 2029 - dc_assert_fp_enabled(); 2025 + dc_assert_fp_enabled(); 2030 2026 2031 - if (is_validating_bw) 2032 - v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] *= 2; 2033 - else 2034 - v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2; 2027 + if (is_validating_bw) 2028 + v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] *= 2; 2029 + else 2030 + v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2; 2035 2031 } 2036 2032 2037 2033 int dcn21_populate_dml_pipes_from_context(struct dc *dc, ··· 2333 2329 k++; 2334 2330 } 2335 2331 2336 - memcpy(dcn2_1_soc.clock_limits, s, sizeof(dcn2_1_soc.clock_limits)); 2332 + memcpy(&dcn2_1_soc.clock_limits, s, sizeof(dcn2_1_soc.clock_limits)); 2337 2333 2338 2334 if (clk_table->num_entries) { 2339 2335 dcn2_1_soc.num_states = clk_table->num_entries + 1;

+17 -1

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

··· 368 368 dc_assert_fp_enabled(); 369 369 370 370 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { 371 - context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 371 + if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || 372 + context->bw_ctx.dml.soc.dram_clock_change_latency_us == 0) 373 + context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 372 374 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us; 373 375 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; 374 376 } ··· 563 561 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 564 562 565 563 pipe_idx++; 564 + } 565 + 566 + // WA: restrict FPO to use first non-strobe mode (NV24 BW issue) 567 + if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && 568 + dc->dml.soc.num_chans <= 4 && 569 + context->bw_ctx.dml.vba.DRAMSpeed <= 1700 && 570 + context->bw_ctx.dml.vba.DRAMSpeed >= 1500) { 571 + 572 + for (i = 0; i < dc->dml.soc.num_states; i++) { 573 + if (dc->dml.soc.clock_limits[i].dram_speed_mts > 1700) { 574 + context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[i].dram_speed_mts; 575 + break; 576 + } 577 + } 566 578 } 567 579 568 580 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

+2 -2

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

··· 149 149 .num_states = 5, 150 150 .sr_exit_time_us = 16.5, 151 151 .sr_enter_plus_exit_time_us = 18.5, 152 - .sr_exit_z8_time_us = 210.0, 153 - .sr_enter_plus_exit_z8_time_us = 310.0, 152 + .sr_exit_z8_time_us = 268.0, 153 + .sr_enter_plus_exit_z8_time_us = 393.0, 154 154 .writeback_latency_us = 12.0, 155 155 .dram_channel_width_bytes = 4, 156 156 .round_trip_ping_latency_dcfclk_cycles = 106,

+14 -3

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

··· 109 109 { 110 110 .state = 0, 111 111 .dcfclk_mhz = 1564.0, 112 - .fabricclk_mhz = 400.0, 112 + .fabricclk_mhz = 2500.0, 113 113 .dispclk_mhz = 2150.0, 114 114 .dppclk_mhz = 2150.0, 115 115 .phyclk_mhz = 810.0, ··· 117 117 .phyclk_d32_mhz = 625.0, 118 118 .socclk_mhz = 1200.0, 119 119 .dscclk_mhz = 716.667, 120 - .dram_speed_mts = 16000.0, 120 + .dram_speed_mts = 18000.0, 121 121 .dtbclk_mhz = 1564.0, 122 122 }, 123 123 }, ··· 148 148 .max_avg_fabric_bw_use_normal_percent = 60.0, 149 149 .max_avg_dram_bw_use_normal_strobe_percent = 50.0, 150 150 .max_avg_dram_bw_use_normal_percent = 15.0, 151 - .num_chans = 8, 151 + .num_chans = 24, 152 152 .dram_channel_width_bytes = 2, 153 153 .fabric_datapath_to_dcn_data_return_bytes = 64, 154 154 .return_bus_width_bytes = 64, ··· 1330 1330 context->bw_ctx.bw.dcn.clk.p_state_change_support = 1331 1331 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] 1332 1332 != dm_dram_clock_change_unsupported; 1333 + 1334 + /* Pstate change might not be supported by hardware, but it might be 1335 + * possible with firmware driven vertical blank stretching. 1336 + */ 1337 + context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching; 1333 1338 1334 1339 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 1335 1340 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); ··· 2875 2870 pipe_idx++; 2876 2871 } 2877 2872 return vactive_found; 2873 + } 2874 + 2875 + void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb) 2876 + { 2877 + dc_assert_fp_enabled(); 2878 + dcn3_2_soc.clock_limits[0].dcfclk_mhz = 1200.0; 2878 2879 }

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

··· 80 80 81 81 bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, uint32_t vactive_margin_req); 82 82 83 + void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb); 84 + 83 85 #endif

+12 -12

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

··· 106 106 .clock_limits = { 107 107 { 108 108 .state = 0, 109 - .dcfclk_mhz = 1564.0, 110 - .fabricclk_mhz = 400.0, 111 - .dispclk_mhz = 2150.0, 112 - .dppclk_mhz = 2150.0, 109 + .dcfclk_mhz = 1434.0, 110 + .fabricclk_mhz = 2250.0, 111 + .dispclk_mhz = 1720.0, 112 + .dppclk_mhz = 1720.0, 113 113 .phyclk_mhz = 810.0, 114 114 .phyclk_d18_mhz = 667.0, 115 - .phyclk_d32_mhz = 625.0, 115 + .phyclk_d32_mhz = 313.0, 116 116 .socclk_mhz = 1200.0, 117 - .dscclk_mhz = 716.667, 118 - .dram_speed_mts = 1600.0, 117 + .dscclk_mhz = 573.333, 118 + .dram_speed_mts = 16000.0, 119 119 .dtbclk_mhz = 1564.0, 120 120 }, 121 121 }, ··· 125 125 .sr_exit_z8_time_us = 285.0, 126 126 .sr_enter_plus_exit_z8_time_us = 320, 127 127 .writeback_latency_us = 12.0, 128 - .round_trip_ping_latency_dcfclk_cycles = 263, 128 + .round_trip_ping_latency_dcfclk_cycles = 207, 129 129 .urgent_latency_pixel_data_only_us = 4, 130 130 .urgent_latency_pixel_mixed_with_vm_data_us = 4, 131 131 .urgent_latency_vm_data_only_us = 4, 132 - .fclk_change_latency_us = 20, 133 - .usr_retraining_latency_us = 2, 134 - .smn_latency_us = 2, 135 - .mall_allocated_for_dcn_mbytes = 64, 132 + .fclk_change_latency_us = 7, 133 + .usr_retraining_latency_us = 0, 134 + .smn_latency_us = 0, 135 + .mall_allocated_for_dcn_mbytes = 32, 136 136 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 137 137 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 138 138 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

··· 1927 1927 1928 1928 dp_disable_link_phy(link, link_res, signal); 1929 1929 1930 + if (link->connector_signal == SIGNAL_TYPE_EDP) { 1931 + if (!link->dc->config.edp_no_power_sequencing) 1932 + link->dc->hwss.edp_power_control(link, false); 1933 + } 1934 + 1930 1935 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 1931 1936 /* set the sink to SST mode after disabling the link */ 1932 1937 enable_mst_on_sink(link, false);

+4 -1

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

··· 1596 1596 * Report and continue with eDP panel mode to 1597 1597 * perform eDP link training with right settings 1598 1598 */ 1599 - cp_psp->funcs.enable_assr(cp_psp->handle, link); 1599 + bool result; 1600 + result = cp_psp->funcs.enable_assr(cp_psp->handle, link); 1601 + if (!result && link->panel_mode != DP_PANEL_MODE_EDP) 1602 + panel_mode = DP_PANEL_MODE_DEFAULT; 1600 1603 } 1601 1604 } 1602 1605

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

··· 83 83 ASSERT(result == DC_OK); 84 84 } 85 85 } 86 + link->panel_mode = panel_mode; 86 87 DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d " 87 88 "eDP panel mode enabled: %d \n", 88 89 link->link_index,

+2 -1

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

··· 130 130 REG_WRITE(DMCUB_INBOX1_WPTR, 0); 131 131 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); 132 132 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); 133 + REG_WRITE(DMCUB_OUTBOX0_RPTR, 0); 134 + REG_WRITE(DMCUB_OUTBOX0_WPTR, 0); 133 135 REG_WRITE(DMCUB_SCRATCH0, 0); 134 136 } 135 137 136 138 void dmub_dcn32_reset_release(struct dmub_srv *dmub) 137 139 { 138 - REG_WRITE(DMCUB_GPINT_DATAIN1, 0); 139 140 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0); 140 141 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); 141 142 REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);

drivers/gpu/drm/amd/display/include/signal_types.h

··· 104 104 { 105 105 return (signal == SIGNAL_TYPE_DISPLAY_PORT || 106 106 signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 107 + signal == SIGNAL_TYPE_VIRTUAL || 107 108 dc_is_hdmi_signal(signal)); 108 109 } 109 110

+2 -2

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h

··· 62 62 #define CTF_OFFSET_HOTSPOT 5 63 63 #define CTF_OFFSET_MEM 5 64 64 65 - static const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5}; 66 - static const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16}; 65 + extern const int pmfw_decoded_link_speed[5]; 66 + extern const int pmfw_decoded_link_width[7]; 67 67 68 68 #define DECODE_GEN_SPEED(gen_speed_idx) (pmfw_decoded_link_speed[gen_speed_idx]) 69 69 #define DECODE_LANE_WIDTH(lane_width_idx) (pmfw_decoded_link_width[lane_width_idx])

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

··· 85 85 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16}; 86 86 static const int link_speed[] = {25, 50, 80, 160}; 87 87 88 + const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5}; 89 + const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16}; 90 + 88 91 int smu_v13_0_init_microcode(struct smu_context *smu) 89 92 { 90 93 struct amdgpu_device *adev = smu->adev;

+1 -1

drivers/gpu/drm/i915/display/icl_dsi.c

··· 1140 1140 1141 1141 /* panel power on related mipi dsi vbt sequences */ 1142 1142 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1143 - intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 1143 + msleep(intel_dsi->panel_on_delay); 1144 1144 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1145 1145 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1146 1146 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);

-11

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

··· 763 763 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0); 764 764 } 765 765 766 - void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) 767 - { 768 - struct intel_connector *connector = intel_dsi->attached_connector; 769 - 770 - /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */ 771 - if (is_vid_mode(intel_dsi) && connector->panel.vbt.dsi.seq_version >= 3) 772 - return; 773 - 774 - msleep(msec); 775 - } 776 - 777 766 void intel_dsi_log_params(struct intel_dsi *intel_dsi) 778 767 { 779 768 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);

-1

drivers/gpu/drm/i915/display/intel_dsi_vbt.h

··· 16 16 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi); 17 17 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi, 18 18 enum mipi_seq seq_id); 19 - void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec); 20 19 void intel_dsi_log_params(struct intel_dsi *intel_dsi); 21 20 22 21 #endif /* __INTEL_DSI_VBT_H__ */

+17

drivers/gpu/drm/i915/display/skl_scaler.c

··· 111 111 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 112 112 const struct drm_display_mode *adjusted_mode = 113 113 &crtc_state->hw.adjusted_mode; 114 + int pipe_src_w = drm_rect_width(&crtc_state->pipe_src); 115 + int pipe_src_h = drm_rect_height(&crtc_state->pipe_src); 114 116 int min_src_w, min_src_h, min_dst_w, min_dst_h; 115 117 int max_src_w, max_src_h, max_dst_w, max_dst_h; 116 118 ··· 206 204 "size is out of scaler range\n", 207 205 crtc->pipe, scaler_user, src_w, src_h, 208 206 dst_w, dst_h); 207 + return -EINVAL; 208 + } 209 + 210 + /* 211 + * The pipe scaler does not use all the bits of PIPESRC, at least 212 + * on the earlier platforms. So even when we're scaling a plane 213 + * the *pipe* source size must not be too large. For simplicity 214 + * we assume the limits match the scaler source size limits. Might 215 + * not be 100% accurate on all platforms, but good enough for now. 216 + */ 217 + if (pipe_src_w > max_src_w || pipe_src_h > max_src_h) { 218 + drm_dbg_kms(&dev_priv->drm, 219 + "scaler_user index %u.%u: pipe src size %ux%u " 220 + "is out of scaler range\n", 221 + crtc->pipe, scaler_user, pipe_src_w, pipe_src_h); 209 222 return -EINVAL; 210 223 } 211 224

+5 -17

drivers/gpu/drm/i915/display/vlv_dsi.c

··· 737 737 { 738 738 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 739 739 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 740 - struct intel_connector *connector = to_intel_connector(conn_state->connector); 741 740 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 742 741 enum pipe pipe = crtc->pipe; 743 742 enum port port; ··· 778 779 if (!IS_GEMINILAKE(dev_priv)) 779 780 intel_dsi_prepare(encoder, pipe_config); 780 781 782 + /* Give the panel time to power-on and then deassert its reset */ 781 783 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 782 - 783 - /* 784 - * Give the panel time to power-on and then deassert its reset. 785 - * Depending on the VBT MIPI sequences version the deassert-seq 786 - * may contain the necessary delay, intel_dsi_msleep() will skip 787 - * the delay in that case. If there is no deassert-seq, then an 788 - * unconditional msleep is used to give the panel time to power-on. 789 - */ 790 - if (connector->panel.vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) { 791 - intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 792 - intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 793 - } else { 794 - msleep(intel_dsi->panel_on_delay); 795 - } 784 + msleep(intel_dsi->panel_on_delay); 785 + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 796 786 797 787 if (IS_GEMINILAKE(dev_priv)) { 798 788 glk_cold_boot = glk_dsi_enable_io(encoder); ··· 815 827 msleep(20); /* XXX */ 816 828 for_each_dsi_port(port, intel_dsi->ports) 817 829 dpi_send_cmd(intel_dsi, TURN_ON, false, port); 818 - intel_dsi_msleep(intel_dsi, 100); 830 + msleep(100); 819 831 820 832 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 821 833 ··· 937 949 /* Assert reset */ 938 950 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 939 951 940 - intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay); 952 + msleep(intel_dsi->panel_off_delay); 941 953 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 942 954 943 955 intel_dsi->panel_power_off_time = ktime_get_boottime();

+12 -8

drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c

··· 635 635 return ver->major < 0xFF && ver->minor < 0xFF && ver->patch < 0xFF; 636 636 } 637 637 638 - static bool guc_check_version_range(struct intel_uc_fw *uc_fw) 638 + static int guc_check_version_range(struct intel_uc_fw *uc_fw) 639 639 { 640 640 struct intel_guc *guc = container_of(uc_fw, struct intel_guc, fw); 641 + struct intel_gt *gt = __uc_fw_to_gt(uc_fw); 641 642 642 643 /* 643 644 * GuC version number components are defined as being 8-bits. ··· 647 646 */ 648 647 649 648 if (!is_ver_8bit(&uc_fw->file_selected.ver)) { 650 - gt_warn(__uc_fw_to_gt(uc_fw), "%s firmware: invalid file version: 0x%02X:%02X:%02X\n", 649 + gt_warn(gt, "%s firmware: invalid file version: 0x%02X:%02X:%02X\n", 651 650 intel_uc_fw_type_repr(uc_fw->type), 652 651 uc_fw->file_selected.ver.major, 653 652 uc_fw->file_selected.ver.minor, 654 653 uc_fw->file_selected.ver.patch); 655 - return false; 654 + return -EINVAL; 656 655 } 657 656 658 657 if (!is_ver_8bit(&guc->submission_version)) { 659 - gt_warn(__uc_fw_to_gt(uc_fw), "%s firmware: invalid submit version: 0x%02X:%02X:%02X\n", 658 + gt_warn(gt, "%s firmware: invalid submit version: 0x%02X:%02X:%02X\n", 660 659 intel_uc_fw_type_repr(uc_fw->type), 661 660 guc->submission_version.major, 662 661 guc->submission_version.minor, 663 662 guc->submission_version.patch); 664 - return false; 663 + return -EINVAL; 665 664 } 666 665 667 - return true; 666 + return i915_inject_probe_error(gt->i915, -EINVAL); 668 667 } 669 668 670 669 static int check_fw_header(struct intel_gt *gt, ··· 773 772 if (err) 774 773 goto fail; 775 774 776 - if (uc_fw->type == INTEL_UC_FW_TYPE_GUC && !guc_check_version_range(uc_fw)) 777 - goto fail; 775 + if (uc_fw->type == INTEL_UC_FW_TYPE_GUC) { 776 + err = guc_check_version_range(uc_fw); 777 + if (err) 778 + goto fail; 779 + } 778 780 779 781 if (uc_fw->file_wanted.ver.major && uc_fw->file_selected.ver.major) { 780 782 /* Check the file's major version was as it claimed */

drivers/gpu/drm/i915/i915_pci.c

··· 1134 1134 static const struct intel_device_info mtl_info = { 1135 1135 XE_HP_FEATURES, 1136 1136 XE_LPDP_FEATURES, 1137 + .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 1138 + BIT(TRANSCODER_C) | BIT(TRANSCODER_D), 1137 1139 /* 1138 1140 * Real graphics IP version will be obtained from hardware GMD_ID 1139 1141 * register. Value provided here is just for sanity checking.

Configure Feed

Configure Feed