tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'pci-v3.18-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI fixes from Bjorn Helgaas:
"These are fixes for an issue with 64-bit PCI bus addresses on 32-bit
PAE kernels, an APM X-Gene problem (it depended on a generic change we
removed before merging), a fix for my hotplug device configuration
changes, and a devicetree documentation update.

Resource management:
- Support 64-bit bridge windows if we have 64-bit dma_addr_t (Yinghai Lu)

PCI device hotplug:
- Apply _HPX Link Control settings to all devices with a link (Yinghai Lu)

Generic host bridge driver:
- Add DT binding for "linux,pci-domain" property (Lucas Stach)

APM X-Gene:
- Assign resources to bus before adding new devices (Duc Dang)"

* tag 'pci-v3.18-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
PCI: Support 64-bit bridge windows if we have 64-bit dma_addr_t
PCI: Apply _HPX Link Control settings to all devices with a link
PCI: Add missing DT binding for "linux,pci-domain" property
PCI: xgene: Assign resources to bus before adding new devices

Linus Torvalds 08685897 a46171d0

+37 -15
+11
Documentation/devicetree/bindings/pci/pci.txt
··· 7 7 8 8 Open Firmware Recommended Practice: Interrupt Mapping 9 9 http://www.openfirmware.org/1275/practice/imap/imap0_9d.pdf 10 + 11 + Additionally to the properties specified in the above standards a host bridge 12 + driver implementation may support the following properties: 13 + 14 + - linux,pci-domain: 15 + If present this property assigns a fixed PCI domain number to a host bridge, 16 + otherwise an unstable (across boots) unique number will be assigned. 17 + It is required to either not set this property at all or set it for all 18 + host bridges in the system, otherwise potentially conflicting domain numbers 19 + may be assigned to root buses behind different host bridges. The domain 20 + number for each host bridge in the system must be unique.
+1 -1
drivers/pci/access.c
··· 444 444 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS; 445 445 } 446 446 447 - static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev) 447 + bool pcie_cap_has_lnkctl(const struct pci_dev *dev) 448 448 { 449 449 int type = pci_pcie_type(dev); 450 450
+6 -1
drivers/pci/host/pci-xgene.c
··· 631 631 if (ret) 632 632 return ret; 633 633 634 - bus = pci_scan_root_bus(&pdev->dev, 0, &xgene_pcie_ops, port, &res); 634 + bus = pci_create_root_bus(&pdev->dev, 0, 635 + &xgene_pcie_ops, port, &res); 635 636 if (!bus) 636 637 return -ENOMEM; 638 + 639 + pci_scan_child_bus(bus); 640 + pci_assign_unassigned_bus_resources(bus); 641 + pci_bus_add_devices(bus); 637 642 638 643 platform_set_drvdata(pdev, port); 639 644 return 0;
+2
drivers/pci/pci.h
··· 6 6 7 7 extern const unsigned char pcie_link_speed[]; 8 8 9 + bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 10 + 9 11 /* Functions internal to the PCI core code */ 10 12 11 13 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
+17 -13
drivers/pci/probe.c
··· 407 407 { 408 408 struct pci_dev *dev = child->self; 409 409 u16 mem_base_lo, mem_limit_lo; 410 - unsigned long base, limit; 410 + u64 base64, limit64; 411 + dma_addr_t base, limit; 411 412 struct pci_bus_region region; 412 413 struct resource *res; 413 414 414 415 res = child->resource[2]; 415 416 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 416 417 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 417 - base = ((unsigned long) mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 418 - limit = ((unsigned long) mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 418 + base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 419 + limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 419 420 420 421 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 421 422 u32 mem_base_hi, mem_limit_hi; ··· 430 429 * this, just assume they are not being used. 431 430 */ 432 431 if (mem_base_hi <= mem_limit_hi) { 433 - #if BITS_PER_LONG == 64 434 - base |= ((unsigned long) mem_base_hi) << 32; 435 - limit |= ((unsigned long) mem_limit_hi) << 32; 436 - #else 437 - if (mem_base_hi || mem_limit_hi) { 438 - dev_err(&dev->dev, "can't handle 64-bit address space for bridge\n"); 439 - return; 440 - } 441 - #endif 432 + base64 |= (u64) mem_base_hi << 32; 433 + limit64 |= (u64) mem_limit_hi << 32; 442 434 } 443 435 } 436 + 437 + base = (dma_addr_t) base64; 438 + limit = (dma_addr_t) limit64; 439 + 440 + if (base != base64) { 441 + dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", 442 + (unsigned long long) base64); 443 + return; 444 + } 445 + 444 446 if (base <= limit) { 445 447 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | 446 448 IORESOURCE_MEM | IORESOURCE_PREFETCH; ··· 1327 1323 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or); 1328 1324 1329 1325 /* Initialize Link Control Register */ 1330 - if (dev->subordinate) 1326 + if (pcie_cap_has_lnkctl(dev)) 1331 1327 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL, 1332 1328 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or); 1333 1329