Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm: drop display-related headers
Now as the headers are generated during the build step, drop
pre-generated copies of the display-related headers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/585860/
Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-12-4bdb277a85a1@linaro.org
-7456
-1181
drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h
-1181
drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h
···
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#ifndef MDP4_XML
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#define MDP4_XML
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/* Autogenerated file, DO NOT EDIT manually!
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This file was generated by the rules-ng-ng headergen tool in this git repository:
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http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
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Copyright (C) 2013-2022 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
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-
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial
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portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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enum mdp4_pipe {
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VG1 = 0,
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VG2 = 1,
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RGB1 = 2,
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RGB2 = 3,
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RGB3 = 4,
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VG3 = 5,
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VG4 = 6,
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};
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enum mdp4_mixer {
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MIXER0 = 0,
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MIXER1 = 1,
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MIXER2 = 2,
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};
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enum mdp4_intf {
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INTF_LCDC_DTV = 0,
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INTF_DSI_VIDEO = 1,
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INTF_DSI_CMD = 2,
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INTF_EBI2_TV = 3,
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};
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enum mdp4_cursor_format {
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CURSOR_ARGB = 1,
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CURSOR_XRGB = 2,
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};
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enum mdp4_frame_format {
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FRAME_LINEAR = 0,
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FRAME_TILE_ARGB_4X4 = 1,
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FRAME_TILE_YCBCR_420 = 2,
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};
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enum mdp4_scale_unit {
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SCALE_FIR = 0,
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SCALE_MN_PHASE = 1,
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SCALE_PIXEL_RPT = 2,
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};
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enum mdp4_dma {
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DMA_P = 0,
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DMA_S = 1,
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DMA_E = 2,
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};
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#define MDP4_IRQ_OVERLAY0_DONE 0x00000001
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#define MDP4_IRQ_OVERLAY1_DONE 0x00000002
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#define MDP4_IRQ_DMA_S_DONE 0x00000004
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#define MDP4_IRQ_DMA_E_DONE 0x00000008
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#define MDP4_IRQ_DMA_P_DONE 0x00000010
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#define MDP4_IRQ_VG1_HISTOGRAM 0x00000020
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#define MDP4_IRQ_VG2_HISTOGRAM 0x00000040
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#define MDP4_IRQ_PRIMARY_VSYNC 0x00000080
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#define MDP4_IRQ_PRIMARY_INTF_UDERRUN 0x00000100
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#define MDP4_IRQ_EXTERNAL_VSYNC 0x00000200
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#define MDP4_IRQ_EXTERNAL_INTF_UDERRUN 0x00000400
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#define MDP4_IRQ_PRIMARY_RDPTR 0x00000800
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#define MDP4_IRQ_DMA_P_HISTOGRAM 0x00020000
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#define MDP4_IRQ_DMA_S_HISTOGRAM 0x04000000
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#define MDP4_IRQ_OVERLAY2_DONE 0x40000000
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#define REG_MDP4_VERSION 0x00000000
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#define MDP4_VERSION_MINOR__MASK 0x00ff0000
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#define MDP4_VERSION_MINOR__SHIFT 16
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static inline uint32_t MDP4_VERSION_MINOR(uint32_t val)
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{
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return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK;
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}
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#define MDP4_VERSION_MAJOR__MASK 0xff000000
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#define MDP4_VERSION_MAJOR__SHIFT 24
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static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val)
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{
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return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK;
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}
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#define REG_MDP4_OVLP0_KICK 0x00000004
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#define REG_MDP4_OVLP1_KICK 0x00000008
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#define REG_MDP4_OVLP2_KICK 0x000000d0
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#define REG_MDP4_DMA_P_KICK 0x0000000c
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#define REG_MDP4_DMA_S_KICK 0x00000010
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#define REG_MDP4_DMA_E_KICK 0x00000014
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#define REG_MDP4_DISP_STATUS 0x00000018
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#define REG_MDP4_DISP_INTF_SEL 0x00000038
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#define MDP4_DISP_INTF_SEL_PRIM__MASK 0x00000003
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#define MDP4_DISP_INTF_SEL_PRIM__SHIFT 0
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static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val)
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{
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return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK;
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}
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#define MDP4_DISP_INTF_SEL_SEC__MASK 0x0000000c
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#define MDP4_DISP_INTF_SEL_SEC__SHIFT 2
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static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val)
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{
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return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK;
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}
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#define MDP4_DISP_INTF_SEL_EXT__MASK 0x00000030
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#define MDP4_DISP_INTF_SEL_EXT__SHIFT 4
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static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)
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{
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return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK;
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}
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#define MDP4_DISP_INTF_SEL_DSI_VIDEO 0x00000040
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#define MDP4_DISP_INTF_SEL_DSI_CMD 0x00000080
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#define REG_MDP4_RESET_STATUS 0x0000003c
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#define REG_MDP4_READ_CNFG 0x0000004c
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#define REG_MDP4_INTR_ENABLE 0x00000050
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#define REG_MDP4_INTR_STATUS 0x00000054
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#define REG_MDP4_INTR_CLEAR 0x00000058
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#define REG_MDP4_EBI2_LCD0 0x00000060
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#define REG_MDP4_EBI2_LCD1 0x00000064
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#define REG_MDP4_PORTMAP_MODE 0x00000070
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#define REG_MDP4_CS_CONTROLLER0 0x000000c0
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#define REG_MDP4_CS_CONTROLLER1 0x000000c4
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#define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK;
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}
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT 4
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK;
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}
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT 8
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK;
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}
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT 12
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK;
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}
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT 16
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK;
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}
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT 20
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK;
228
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}
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT 24
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK;
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}
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT 28
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static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
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{
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return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK;
242
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}
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#define MDP4_LAYERMIXER2_IN_CFG_PIPE7_MIXER1 0x80000000
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#define REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD 0x000100fc
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#define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100
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#define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007
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#define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
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{
252
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return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK;
253
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}
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#define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008
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#define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070
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#define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT 4
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
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{
259
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return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK;
260
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}
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#define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080
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#define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700
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#define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT 8
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
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{
266
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return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK;
267
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}
268
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#define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800
269
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#define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000
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#define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT 12
271
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
272
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{
273
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return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK;
274
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}
275
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#define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000
276
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#define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000
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#define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT 16
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
279
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{
280
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return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK;
281
-
}
282
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#define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000
283
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#define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000
284
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#define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT 20
285
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
286
-
{
287
-
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK;
288
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}
289
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#define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000
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#define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000
291
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#define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT 24
292
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
293
-
{
294
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return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK;
295
-
}
296
-
#define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000
297
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#define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000
298
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#define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT 28
299
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static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
300
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{
301
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return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK;
302
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}
303
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#define MDP4_LAYERMIXER_IN_CFG_PIPE7_MIXER1 0x80000000
304
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305
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#define REG_MDP4_VG2_SRC_FORMAT 0x00030050
306
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307
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#define REG_MDP4_VG2_CONST_COLOR 0x00031008
308
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309
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#define REG_MDP4_OVERLAY_FLUSH 0x00018000
310
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#define MDP4_OVERLAY_FLUSH_OVLP0 0x00000001
311
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#define MDP4_OVERLAY_FLUSH_OVLP1 0x00000002
312
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#define MDP4_OVERLAY_FLUSH_VG1 0x00000004
313
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#define MDP4_OVERLAY_FLUSH_VG2 0x00000008
314
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#define MDP4_OVERLAY_FLUSH_RGB1 0x00000010
315
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#define MDP4_OVERLAY_FLUSH_RGB2 0x00000020
316
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317
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static inline uint32_t __offset_OVLP(uint32_t idx)
318
-
{
319
-
switch (idx) {
320
-
case 0: return 0x00010000;
321
-
case 1: return 0x00018000;
322
-
case 2: return 0x00088000;
323
-
default: return INVALID_IDX(idx);
324
-
}
325
-
}
326
-
static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); }
327
-
328
-
static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); }
329
-
330
-
static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); }
331
-
#define MDP4_OVLP_SIZE_HEIGHT__MASK 0xffff0000
332
-
#define MDP4_OVLP_SIZE_HEIGHT__SHIFT 16
333
-
static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val)
334
-
{
335
-
return ((val) << MDP4_OVLP_SIZE_HEIGHT__SHIFT) & MDP4_OVLP_SIZE_HEIGHT__MASK;
336
-
}
337
-
#define MDP4_OVLP_SIZE_WIDTH__MASK 0x0000ffff
338
-
#define MDP4_OVLP_SIZE_WIDTH__SHIFT 0
339
-
static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val)
340
-
{
341
-
return ((val) << MDP4_OVLP_SIZE_WIDTH__SHIFT) & MDP4_OVLP_SIZE_WIDTH__MASK;
342
-
}
343
-
344
-
static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); }
345
-
346
-
static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); }
347
-
348
-
static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); }
349
-
350
-
static inline uint32_t __offset_STAGE(uint32_t idx)
351
-
{
352
-
switch (idx) {
353
-
case 0: return 0x00000104;
354
-
case 1: return 0x00000124;
355
-
case 2: return 0x00000144;
356
-
case 3: return 0x00000160;
357
-
default: return INVALID_IDX(idx);
358
-
}
359
-
}
360
-
static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
361
-
362
-
static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
363
-
#define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003
364
-
#define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0
365
-
static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val)
366
-
{
367
-
return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK;
368
-
}
369
-
#define MDP4_OVLP_STAGE_OP_FG_INV_ALPHA 0x00000004
370
-
#define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008
371
-
#define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030
372
-
#define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT 4
373
-
static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val)
374
-
{
375
-
return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK;
376
-
}
377
-
#define MDP4_OVLP_STAGE_OP_BG_INV_ALPHA 0x00000040
378
-
#define MDP4_OVLP_STAGE_OP_BG_MOD_ALPHA 0x00000080
379
-
#define MDP4_OVLP_STAGE_OP_FG_TRANSP 0x00000100
380
-
#define MDP4_OVLP_STAGE_OP_BG_TRANSP 0x00000200
381
-
382
-
static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); }
383
-
384
-
static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); }
385
-
386
-
static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); }
387
-
388
-
static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); }
389
-
390
-
static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); }
391
-
392
-
static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); }
393
-
394
-
static inline uint32_t __offset_STAGE_CO3(uint32_t idx)
395
-
{
396
-
switch (idx) {
397
-
case 0: return 0x00001004;
398
-
case 1: return 0x00001404;
399
-
case 2: return 0x00001804;
400
-
case 3: return 0x00001b84;
401
-
default: return INVALID_IDX(idx);
402
-
}
403
-
}
404
-
static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
405
-
406
-
static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
407
-
#define MDP4_OVLP_STAGE_CO3_SEL_FG_ALPHA 0x00000001
408
-
409
-
static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i0); }
410
-
411
-
static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i0); }
412
-
413
-
static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(i0); }
414
-
415
-
static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(i0); }
416
-
417
-
static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0); }
418
-
419
-
static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); }
420
-
421
-
422
-
static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
423
-
424
-
static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
425
-
426
-
static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
427
-
428
-
static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
429
-
430
-
static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
431
-
432
-
static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
433
-
434
-
static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
435
-
436
-
static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
437
-
438
-
static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
439
-
440
-
static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
441
-
442
-
#define REG_MDP4_DMA_P_OP_MODE 0x00090070
443
-
444
-
static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; }
445
-
446
-
static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
447
-
448
-
static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
449
-
450
-
#define REG_MDP4_DMA_S_OP_MODE 0x000a0028
451
-
452
-
static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; }
453
-
454
-
static inline uint32_t __offset_DMA(enum mdp4_dma idx)
455
-
{
456
-
switch (idx) {
457
-
case DMA_P: return 0x00090000;
458
-
case DMA_S: return 0x000a0000;
459
-
case DMA_E: return 0x000b0000;
460
-
default: return INVALID_IDX(idx);
461
-
}
462
-
}
463
-
static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
464
-
465
-
static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
466
-
#define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003
467
-
#define MDP4_DMA_CONFIG_G_BPC__SHIFT 0
468
-
static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val)
469
-
{
470
-
return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK;
471
-
}
472
-
#define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c
473
-
#define MDP4_DMA_CONFIG_B_BPC__SHIFT 2
474
-
static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val)
475
-
{
476
-
return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK;
477
-
}
478
-
#define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030
479
-
#define MDP4_DMA_CONFIG_R_BPC__SHIFT 4
480
-
static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val)
481
-
{
482
-
return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK;
483
-
}
484
-
#define MDP4_DMA_CONFIG_PACK_ALIGN_MSB 0x00000080
485
-
#define MDP4_DMA_CONFIG_PACK__MASK 0x0000ff00
486
-
#define MDP4_DMA_CONFIG_PACK__SHIFT 8
487
-
static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val)
488
-
{
489
-
return ((val) << MDP4_DMA_CONFIG_PACK__SHIFT) & MDP4_DMA_CONFIG_PACK__MASK;
490
-
}
491
-
#define MDP4_DMA_CONFIG_DEFLKR_EN 0x01000000
492
-
#define MDP4_DMA_CONFIG_DITHER_EN 0x01000000
493
-
494
-
static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); }
495
-
#define MDP4_DMA_SRC_SIZE_HEIGHT__MASK 0xffff0000
496
-
#define MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT 16
497
-
static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val)
498
-
{
499
-
return ((val) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK;
500
-
}
501
-
#define MDP4_DMA_SRC_SIZE_WIDTH__MASK 0x0000ffff
502
-
#define MDP4_DMA_SRC_SIZE_WIDTH__SHIFT 0
503
-
static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val)
504
-
{
505
-
return ((val) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT) & MDP4_DMA_SRC_SIZE_WIDTH__MASK;
506
-
}
507
-
508
-
static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); }
509
-
510
-
static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); }
511
-
512
-
static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); }
513
-
#define MDP4_DMA_DST_SIZE_HEIGHT__MASK 0xffff0000
514
-
#define MDP4_DMA_DST_SIZE_HEIGHT__SHIFT 16
515
-
static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val)
516
-
{
517
-
return ((val) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT) & MDP4_DMA_DST_SIZE_HEIGHT__MASK;
518
-
}
519
-
#define MDP4_DMA_DST_SIZE_WIDTH__MASK 0x0000ffff
520
-
#define MDP4_DMA_DST_SIZE_WIDTH__SHIFT 0
521
-
static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val)
522
-
{
523
-
return ((val) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT) & MDP4_DMA_DST_SIZE_WIDTH__MASK;
524
-
}
525
-
526
-
static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); }
527
-
#define MDP4_DMA_CURSOR_SIZE_WIDTH__MASK 0x0000007f
528
-
#define MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT 0
529
-
static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val)
530
-
{
531
-
return ((val) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK;
532
-
}
533
-
#define MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK 0x007f0000
534
-
#define MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT 16
535
-
static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val)
536
-
{
537
-
return ((val) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK;
538
-
}
539
-
540
-
static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0); }
541
-
542
-
static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0); }
543
-
#define MDP4_DMA_CURSOR_POS_X__MASK 0x0000ffff
544
-
#define MDP4_DMA_CURSOR_POS_X__SHIFT 0
545
-
static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val)
546
-
{
547
-
return ((val) << MDP4_DMA_CURSOR_POS_X__SHIFT) & MDP4_DMA_CURSOR_POS_X__MASK;
548
-
}
549
-
#define MDP4_DMA_CURSOR_POS_Y__MASK 0xffff0000
550
-
#define MDP4_DMA_CURSOR_POS_Y__SHIFT 16
551
-
static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val)
552
-
{
553
-
return ((val) << MDP4_DMA_CURSOR_POS_Y__SHIFT) & MDP4_DMA_CURSOR_POS_Y__MASK;
554
-
}
555
-
556
-
static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0); }
557
-
#define MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN 0x00000001
558
-
#define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK 0x00000006
559
-
#define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT 1
560
-
static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val)
561
-
{
562
-
return ((val) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK;
563
-
}
564
-
#define MDP4_DMA_CURSOR_BLEND_CONFIG_TRANSP_EN 0x00000008
565
-
566
-
static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0); }
567
-
568
-
static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0); }
569
-
570
-
static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0); }
571
-
572
-
static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0); }
573
-
574
-
static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); }
575
-
576
-
577
-
static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
578
-
579
-
static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
580
-
581
-
static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
582
-
583
-
static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
584
-
585
-
static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
586
-
587
-
static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
588
-
589
-
static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
590
-
591
-
static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
592
-
593
-
static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
594
-
595
-
static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
596
-
597
-
static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
598
-
599
-
static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
600
-
#define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
601
-
#define MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
602
-
static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
603
-
{
604
-
return ((val) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK;
605
-
}
606
-
#define MDP4_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
607
-
#define MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT 0
608
-
static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val)
609
-
{
610
-
return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK;
611
-
}
612
-
613
-
static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; }
614
-
#define MDP4_PIPE_SRC_XY_Y__MASK 0xffff0000
615
-
#define MDP4_PIPE_SRC_XY_Y__SHIFT 16
616
-
static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val)
617
-
{
618
-
return ((val) << MDP4_PIPE_SRC_XY_Y__SHIFT) & MDP4_PIPE_SRC_XY_Y__MASK;
619
-
}
620
-
#define MDP4_PIPE_SRC_XY_X__MASK 0x0000ffff
621
-
#define MDP4_PIPE_SRC_XY_X__SHIFT 0
622
-
static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val)
623
-
{
624
-
return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK;
625
-
}
626
-
627
-
static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; }
628
-
#define MDP4_PIPE_DST_SIZE_HEIGHT__MASK 0xffff0000
629
-
#define MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT 16
630
-
static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val)
631
-
{
632
-
return ((val) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK;
633
-
}
634
-
#define MDP4_PIPE_DST_SIZE_WIDTH__MASK 0x0000ffff
635
-
#define MDP4_PIPE_DST_SIZE_WIDTH__SHIFT 0
636
-
static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val)
637
-
{
638
-
return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK;
639
-
}
640
-
641
-
static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; }
642
-
#define MDP4_PIPE_DST_XY_Y__MASK 0xffff0000
643
-
#define MDP4_PIPE_DST_XY_Y__SHIFT 16
644
-
static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val)
645
-
{
646
-
return ((val) << MDP4_PIPE_DST_XY_Y__SHIFT) & MDP4_PIPE_DST_XY_Y__MASK;
647
-
}
648
-
#define MDP4_PIPE_DST_XY_X__MASK 0x0000ffff
649
-
#define MDP4_PIPE_DST_XY_X__SHIFT 0
650
-
static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val)
651
-
{
652
-
return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK;
653
-
}
654
-
655
-
static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0; }
656
-
657
-
static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0; }
658
-
659
-
static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0; }
660
-
661
-
static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0; }
662
-
663
-
static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; }
664
-
#define MDP4_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
665
-
#define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT 0
666
-
static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val)
667
-
{
668
-
return ((val) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK;
669
-
}
670
-
#define MDP4_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
671
-
#define MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT 16
672
-
static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val)
673
-
{
674
-
return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK;
675
-
}
676
-
677
-
static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; }
678
-
#define MDP4_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
679
-
#define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT 0
680
-
static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val)
681
-
{
682
-
return ((val) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK;
683
-
}
684
-
#define MDP4_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
685
-
#define MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT 16
686
-
static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)
687
-
{
688
-
return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK;
689
-
}
690
-
691
-
static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; }
692
-
#define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK 0xffff0000
693
-
#define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT 16
694
-
static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val)
695
-
{
696
-
return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK;
697
-
}
698
-
#define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK 0x0000ffff
699
-
#define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT 0
700
-
static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val)
701
-
{
702
-
return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK;
703
-
}
704
-
705
-
static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; }
706
-
#define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
707
-
#define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
708
-
static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
709
-
{
710
-
return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK;
711
-
}
712
-
#define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
713
-
#define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
714
-
static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
715
-
{
716
-
return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK;
717
-
}
718
-
#define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
719
-
#define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
720
-
static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
721
-
{
722
-
return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK;
723
-
}
724
-
#define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
725
-
#define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
726
-
static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
727
-
{
728
-
return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK;
729
-
}
730
-
#define MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
731
-
#define MDP4_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
732
-
#define MDP4_PIPE_SRC_FORMAT_CPP__SHIFT 9
733
-
static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val)
734
-
{
735
-
return ((val) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CPP__MASK;
736
-
}
737
-
#define MDP4_PIPE_SRC_FORMAT_ROTATED_90 0x00001000
738
-
#define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00006000
739
-
#define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 13
740
-
static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
741
-
{
742
-
return ((val) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
743
-
}
744
-
#define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
745
-
#define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
746
-
#define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK 0x00180000
747
-
#define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT 19
748
-
static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val)
749
-
{
750
-
return ((val) << MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT) & MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK;
751
-
}
752
-
#define MDP4_PIPE_SRC_FORMAT_SOLID_FILL 0x00400000
753
-
#define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x0c000000
754
-
#define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 26
755
-
static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
756
-
{
757
-
return ((val) << MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
758
-
}
759
-
#define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK 0x60000000
760
-
#define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT 29
761
-
static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val)
762
-
{
763
-
return ((val) << MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT) & MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK;
764
-
}
765
-
766
-
static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0; }
767
-
#define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
768
-
#define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
769
-
static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
770
-
{
771
-
return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK;
772
-
}
773
-
#define MDP4_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
774
-
#define MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
775
-
static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
776
-
{
777
-
return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK;
778
-
}
779
-
#define MDP4_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
780
-
#define MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
781
-
static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
782
-
{
783
-
return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK;
784
-
}
785
-
#define MDP4_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
786
-
#define MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
787
-
static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
788
-
{
789
-
return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK;
790
-
}
791
-
792
-
static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; }
793
-
#define MDP4_PIPE_OP_MODE_SCALEX_EN 0x00000001
794
-
#define MDP4_PIPE_OP_MODE_SCALEY_EN 0x00000002
795
-
#define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK 0x0000000c
796
-
#define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT 2
797
-
static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val)
798
-
{
799
-
return ((val) << MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK;
800
-
}
801
-
#define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK 0x00000030
802
-
#define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT 4
803
-
static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val)
804
-
{
805
-
return ((val) << MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK;
806
-
}
807
-
#define MDP4_PIPE_OP_MODE_SRC_YCBCR 0x00000200
808
-
#define MDP4_PIPE_OP_MODE_DST_YCBCR 0x00000400
809
-
#define MDP4_PIPE_OP_MODE_CSC_EN 0x00000800
810
-
#define MDP4_PIPE_OP_MODE_FLIP_LR 0x00002000
811
-
#define MDP4_PIPE_OP_MODE_FLIP_UD 0x00004000
812
-
#define MDP4_PIPE_OP_MODE_DITHER_EN 0x00008000
813
-
#define MDP4_PIPE_OP_MODE_IGC_LUT_EN 0x00010000
814
-
#define MDP4_PIPE_OP_MODE_DEINT_EN 0x00040000
815
-
#define MDP4_PIPE_OP_MODE_DEINT_ODD_REF 0x00080000
816
-
817
-
static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; }
818
-
819
-
static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; }
820
-
821
-
static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; }
822
-
823
-
static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; }
824
-
825
-
static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; }
826
-
827
-
828
-
static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
829
-
830
-
static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
831
-
832
-
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
833
-
834
-
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
835
-
836
-
static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
837
-
838
-
static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
839
-
840
-
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
841
-
842
-
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
843
-
844
-
static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
845
-
846
-
static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
847
-
848
-
#define REG_MDP4_LCDC 0x000c0000
849
-
850
-
#define REG_MDP4_LCDC_ENABLE 0x000c0000
851
-
852
-
#define REG_MDP4_LCDC_HSYNC_CTRL 0x000c0004
853
-
#define MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
854
-
#define MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT 0
855
-
static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val)
856
-
{
857
-
return ((val) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK;
858
-
}
859
-
#define MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK 0xffff0000
860
-
#define MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT 16
861
-
static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val)
862
-
{
863
-
return ((val) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK;
864
-
}
865
-
866
-
#define REG_MDP4_LCDC_VSYNC_PERIOD 0x000c0008
867
-
868
-
#define REG_MDP4_LCDC_VSYNC_LEN 0x000c000c
869
-
870
-
#define REG_MDP4_LCDC_DISPLAY_HCTRL 0x000c0010
871
-
#define MDP4_LCDC_DISPLAY_HCTRL_START__MASK 0x0000ffff
872
-
#define MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT 0
873
-
static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val)
874
-
{
875
-
return ((val) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK;
876
-
}
877
-
#define MDP4_LCDC_DISPLAY_HCTRL_END__MASK 0xffff0000
878
-
#define MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT 16
879
-
static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val)
880
-
{
881
-
return ((val) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK;
882
-
}
883
-
884
-
#define REG_MDP4_LCDC_DISPLAY_VSTART 0x000c0014
885
-
886
-
#define REG_MDP4_LCDC_DISPLAY_VEND 0x000c0018
887
-
888
-
#define REG_MDP4_LCDC_ACTIVE_HCTL 0x000c001c
889
-
#define MDP4_LCDC_ACTIVE_HCTL_START__MASK 0x00007fff
890
-
#define MDP4_LCDC_ACTIVE_HCTL_START__SHIFT 0
891
-
static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val)
892
-
{
893
-
return ((val) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_START__MASK;
894
-
}
895
-
#define MDP4_LCDC_ACTIVE_HCTL_END__MASK 0x7fff0000
896
-
#define MDP4_LCDC_ACTIVE_HCTL_END__SHIFT 16
897
-
static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val)
898
-
{
899
-
return ((val) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_END__MASK;
900
-
}
901
-
#define MDP4_LCDC_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
902
-
903
-
#define REG_MDP4_LCDC_ACTIVE_VSTART 0x000c0020
904
-
905
-
#define REG_MDP4_LCDC_ACTIVE_VEND 0x000c0024
906
-
907
-
#define REG_MDP4_LCDC_BORDER_CLR 0x000c0028
908
-
909
-
#define REG_MDP4_LCDC_UNDERFLOW_CLR 0x000c002c
910
-
#define MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
911
-
#define MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT 0
912
-
static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val)
913
-
{
914
-
return ((val) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK;
915
-
}
916
-
#define MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
917
-
918
-
#define REG_MDP4_LCDC_HSYNC_SKEW 0x000c0030
919
-
920
-
#define REG_MDP4_LCDC_TEST_CNTL 0x000c0034
921
-
922
-
#define REG_MDP4_LCDC_CTRL_POLARITY 0x000c0038
923
-
#define MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW 0x00000001
924
-
#define MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW 0x00000002
925
-
#define MDP4_LCDC_CTRL_POLARITY_DATA_EN_LOW 0x00000004
926
-
927
-
#define REG_MDP4_LCDC_LVDS_INTF_CTL 0x000c2000
928
-
#define MDP4_LCDC_LVDS_INTF_CTL_MODE_SEL 0x00000004
929
-
#define MDP4_LCDC_LVDS_INTF_CTL_RGB_OUT 0x00000008
930
-
#define MDP4_LCDC_LVDS_INTF_CTL_CH_SWAP 0x00000010
931
-
#define MDP4_LCDC_LVDS_INTF_CTL_CH1_RES_BIT 0x00000020
932
-
#define MDP4_LCDC_LVDS_INTF_CTL_CH2_RES_BIT 0x00000040
933
-
#define MDP4_LCDC_LVDS_INTF_CTL_ENABLE 0x00000080
934
-
#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN 0x00000100
935
-
#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN 0x00000200
936
-
#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN 0x00000400
937
-
#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN 0x00000800
938
-
#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN 0x00001000
939
-
#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN 0x00002000
940
-
#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN 0x00004000
941
-
#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE3_EN 0x00008000
942
-
#define MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN 0x00010000
943
-
#define MDP4_LCDC_LVDS_INTF_CTL_CH2_CLK_LANE_EN 0x00020000
944
-
945
-
static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; }
946
-
947
-
static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0; }
948
-
#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK 0x000000ff
949
-
#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT 0
950
-
static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val)
951
-
{
952
-
return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK;
953
-
}
954
-
#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK 0x0000ff00
955
-
#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT 8
956
-
static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val)
957
-
{
958
-
return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK;
959
-
}
960
-
#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK 0x00ff0000
961
-
#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT 16
962
-
static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val)
963
-
{
964
-
return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK;
965
-
}
966
-
#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK 0xff000000
967
-
#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT 24
968
-
static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val)
969
-
{
970
-
return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK;
971
-
}
972
-
973
-
static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0; }
974
-
#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK 0x000000ff
975
-
#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT 0
976
-
static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val)
977
-
{
978
-
return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK;
979
-
}
980
-
#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK 0x0000ff00
981
-
#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT 8
982
-
static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val)
983
-
{
984
-
return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK;
985
-
}
986
-
#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK 0x00ff0000
987
-
#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT 16
988
-
static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val)
989
-
{
990
-
return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK;
991
-
}
992
-
993
-
#define REG_MDP4_LCDC_LVDS_PHY_RESET 0x000c2034
994
-
995
-
#define REG_MDP4_LVDS_PHY_PLL_CTRL_0 0x000c3000
996
-
997
-
#define REG_MDP4_LVDS_PHY_PLL_CTRL_1 0x000c3004
998
-
999
-
#define REG_MDP4_LVDS_PHY_PLL_CTRL_2 0x000c3008
1000
-
1001
-
#define REG_MDP4_LVDS_PHY_PLL_CTRL_3 0x000c300c
1002
-
1003
-
#define REG_MDP4_LVDS_PHY_PLL_CTRL_5 0x000c3014
1004
-
1005
-
#define REG_MDP4_LVDS_PHY_PLL_CTRL_6 0x000c3018
1006
-
1007
-
#define REG_MDP4_LVDS_PHY_PLL_CTRL_7 0x000c301c
1008
-
1009
-
#define REG_MDP4_LVDS_PHY_PLL_CTRL_8 0x000c3020
1010
-
1011
-
#define REG_MDP4_LVDS_PHY_PLL_CTRL_9 0x000c3024
1012
-
1013
-
#define REG_MDP4_LVDS_PHY_PLL_LOCKED 0x000c3080
1014
-
1015
-
#define REG_MDP4_LVDS_PHY_CFG2 0x000c3108
1016
-
1017
-
#define REG_MDP4_LVDS_PHY_CFG0 0x000c3100
1018
-
#define MDP4_LVDS_PHY_CFG0_SERIALIZATION_ENBLE 0x00000010
1019
-
#define MDP4_LVDS_PHY_CFG0_CHANNEL0 0x00000040
1020
-
#define MDP4_LVDS_PHY_CFG0_CHANNEL1 0x00000080
1021
-
1022
-
#define REG_MDP4_DTV 0x000d0000
1023
-
1024
-
#define REG_MDP4_DTV_ENABLE 0x000d0000
1025
-
1026
-
#define REG_MDP4_DTV_HSYNC_CTRL 0x000d0004
1027
-
#define MDP4_DTV_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
1028
-
#define MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT 0
1029
-
static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val)
1030
-
{
1031
-
return ((val) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK;
1032
-
}
1033
-
#define MDP4_DTV_HSYNC_CTRL_PERIOD__MASK 0xffff0000
1034
-
#define MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT 16
1035
-
static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val)
1036
-
{
1037
-
return ((val) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK;
1038
-
}
1039
-
1040
-
#define REG_MDP4_DTV_VSYNC_PERIOD 0x000d0008
1041
-
1042
-
#define REG_MDP4_DTV_VSYNC_LEN 0x000d000c
1043
-
1044
-
#define REG_MDP4_DTV_DISPLAY_HCTRL 0x000d0018
1045
-
#define MDP4_DTV_DISPLAY_HCTRL_START__MASK 0x0000ffff
1046
-
#define MDP4_DTV_DISPLAY_HCTRL_START__SHIFT 0
1047
-
static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val)
1048
-
{
1049
-
return ((val) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_START__MASK;
1050
-
}
1051
-
#define MDP4_DTV_DISPLAY_HCTRL_END__MASK 0xffff0000
1052
-
#define MDP4_DTV_DISPLAY_HCTRL_END__SHIFT 16
1053
-
static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val)
1054
-
{
1055
-
return ((val) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_END__MASK;
1056
-
}
1057
-
1058
-
#define REG_MDP4_DTV_DISPLAY_VSTART 0x000d001c
1059
-
1060
-
#define REG_MDP4_DTV_DISPLAY_VEND 0x000d0020
1061
-
1062
-
#define REG_MDP4_DTV_ACTIVE_HCTL 0x000d002c
1063
-
#define MDP4_DTV_ACTIVE_HCTL_START__MASK 0x00007fff
1064
-
#define MDP4_DTV_ACTIVE_HCTL_START__SHIFT 0
1065
-
static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val)
1066
-
{
1067
-
return ((val) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT) & MDP4_DTV_ACTIVE_HCTL_START__MASK;
1068
-
}
1069
-
#define MDP4_DTV_ACTIVE_HCTL_END__MASK 0x7fff0000
1070
-
#define MDP4_DTV_ACTIVE_HCTL_END__SHIFT 16
1071
-
static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val)
1072
-
{
1073
-
return ((val) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT) & MDP4_DTV_ACTIVE_HCTL_END__MASK;
1074
-
}
1075
-
#define MDP4_DTV_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
1076
-
1077
-
#define REG_MDP4_DTV_ACTIVE_VSTART 0x000d0030
1078
-
1079
-
#define REG_MDP4_DTV_ACTIVE_VEND 0x000d0038
1080
-
1081
-
#define REG_MDP4_DTV_BORDER_CLR 0x000d0040
1082
-
1083
-
#define REG_MDP4_DTV_UNDERFLOW_CLR 0x000d0044
1084
-
#define MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
1085
-
#define MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT 0
1086
-
static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val)
1087
-
{
1088
-
return ((val) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK;
1089
-
}
1090
-
#define MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
1091
-
1092
-
#define REG_MDP4_DTV_HSYNC_SKEW 0x000d0048
1093
-
1094
-
#define REG_MDP4_DTV_TEST_CNTL 0x000d004c
1095
-
1096
-
#define REG_MDP4_DTV_CTRL_POLARITY 0x000d0050
1097
-
#define MDP4_DTV_CTRL_POLARITY_HSYNC_LOW 0x00000001
1098
-
#define MDP4_DTV_CTRL_POLARITY_VSYNC_LOW 0x00000002
1099
-
#define MDP4_DTV_CTRL_POLARITY_DATA_EN_LOW 0x00000004
1100
-
1101
-
#define REG_MDP4_DSI 0x000e0000
1102
-
1103
-
#define REG_MDP4_DSI_ENABLE 0x000e0000
1104
-
1105
-
#define REG_MDP4_DSI_HSYNC_CTRL 0x000e0004
1106
-
#define MDP4_DSI_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
1107
-
#define MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT 0
1108
-
static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val)
1109
-
{
1110
-
return ((val) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK;
1111
-
}
1112
-
#define MDP4_DSI_HSYNC_CTRL_PERIOD__MASK 0xffff0000
1113
-
#define MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT 16
1114
-
static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val)
1115
-
{
1116
-
return ((val) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK;
1117
-
}
1118
-
1119
-
#define REG_MDP4_DSI_VSYNC_PERIOD 0x000e0008
1120
-
1121
-
#define REG_MDP4_DSI_VSYNC_LEN 0x000e000c
1122
-
1123
-
#define REG_MDP4_DSI_DISPLAY_HCTRL 0x000e0010
1124
-
#define MDP4_DSI_DISPLAY_HCTRL_START__MASK 0x0000ffff
1125
-
#define MDP4_DSI_DISPLAY_HCTRL_START__SHIFT 0
1126
-
static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val)
1127
-
{
1128
-
return ((val) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_START__MASK;
1129
-
}
1130
-
#define MDP4_DSI_DISPLAY_HCTRL_END__MASK 0xffff0000
1131
-
#define MDP4_DSI_DISPLAY_HCTRL_END__SHIFT 16
1132
-
static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val)
1133
-
{
1134
-
return ((val) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_END__MASK;
1135
-
}
1136
-
1137
-
#define REG_MDP4_DSI_DISPLAY_VSTART 0x000e0014
1138
-
1139
-
#define REG_MDP4_DSI_DISPLAY_VEND 0x000e0018
1140
-
1141
-
#define REG_MDP4_DSI_ACTIVE_HCTL 0x000e001c
1142
-
#define MDP4_DSI_ACTIVE_HCTL_START__MASK 0x00007fff
1143
-
#define MDP4_DSI_ACTIVE_HCTL_START__SHIFT 0
1144
-
static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val)
1145
-
{
1146
-
return ((val) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT) & MDP4_DSI_ACTIVE_HCTL_START__MASK;
1147
-
}
1148
-
#define MDP4_DSI_ACTIVE_HCTL_END__MASK 0x7fff0000
1149
-
#define MDP4_DSI_ACTIVE_HCTL_END__SHIFT 16
1150
-
static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val)
1151
-
{
1152
-
return ((val) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT) & MDP4_DSI_ACTIVE_HCTL_END__MASK;
1153
-
}
1154
-
#define MDP4_DSI_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
1155
-
1156
-
#define REG_MDP4_DSI_ACTIVE_VSTART 0x000e0020
1157
-
1158
-
#define REG_MDP4_DSI_ACTIVE_VEND 0x000e0024
1159
-
1160
-
#define REG_MDP4_DSI_BORDER_CLR 0x000e0028
1161
-
1162
-
#define REG_MDP4_DSI_UNDERFLOW_CLR 0x000e002c
1163
-
#define MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
1164
-
#define MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT 0
1165
-
static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val)
1166
-
{
1167
-
return ((val) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK;
1168
-
}
1169
-
#define MDP4_DSI_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
1170
-
1171
-
#define REG_MDP4_DSI_HSYNC_SKEW 0x000e0030
1172
-
1173
-
#define REG_MDP4_DSI_TEST_CNTL 0x000e0034
1174
-
1175
-
#define REG_MDP4_DSI_CTRL_POLARITY 0x000e0038
1176
-
#define MDP4_DSI_CTRL_POLARITY_HSYNC_LOW 0x00000001
1177
-
#define MDP4_DSI_CTRL_POLARITY_VSYNC_LOW 0x00000002
1178
-
#define MDP4_DSI_CTRL_POLARITY_DATA_EN_LOW 0x00000004
1179
-
1180
-
1181
-
#endif /* MDP4_XML */
-1979
drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h
-1979
drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h
···
1
-
#ifndef MDP5_XML
2
-
#define MDP5_XML
3
-
4
-
/* Autogenerated file, DO NOT EDIT manually!
5
-
6
-
This file was generated by the rules-ng-ng headergen tool in this git repository:
7
-
http://github.com/freedreno/envytools/
8
-
git clone https://github.com/freedreno/envytools.git
9
-
10
-
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
12
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
13
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
14
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
15
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
16
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
17
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
18
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
19
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
20
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
21
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
22
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
23
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
24
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
25
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
26
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
27
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
28
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
29
-
30
-
Copyright (C) 2013-2022 by the following authors:
31
-
- Rob Clark <robdclark@gmail.com> (robclark)
32
-
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
33
-
34
-
Permission is hereby granted, free of charge, to any person obtaining
35
-
a copy of this software and associated documentation files (the
36
-
"Software"), to deal in the Software without restriction, including
37
-
without limitation the rights to use, copy, modify, merge, publish,
38
-
distribute, sublicense, and/or sell copies of the Software, and to
39
-
permit persons to whom the Software is furnished to do so, subject to
40
-
the following conditions:
41
-
42
-
The above copyright notice and this permission notice (including the
43
-
next paragraph) shall be included in all copies or substantial
44
-
portions of the Software.
45
-
46
-
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
47
-
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
48
-
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
49
-
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
50
-
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
51
-
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
52
-
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
53
-
*/
54
-
55
-
56
-
enum mdp5_intf_type {
57
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INTF_DISABLED = 0,
58
-
INTF_DSI = 1,
59
-
INTF_HDMI = 3,
60
-
INTF_LCDC = 5,
61
-
INTF_eDP = 9,
62
-
INTF_VIRTUAL = 100,
63
-
INTF_WB = 101,
64
-
};
65
-
66
-
enum mdp5_intfnum {
67
-
NO_INTF = 0,
68
-
INTF0 = 1,
69
-
INTF1 = 2,
70
-
INTF2 = 3,
71
-
INTF3 = 4,
72
-
};
73
-
74
-
enum mdp5_pipe {
75
-
SSPP_NONE = 0,
76
-
SSPP_VIG0 = 1,
77
-
SSPP_VIG1 = 2,
78
-
SSPP_VIG2 = 3,
79
-
SSPP_RGB0 = 4,
80
-
SSPP_RGB1 = 5,
81
-
SSPP_RGB2 = 6,
82
-
SSPP_DMA0 = 7,
83
-
SSPP_DMA1 = 8,
84
-
SSPP_VIG3 = 9,
85
-
SSPP_RGB3 = 10,
86
-
SSPP_CURSOR0 = 11,
87
-
SSPP_CURSOR1 = 12,
88
-
};
89
-
90
-
enum mdp5_format {
91
-
DUMMY = 0,
92
-
};
93
-
94
-
enum mdp5_ctl_mode {
95
-
MODE_NONE = 0,
96
-
MODE_WB_0_BLOCK = 1,
97
-
MODE_WB_1_BLOCK = 2,
98
-
MODE_WB_0_LINE = 3,
99
-
MODE_WB_1_LINE = 4,
100
-
MODE_WB_2_LINE = 5,
101
-
};
102
-
103
-
enum mdp5_pack_3d {
104
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PACK_3D_FRAME_INT = 0,
105
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PACK_3D_H_ROW_INT = 1,
106
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PACK_3D_V_ROW_INT = 2,
107
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PACK_3D_COL_INT = 3,
108
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};
109
-
110
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enum mdp5_scale_filter {
111
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SCALE_FILTER_NEAREST = 0,
112
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SCALE_FILTER_BIL = 1,
113
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SCALE_FILTER_PCMN = 2,
114
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SCALE_FILTER_CA = 3,
115
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};
116
-
117
-
enum mdp5_pipe_bwc {
118
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BWC_LOSSLESS = 0,
119
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BWC_Q_HIGH = 1,
120
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BWC_Q_MED = 2,
121
-
};
122
-
123
-
enum mdp5_cursor_format {
124
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CURSOR_FMT_ARGB8888 = 0,
125
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CURSOR_FMT_ARGB1555 = 2,
126
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CURSOR_FMT_ARGB4444 = 4,
127
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};
128
-
129
-
enum mdp5_cursor_alpha {
130
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CURSOR_ALPHA_CONST = 0,
131
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CURSOR_ALPHA_PER_PIXEL = 2,
132
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};
133
-
134
-
enum mdp5_igc_type {
135
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IGC_VIG = 0,
136
-
IGC_RGB = 1,
137
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IGC_DMA = 2,
138
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IGC_DSPP = 3,
139
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};
140
-
141
-
enum mdp5_data_format {
142
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DATA_FORMAT_RGB = 0,
143
-
DATA_FORMAT_YUV = 1,
144
-
};
145
-
146
-
enum mdp5_block_size {
147
-
BLOCK_SIZE_64 = 0,
148
-
BLOCK_SIZE_128 = 1,
149
-
};
150
-
151
-
enum mdp5_rotate_mode {
152
-
ROTATE_0 = 0,
153
-
ROTATE_90 = 1,
154
-
};
155
-
156
-
enum mdp5_chroma_downsample_method {
157
-
DS_MTHD_NO_PIXEL_DROP = 0,
158
-
DS_MTHD_PIXEL_DROP = 1,
159
-
};
160
-
161
-
#define MDP5_IRQ_WB_0_DONE 0x00000001
162
-
#define MDP5_IRQ_WB_1_DONE 0x00000002
163
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#define MDP5_IRQ_WB_2_DONE 0x00000010
164
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#define MDP5_IRQ_PING_PONG_0_DONE 0x00000100
165
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#define MDP5_IRQ_PING_PONG_1_DONE 0x00000200
166
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#define MDP5_IRQ_PING_PONG_2_DONE 0x00000400
167
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#define MDP5_IRQ_PING_PONG_3_DONE 0x00000800
168
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#define MDP5_IRQ_PING_PONG_0_RD_PTR 0x00001000
169
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#define MDP5_IRQ_PING_PONG_1_RD_PTR 0x00002000
170
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#define MDP5_IRQ_PING_PONG_2_RD_PTR 0x00004000
171
-
#define MDP5_IRQ_PING_PONG_3_RD_PTR 0x00008000
172
-
#define MDP5_IRQ_PING_PONG_0_WR_PTR 0x00010000
173
-
#define MDP5_IRQ_PING_PONG_1_WR_PTR 0x00020000
174
-
#define MDP5_IRQ_PING_PONG_2_WR_PTR 0x00040000
175
-
#define MDP5_IRQ_PING_PONG_3_WR_PTR 0x00080000
176
-
#define MDP5_IRQ_PING_PONG_0_AUTO_REF 0x00100000
177
-
#define MDP5_IRQ_PING_PONG_1_AUTO_REF 0x00200000
178
-
#define MDP5_IRQ_PING_PONG_2_AUTO_REF 0x00400000
179
-
#define MDP5_IRQ_PING_PONG_3_AUTO_REF 0x00800000
180
-
#define MDP5_IRQ_INTF0_UNDER_RUN 0x01000000
181
-
#define MDP5_IRQ_INTF0_VSYNC 0x02000000
182
-
#define MDP5_IRQ_INTF1_UNDER_RUN 0x04000000
183
-
#define MDP5_IRQ_INTF1_VSYNC 0x08000000
184
-
#define MDP5_IRQ_INTF2_UNDER_RUN 0x10000000
185
-
#define MDP5_IRQ_INTF2_VSYNC 0x20000000
186
-
#define MDP5_IRQ_INTF3_UNDER_RUN 0x40000000
187
-
#define MDP5_IRQ_INTF3_VSYNC 0x80000000
188
-
#define REG_MDSS_HW_VERSION 0x00000000
189
-
#define MDSS_HW_VERSION_STEP__MASK 0x0000ffff
190
-
#define MDSS_HW_VERSION_STEP__SHIFT 0
191
-
static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val)
192
-
{
193
-
return ((val) << MDSS_HW_VERSION_STEP__SHIFT) & MDSS_HW_VERSION_STEP__MASK;
194
-
}
195
-
#define MDSS_HW_VERSION_MINOR__MASK 0x0fff0000
196
-
#define MDSS_HW_VERSION_MINOR__SHIFT 16
197
-
static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val)
198
-
{
199
-
return ((val) << MDSS_HW_VERSION_MINOR__SHIFT) & MDSS_HW_VERSION_MINOR__MASK;
200
-
}
201
-
#define MDSS_HW_VERSION_MAJOR__MASK 0xf0000000
202
-
#define MDSS_HW_VERSION_MAJOR__SHIFT 28
203
-
static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val)
204
-
{
205
-
return ((val) << MDSS_HW_VERSION_MAJOR__SHIFT) & MDSS_HW_VERSION_MAJOR__MASK;
206
-
}
207
-
208
-
#define REG_MDSS_HW_INTR_STATUS 0x00000010
209
-
#define MDSS_HW_INTR_STATUS_INTR_MDP 0x00000001
210
-
#define MDSS_HW_INTR_STATUS_INTR_DSI0 0x00000010
211
-
#define MDSS_HW_INTR_STATUS_INTR_DSI1 0x00000020
212
-
#define MDSS_HW_INTR_STATUS_INTR_HDMI 0x00000100
213
-
#define MDSS_HW_INTR_STATUS_INTR_EDP 0x00001000
214
-
215
-
#define REG_MDP5_HW_VERSION 0x00000000
216
-
#define MDP5_HW_VERSION_STEP__MASK 0x0000ffff
217
-
#define MDP5_HW_VERSION_STEP__SHIFT 0
218
-
static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val)
219
-
{
220
-
return ((val) << MDP5_HW_VERSION_STEP__SHIFT) & MDP5_HW_VERSION_STEP__MASK;
221
-
}
222
-
#define MDP5_HW_VERSION_MINOR__MASK 0x0fff0000
223
-
#define MDP5_HW_VERSION_MINOR__SHIFT 16
224
-
static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val)
225
-
{
226
-
return ((val) << MDP5_HW_VERSION_MINOR__SHIFT) & MDP5_HW_VERSION_MINOR__MASK;
227
-
}
228
-
#define MDP5_HW_VERSION_MAJOR__MASK 0xf0000000
229
-
#define MDP5_HW_VERSION_MAJOR__SHIFT 28
230
-
static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val)
231
-
{
232
-
return ((val) << MDP5_HW_VERSION_MAJOR__SHIFT) & MDP5_HW_VERSION_MAJOR__MASK;
233
-
}
234
-
235
-
#define REG_MDP5_DISP_INTF_SEL 0x00000004
236
-
#define MDP5_DISP_INTF_SEL_INTF0__MASK 0x000000ff
237
-
#define MDP5_DISP_INTF_SEL_INTF0__SHIFT 0
238
-
static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val)
239
-
{
240
-
return ((val) << MDP5_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_DISP_INTF_SEL_INTF0__MASK;
241
-
}
242
-
#define MDP5_DISP_INTF_SEL_INTF1__MASK 0x0000ff00
243
-
#define MDP5_DISP_INTF_SEL_INTF1__SHIFT 8
244
-
static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val)
245
-
{
246
-
return ((val) << MDP5_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_DISP_INTF_SEL_INTF1__MASK;
247
-
}
248
-
#define MDP5_DISP_INTF_SEL_INTF2__MASK 0x00ff0000
249
-
#define MDP5_DISP_INTF_SEL_INTF2__SHIFT 16
250
-
static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val)
251
-
{
252
-
return ((val) << MDP5_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_DISP_INTF_SEL_INTF2__MASK;
253
-
}
254
-
#define MDP5_DISP_INTF_SEL_INTF3__MASK 0xff000000
255
-
#define MDP5_DISP_INTF_SEL_INTF3__SHIFT 24
256
-
static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val)
257
-
{
258
-
return ((val) << MDP5_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_DISP_INTF_SEL_INTF3__MASK;
259
-
}
260
-
261
-
#define REG_MDP5_INTR_EN 0x00000010
262
-
263
-
#define REG_MDP5_INTR_STATUS 0x00000014
264
-
265
-
#define REG_MDP5_INTR_CLEAR 0x00000018
266
-
267
-
#define REG_MDP5_HIST_INTR_EN 0x0000001c
268
-
269
-
#define REG_MDP5_HIST_INTR_STATUS 0x00000020
270
-
271
-
#define REG_MDP5_HIST_INTR_CLEAR 0x00000024
272
-
273
-
#define REG_MDP5_SPARE_0 0x00000028
274
-
#define MDP5_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN 0x00000001
275
-
276
-
static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; }
277
-
278
-
static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; }
279
-
#define MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK 0x000000ff
280
-
#define MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT 0
281
-
static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)
282
-
{
283
-
return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK;
284
-
}
285
-
#define MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK 0x0000ff00
286
-
#define MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT 8
287
-
static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)
288
-
{
289
-
return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK;
290
-
}
291
-
#define MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff0000
292
-
#define MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT 16
293
-
static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)
294
-
{
295
-
return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK;
296
-
}
297
-
298
-
static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; }
299
-
300
-
static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; }
301
-
#define MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK 0x000000ff
302
-
#define MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT 0
303
-
static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)
304
-
{
305
-
return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK;
306
-
}
307
-
#define MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK 0x0000ff00
308
-
#define MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT 8
309
-
static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)
310
-
{
311
-
return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK;
312
-
}
313
-
#define MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff0000
314
-
#define MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT 16
315
-
static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)
316
-
{
317
-
return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK;
318
-
}
319
-
320
-
static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)
321
-
{
322
-
switch (idx) {
323
-
case IGC_VIG: return 0x00000200;
324
-
case IGC_RGB: return 0x00000210;
325
-
case IGC_DMA: return 0x00000220;
326
-
case IGC_DSPP: return 0x00000300;
327
-
default: return INVALID_IDX(idx);
328
-
}
329
-
}
330
-
static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); }
331
-
332
-
static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
333
-
334
-
static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
335
-
#define MDP5_IGC_LUT_REG_VAL__MASK 0x00000fff
336
-
#define MDP5_IGC_LUT_REG_VAL__SHIFT 0
337
-
static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val)
338
-
{
339
-
return ((val) << MDP5_IGC_LUT_REG_VAL__SHIFT) & MDP5_IGC_LUT_REG_VAL__MASK;
340
-
}
341
-
#define MDP5_IGC_LUT_REG_INDEX_UPDATE 0x02000000
342
-
#define MDP5_IGC_LUT_REG_DISABLE_PIPE_0 0x10000000
343
-
#define MDP5_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000
344
-
#define MDP5_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000
345
-
346
-
#define REG_MDP5_SPLIT_DPL_EN 0x000002f4
347
-
348
-
#define REG_MDP5_SPLIT_DPL_UPPER 0x000002f8
349
-
#define MDP5_SPLIT_DPL_UPPER_SMART_PANEL 0x00000002
350
-
#define MDP5_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN 0x00000004
351
-
#define MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX 0x00000010
352
-
#define MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX 0x00000100
353
-
354
-
#define REG_MDP5_SPLIT_DPL_LOWER 0x000003f0
355
-
#define MDP5_SPLIT_DPL_LOWER_SMART_PANEL 0x00000002
356
-
#define MDP5_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN 0x00000004
357
-
#define MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC 0x00000010
358
-
#define MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC 0x00000100
359
-
360
-
static inline uint32_t __offset_CTL(uint32_t idx)
361
-
{
362
-
switch (idx) {
363
-
case 0: return (mdp5_cfg->ctl.base[0]);
364
-
case 1: return (mdp5_cfg->ctl.base[1]);
365
-
case 2: return (mdp5_cfg->ctl.base[2]);
366
-
case 3: return (mdp5_cfg->ctl.base[3]);
367
-
case 4: return (mdp5_cfg->ctl.base[4]);
368
-
default: return INVALID_IDX(idx);
369
-
}
370
-
}
371
-
static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }
372
-
373
-
static inline uint32_t __offset_LAYER(uint32_t idx)
374
-
{
375
-
switch (idx) {
376
-
case 0: return 0x00000000;
377
-
case 1: return 0x00000004;
378
-
case 2: return 0x00000008;
379
-
case 3: return 0x0000000c;
380
-
case 4: return 0x00000010;
381
-
case 5: return 0x00000024;
382
-
default: return INVALID_IDX(idx);
383
-
}
384
-
}
385
-
static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
386
-
387
-
static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
388
-
#define MDP5_CTL_LAYER_REG_VIG0__MASK 0x00000007
389
-
#define MDP5_CTL_LAYER_REG_VIG0__SHIFT 0
390
-
static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(uint32_t val)
391
-
{
392
-
return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK;
393
-
}
394
-
#define MDP5_CTL_LAYER_REG_VIG1__MASK 0x00000038
395
-
#define MDP5_CTL_LAYER_REG_VIG1__SHIFT 3
396
-
static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(uint32_t val)
397
-
{
398
-
return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK;
399
-
}
400
-
#define MDP5_CTL_LAYER_REG_VIG2__MASK 0x000001c0
401
-
#define MDP5_CTL_LAYER_REG_VIG2__SHIFT 6
402
-
static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(uint32_t val)
403
-
{
404
-
return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK;
405
-
}
406
-
#define MDP5_CTL_LAYER_REG_RGB0__MASK 0x00000e00
407
-
#define MDP5_CTL_LAYER_REG_RGB0__SHIFT 9
408
-
static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(uint32_t val)
409
-
{
410
-
return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK;
411
-
}
412
-
#define MDP5_CTL_LAYER_REG_RGB1__MASK 0x00007000
413
-
#define MDP5_CTL_LAYER_REG_RGB1__SHIFT 12
414
-
static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(uint32_t val)
415
-
{
416
-
return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK;
417
-
}
418
-
#define MDP5_CTL_LAYER_REG_RGB2__MASK 0x00038000
419
-
#define MDP5_CTL_LAYER_REG_RGB2__SHIFT 15
420
-
static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(uint32_t val)
421
-
{
422
-
return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK;
423
-
}
424
-
#define MDP5_CTL_LAYER_REG_DMA0__MASK 0x001c0000
425
-
#define MDP5_CTL_LAYER_REG_DMA0__SHIFT 18
426
-
static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(uint32_t val)
427
-
{
428
-
return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK;
429
-
}
430
-
#define MDP5_CTL_LAYER_REG_DMA1__MASK 0x00e00000
431
-
#define MDP5_CTL_LAYER_REG_DMA1__SHIFT 21
432
-
static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(uint32_t val)
433
-
{
434
-
return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK;
435
-
}
436
-
#define MDP5_CTL_LAYER_REG_BORDER_COLOR 0x01000000
437
-
#define MDP5_CTL_LAYER_REG_CURSOR_OUT 0x02000000
438
-
#define MDP5_CTL_LAYER_REG_VIG3__MASK 0x1c000000
439
-
#define MDP5_CTL_LAYER_REG_VIG3__SHIFT 26
440
-
static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(uint32_t val)
441
-
{
442
-
return ((val) << MDP5_CTL_LAYER_REG_VIG3__SHIFT) & MDP5_CTL_LAYER_REG_VIG3__MASK;
443
-
}
444
-
#define MDP5_CTL_LAYER_REG_RGB3__MASK 0xe0000000
445
-
#define MDP5_CTL_LAYER_REG_RGB3__SHIFT 29
446
-
static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(uint32_t val)
447
-
{
448
-
return ((val) << MDP5_CTL_LAYER_REG_RGB3__SHIFT) & MDP5_CTL_LAYER_REG_RGB3__MASK;
449
-
}
450
-
451
-
static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }
452
-
#define MDP5_CTL_OP_MODE__MASK 0x0000000f
453
-
#define MDP5_CTL_OP_MODE__SHIFT 0
454
-
static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)
455
-
{
456
-
return ((val) << MDP5_CTL_OP_MODE__SHIFT) & MDP5_CTL_OP_MODE__MASK;
457
-
}
458
-
#define MDP5_CTL_OP_INTF_NUM__MASK 0x00000070
459
-
#define MDP5_CTL_OP_INTF_NUM__SHIFT 4
460
-
static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)
461
-
{
462
-
return ((val) << MDP5_CTL_OP_INTF_NUM__SHIFT) & MDP5_CTL_OP_INTF_NUM__MASK;
463
-
}
464
-
#define MDP5_CTL_OP_CMD_MODE 0x00020000
465
-
#define MDP5_CTL_OP_PACK_3D_ENABLE 0x00080000
466
-
#define MDP5_CTL_OP_PACK_3D__MASK 0x00300000
467
-
#define MDP5_CTL_OP_PACK_3D__SHIFT 20
468
-
static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)
469
-
{
470
-
return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK;
471
-
}
472
-
473
-
static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }
474
-
#define MDP5_CTL_FLUSH_VIG0 0x00000001
475
-
#define MDP5_CTL_FLUSH_VIG1 0x00000002
476
-
#define MDP5_CTL_FLUSH_VIG2 0x00000004
477
-
#define MDP5_CTL_FLUSH_RGB0 0x00000008
478
-
#define MDP5_CTL_FLUSH_RGB1 0x00000010
479
-
#define MDP5_CTL_FLUSH_RGB2 0x00000020
480
-
#define MDP5_CTL_FLUSH_LM0 0x00000040
481
-
#define MDP5_CTL_FLUSH_LM1 0x00000080
482
-
#define MDP5_CTL_FLUSH_LM2 0x00000100
483
-
#define MDP5_CTL_FLUSH_LM3 0x00000200
484
-
#define MDP5_CTL_FLUSH_LM4 0x00000400
485
-
#define MDP5_CTL_FLUSH_DMA0 0x00000800
486
-
#define MDP5_CTL_FLUSH_DMA1 0x00001000
487
-
#define MDP5_CTL_FLUSH_DSPP0 0x00002000
488
-
#define MDP5_CTL_FLUSH_DSPP1 0x00004000
489
-
#define MDP5_CTL_FLUSH_DSPP2 0x00008000
490
-
#define MDP5_CTL_FLUSH_WB 0x00010000
491
-
#define MDP5_CTL_FLUSH_CTL 0x00020000
492
-
#define MDP5_CTL_FLUSH_VIG3 0x00040000
493
-
#define MDP5_CTL_FLUSH_RGB3 0x00080000
494
-
#define MDP5_CTL_FLUSH_LM5 0x00100000
495
-
#define MDP5_CTL_FLUSH_DSPP3 0x00200000
496
-
#define MDP5_CTL_FLUSH_CURSOR_0 0x00400000
497
-
#define MDP5_CTL_FLUSH_CURSOR_1 0x00800000
498
-
#define MDP5_CTL_FLUSH_CHROMADOWN_0 0x04000000
499
-
#define MDP5_CTL_FLUSH_TIMING_3 0x10000000
500
-
#define MDP5_CTL_FLUSH_TIMING_2 0x20000000
501
-
#define MDP5_CTL_FLUSH_TIMING_1 0x40000000
502
-
#define MDP5_CTL_FLUSH_TIMING_0 0x80000000
503
-
504
-
static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }
505
-
506
-
static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }
507
-
508
-
static inline uint32_t __offset_LAYER_EXT(uint32_t idx)
509
-
{
510
-
switch (idx) {
511
-
case 0: return 0x00000040;
512
-
case 1: return 0x00000044;
513
-
case 2: return 0x00000048;
514
-
case 3: return 0x0000004c;
515
-
case 4: return 0x00000050;
516
-
case 5: return 0x00000054;
517
-
default: return INVALID_IDX(idx);
518
-
}
519
-
}
520
-
static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
521
-
522
-
static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
523
-
#define MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3 0x00000001
524
-
#define MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3 0x00000004
525
-
#define MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3 0x00000010
526
-
#define MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3 0x00000040
527
-
#define MDP5_CTL_LAYER_EXT_REG_RGB0_BIT3 0x00000100
528
-
#define MDP5_CTL_LAYER_EXT_REG_RGB1_BIT3 0x00000400
529
-
#define MDP5_CTL_LAYER_EXT_REG_RGB2_BIT3 0x00001000
530
-
#define MDP5_CTL_LAYER_EXT_REG_RGB3_BIT3 0x00004000
531
-
#define MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3 0x00010000
532
-
#define MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3 0x00040000
533
-
#define MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK 0x00f00000
534
-
#define MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT 20
535
-
static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val)
536
-
{
537
-
return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK;
538
-
}
539
-
#define MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK 0x3c000000
540
-
#define MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT 26
541
-
static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val)
542
-
{
543
-
return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK;
544
-
}
545
-
546
-
static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)
547
-
{
548
-
switch (idx) {
549
-
case SSPP_NONE: return (INVALID_IDX(idx));
550
-
case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]);
551
-
case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]);
552
-
case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]);
553
-
case SSPP_RGB0: return (mdp5_cfg->pipe_rgb.base[0]);
554
-
case SSPP_RGB1: return (mdp5_cfg->pipe_rgb.base[1]);
555
-
case SSPP_RGB2: return (mdp5_cfg->pipe_rgb.base[2]);
556
-
case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]);
557
-
case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]);
558
-
case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]);
559
-
case SSPP_RGB3: return (mdp5_cfg->pipe_rgb.base[3]);
560
-
case SSPP_CURSOR0: return (mdp5_cfg->pipe_cursor.base[0]);
561
-
case SSPP_CURSOR1: return (mdp5_cfg->pipe_cursor.base[1]);
562
-
default: return INVALID_IDX(idx);
563
-
}
564
-
}
565
-
static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
566
-
567
-
static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0); }
568
-
#define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00080000
569
-
#define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 19
570
-
static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)
571
-
{
572
-
return ((val) << MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
573
-
}
574
-
#define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00040000
575
-
#define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 18
576
-
static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)
577
-
{
578
-
return ((val) << MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
579
-
}
580
-
#define MDP5_PIPE_OP_MODE_CSC_1_EN 0x00020000
581
-
582
-
static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); }
583
-
584
-
static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); }
585
-
586
-
static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); }
587
-
588
-
static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); }
589
-
#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff
590
-
#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT 0
591
-
static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val)
592
-
{
593
-
return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK;
594
-
}
595
-
#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000
596
-
#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT 16
597
-
static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val)
598
-
{
599
-
return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK;
600
-
}
601
-
602
-
static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); }
603
-
#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff
604
-
#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT 0
605
-
static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val)
606
-
{
607
-
return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK;
608
-
}
609
-
#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000
610
-
#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT 16
611
-
static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val)
612
-
{
613
-
return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK;
614
-
}
615
-
616
-
static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); }
617
-
#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff
618
-
#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT 0
619
-
static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val)
620
-
{
621
-
return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK;
622
-
}
623
-
#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000
624
-
#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT 16
625
-
static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val)
626
-
{
627
-
return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK;
628
-
}
629
-
630
-
static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); }
631
-
#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff
632
-
#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT 0
633
-
static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val)
634
-
{
635
-
return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK;
636
-
}
637
-
#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000
638
-
#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT 16
639
-
static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val)
640
-
{
641
-
return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK;
642
-
}
643
-
644
-
static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0); }
645
-
#define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff
646
-
#define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT 0
647
-
static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val)
648
-
{
649
-
return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK;
650
-
}
651
-
652
-
static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
653
-
654
-
static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
655
-
#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK 0x000000ff
656
-
#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT 0
657
-
static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val)
658
-
{
659
-
return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK;
660
-
}
661
-
#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK 0x0000ff00
662
-
#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT 8
663
-
static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val)
664
-
{
665
-
return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK;
666
-
}
667
-
668
-
static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
669
-
670
-
static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
671
-
#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK 0x000000ff
672
-
#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT 0
673
-
static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val)
674
-
{
675
-
return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK;
676
-
}
677
-
#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK 0x0000ff00
678
-
#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT 8
679
-
static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val)
680
-
{
681
-
return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK;
682
-
}
683
-
684
-
static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
685
-
686
-
static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
687
-
#define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK 0x000001ff
688
-
#define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT 0
689
-
static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val)
690
-
{
691
-
return ((val) << MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK;
692
-
}
693
-
694
-
static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
695
-
696
-
static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
697
-
#define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK 0x000001ff
698
-
#define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT 0
699
-
static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val)
700
-
{
701
-
return ((val) << MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK;
702
-
}
703
-
704
-
static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
705
-
#define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
706
-
#define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
707
-
static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
708
-
{
709
-
return ((val) << MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_SIZE_HEIGHT__MASK;
710
-
}
711
-
#define MDP5_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
712
-
#define MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT 0
713
-
static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)
714
-
{
715
-
return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK;
716
-
}
717
-
718
-
static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); }
719
-
#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK 0xffff0000
720
-
#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT 16
721
-
static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)
722
-
{
723
-
return ((val) << MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK;
724
-
}
725
-
#define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK 0x0000ffff
726
-
#define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT 0
727
-
static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)
728
-
{
729
-
return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK;
730
-
}
731
-
732
-
static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); }
733
-
#define MDP5_PIPE_SRC_XY_Y__MASK 0xffff0000
734
-
#define MDP5_PIPE_SRC_XY_Y__SHIFT 16
735
-
static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)
736
-
{
737
-
return ((val) << MDP5_PIPE_SRC_XY_Y__SHIFT) & MDP5_PIPE_SRC_XY_Y__MASK;
738
-
}
739
-
#define MDP5_PIPE_SRC_XY_X__MASK 0x0000ffff
740
-
#define MDP5_PIPE_SRC_XY_X__SHIFT 0
741
-
static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)
742
-
{
743
-
return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK;
744
-
}
745
-
746
-
static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); }
747
-
#define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK 0xffff0000
748
-
#define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT 16
749
-
static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)
750
-
{
751
-
return ((val) << MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_OUT_SIZE_HEIGHT__MASK;
752
-
}
753
-
#define MDP5_PIPE_OUT_SIZE_WIDTH__MASK 0x0000ffff
754
-
#define MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT 0
755
-
static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)
756
-
{
757
-
return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK;
758
-
}
759
-
760
-
static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); }
761
-
#define MDP5_PIPE_OUT_XY_Y__MASK 0xffff0000
762
-
#define MDP5_PIPE_OUT_XY_Y__SHIFT 16
763
-
static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)
764
-
{
765
-
return ((val) << MDP5_PIPE_OUT_XY_Y__SHIFT) & MDP5_PIPE_OUT_XY_Y__MASK;
766
-
}
767
-
#define MDP5_PIPE_OUT_XY_X__MASK 0x0000ffff
768
-
#define MDP5_PIPE_OUT_XY_X__SHIFT 0
769
-
static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)
770
-
{
771
-
return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK;
772
-
}
773
-
774
-
static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); }
775
-
776
-
static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); }
777
-
778
-
static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); }
779
-
780
-
static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); }
781
-
782
-
static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); }
783
-
#define MDP5_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
784
-
#define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT 0
785
-
static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)
786
-
{
787
-
return ((val) << MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P0__MASK;
788
-
}
789
-
#define MDP5_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
790
-
#define MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT 16
791
-
static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)
792
-
{
793
-
return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK;
794
-
}
795
-
796
-
static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); }
797
-
#define MDP5_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
798
-
#define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT 0
799
-
static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)
800
-
{
801
-
return ((val) << MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P2__MASK;
802
-
}
803
-
#define MDP5_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
804
-
#define MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT 16
805
-
static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)
806
-
{
807
-
return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK;
808
-
}
809
-
810
-
static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); }
811
-
812
-
static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); }
813
-
#define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
814
-
#define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
815
-
static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
816
-
{
817
-
return ((val) << MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_G_BPC__MASK;
818
-
}
819
-
#define MDP5_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
820
-
#define MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
821
-
static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
822
-
{
823
-
return ((val) << MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_B_BPC__MASK;
824
-
}
825
-
#define MDP5_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
826
-
#define MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
827
-
static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
828
-
{
829
-
return ((val) << MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_R_BPC__MASK;
830
-
}
831
-
#define MDP5_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
832
-
#define MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
833
-
static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
834
-
{
835
-
return ((val) << MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_A_BPC__MASK;
836
-
}
837
-
#define MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
838
-
#define MDP5_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
839
-
#define MDP5_PIPE_SRC_FORMAT_CPP__SHIFT 9
840
-
static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)
841
-
{
842
-
return ((val) << MDP5_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CPP__MASK;
843
-
}
844
-
#define MDP5_PIPE_SRC_FORMAT_ROT90 0x00000800
845
-
#define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00003000
846
-
#define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 12
847
-
static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
848
-
{
849
-
return ((val) << MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
850
-
}
851
-
#define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
852
-
#define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
853
-
#define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK 0x00180000
854
-
#define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT 19
855
-
static inline uint32_t MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val)
856
-
{
857
-
return ((val) << MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT) & MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK;
858
-
}
859
-
#define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x01800000
860
-
#define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 23
861
-
static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
862
-
{
863
-
return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
864
-
}
865
-
866
-
static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); }
867
-
#define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
868
-
#define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
869
-
static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
870
-
{
871
-
return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM0__MASK;
872
-
}
873
-
#define MDP5_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
874
-
#define MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
875
-
static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
876
-
{
877
-
return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM1__MASK;
878
-
}
879
-
#define MDP5_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
880
-
#define MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
881
-
static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
882
-
{
883
-
return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM2__MASK;
884
-
}
885
-
#define MDP5_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
886
-
#define MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
887
-
static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
888
-
{
889
-
return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK;
890
-
}
891
-
892
-
static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); }
893
-
#define MDP5_PIPE_SRC_OP_MODE_BWC_EN 0x00000001
894
-
#define MDP5_PIPE_SRC_OP_MODE_BWC__MASK 0x00000006
895
-
#define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT 1
896
-
static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)
897
-
{
898
-
return ((val) << MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT) & MDP5_PIPE_SRC_OP_MODE_BWC__MASK;
899
-
}
900
-
#define MDP5_PIPE_SRC_OP_MODE_FLIP_LR 0x00002000
901
-
#define MDP5_PIPE_SRC_OP_MODE_FLIP_UD 0x00004000
902
-
#define MDP5_PIPE_SRC_OP_MODE_IGC_EN 0x00010000
903
-
#define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_0 0x00020000
904
-
#define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1 0x00040000
905
-
#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE 0x00400000
906
-
#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD 0x00800000
907
-
#define MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE 0x80000000
908
-
909
-
static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); }
910
-
911
-
static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); }
912
-
913
-
static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); }
914
-
915
-
static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); }
916
-
917
-
static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); }
918
-
919
-
static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); }
920
-
921
-
static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); }
922
-
923
-
static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); }
924
-
925
-
static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); }
926
-
927
-
static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); }
928
-
929
-
static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); }
930
-
931
-
static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); }
932
-
#define MDP5_PIPE_DECIMATION_VERT__MASK 0x000000ff
933
-
#define MDP5_PIPE_DECIMATION_VERT__SHIFT 0
934
-
static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)
935
-
{
936
-
return ((val) << MDP5_PIPE_DECIMATION_VERT__SHIFT) & MDP5_PIPE_DECIMATION_VERT__MASK;
937
-
}
938
-
#define MDP5_PIPE_DECIMATION_HORZ__MASK 0x0000ff00
939
-
#define MDP5_PIPE_DECIMATION_HORZ__SHIFT 8
940
-
static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)
941
-
{
942
-
return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK;
943
-
}
944
-
945
-
static inline uint32_t __offset_SW_PIX_EXT(enum mdp_component_type idx)
946
-
{
947
-
switch (idx) {
948
-
case COMP_0: return 0x00000100;
949
-
case COMP_1_2: return 0x00000110;
950
-
case COMP_3: return 0x00000120;
951
-
default: return INVALID_IDX(idx);
952
-
}
953
-
}
954
-
static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
955
-
956
-
static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
957
-
#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK 0x000000ff
958
-
#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT 0
959
-
static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val)
960
-
{
961
-
return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK;
962
-
}
963
-
#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK 0x0000ff00
964
-
#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT 8
965
-
static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val)
966
-
{
967
-
return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK;
968
-
}
969
-
#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK 0x00ff0000
970
-
#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT 16
971
-
static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val)
972
-
{
973
-
return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK;
974
-
}
975
-
#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK 0xff000000
976
-
#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT 24
977
-
static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val)
978
-
{
979
-
return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK;
980
-
}
981
-
982
-
static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
983
-
#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK 0x000000ff
984
-
#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT 0
985
-
static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val)
986
-
{
987
-
return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK;
988
-
}
989
-
#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK 0x0000ff00
990
-
#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT 8
991
-
static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val)
992
-
{
993
-
return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK;
994
-
}
995
-
#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK 0x00ff0000
996
-
#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT 16
997
-
static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val)
998
-
{
999
-
return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK;
1000
-
}
1001
-
#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK 0xff000000
1002
-
#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT 24
1003
-
static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val)
1004
-
{
1005
-
return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK;
1006
-
}
1007
-
1008
-
static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
1009
-
#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK 0x0000ffff
1010
-
#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT 0
1011
-
static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val)
1012
-
{
1013
-
return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK;
1014
-
}
1015
-
#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK 0xffff0000
1016
-
#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT 16
1017
-
static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val)
1018
-
{
1019
-
return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK;
1020
-
}
1021
-
1022
-
static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); }
1023
-
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001
1024
-
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002
1025
-
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK 0x00000300
1026
-
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT 8
1027
-
static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val)
1028
-
{
1029
-
return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK;
1030
-
}
1031
-
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK 0x00000c00
1032
-
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT 10
1033
-
static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val)
1034
-
{
1035
-
return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK;
1036
-
}
1037
-
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK 0x00003000
1038
-
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT 12
1039
-
static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val)
1040
-
{
1041
-
return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK;
1042
-
}
1043
-
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK 0x0000c000
1044
-
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT 14
1045
-
static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val)
1046
-
{
1047
-
return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK;
1048
-
}
1049
-
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK 0x00030000
1050
-
#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT 16
1051
-
static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val)
1052
-
{
1053
-
return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK;
1054
-
}
1055
-
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK 0x000c0000
1056
-
#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT 18
1057
-
static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val)
1058
-
{
1059
-
return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK;
1060
-
}
1061
-
1062
-
static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); }
1063
-
1064
-
static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); }
1065
-
1066
-
static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0); }
1067
-
1068
-
static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0); }
1069
-
1070
-
static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); }
1071
-
1072
-
static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); }
1073
-
1074
-
static inline uint32_t __offset_LM(uint32_t idx)
1075
-
{
1076
-
switch (idx) {
1077
-
case 0: return (mdp5_cfg->lm.base[0]);
1078
-
case 1: return (mdp5_cfg->lm.base[1]);
1079
-
case 2: return (mdp5_cfg->lm.base[2]);
1080
-
case 3: return (mdp5_cfg->lm.base[3]);
1081
-
case 4: return (mdp5_cfg->lm.base[4]);
1082
-
case 5: return (mdp5_cfg->lm.base[5]);
1083
-
default: return INVALID_IDX(idx);
1084
-
}
1085
-
}
1086
-
static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
1087
-
1088
-
static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
1089
-
#define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA 0x00000002
1090
-
#define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA 0x00000004
1091
-
#define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA 0x00000008
1092
-
#define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA 0x00000010
1093
-
#define MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA 0x00000020
1094
-
#define MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA 0x00000040
1095
-
#define MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA 0x00000080
1096
-
#define MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT 0x80000000
1097
-
1098
-
static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }
1099
-
#define MDP5_LM_OUT_SIZE_HEIGHT__MASK 0xffff0000
1100
-
#define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT 16
1101
-
static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)
1102
-
{
1103
-
return ((val) << MDP5_LM_OUT_SIZE_HEIGHT__SHIFT) & MDP5_LM_OUT_SIZE_HEIGHT__MASK;
1104
-
}
1105
-
#define MDP5_LM_OUT_SIZE_WIDTH__MASK 0x0000ffff
1106
-
#define MDP5_LM_OUT_SIZE_WIDTH__SHIFT 0
1107
-
static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)
1108
-
{
1109
-
return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK;
1110
-
}
1111
-
1112
-
static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0); }
1113
-
1114
-
static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); }
1115
-
1116
-
static inline uint32_t __offset_BLEND(uint32_t idx)
1117
-
{
1118
-
switch (idx) {
1119
-
case 0: return 0x00000020;
1120
-
case 1: return 0x00000050;
1121
-
case 2: return 0x00000080;
1122
-
case 3: return 0x000000b0;
1123
-
case 4: return 0x00000230;
1124
-
case 5: return 0x00000260;
1125
-
case 6: return 0x00000290;
1126
-
default: return INVALID_IDX(idx);
1127
-
}
1128
-
}
1129
-
static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
1130
-
1131
-
static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
1132
-
#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK 0x00000003
1133
-
#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT 0
1134
-
static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)
1135
-
{
1136
-
return ((val) << MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK;
1137
-
}
1138
-
#define MDP5_LM_BLEND_OP_MODE_FG_INV_ALPHA 0x00000004
1139
-
#define MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA 0x00000008
1140
-
#define MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA 0x00000010
1141
-
#define MDP5_LM_BLEND_OP_MODE_FG_TRANSP_EN 0x00000020
1142
-
#define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK 0x00000300
1143
-
#define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT 8
1144
-
static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)
1145
-
{
1146
-
return ((val) << MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK;
1147
-
}
1148
-
#define MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA 0x00000400
1149
-
#define MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA 0x00000800
1150
-
#define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA 0x00001000
1151
-
#define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN 0x00002000
1152
-
1153
-
static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_LM(i0) + __offset_BLEND(i1); }
1154
-
1155
-
static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_LM(i0) + __offset_BLEND(i1); }
1156
-
1157
-
static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_LM(i0) + __offset_BLEND(i1); }
1158
-
1159
-
static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_LM(i0) + __offset_BLEND(i1); }
1160
-
1161
-
static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_LM(i0) + __offset_BLEND(i1); }
1162
-
1163
-
static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_LM(i0) + __offset_BLEND(i1); }
1164
-
1165
-
static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_LM(i0) + __offset_BLEND(i1); }
1166
-
1167
-
static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + __offset_BLEND(i1); }
1168
-
1169
-
static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + __offset_BLEND(i1); }
1170
-
1171
-
static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + __offset_BLEND(i1); }
1172
-
1173
-
static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); }
1174
-
#define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK 0x0000ffff
1175
-
#define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT 0
1176
-
static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)
1177
-
{
1178
-
return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK;
1179
-
}
1180
-
#define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK 0xffff0000
1181
-
#define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT 16
1182
-
static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)
1183
-
{
1184
-
return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK;
1185
-
}
1186
-
1187
-
static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }
1188
-
#define MDP5_LM_CURSOR_SIZE_ROI_W__MASK 0x0000ffff
1189
-
#define MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT 0
1190
-
static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)
1191
-
{
1192
-
return ((val) << MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_W__MASK;
1193
-
}
1194
-
#define MDP5_LM_CURSOR_SIZE_ROI_H__MASK 0xffff0000
1195
-
#define MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT 16
1196
-
static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)
1197
-
{
1198
-
return ((val) << MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_H__MASK;
1199
-
}
1200
-
1201
-
static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }
1202
-
#define MDP5_LM_CURSOR_XY_SRC_X__MASK 0x0000ffff
1203
-
#define MDP5_LM_CURSOR_XY_SRC_X__SHIFT 0
1204
-
static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)
1205
-
{
1206
-
return ((val) << MDP5_LM_CURSOR_XY_SRC_X__SHIFT) & MDP5_LM_CURSOR_XY_SRC_X__MASK;
1207
-
}
1208
-
#define MDP5_LM_CURSOR_XY_SRC_Y__MASK 0xffff0000
1209
-
#define MDP5_LM_CURSOR_XY_SRC_Y__SHIFT 16
1210
-
static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)
1211
-
{
1212
-
return ((val) << MDP5_LM_CURSOR_XY_SRC_Y__SHIFT) & MDP5_LM_CURSOR_XY_SRC_Y__MASK;
1213
-
}
1214
-
1215
-
static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); }
1216
-
#define MDP5_LM_CURSOR_STRIDE_STRIDE__MASK 0x0000ffff
1217
-
#define MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT 0
1218
-
static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)
1219
-
{
1220
-
return ((val) << MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT) & MDP5_LM_CURSOR_STRIDE_STRIDE__MASK;
1221
-
}
1222
-
1223
-
static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); }
1224
-
#define MDP5_LM_CURSOR_FORMAT_FORMAT__MASK 0x00000007
1225
-
#define MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT 0
1226
-
static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)
1227
-
{
1228
-
return ((val) << MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT) & MDP5_LM_CURSOR_FORMAT_FORMAT__MASK;
1229
-
}
1230
-
1231
-
static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); }
1232
-
1233
-
static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); }
1234
-
#define MDP5_LM_CURSOR_START_XY_X_START__MASK 0x0000ffff
1235
-
#define MDP5_LM_CURSOR_START_XY_X_START__SHIFT 0
1236
-
static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)
1237
-
{
1238
-
return ((val) << MDP5_LM_CURSOR_START_XY_X_START__SHIFT) & MDP5_LM_CURSOR_START_XY_X_START__MASK;
1239
-
}
1240
-
#define MDP5_LM_CURSOR_START_XY_Y_START__MASK 0xffff0000
1241
-
#define MDP5_LM_CURSOR_START_XY_Y_START__SHIFT 16
1242
-
static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)
1243
-
{
1244
-
return ((val) << MDP5_LM_CURSOR_START_XY_Y_START__SHIFT) & MDP5_LM_CURSOR_START_XY_Y_START__MASK;
1245
-
}
1246
-
1247
-
static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); }
1248
-
#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN 0x00000001
1249
-
#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK 0x00000006
1250
-
#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT 1
1251
-
static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)
1252
-
{
1253
-
return ((val) << MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT) & MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK;
1254
-
}
1255
-
#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_TRANSP_EN 0x00000008
1256
-
1257
-
static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); }
1258
-
1259
-
static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0); }
1260
-
1261
-
static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0); }
1262
-
1263
-
static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0); }
1264
-
1265
-
static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0); }
1266
-
1267
-
static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }
1268
-
1269
-
static inline uint32_t __offset_DSPP(uint32_t idx)
1270
-
{
1271
-
switch (idx) {
1272
-
case 0: return (mdp5_cfg->dspp.base[0]);
1273
-
case 1: return (mdp5_cfg->dspp.base[1]);
1274
-
case 2: return (mdp5_cfg->dspp.base[2]);
1275
-
case 3: return (mdp5_cfg->dspp.base[3]);
1276
-
default: return INVALID_IDX(idx);
1277
-
}
1278
-
}
1279
-
static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
1280
-
1281
-
static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
1282
-
#define MDP5_DSPP_OP_MODE_IGC_LUT_EN 0x00000001
1283
-
#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK 0x0000000e
1284
-
#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT 1
1285
-
static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)
1286
-
{
1287
-
return ((val) << MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT) & MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK;
1288
-
}
1289
-
#define MDP5_DSPP_OP_MODE_PCC_EN 0x00000010
1290
-
#define MDP5_DSPP_OP_MODE_DITHER_EN 0x00000100
1291
-
#define MDP5_DSPP_OP_MODE_HIST_EN 0x00010000
1292
-
#define MDP5_DSPP_OP_MODE_AUTO_CLEAR 0x00020000
1293
-
#define MDP5_DSPP_OP_MODE_HIST_LUT_EN 0x00080000
1294
-
#define MDP5_DSPP_OP_MODE_PA_EN 0x00100000
1295
-
#define MDP5_DSPP_OP_MODE_GAMUT_EN 0x00800000
1296
-
#define MDP5_DSPP_OP_MODE_GAMUT_ORDER 0x01000000
1297
-
1298
-
static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); }
1299
-
1300
-
static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); }
1301
-
1302
-
static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); }
1303
-
1304
-
static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); }
1305
-
1306
-
static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); }
1307
-
1308
-
static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }
1309
-
1310
-
static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); }
1311
-
1312
-
static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }
1313
-
1314
-
static inline uint32_t __offset_PP(uint32_t idx)
1315
-
{
1316
-
switch (idx) {
1317
-
case 0: return (mdp5_cfg->pp.base[0]);
1318
-
case 1: return (mdp5_cfg->pp.base[1]);
1319
-
case 2: return (mdp5_cfg->pp.base[2]);
1320
-
case 3: return (mdp5_cfg->pp.base[3]);
1321
-
default: return INVALID_IDX(idx);
1322
-
}
1323
-
}
1324
-
static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
1325
-
1326
-
static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
1327
-
1328
-
static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP(i0); }
1329
-
#define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK 0x0007ffff
1330
-
#define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT 0
1331
-
static inline uint32_t MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val)
1332
-
{
1333
-
return ((val) << MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT) & MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK;
1334
-
}
1335
-
#define MDP5_PP_SYNC_CONFIG_VSYNC_COUNTER_EN 0x00080000
1336
-
#define MDP5_PP_SYNC_CONFIG_VSYNC_IN_EN 0x00100000
1337
-
1338
-
static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_PP(i0); }
1339
-
1340
-
static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0); }
1341
-
#define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK 0x0000ffff
1342
-
#define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT 0
1343
-
static inline uint32_t MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val)
1344
-
{
1345
-
return ((val) << MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK;
1346
-
}
1347
-
#define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK 0xffff0000
1348
-
#define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT 16
1349
-
static inline uint32_t MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val)
1350
-
{
1351
-
return ((val) << MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK;
1352
-
}
1353
-
1354
-
static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0); }
1355
-
1356
-
static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0); }
1357
-
#define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK 0x0000ffff
1358
-
#define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT 0
1359
-
static inline uint32_t MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val)
1360
-
{
1361
-
return ((val) << MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK;
1362
-
}
1363
-
#define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK 0xffff0000
1364
-
#define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT 16
1365
-
static inline uint32_t MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val)
1366
-
{
1367
-
return ((val) << MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK;
1368
-
}
1369
-
1370
-
static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); }
1371
-
#define MDP5_PP_SYNC_THRESH_START__MASK 0x0000ffff
1372
-
#define MDP5_PP_SYNC_THRESH_START__SHIFT 0
1373
-
static inline uint32_t MDP5_PP_SYNC_THRESH_START(uint32_t val)
1374
-
{
1375
-
return ((val) << MDP5_PP_SYNC_THRESH_START__SHIFT) & MDP5_PP_SYNC_THRESH_START__MASK;
1376
-
}
1377
-
#define MDP5_PP_SYNC_THRESH_CONTINUE__MASK 0xffff0000
1378
-
#define MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT 16
1379
-
static inline uint32_t MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val)
1380
-
{
1381
-
return ((val) << MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT) & MDP5_PP_SYNC_THRESH_CONTINUE__MASK;
1382
-
}
1383
-
1384
-
static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); }
1385
-
1386
-
static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); }
1387
-
1388
-
static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); }
1389
-
1390
-
static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0); }
1391
-
1392
-
static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0); }
1393
-
1394
-
static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_PP(i0); }
1395
-
1396
-
static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); }
1397
-
1398
-
static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0); }
1399
-
1400
-
static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0); }
1401
-
1402
-
static inline uint32_t __offset_WB(uint32_t idx)
1403
-
{
1404
-
switch (idx) {
1405
-
#if 0 /* TEMPORARY until patch that adds wb.base[] is merged */
1406
-
case 0: return (mdp5_cfg->wb.base[0]);
1407
-
case 1: return (mdp5_cfg->wb.base[1]);
1408
-
case 2: return (mdp5_cfg->wb.base[2]);
1409
-
case 3: return (mdp5_cfg->wb.base[3]);
1410
-
case 4: return (mdp5_cfg->wb.base[4]);
1411
-
#endif
1412
-
default: return INVALID_IDX(idx);
1413
-
}
1414
-
}
1415
-
static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
1416
-
1417
-
static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
1418
-
#define MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK 0x00000003
1419
-
#define MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT 0
1420
-
static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val)
1421
-
{
1422
-
return ((val) << MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK;
1423
-
}
1424
-
#define MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK 0x0000000c
1425
-
#define MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT 2
1426
-
static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val)
1427
-
{
1428
-
return ((val) << MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK;
1429
-
}
1430
-
#define MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK 0x00000030
1431
-
#define MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT 4
1432
-
static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val)
1433
-
{
1434
-
return ((val) << MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK;
1435
-
}
1436
-
#define MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK 0x000000c0
1437
-
#define MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT 6
1438
-
static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val)
1439
-
{
1440
-
return ((val) << MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK;
1441
-
}
1442
-
#define MDP5_WB_DST_FORMAT_DSTC3_EN 0x00000100
1443
-
#define MDP5_WB_DST_FORMAT_DST_BPP__MASK 0x00000600
1444
-
#define MDP5_WB_DST_FORMAT_DST_BPP__SHIFT 9
1445
-
static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val)
1446
-
{
1447
-
return ((val) << MDP5_WB_DST_FORMAT_DST_BPP__SHIFT) & MDP5_WB_DST_FORMAT_DST_BPP__MASK;
1448
-
}
1449
-
#define MDP5_WB_DST_FORMAT_PACK_COUNT__MASK 0x00003000
1450
-
#define MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT 12
1451
-
static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val)
1452
-
{
1453
-
return ((val) << MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT) & MDP5_WB_DST_FORMAT_PACK_COUNT__MASK;
1454
-
}
1455
-
#define MDP5_WB_DST_FORMAT_DST_ALPHA_X 0x00004000
1456
-
#define MDP5_WB_DST_FORMAT_PACK_TIGHT 0x00020000
1457
-
#define MDP5_WB_DST_FORMAT_PACK_ALIGN_MSB 0x00040000
1458
-
#define MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK 0x00180000
1459
-
#define MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT 19
1460
-
static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val)
1461
-
{
1462
-
return ((val) << MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT) & MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK;
1463
-
}
1464
-
#define MDP5_WB_DST_FORMAT_DST_DITHER_EN 0x00400000
1465
-
#define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK 0x03800000
1466
-
#define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT 23
1467
-
static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val)
1468
-
{
1469
-
return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK;
1470
-
}
1471
-
#define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK 0x3c000000
1472
-
#define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT 26
1473
-
static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val)
1474
-
{
1475
-
return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK;
1476
-
}
1477
-
#define MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK 0xc0000000
1478
-
#define MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT 30
1479
-
static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val)
1480
-
{
1481
-
return ((val) << MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT) & MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK;
1482
-
}
1483
-
1484
-
static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); }
1485
-
#define MDP5_WB_DST_OP_MODE_BWC_ENC_EN 0x00000001
1486
-
#define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK 0x00000006
1487
-
#define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT 1
1488
-
static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val)
1489
-
{
1490
-
return ((val) << MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT) & MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK;
1491
-
}
1492
-
#define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK 0x00000010
1493
-
#define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT 4
1494
-
static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val)
1495
-
{
1496
-
return ((val) << MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT) & MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK;
1497
-
}
1498
-
#define MDP5_WB_DST_OP_MODE_ROT_MODE__MASK 0x00000020
1499
-
#define MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT 5
1500
-
static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val)
1501
-
{
1502
-
return ((val) << MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT) & MDP5_WB_DST_OP_MODE_ROT_MODE__MASK;
1503
-
}
1504
-
#define MDP5_WB_DST_OP_MODE_ROT_EN 0x00000040
1505
-
#define MDP5_WB_DST_OP_MODE_CSC_EN 0x00000100
1506
-
#define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00000200
1507
-
#define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 9
1508
-
static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val)
1509
-
{
1510
-
return ((val) << MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
1511
-
}
1512
-
#define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00000400
1513
-
#define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 10
1514
-
static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val)
1515
-
{
1516
-
return ((val) << MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
1517
-
}
1518
-
#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_EN 0x00000800
1519
-
#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK 0x00001000
1520
-
#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT 12
1521
-
static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val)
1522
-
{
1523
-
return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK;
1524
-
}
1525
-
#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK 0x00002000
1526
-
#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT 13
1527
-
static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val)
1528
-
{
1529
-
return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK;
1530
-
}
1531
-
#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK 0x00004000
1532
-
#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT 14
1533
-
static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val)
1534
-
{
1535
-
return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK;
1536
-
}
1537
-
1538
-
static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(i0); }
1539
-
#define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK 0x00000003
1540
-
#define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT 0
1541
-
static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val)
1542
-
{
1543
-
return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK;
1544
-
}
1545
-
#define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK 0x00000300
1546
-
#define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT 8
1547
-
static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val)
1548
-
{
1549
-
return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK;
1550
-
}
1551
-
#define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK 0x00030000
1552
-
#define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT 16
1553
-
static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val)
1554
-
{
1555
-
return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK;
1556
-
}
1557
-
#define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK 0x03000000
1558
-
#define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT 24
1559
-
static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val)
1560
-
{
1561
-
return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK;
1562
-
}
1563
-
1564
-
static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); }
1565
-
1566
-
static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); }
1567
-
1568
-
static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); }
1569
-
1570
-
static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); }
1571
-
1572
-
static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0); }
1573
-
#define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK 0x0000ffff
1574
-
#define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT 0
1575
-
static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val)
1576
-
{
1577
-
return ((val) << MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK;
1578
-
}
1579
-
#define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK 0xffff0000
1580
-
#define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT 16
1581
-
static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val)
1582
-
{
1583
-
return ((val) << MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK;
1584
-
}
1585
-
1586
-
static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0); }
1587
-
#define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK 0x0000ffff
1588
-
#define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT 0
1589
-
static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val)
1590
-
{
1591
-
return ((val) << MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK;
1592
-
}
1593
-
#define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK 0xffff0000
1594
-
#define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT 16
1595
-
static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val)
1596
-
{
1597
-
return ((val) << MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK;
1598
-
}
1599
-
1600
-
static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_WB(i0); }
1601
-
1602
-
static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_WB(i0); }
1603
-
1604
-
static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_WB(i0); }
1605
-
1606
-
static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_WB(i0); }
1607
-
1608
-
static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_WB(i0); }
1609
-
1610
-
static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(i0); }
1611
-
1612
-
static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB(i0); }
1613
-
1614
-
static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset_WB(i0); }
1615
-
1616
-
static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset_WB(i0); }
1617
-
1618
-
static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset_WB(i0); }
1619
-
1620
-
static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset_WB(i0); }
1621
-
1622
-
static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); }
1623
-
#define MDP5_WB_OUT_SIZE_DST_W__MASK 0x0000ffff
1624
-
#define MDP5_WB_OUT_SIZE_DST_W__SHIFT 0
1625
-
static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val)
1626
-
{
1627
-
return ((val) << MDP5_WB_OUT_SIZE_DST_W__SHIFT) & MDP5_WB_OUT_SIZE_DST_W__MASK;
1628
-
}
1629
-
#define MDP5_WB_OUT_SIZE_DST_H__MASK 0xffff0000
1630
-
#define MDP5_WB_OUT_SIZE_DST_H__SHIFT 16
1631
-
static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val)
1632
-
{
1633
-
return ((val) << MDP5_WB_OUT_SIZE_DST_H__SHIFT) & MDP5_WB_OUT_SIZE_DST_H__MASK;
1634
-
}
1635
-
1636
-
static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0); }
1637
-
1638
-
static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_WB(i0); }
1639
-
#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff
1640
-
#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT 0
1641
-
static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val)
1642
-
{
1643
-
return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK;
1644
-
}
1645
-
#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000
1646
-
#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT 16
1647
-
static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val)
1648
-
{
1649
-
return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK;
1650
-
}
1651
-
1652
-
static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_WB(i0); }
1653
-
#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff
1654
-
#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT 0
1655
-
static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val)
1656
-
{
1657
-
return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK;
1658
-
}
1659
-
#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000
1660
-
#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT 16
1661
-
static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val)
1662
-
{
1663
-
return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK;
1664
-
}
1665
-
1666
-
static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_WB(i0); }
1667
-
#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff
1668
-
#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT 0
1669
-
static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val)
1670
-
{
1671
-
return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK;
1672
-
}
1673
-
#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000
1674
-
#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT 16
1675
-
static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val)
1676
-
{
1677
-
return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK;
1678
-
}
1679
-
1680
-
static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_WB(i0); }
1681
-
#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff
1682
-
#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT 0
1683
-
static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val)
1684
-
{
1685
-
return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK;
1686
-
}
1687
-
#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000
1688
-
#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT 16
1689
-
static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val)
1690
-
{
1691
-
return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK;
1692
-
}
1693
-
1694
-
static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_WB(i0); }
1695
-
#define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff
1696
-
#define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT 0
1697
-
static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val)
1698
-
{
1699
-
return ((val) << MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK;
1700
-
}
1701
-
1702
-
static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
1703
-
1704
-
static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
1705
-
#define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK 0x000000ff
1706
-
#define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT 0
1707
-
static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val)
1708
-
{
1709
-
return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK;
1710
-
}
1711
-
#define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK 0x0000ff00
1712
-
#define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT 8
1713
-
static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val)
1714
-
{
1715
-
return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK;
1716
-
}
1717
-
1718
-
static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
1719
-
1720
-
static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
1721
-
#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK 0x000000ff
1722
-
#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT 0
1723
-
static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val)
1724
-
{
1725
-
return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK;
1726
-
}
1727
-
#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK 0x0000ff00
1728
-
#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT 8
1729
-
static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val)
1730
-
{
1731
-
return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK;
1732
-
}
1733
-
1734
-
static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
1735
-
1736
-
static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
1737
-
#define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK 0x000001ff
1738
-
#define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT 0
1739
-
static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val)
1740
-
{
1741
-
return ((val) << MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK;
1742
-
}
1743
-
1744
-
static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
1745
-
1746
-
static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
1747
-
#define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK 0x000001ff
1748
-
#define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT 0
1749
-
static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val)
1750
-
{
1751
-
return ((val) << MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK;
1752
-
}
1753
-
1754
-
static inline uint32_t __offset_INTF(uint32_t idx)
1755
-
{
1756
-
switch (idx) {
1757
-
case 0: return (mdp5_cfg->intf.base[0]);
1758
-
case 1: return (mdp5_cfg->intf.base[1]);
1759
-
case 2: return (mdp5_cfg->intf.base[2]);
1760
-
case 3: return (mdp5_cfg->intf.base[3]);
1761
-
case 4: return (mdp5_cfg->intf.base[4]);
1762
-
default: return INVALID_IDX(idx);
1763
-
}
1764
-
}
1765
-
static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
1766
-
1767
-
static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
1768
-
1769
-
static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }
1770
-
1771
-
static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); }
1772
-
#define MDP5_INTF_HSYNC_CTL_PULSEW__MASK 0x0000ffff
1773
-
#define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT 0
1774
-
static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)
1775
-
{
1776
-
return ((val) << MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT) & MDP5_INTF_HSYNC_CTL_PULSEW__MASK;
1777
-
}
1778
-
#define MDP5_INTF_HSYNC_CTL_PERIOD__MASK 0xffff0000
1779
-
#define MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT 16
1780
-
static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)
1781
-
{
1782
-
return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK;
1783
-
}
1784
-
1785
-
static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); }
1786
-
1787
-
static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); }
1788
-
1789
-
static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); }
1790
-
1791
-
static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); }
1792
-
1793
-
static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); }
1794
-
1795
-
static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); }
1796
-
1797
-
static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); }
1798
-
1799
-
static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); }
1800
-
1801
-
static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); }
1802
-
#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK 0x7fffffff
1803
-
#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT 0
1804
-
static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)
1805
-
{
1806
-
return ((val) << MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK;
1807
-
}
1808
-
#define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE 0x80000000
1809
-
1810
-
static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); }
1811
-
#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK 0x7fffffff
1812
-
#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT 0
1813
-
static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)
1814
-
{
1815
-
return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK;
1816
-
}
1817
-
1818
-
static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); }
1819
-
1820
-
static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); }
1821
-
1822
-
static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); }
1823
-
#define MDP5_INTF_DISPLAY_HCTL_START__MASK 0x0000ffff
1824
-
#define MDP5_INTF_DISPLAY_HCTL_START__SHIFT 0
1825
-
static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)
1826
-
{
1827
-
return ((val) << MDP5_INTF_DISPLAY_HCTL_START__SHIFT) & MDP5_INTF_DISPLAY_HCTL_START__MASK;
1828
-
}
1829
-
#define MDP5_INTF_DISPLAY_HCTL_END__MASK 0xffff0000
1830
-
#define MDP5_INTF_DISPLAY_HCTL_END__SHIFT 16
1831
-
static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)
1832
-
{
1833
-
return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK;
1834
-
}
1835
-
1836
-
static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); }
1837
-
#define MDP5_INTF_ACTIVE_HCTL_START__MASK 0x00007fff
1838
-
#define MDP5_INTF_ACTIVE_HCTL_START__SHIFT 0
1839
-
static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)
1840
-
{
1841
-
return ((val) << MDP5_INTF_ACTIVE_HCTL_START__SHIFT) & MDP5_INTF_ACTIVE_HCTL_START__MASK;
1842
-
}
1843
-
#define MDP5_INTF_ACTIVE_HCTL_END__MASK 0x7fff0000
1844
-
#define MDP5_INTF_ACTIVE_HCTL_END__SHIFT 16
1845
-
static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)
1846
-
{
1847
-
return ((val) << MDP5_INTF_ACTIVE_HCTL_END__SHIFT) & MDP5_INTF_ACTIVE_HCTL_END__MASK;
1848
-
}
1849
-
#define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE 0x80000000
1850
-
1851
-
static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); }
1852
-
1853
-
static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); }
1854
-
1855
-
static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); }
1856
-
1857
-
static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); }
1858
-
#define MDP5_INTF_POLARITY_CTL_HSYNC_LOW 0x00000001
1859
-
#define MDP5_INTF_POLARITY_CTL_VSYNC_LOW 0x00000002
1860
-
#define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW 0x00000004
1861
-
1862
-
static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); }
1863
-
1864
-
static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); }
1865
-
1866
-
static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); }
1867
-
1868
-
static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); }
1869
-
1870
-
static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); }
1871
-
1872
-
static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); }
1873
-
1874
-
static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); }
1875
-
1876
-
static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); }
1877
-
1878
-
static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); }
1879
-
1880
-
static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); }
1881
-
1882
-
static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); }
1883
-
1884
-
static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); }
1885
-
1886
-
static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); }
1887
-
1888
-
static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); }
1889
-
1890
-
static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); }
1891
-
1892
-
static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); }
1893
-
1894
-
static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); }
1895
-
1896
-
static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); }
1897
-
1898
-
static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); }
1899
-
1900
-
static inline uint32_t __offset_AD(uint32_t idx)
1901
-
{
1902
-
switch (idx) {
1903
-
case 0: return (mdp5_cfg->ad.base[0]);
1904
-
case 1: return (mdp5_cfg->ad.base[1]);
1905
-
default: return INVALID_IDX(idx);
1906
-
}
1907
-
}
1908
-
static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1909
-
1910
-
static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1911
-
1912
-
static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }
1913
-
1914
-
static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }
1915
-
1916
-
static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }
1917
-
1918
-
static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }
1919
-
1920
-
static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }
1921
-
1922
-
static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }
1923
-
1924
-
static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }
1925
-
1926
-
static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }
1927
-
1928
-
static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }
1929
-
1930
-
static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }
1931
-
1932
-
static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }
1933
-
1934
-
static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }
1935
-
1936
-
static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }
1937
-
1938
-
static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }
1939
-
1940
-
static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }
1941
-
1942
-
static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }
1943
-
1944
-
static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }
1945
-
1946
-
static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }
1947
-
1948
-
static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }
1949
-
1950
-
static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }
1951
-
1952
-
static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }
1953
-
1954
-
static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }
1955
-
1956
-
static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }
1957
-
1958
-
static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }
1959
-
1960
-
static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }
1961
-
1962
-
static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }
1963
-
1964
-
static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }
1965
-
1966
-
static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }
1967
-
1968
-
static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }
1969
-
1970
-
static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }
1971
-
1972
-
static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }
1973
-
1974
-
static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }
1975
-
1976
-
static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }
1977
-
1978
-
1979
-
#endif /* MDP5_XML */
-111
drivers/gpu/drm/msm/disp/mdp_common.xml.h
-111
drivers/gpu/drm/msm/disp/mdp_common.xml.h
···
1
-
#ifndef MDP_COMMON_XML
2
-
#define MDP_COMMON_XML
3
-
4
-
/* Autogenerated file, DO NOT EDIT manually!
5
-
6
-
This file was generated by the rules-ng-ng headergen tool in this git repository:
7
-
http://github.com/freedreno/envytools/
8
-
git clone https://github.com/freedreno/envytools.git
9
-
10
-
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
12
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
13
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
14
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
15
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
16
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
17
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
18
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
19
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
20
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
21
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
22
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
23
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
24
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
25
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
26
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
27
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
28
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
29
-
30
-
Copyright (C) 2013-2022 by the following authors:
31
-
- Rob Clark <robdclark@gmail.com> (robclark)
32
-
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
33
-
34
-
Permission is hereby granted, free of charge, to any person obtaining
35
-
a copy of this software and associated documentation files (the
36
-
"Software"), to deal in the Software without restriction, including
37
-
without limitation the rights to use, copy, modify, merge, publish,
38
-
distribute, sublicense, and/or sell copies of the Software, and to
39
-
permit persons to whom the Software is furnished to do so, subject to
40
-
the following conditions:
41
-
42
-
The above copyright notice and this permission notice (including the
43
-
next paragraph) shall be included in all copies or substantial
44
-
portions of the Software.
45
-
46
-
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
47
-
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
48
-
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
49
-
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
50
-
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
51
-
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
52
-
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
53
-
*/
54
-
55
-
56
-
enum mdp_chroma_samp_type {
57
-
CHROMA_FULL = 0,
58
-
CHROMA_H2V1 = 1,
59
-
CHROMA_H1V2 = 2,
60
-
CHROMA_420 = 3,
61
-
};
62
-
63
-
enum mdp_fetch_type {
64
-
MDP_PLANE_INTERLEAVED = 0,
65
-
MDP_PLANE_PLANAR = 1,
66
-
MDP_PLANE_PSEUDO_PLANAR = 2,
67
-
};
68
-
69
-
enum mdp_mixer_stage_id {
70
-
STAGE_UNUSED = 0,
71
-
STAGE_BASE = 1,
72
-
STAGE0 = 2,
73
-
STAGE1 = 3,
74
-
STAGE2 = 4,
75
-
STAGE3 = 5,
76
-
STAGE4 = 6,
77
-
STAGE5 = 7,
78
-
STAGE6 = 8,
79
-
STAGE_MAX = 8,
80
-
};
81
-
82
-
enum mdp_alpha_type {
83
-
FG_CONST = 0,
84
-
BG_CONST = 1,
85
-
FG_PIXEL = 2,
86
-
BG_PIXEL = 3,
87
-
};
88
-
89
-
enum mdp_component_type {
90
-
COMP_0 = 0,
91
-
COMP_1_2 = 1,
92
-
COMP_3 = 2,
93
-
COMP_MAX = 3,
94
-
};
95
-
96
-
enum mdp_bpc {
97
-
BPC1 = 0,
98
-
BPC5 = 1,
99
-
BPC6 = 2,
100
-
BPC8 = 3,
101
-
};
102
-
103
-
enum mdp_bpc_alpha {
104
-
BPC1A = 0,
105
-
BPC4A = 1,
106
-
BPC6A = 2,
107
-
BPC8A = 3,
108
-
};
109
-
110
-
111
-
#endif /* MDP_COMMON_XML */
-790
drivers/gpu/drm/msm/dsi/dsi.xml.h
-790
drivers/gpu/drm/msm/dsi/dsi.xml.h
···
1
-
#ifndef DSI_XML
2
-
#define DSI_XML
3
-
4
-
/* Autogenerated file, DO NOT EDIT manually!
5
-
6
-
This file was generated by the rules-ng-ng headergen tool in this git repository:
7
-
http://github.com/freedreno/envytools/
8
-
git clone https://github.com/freedreno/envytools.git
9
-
10
-
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
12
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
13
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
14
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
15
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
16
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
17
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
18
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
19
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
20
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
21
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
22
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
23
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
24
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
25
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
26
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
27
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
28
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
29
-
30
-
Copyright (C) 2013-2022 by the following authors:
31
-
- Rob Clark <robdclark@gmail.com> (robclark)
32
-
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
33
-
34
-
Permission is hereby granted, free of charge, to any person obtaining
35
-
a copy of this software and associated documentation files (the
36
-
"Software"), to deal in the Software without restriction, including
37
-
without limitation the rights to use, copy, modify, merge, publish,
38
-
distribute, sublicense, and/or sell copies of the Software, and to
39
-
permit persons to whom the Software is furnished to do so, subject to
40
-
the following conditions:
41
-
42
-
The above copyright notice and this permission notice (including the
43
-
next paragraph) shall be included in all copies or substantial
44
-
portions of the Software.
45
-
46
-
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
47
-
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
48
-
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
49
-
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
50
-
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
51
-
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
52
-
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
53
-
*/
54
-
55
-
56
-
enum dsi_traffic_mode {
57
-
NON_BURST_SYNCH_PULSE = 0,
58
-
NON_BURST_SYNCH_EVENT = 1,
59
-
BURST_MODE = 2,
60
-
};
61
-
62
-
enum dsi_vid_dst_format {
63
-
VID_DST_FORMAT_RGB565 = 0,
64
-
VID_DST_FORMAT_RGB666 = 1,
65
-
VID_DST_FORMAT_RGB666_LOOSE = 2,
66
-
VID_DST_FORMAT_RGB888 = 3,
67
-
};
68
-
69
-
enum dsi_rgb_swap {
70
-
SWAP_RGB = 0,
71
-
SWAP_RBG = 1,
72
-
SWAP_BGR = 2,
73
-
SWAP_BRG = 3,
74
-
SWAP_GRB = 4,
75
-
SWAP_GBR = 5,
76
-
};
77
-
78
-
enum dsi_cmd_trigger {
79
-
TRIGGER_NONE = 0,
80
-
TRIGGER_SEOF = 1,
81
-
TRIGGER_TE = 2,
82
-
TRIGGER_SW = 4,
83
-
TRIGGER_SW_SEOF = 5,
84
-
TRIGGER_SW_TE = 6,
85
-
};
86
-
87
-
enum dsi_cmd_dst_format {
88
-
CMD_DST_FORMAT_RGB111 = 0,
89
-
CMD_DST_FORMAT_RGB332 = 3,
90
-
CMD_DST_FORMAT_RGB444 = 4,
91
-
CMD_DST_FORMAT_RGB565 = 6,
92
-
CMD_DST_FORMAT_RGB666 = 7,
93
-
CMD_DST_FORMAT_RGB888 = 8,
94
-
};
95
-
96
-
enum dsi_lane_swap {
97
-
LANE_SWAP_0123 = 0,
98
-
LANE_SWAP_3012 = 1,
99
-
LANE_SWAP_2301 = 2,
100
-
LANE_SWAP_1230 = 3,
101
-
LANE_SWAP_0321 = 4,
102
-
LANE_SWAP_1032 = 5,
103
-
LANE_SWAP_2103 = 6,
104
-
LANE_SWAP_3210 = 7,
105
-
};
106
-
107
-
enum video_config_bpp {
108
-
VIDEO_CONFIG_18BPP = 0,
109
-
VIDEO_CONFIG_24BPP = 1,
110
-
};
111
-
112
-
enum video_pattern_sel {
113
-
VID_PRBS = 0,
114
-
VID_INCREMENTAL = 1,
115
-
VID_FIXED = 2,
116
-
VID_MDSS_GENERAL_PATTERN = 3,
117
-
};
118
-
119
-
enum cmd_mdp_stream0_pattern_sel {
120
-
CMD_MDP_PRBS = 0,
121
-
CMD_MDP_INCREMENTAL = 1,
122
-
CMD_MDP_FIXED = 2,
123
-
CMD_MDP_MDSS_GENERAL_PATTERN = 3,
124
-
};
125
-
126
-
enum cmd_dma_pattern_sel {
127
-
CMD_DMA_PRBS = 0,
128
-
CMD_DMA_INCREMENTAL = 1,
129
-
CMD_DMA_FIXED = 2,
130
-
CMD_DMA_CUSTOM_PATTERN_DMA_FIFO = 3,
131
-
};
132
-
133
-
#define DSI_IRQ_CMD_DMA_DONE 0x00000001
134
-
#define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
135
-
#define DSI_IRQ_CMD_MDP_DONE 0x00000100
136
-
#define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
137
-
#define DSI_IRQ_VIDEO_DONE 0x00010000
138
-
#define DSI_IRQ_MASK_VIDEO_DONE 0x00020000
139
-
#define DSI_IRQ_BTA_DONE 0x00100000
140
-
#define DSI_IRQ_MASK_BTA_DONE 0x00200000
141
-
#define DSI_IRQ_ERROR 0x01000000
142
-
#define DSI_IRQ_MASK_ERROR 0x02000000
143
-
#define REG_DSI_6G_HW_VERSION 0x00000000
144
-
#define DSI_6G_HW_VERSION_MAJOR__MASK 0xf0000000
145
-
#define DSI_6G_HW_VERSION_MAJOR__SHIFT 28
146
-
static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val)
147
-
{
148
-
return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK;
149
-
}
150
-
#define DSI_6G_HW_VERSION_MINOR__MASK 0x0fff0000
151
-
#define DSI_6G_HW_VERSION_MINOR__SHIFT 16
152
-
static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val)
153
-
{
154
-
return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK;
155
-
}
156
-
#define DSI_6G_HW_VERSION_STEP__MASK 0x0000ffff
157
-
#define DSI_6G_HW_VERSION_STEP__SHIFT 0
158
-
static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val)
159
-
{
160
-
return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK;
161
-
}
162
-
163
-
#define REG_DSI_CTRL 0x00000000
164
-
#define DSI_CTRL_ENABLE 0x00000001
165
-
#define DSI_CTRL_VID_MODE_EN 0x00000002
166
-
#define DSI_CTRL_CMD_MODE_EN 0x00000004
167
-
#define DSI_CTRL_LANE0 0x00000010
168
-
#define DSI_CTRL_LANE1 0x00000020
169
-
#define DSI_CTRL_LANE2 0x00000040
170
-
#define DSI_CTRL_LANE3 0x00000080
171
-
#define DSI_CTRL_CLK_EN 0x00000100
172
-
#define DSI_CTRL_ECC_CHECK 0x00100000
173
-
#define DSI_CTRL_CRC_CHECK 0x01000000
174
-
175
-
#define REG_DSI_STATUS0 0x00000004
176
-
#define DSI_STATUS0_CMD_MODE_ENGINE_BUSY 0x00000001
177
-
#define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002
178
-
#define DSI_STATUS0_CMD_MODE_MDP_BUSY 0x00000004
179
-
#define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008
180
-
#define DSI_STATUS0_DSI_BUSY 0x00000010
181
-
#define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000
182
-
183
-
#define REG_DSI_FIFO_STATUS 0x00000008
184
-
#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_OVERFLOW 0x00000001
185
-
#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_UNDERFLOW 0x00000008
186
-
#define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080
187
-
#define DSI_FIFO_STATUS_CMD_DMA_FIFO_RD_WATERMARK_REACH 0x00000100
188
-
#define DSI_FIFO_STATUS_CMD_DMA_FIFO_WR_WATERMARK_REACH 0x00000200
189
-
#define DSI_FIFO_STATUS_CMD_DMA_FIFO_UNDERFLOW 0x00000400
190
-
#define DSI_FIFO_STATUS_DLN0_LP_FIFO_EMPTY 0x00001000
191
-
#define DSI_FIFO_STATUS_DLN0_LP_FIFO_FULL 0x00002000
192
-
#define DSI_FIFO_STATUS_DLN0_LP_FIFO_OVERFLOW 0x00004000
193
-
#define DSI_FIFO_STATUS_DLN0_HS_FIFO_EMPTY 0x00010000
194
-
#define DSI_FIFO_STATUS_DLN0_HS_FIFO_FULL 0x00020000
195
-
#define DSI_FIFO_STATUS_DLN0_HS_FIFO_OVERFLOW 0x00040000
196
-
#define DSI_FIFO_STATUS_DLN0_HS_FIFO_UNDERFLOW 0x00080000
197
-
#define DSI_FIFO_STATUS_DLN1_HS_FIFO_EMPTY 0x00100000
198
-
#define DSI_FIFO_STATUS_DLN1_HS_FIFO_FULL 0x00200000
199
-
#define DSI_FIFO_STATUS_DLN1_HS_FIFO_OVERFLOW 0x00400000
200
-
#define DSI_FIFO_STATUS_DLN1_HS_FIFO_UNDERFLOW 0x00800000
201
-
#define DSI_FIFO_STATUS_DLN2_HS_FIFO_EMPTY 0x01000000
202
-
#define DSI_FIFO_STATUS_DLN2_HS_FIFO_FULL 0x02000000
203
-
#define DSI_FIFO_STATUS_DLN2_HS_FIFO_OVERFLOW 0x04000000
204
-
#define DSI_FIFO_STATUS_DLN2_HS_FIFO_UNDERFLOW 0x08000000
205
-
#define DSI_FIFO_STATUS_DLN3_HS_FIFO_EMPTY 0x10000000
206
-
#define DSI_FIFO_STATUS_DLN3_HS_FIFO_FULL 0x20000000
207
-
#define DSI_FIFO_STATUS_DLN3_HS_FIFO_OVERFLOW 0x40000000
208
-
#define DSI_FIFO_STATUS_DLN3_HS_FIFO_UNDERFLOW 0x80000000
209
-
210
-
#define REG_DSI_VID_CFG0 0x0000000c
211
-
#define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003
212
-
#define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0
213
-
static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val)
214
-
{
215
-
return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK;
216
-
}
217
-
#define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030
218
-
#define DSI_VID_CFG0_DST_FORMAT__SHIFT 4
219
-
static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val)
220
-
{
221
-
return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK;
222
-
}
223
-
#define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300
224
-
#define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT 8
225
-
static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val)
226
-
{
227
-
return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK;
228
-
}
229
-
#define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000
230
-
#define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000
231
-
#define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000
232
-
#define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000
233
-
#define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000
234
-
#define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000
235
-
236
-
#define REG_DSI_VID_CFG1 0x0000001c
237
-
#define DSI_VID_CFG1_R_SEL 0x00000001
238
-
#define DSI_VID_CFG1_G_SEL 0x00000010
239
-
#define DSI_VID_CFG1_B_SEL 0x00000100
240
-
#define DSI_VID_CFG1_RGB_SWAP__MASK 0x00007000
241
-
#define DSI_VID_CFG1_RGB_SWAP__SHIFT 12
242
-
static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val)
243
-
{
244
-
return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK;
245
-
}
246
-
247
-
#define REG_DSI_ACTIVE_H 0x00000020
248
-
#define DSI_ACTIVE_H_START__MASK 0x00000fff
249
-
#define DSI_ACTIVE_H_START__SHIFT 0
250
-
static inline uint32_t DSI_ACTIVE_H_START(uint32_t val)
251
-
{
252
-
return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK;
253
-
}
254
-
#define DSI_ACTIVE_H_END__MASK 0x0fff0000
255
-
#define DSI_ACTIVE_H_END__SHIFT 16
256
-
static inline uint32_t DSI_ACTIVE_H_END(uint32_t val)
257
-
{
258
-
return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK;
259
-
}
260
-
261
-
#define REG_DSI_ACTIVE_V 0x00000024
262
-
#define DSI_ACTIVE_V_START__MASK 0x00000fff
263
-
#define DSI_ACTIVE_V_START__SHIFT 0
264
-
static inline uint32_t DSI_ACTIVE_V_START(uint32_t val)
265
-
{
266
-
return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK;
267
-
}
268
-
#define DSI_ACTIVE_V_END__MASK 0x0fff0000
269
-
#define DSI_ACTIVE_V_END__SHIFT 16
270
-
static inline uint32_t DSI_ACTIVE_V_END(uint32_t val)
271
-
{
272
-
return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK;
273
-
}
274
-
275
-
#define REG_DSI_TOTAL 0x00000028
276
-
#define DSI_TOTAL_H_TOTAL__MASK 0x00000fff
277
-
#define DSI_TOTAL_H_TOTAL__SHIFT 0
278
-
static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val)
279
-
{
280
-
return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK;
281
-
}
282
-
#define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000
283
-
#define DSI_TOTAL_V_TOTAL__SHIFT 16
284
-
static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val)
285
-
{
286
-
return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK;
287
-
}
288
-
289
-
#define REG_DSI_ACTIVE_HSYNC 0x0000002c
290
-
#define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff
291
-
#define DSI_ACTIVE_HSYNC_START__SHIFT 0
292
-
static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val)
293
-
{
294
-
return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK;
295
-
}
296
-
#define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000
297
-
#define DSI_ACTIVE_HSYNC_END__SHIFT 16
298
-
static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val)
299
-
{
300
-
return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK;
301
-
}
302
-
303
-
#define REG_DSI_ACTIVE_VSYNC_HPOS 0x00000030
304
-
#define DSI_ACTIVE_VSYNC_HPOS_START__MASK 0x00000fff
305
-
#define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT 0
306
-
static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val)
307
-
{
308
-
return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK;
309
-
}
310
-
#define DSI_ACTIVE_VSYNC_HPOS_END__MASK 0x0fff0000
311
-
#define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT 16
312
-
static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val)
313
-
{
314
-
return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK;
315
-
}
316
-
317
-
#define REG_DSI_ACTIVE_VSYNC_VPOS 0x00000034
318
-
#define DSI_ACTIVE_VSYNC_VPOS_START__MASK 0x00000fff
319
-
#define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT 0
320
-
static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val)
321
-
{
322
-
return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK;
323
-
}
324
-
#define DSI_ACTIVE_VSYNC_VPOS_END__MASK 0x0fff0000
325
-
#define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT 16
326
-
static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val)
327
-
{
328
-
return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK;
329
-
}
330
-
331
-
#define REG_DSI_CMD_DMA_CTRL 0x00000038
332
-
#define DSI_CMD_DMA_CTRL_BROADCAST_EN 0x80000000
333
-
#define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000
334
-
#define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000
335
-
336
-
#define REG_DSI_CMD_CFG0 0x0000003c
337
-
#define DSI_CMD_CFG0_DST_FORMAT__MASK 0x0000000f
338
-
#define DSI_CMD_CFG0_DST_FORMAT__SHIFT 0
339
-
static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val)
340
-
{
341
-
return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK;
342
-
}
343
-
#define DSI_CMD_CFG0_R_SEL 0x00000010
344
-
#define DSI_CMD_CFG0_G_SEL 0x00000100
345
-
#define DSI_CMD_CFG0_B_SEL 0x00001000
346
-
#define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK 0x00f00000
347
-
#define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT 20
348
-
static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val)
349
-
{
350
-
return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK;
351
-
}
352
-
#define DSI_CMD_CFG0_RGB_SWAP__MASK 0x00070000
353
-
#define DSI_CMD_CFG0_RGB_SWAP__SHIFT 16
354
-
static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val)
355
-
{
356
-
return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK;
357
-
}
358
-
359
-
#define REG_DSI_CMD_CFG1 0x00000040
360
-
#define DSI_CMD_CFG1_WR_MEM_START__MASK 0x000000ff
361
-
#define DSI_CMD_CFG1_WR_MEM_START__SHIFT 0
362
-
static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val)
363
-
{
364
-
return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK;
365
-
}
366
-
#define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK 0x0000ff00
367
-
#define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT 8
368
-
static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val)
369
-
{
370
-
return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK;
371
-
}
372
-
#define DSI_CMD_CFG1_INSERT_DCS_COMMAND 0x00010000
373
-
374
-
#define REG_DSI_DMA_BASE 0x00000044
375
-
376
-
#define REG_DSI_DMA_LEN 0x00000048
377
-
378
-
#define REG_DSI_CMD_MDP_STREAM0_CTRL 0x00000054
379
-
#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK 0x0000003f
380
-
#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT 0
381
-
static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(uint32_t val)
382
-
{
383
-
return ((val) << DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK;
384
-
}
385
-
#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
386
-
#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT 8
387
-
static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(uint32_t val)
388
-
{
389
-
return ((val) << DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK;
390
-
}
391
-
#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK 0xffff0000
392
-
#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT 16
393
-
static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(uint32_t val)
394
-
{
395
-
return ((val) << DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK;
396
-
}
397
-
398
-
#define REG_DSI_CMD_MDP_STREAM0_TOTAL 0x00000058
399
-
#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK 0x00000fff
400
-
#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT 0
401
-
static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(uint32_t val)
402
-
{
403
-
return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK;
404
-
}
405
-
#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK 0x0fff0000
406
-
#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT 16
407
-
static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(uint32_t val)
408
-
{
409
-
return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK;
410
-
}
411
-
412
-
#define REG_DSI_CMD_MDP_STREAM1_CTRL 0x0000005c
413
-
#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK 0x0000003f
414
-
#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT 0
415
-
static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE(uint32_t val)
416
-
{
417
-
return ((val) << DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK;
418
-
}
419
-
#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
420
-
#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT 8
421
-
static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL(uint32_t val)
422
-
{
423
-
return ((val) << DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK;
424
-
}
425
-
#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK 0xffff0000
426
-
#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT 16
427
-
static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT(uint32_t val)
428
-
{
429
-
return ((val) << DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK;
430
-
}
431
-
432
-
#define REG_DSI_CMD_MDP_STREAM1_TOTAL 0x00000060
433
-
#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK 0x0000ffff
434
-
#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT 0
435
-
static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL(uint32_t val)
436
-
{
437
-
return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK;
438
-
}
439
-
#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK 0xffff0000
440
-
#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT 16
441
-
static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL(uint32_t val)
442
-
{
443
-
return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK;
444
-
}
445
-
446
-
#define REG_DSI_ACK_ERR_STATUS 0x00000064
447
-
448
-
static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; }
449
-
450
-
static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; }
451
-
452
-
#define REG_DSI_TRIG_CTRL 0x00000080
453
-
#define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x00000007
454
-
#define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0
455
-
static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val)
456
-
{
457
-
return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK;
458
-
}
459
-
#define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x00000070
460
-
#define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT 4
461
-
static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val)
462
-
{
463
-
return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK;
464
-
}
465
-
#define DSI_TRIG_CTRL_STREAM__MASK 0x00000300
466
-
#define DSI_TRIG_CTRL_STREAM__SHIFT 8
467
-
static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val)
468
-
{
469
-
return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK;
470
-
}
471
-
#define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME 0x00001000
472
-
#define DSI_TRIG_CTRL_TE 0x80000000
473
-
474
-
#define REG_DSI_TRIG_DMA 0x0000008c
475
-
476
-
#define REG_DSI_DLN0_PHY_ERR 0x000000b0
477
-
#define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC 0x00000001
478
-
#define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC 0x00000010
479
-
#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL 0x00000100
480
-
#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000
481
-
#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000
482
-
483
-
#define REG_DSI_LP_TIMER_CTRL 0x000000b4
484
-
#define DSI_LP_TIMER_CTRL_LP_RX_TO__MASK 0x0000ffff
485
-
#define DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT 0
486
-
static inline uint32_t DSI_LP_TIMER_CTRL_LP_RX_TO(uint32_t val)
487
-
{
488
-
return ((val) << DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT) & DSI_LP_TIMER_CTRL_LP_RX_TO__MASK;
489
-
}
490
-
#define DSI_LP_TIMER_CTRL_BTA_TO__MASK 0xffff0000
491
-
#define DSI_LP_TIMER_CTRL_BTA_TO__SHIFT 16
492
-
static inline uint32_t DSI_LP_TIMER_CTRL_BTA_TO(uint32_t val)
493
-
{
494
-
return ((val) << DSI_LP_TIMER_CTRL_BTA_TO__SHIFT) & DSI_LP_TIMER_CTRL_BTA_TO__MASK;
495
-
}
496
-
497
-
#define REG_DSI_HS_TIMER_CTRL 0x000000b8
498
-
#define DSI_HS_TIMER_CTRL_HS_TX_TO__MASK 0x0000ffff
499
-
#define DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT 0
500
-
static inline uint32_t DSI_HS_TIMER_CTRL_HS_TX_TO(uint32_t val)
501
-
{
502
-
return ((val) << DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT) & DSI_HS_TIMER_CTRL_HS_TX_TO__MASK;
503
-
}
504
-
#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK 0x000f0000
505
-
#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT 16
506
-
static inline uint32_t DSI_HS_TIMER_CTRL_TIMER_RESOLUTION(uint32_t val)
507
-
{
508
-
return ((val) << DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT) & DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK;
509
-
}
510
-
#define DSI_HS_TIMER_CTRL_HS_TX_TO_STOP_EN 0x10000000
511
-
512
-
#define REG_DSI_TIMEOUT_STATUS 0x000000bc
513
-
514
-
#define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0
515
-
#define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f
516
-
#define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0
517
-
static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val)
518
-
{
519
-
return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK;
520
-
}
521
-
#define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00
522
-
#define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT 8
523
-
static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)
524
-
{
525
-
return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK;
526
-
}
527
-
528
-
#define REG_DSI_EOT_PACKET_CTRL 0x000000c8
529
-
#define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001
530
-
#define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010
531
-
532
-
#define REG_DSI_LANE_STATUS 0x000000a4
533
-
#define DSI_LANE_STATUS_DLN0_STOPSTATE 0x00000001
534
-
#define DSI_LANE_STATUS_DLN1_STOPSTATE 0x00000002
535
-
#define DSI_LANE_STATUS_DLN2_STOPSTATE 0x00000004
536
-
#define DSI_LANE_STATUS_DLN3_STOPSTATE 0x00000008
537
-
#define DSI_LANE_STATUS_CLKLN_STOPSTATE 0x00000010
538
-
#define DSI_LANE_STATUS_DLN0_ULPS_ACTIVE_NOT 0x00000100
539
-
#define DSI_LANE_STATUS_DLN1_ULPS_ACTIVE_NOT 0x00000200
540
-
#define DSI_LANE_STATUS_DLN2_ULPS_ACTIVE_NOT 0x00000400
541
-
#define DSI_LANE_STATUS_DLN3_ULPS_ACTIVE_NOT 0x00000800
542
-
#define DSI_LANE_STATUS_CLKLN_ULPS_ACTIVE_NOT 0x00001000
543
-
#define DSI_LANE_STATUS_DLN0_DIRECTION 0x00010000
544
-
545
-
#define REG_DSI_LANE_CTRL 0x000000a8
546
-
#define DSI_LANE_CTRL_HS_REQ_SEL_PHY 0x01000000
547
-
#define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000
548
-
549
-
#define REG_DSI_LANE_SWAP_CTRL 0x000000ac
550
-
#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007
551
-
#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0
552
-
static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val)
553
-
{
554
-
return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK;
555
-
}
556
-
557
-
#define REG_DSI_ERR_INT_MASK0 0x00000108
558
-
559
-
#define REG_DSI_INTR_CTRL 0x0000010c
560
-
561
-
#define REG_DSI_RESET 0x00000114
562
-
563
-
#define REG_DSI_CLK_CTRL 0x00000118
564
-
#define DSI_CLK_CTRL_AHBS_HCLK_ON 0x00000001
565
-
#define DSI_CLK_CTRL_AHBM_SCLK_ON 0x00000002
566
-
#define DSI_CLK_CTRL_PCLK_ON 0x00000004
567
-
#define DSI_CLK_CTRL_DSICLK_ON 0x00000008
568
-
#define DSI_CLK_CTRL_BYTECLK_ON 0x00000010
569
-
#define DSI_CLK_CTRL_ESCCLK_ON 0x00000020
570
-
#define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200
571
-
572
-
#define REG_DSI_CLK_STATUS 0x0000011c
573
-
#define DSI_CLK_STATUS_DSI_AON_AHBM_HCLK_ACTIVE 0x00000001
574
-
#define DSI_CLK_STATUS_DSI_DYN_AHBM_HCLK_ACTIVE 0x00000002
575
-
#define DSI_CLK_STATUS_DSI_AON_AHBS_HCLK_ACTIVE 0x00000004
576
-
#define DSI_CLK_STATUS_DSI_DYN_AHBS_HCLK_ACTIVE 0x00000008
577
-
#define DSI_CLK_STATUS_DSI_AON_DSICLK_ACTIVE 0x00000010
578
-
#define DSI_CLK_STATUS_DSI_DYN_DSICLK_ACTIVE 0x00000020
579
-
#define DSI_CLK_STATUS_DSI_AON_BYTECLK_ACTIVE 0x00000040
580
-
#define DSI_CLK_STATUS_DSI_DYN_BYTECLK_ACTIVE 0x00000080
581
-
#define DSI_CLK_STATUS_DSI_AON_ESCCLK_ACTIVE 0x00000100
582
-
#define DSI_CLK_STATUS_DSI_AON_PCLK_ACTIVE 0x00000200
583
-
#define DSI_CLK_STATUS_DSI_DYN_PCLK_ACTIVE 0x00000400
584
-
#define DSI_CLK_STATUS_DSI_DYN_CMD_PCLK_ACTIVE 0x00001000
585
-
#define DSI_CLK_STATUS_DSI_CMD_PCLK_ACTIVE 0x00002000
586
-
#define DSI_CLK_STATUS_DSI_VID_PCLK_ACTIVE 0x00004000
587
-
#define DSI_CLK_STATUS_DSI_CAM_BIST_PCLK_ACT 0x00008000
588
-
#define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000
589
-
590
-
#define REG_DSI_PHY_RESET 0x00000128
591
-
#define DSI_PHY_RESET_RESET 0x00000001
592
-
593
-
#define REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL 0x00000160
594
-
595
-
#define REG_DSI_TPG_MAIN_CONTROL 0x00000198
596
-
#define DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN 0x00000100
597
-
598
-
#define REG_DSI_TPG_VIDEO_CONFIG 0x000001a0
599
-
#define DSI_TPG_VIDEO_CONFIG_BPP__MASK 0x00000003
600
-
#define DSI_TPG_VIDEO_CONFIG_BPP__SHIFT 0
601
-
static inline uint32_t DSI_TPG_VIDEO_CONFIG_BPP(enum video_config_bpp val)
602
-
{
603
-
return ((val) << DSI_TPG_VIDEO_CONFIG_BPP__SHIFT) & DSI_TPG_VIDEO_CONFIG_BPP__MASK;
604
-
}
605
-
#define DSI_TPG_VIDEO_CONFIG_RGB 0x00000004
606
-
607
-
#define REG_DSI_TEST_PATTERN_GEN_CTRL 0x00000158
608
-
#define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__MASK 0x00030000
609
-
#define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__SHIFT 16
610
-
static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL(enum cmd_dma_pattern_sel val)
611
-
{
612
-
return ((val) << DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__SHIFT) & DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__MASK;
613
-
}
614
-
#define DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__MASK 0x00000300
615
-
#define DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__SHIFT 8
616
-
static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(enum cmd_mdp_stream0_pattern_sel val)
617
-
{
618
-
return ((val) << DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__SHIFT) & DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__MASK;
619
-
}
620
-
#define DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__MASK 0x00000030
621
-
#define DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__SHIFT 4
622
-
static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(enum video_pattern_sel val)
623
-
{
624
-
return ((val) << DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__SHIFT) & DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__MASK;
625
-
}
626
-
#define DSI_TEST_PATTERN_GEN_CTRL_TPG_DMA_FIFO_MODE 0x00000004
627
-
#define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_TPG_EN 0x00000002
628
-
#define DSI_TEST_PATTERN_GEN_CTRL_EN 0x00000001
629
-
630
-
#define REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0 0x00000168
631
-
632
-
#define REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER 0x00000180
633
-
#define DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER 0x00000001
634
-
635
-
#define REG_DSI_TPG_MAIN_CONTROL2 0x0000019c
636
-
#define DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN 0x00000080
637
-
#define DSI_TPG_MAIN_CONTROL2_CMD_MDP1_CHECKERED_RECTANGLE_PATTERN 0x00010000
638
-
#define DSI_TPG_MAIN_CONTROL2_CMD_MDP2_CHECKERED_RECTANGLE_PATTERN 0x02000000
639
-
640
-
#define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c
641
-
#define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001
642
-
643
-
#define REG_DSI_CMD_MODE_MDP_CTRL2 0x000001b4
644
-
#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK 0x0000000f
645
-
#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT 0
646
-
static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2(enum dsi_cmd_dst_format val)
647
-
{
648
-
return ((val) << DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK;
649
-
}
650
-
#define DSI_CMD_MODE_MDP_CTRL2_R_SEL 0x00000010
651
-
#define DSI_CMD_MODE_MDP_CTRL2_G_SEL 0x00000020
652
-
#define DSI_CMD_MODE_MDP_CTRL2_B_SEL 0x00000040
653
-
#define DSI_CMD_MODE_MDP_CTRL2_BYTE_MSB_LSB_FLIP 0x00000080
654
-
#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK 0x00000700
655
-
#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT 8
656
-
static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP(enum dsi_rgb_swap val)
657
-
{
658
-
return ((val) << DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK;
659
-
}
660
-
#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK 0x00007000
661
-
#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT 12
662
-
static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap val)
663
-
{
664
-
return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK;
665
-
}
666
-
#define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000
667
-
#define DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN 0x00100000
668
-
669
-
#define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8
670
-
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f
671
-
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT 0
672
-
static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE(uint32_t val)
673
-
{
674
-
return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK;
675
-
}
676
-
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
677
-
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT 8
678
-
static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL(uint32_t val)
679
-
{
680
-
return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK;
681
-
}
682
-
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK 0xffff0000
683
-
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT 16
684
-
static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT(uint32_t val)
685
-
{
686
-
return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK;
687
-
}
688
-
689
-
#define REG_DSI_RDBK_DATA_CTRL 0x000001d0
690
-
#define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000
691
-
#define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16
692
-
static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val)
693
-
{
694
-
return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK;
695
-
}
696
-
#define DSI_RDBK_DATA_CTRL_CLR 0x00000001
697
-
698
-
#define REG_DSI_VERSION 0x000001f0
699
-
#define DSI_VERSION_MAJOR__MASK 0xff000000
700
-
#define DSI_VERSION_MAJOR__SHIFT 24
701
-
static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
702
-
{
703
-
return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK;
704
-
}
705
-
706
-
#define REG_DSI_CPHY_MODE_CTRL 0x000002d4
707
-
708
-
#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c
709
-
#define DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__MASK 0xffff0000
710
-
#define DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__SHIFT 16
711
-
static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(uint32_t val)
712
-
{
713
-
return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__MASK;
714
-
}
715
-
#define DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__MASK 0x00003f00
716
-
#define DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__SHIFT 8
717
-
static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(uint32_t val)
718
-
{
719
-
return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__MASK;
720
-
}
721
-
#define DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__MASK 0x000000c0
722
-
#define DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__SHIFT 6
723
-
static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(uint32_t val)
724
-
{
725
-
return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__MASK;
726
-
}
727
-
#define DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__MASK 0x00000030
728
-
#define DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__SHIFT 4
729
-
static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(uint32_t val)
730
-
{
731
-
return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__MASK;
732
-
}
733
-
#define DSI_VIDEO_COMPRESSION_MODE_CTRL_EN 0x00000001
734
-
735
-
#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4
736
-
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__MASK 0x3f000000
737
-
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__SHIFT 24
738
-
static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE(uint32_t val)
739
-
{
740
-
return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__MASK;
741
-
}
742
-
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__MASK 0x00c00000
743
-
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__SHIFT 22
744
-
static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE(uint32_t val)
745
-
{
746
-
return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__MASK;
747
-
}
748
-
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__MASK 0x00300000
749
-
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__SHIFT 20
750
-
static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM(uint32_t val)
751
-
{
752
-
return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__MASK;
753
-
}
754
-
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EN 0x00010000
755
-
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__MASK 0x00003f00
756
-
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__SHIFT 8
757
-
static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(uint32_t val)
758
-
{
759
-
return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__MASK;
760
-
}
761
-
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__MASK 0x000000c0
762
-
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__SHIFT 6
763
-
static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE(uint32_t val)
764
-
{
765
-
return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__MASK;
766
-
}
767
-
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__MASK 0x00000030
768
-
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__SHIFT 4
769
-
static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM(uint32_t val)
770
-
{
771
-
return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__MASK;
772
-
}
773
-
#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EN 0x00000001
774
-
775
-
#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8
776
-
#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__MASK 0xffff0000
777
-
#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__SHIFT 16
778
-
static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH(uint32_t val)
779
-
{
780
-
return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__MASK;
781
-
}
782
-
#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK 0x0000ffff
783
-
#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__SHIFT 0
784
-
static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(uint32_t val)
785
-
{
786
-
return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK;
787
-
}
788
-
789
-
790
-
#endif /* DSI_XML */
-227
drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h
-227
drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h
···
1
-
#ifndef DSI_PHY_10NM_XML
2
-
#define DSI_PHY_10NM_XML
3
-
4
-
/* Autogenerated file, DO NOT EDIT manually!
5
-
6
-
This file was generated by the rules-ng-ng headergen tool in this git repository:
7
-
http://github.com/freedreno/envytools/
8
-
git clone https://github.com/freedreno/envytools.git
9
-
10
-
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
12
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
13
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
14
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
15
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
16
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
17
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
18
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
19
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
20
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
21
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
22
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
23
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
24
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
25
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
26
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
27
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
28
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
29
-
30
-
Copyright (C) 2013-2022 by the following authors:
31
-
- Rob Clark <robdclark@gmail.com> (robclark)
32
-
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
33
-
34
-
Permission is hereby granted, free of charge, to any person obtaining
35
-
a copy of this software and associated documentation files (the
36
-
"Software"), to deal in the Software without restriction, including
37
-
without limitation the rights to use, copy, modify, merge, publish,
38
-
distribute, sublicense, and/or sell copies of the Software, and to
39
-
permit persons to whom the Software is furnished to do so, subject to
40
-
the following conditions:
41
-
42
-
The above copyright notice and this permission notice (including the
43
-
next paragraph) shall be included in all copies or substantial
44
-
portions of the Software.
45
-
46
-
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
47
-
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
48
-
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
49
-
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
50
-
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
51
-
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
52
-
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
53
-
*/
54
-
55
-
56
-
#define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000
57
-
58
-
#define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004
59
-
60
-
#define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008
61
-
62
-
#define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c
63
-
64
-
#define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010
65
-
66
-
#define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014
67
-
68
-
#define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018
69
-
70
-
#define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c
71
-
72
-
#define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020
73
-
74
-
#define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024
75
-
76
-
#define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028
77
-
78
-
#define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c
79
-
80
-
#define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030
81
-
82
-
#define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034
83
-
84
-
#define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038
85
-
86
-
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098
87
-
88
-
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c
89
-
90
-
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0
91
-
92
-
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4
93
-
94
-
#define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8
95
-
96
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac
97
-
98
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0
99
-
100
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4
101
-
102
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8
103
-
104
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc
105
-
106
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0
107
-
108
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4
109
-
110
-
#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8
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112
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#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc
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114
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#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0
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#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4
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#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8
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#define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec
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#define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4
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-
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#define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8
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static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
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static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
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static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
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static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
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static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
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static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
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static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }
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static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
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static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; }
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static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; }
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static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; }
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static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }
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static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }
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#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
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#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
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#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
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158
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#define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c
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#define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020
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#define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024
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#define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c
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#define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030
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168
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#define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054
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#define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064
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172
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#define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c
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174
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#define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080
175
-
176
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#define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094
177
-
178
-
#define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4
179
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180
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#define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8
181
-
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#define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4
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#define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc
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186
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#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0
187
-
188
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#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4
189
-
190
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#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8
191
-
192
-
#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c
193
-
194
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#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110
195
-
196
-
#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114
197
-
198
-
#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118
199
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200
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#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c
201
-
202
-
#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120
203
-
204
-
#define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c
205
-
206
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#define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140
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208
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#define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144
209
-
210
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#define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c
211
-
212
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#define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154
213
-
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#define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c
215
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216
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#define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164
217
-
218
-
#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180
219
-
220
-
#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184
221
-
222
-
#define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c
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-
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#define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0
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-
227
-
#endif /* DSI_PHY_10NM_XML */
-309
drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h
-309
drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h
···
1
-
#ifndef DSI_PHY_14NM_XML
2
-
#define DSI_PHY_14NM_XML
3
-
4
-
/* Autogenerated file, DO NOT EDIT manually!
5
-
6
-
This file was generated by the rules-ng-ng headergen tool in this git repository:
7
-
http://github.com/freedreno/envytools/
8
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git clone https://github.com/freedreno/envytools.git
9
-
10
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The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
12
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
13
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
15
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
16
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
17
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
18
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
19
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
20
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
21
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
22
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
23
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
24
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
25
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
26
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
27
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
28
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
29
-
30
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Copyright (C) 2013-2022 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
33
-
34
-
Permission is hereby granted, free of charge, to any person obtaining
35
-
a copy of this software and associated documentation files (the
36
-
"Software"), to deal in the Software without restriction, including
37
-
without limitation the rights to use, copy, modify, merge, publish,
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-
distribute, sublicense, and/or sell copies of the Software, and to
39
-
permit persons to whom the Software is furnished to do so, subject to
40
-
the following conditions:
41
-
42
-
The above copyright notice and this permission notice (including the
43
-
next paragraph) shall be included in all copies or substantial
44
-
portions of the Software.
45
-
46
-
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
47
-
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
48
-
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
53
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*/
54
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#define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000
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#define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004
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#define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008
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#define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c
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#define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010
65
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#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0
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#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT 4
67
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static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)
68
-
{
69
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return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK;
70
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}
71
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#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0
72
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#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT 4
73
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static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)
74
-
{
75
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return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK;
76
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}
77
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78
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#define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014
79
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#define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001
80
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81
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#define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018
82
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#define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004
83
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84
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#define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c
85
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#define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020
87
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88
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#define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024
89
-
90
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#define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028
91
-
92
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#define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c
93
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94
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#define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030
95
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96
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#define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034
97
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98
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#define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038
99
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100
-
#define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c
101
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102
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#define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040
103
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104
-
#define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044
105
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106
-
#define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048
107
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#define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001
108
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109
-
#define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c
110
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#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f
111
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#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0
112
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static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)
113
-
{
114
-
return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK;
115
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}
116
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117
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static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
118
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119
-
static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
120
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#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0
121
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#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT 6
122
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static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)
123
-
{
124
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return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK;
125
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}
126
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127
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static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
128
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#define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001
129
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130
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static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
131
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132
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static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
133
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134
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static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
135
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136
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static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }
137
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138
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static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; }
139
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#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
140
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0
141
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static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)
142
-
{
143
-
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK;
144
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}
145
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146
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static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; }
147
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#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
148
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#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0
149
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static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)
150
-
{
151
-
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK;
152
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}
153
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154
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static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; }
155
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#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
156
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#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
157
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static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
158
-
{
159
-
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK;
160
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}
161
-
162
-
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; }
163
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
164
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
165
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static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
166
-
{
167
-
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK;
168
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}
169
-
170
-
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; }
171
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
172
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0
173
-
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)
174
-
{
175
-
return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK;
176
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}
177
-
178
-
static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; }
179
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007
180
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0
181
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static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)
182
-
{
183
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return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK;
184
-
}
185
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
186
-
#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT 4
187
-
static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)
188
-
{
189
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return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK;
190
-
}
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static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; }
193
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#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007
194
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#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0
195
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static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)
196
-
{
197
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return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK;
198
-
}
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static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; }
201
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#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
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#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
203
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static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
204
-
{
205
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return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK;
206
-
}
207
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208
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static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; }
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210
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static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; }
211
-
212
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static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }
213
-
214
-
#define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000
215
-
216
-
#define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004
217
-
218
-
#define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010
219
-
220
-
#define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c
221
-
222
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#define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028
223
-
224
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#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c
225
-
226
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#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030
227
-
228
-
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034
229
-
230
-
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038
231
-
232
-
#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c
233
-
234
-
#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040
235
-
236
-
#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044
237
-
238
-
#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048
239
-
240
-
#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c
241
-
242
-
#define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c
243
-
244
-
#define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058
245
-
246
-
#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c
247
-
248
-
#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070
249
-
250
-
#define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074
251
-
252
-
#define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078
253
-
254
-
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c
255
-
256
-
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080
257
-
258
-
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084
259
-
260
-
#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088
261
-
262
-
#define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c
263
-
264
-
#define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090
265
-
266
-
#define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094
267
-
268
-
#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098
269
-
270
-
#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c
271
-
272
-
#define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0
273
-
274
-
#define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4
275
-
276
-
#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8
277
-
278
-
#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac
279
-
280
-
#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4
281
-
282
-
#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8
283
-
284
-
#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc
285
-
286
-
#define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0
287
-
288
-
#define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4
289
-
290
-
#define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc
291
-
292
-
#define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8
293
-
294
-
#define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0
295
-
296
-
#define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4
297
-
298
-
#define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8
299
-
300
-
#define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc
301
-
302
-
#define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100
303
-
304
-
#define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104
305
-
306
-
#define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108
307
-
308
-
309
-
#endif /* DSI_PHY_14NM_XML */
-237
drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h
-237
drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h
···
1
-
#ifndef DSI_PHY_20NM_XML
2
-
#define DSI_PHY_20NM_XML
3
-
4
-
/* Autogenerated file, DO NOT EDIT manually!
5
-
6
-
This file was generated by the rules-ng-ng headergen tool in this git repository:
7
-
http://github.com/freedreno/envytools/
8
-
git clone https://github.com/freedreno/envytools.git
9
-
10
-
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
12
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
13
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
14
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
15
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
16
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
17
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
18
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
19
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
20
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
21
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
22
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
23
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
24
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
25
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
26
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
27
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
28
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
29
-
30
-
Copyright (C) 2013-2022 by the following authors:
31
-
- Rob Clark <robdclark@gmail.com> (robclark)
32
-
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
33
-
34
-
Permission is hereby granted, free of charge, to any person obtaining
35
-
a copy of this software and associated documentation files (the
36
-
"Software"), to deal in the Software without restriction, including
37
-
without limitation the rights to use, copy, modify, merge, publish,
38
-
distribute, sublicense, and/or sell copies of the Software, and to
39
-
permit persons to whom the Software is furnished to do so, subject to
40
-
the following conditions:
41
-
42
-
The above copyright notice and this permission notice (including the
43
-
next paragraph) shall be included in all copies or substantial
44
-
portions of the Software.
45
-
46
-
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
47
-
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
48
-
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
49
-
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
50
-
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
51
-
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
52
-
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
53
-
*/
54
-
55
-
56
-
static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
57
-
58
-
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
59
-
60
-
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
61
-
62
-
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
63
-
64
-
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
65
-
66
-
static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
67
-
68
-
static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
69
-
70
-
static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
71
-
72
-
static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
73
-
74
-
static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
75
-
76
-
#define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100
77
-
78
-
#define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104
79
-
80
-
#define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108
81
-
82
-
#define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c
83
-
84
-
#define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110
85
-
86
-
#define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114
87
-
88
-
#define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118
89
-
90
-
#define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c
91
-
92
-
#define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120
93
-
94
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140
95
-
#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
96
-
#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
97
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
98
-
{
99
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
100
-
}
101
-
102
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144
103
-
#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
104
-
#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
105
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
106
-
{
107
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
108
-
}
109
-
110
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148
111
-
#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
112
-
#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
113
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
114
-
{
115
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
116
-
}
117
-
118
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c
119
-
#define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
120
-
121
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150
122
-
#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
123
-
#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
124
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
125
-
{
126
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
127
-
}
128
-
129
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154
130
-
#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
131
-
#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
132
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
133
-
{
134
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
135
-
}
136
-
137
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158
138
-
#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
139
-
#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
140
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
141
-
{
142
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
143
-
}
144
-
145
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c
146
-
#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
147
-
#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
148
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
149
-
{
150
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
151
-
}
152
-
153
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160
154
-
#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
155
-
#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
156
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
157
-
{
158
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
159
-
}
160
-
161
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164
162
-
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
163
-
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
164
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
165
-
{
166
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
167
-
}
168
-
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
169
-
#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
170
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
171
-
{
172
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
173
-
}
174
-
175
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168
176
-
#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
177
-
#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
178
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
179
-
{
180
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
181
-
}
182
-
183
-
#define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c
184
-
#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
185
-
#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
186
-
static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
187
-
{
188
-
return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
189
-
}
190
-
191
-
#define REG_DSI_20nm_PHY_CTRL_0 0x00000170
192
-
193
-
#define REG_DSI_20nm_PHY_CTRL_1 0x00000174
194
-
195
-
#define REG_DSI_20nm_PHY_CTRL_2 0x00000178
196
-
197
-
#define REG_DSI_20nm_PHY_CTRL_3 0x0000017c
198
-
199
-
#define REG_DSI_20nm_PHY_CTRL_4 0x00000180
200
-
201
-
#define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184
202
-
203
-
#define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188
204
-
205
-
#define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4
206
-
207
-
#define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8
208
-
209
-
#define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc
210
-
211
-
#define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0
212
-
213
-
#define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4
214
-
215
-
#define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8
216
-
217
-
#define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4
218
-
#define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
219
-
220
-
#define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc
221
-
222
-
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000
223
-
224
-
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004
225
-
226
-
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008
227
-
228
-
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c
229
-
230
-
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010
231
-
232
-
#define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014
233
-
234
-
#define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
235
-
236
-
237
-
#endif /* DSI_PHY_20NM_XML */
-384
drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h
-384
drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h
···
1
-
#ifndef DSI_PHY_28NM_XML
2
-
#define DSI_PHY_28NM_XML
3
-
4
-
/* Autogenerated file, DO NOT EDIT manually!
5
-
6
-
This file was generated by the rules-ng-ng headergen tool in this git repository:
7
-
http://github.com/freedreno/envytools/
8
-
git clone https://github.com/freedreno/envytools.git
9
-
10
-
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
12
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
13
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
14
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
15
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
16
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
17
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
18
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
19
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
20
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
21
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
22
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
23
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
24
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
25
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
26
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
27
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
28
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
29
-
30
-
Copyright (C) 2013-2022 by the following authors:
31
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- Rob Clark <robdclark@gmail.com> (robclark)
32
-
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
33
-
34
-
Permission is hereby granted, free of charge, to any person obtaining
35
-
a copy of this software and associated documentation files (the
36
-
"Software"), to deal in the Software without restriction, including
37
-
without limitation the rights to use, copy, modify, merge, publish,
38
-
distribute, sublicense, and/or sell copies of the Software, and to
39
-
permit persons to whom the Software is furnished to do so, subject to
40
-
the following conditions:
41
-
42
-
The above copyright notice and this permission notice (including the
43
-
next paragraph) shall be included in all copies or substantial
44
-
portions of the Software.
45
-
46
-
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
47
-
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
48
-
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
49
-
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
50
-
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
51
-
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
52
-
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
53
-
*/
54
-
55
-
56
-
static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
57
-
58
-
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
59
-
60
-
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
61
-
62
-
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
63
-
64
-
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
65
-
66
-
static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
67
-
68
-
static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
69
-
70
-
static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
71
-
72
-
static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
73
-
74
-
static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
75
-
76
-
#define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100
77
-
78
-
#define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104
79
-
80
-
#define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108
81
-
82
-
#define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c
83
-
84
-
#define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110
85
-
86
-
#define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114
87
-
88
-
#define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118
89
-
90
-
#define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c
91
-
92
-
#define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120
93
-
94
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140
95
-
#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
96
-
#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
97
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
98
-
{
99
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
100
-
}
101
-
102
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144
103
-
#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
104
-
#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
105
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
106
-
{
107
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
108
-
}
109
-
110
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148
111
-
#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
112
-
#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
113
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
114
-
{
115
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
116
-
}
117
-
118
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c
119
-
#define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
120
-
121
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150
122
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#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
123
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#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
124
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
125
-
{
126
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return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
127
-
}
128
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129
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#define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154
130
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#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
131
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#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
132
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
133
-
{
134
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
135
-
}
136
-
137
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158
138
-
#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
139
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#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
140
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
141
-
{
142
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
143
-
}
144
-
145
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c
146
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#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
147
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#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
148
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static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
149
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{
150
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
151
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}
152
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153
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160
154
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#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
155
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#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
156
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static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
157
-
{
158
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
159
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}
160
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161
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#define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164
162
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#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
163
-
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
164
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
165
-
{
166
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
167
-
}
168
-
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
169
-
#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
170
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
171
-
{
172
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
173
-
}
174
-
175
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168
176
-
#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
177
-
#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
178
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
179
-
{
180
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
181
-
}
182
-
183
-
#define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c
184
-
#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
185
-
#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
186
-
static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
187
-
{
188
-
return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
189
-
}
190
-
191
-
#define REG_DSI_28nm_PHY_CTRL_0 0x00000170
192
-
193
-
#define REG_DSI_28nm_PHY_CTRL_1 0x00000174
194
-
195
-
#define REG_DSI_28nm_PHY_CTRL_2 0x00000178
196
-
197
-
#define REG_DSI_28nm_PHY_CTRL_3 0x0000017c
198
-
199
-
#define REG_DSI_28nm_PHY_CTRL_4 0x00000180
200
-
201
-
#define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184
202
-
203
-
#define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188
204
-
205
-
#define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4
206
-
207
-
#define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8
208
-
209
-
#define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc
210
-
211
-
#define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0
212
-
213
-
#define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4
214
-
215
-
#define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8
216
-
217
-
#define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4
218
-
#define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
219
-
220
-
#define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc
221
-
222
-
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000
223
-
224
-
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004
225
-
226
-
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008
227
-
228
-
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c
229
-
230
-
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010
231
-
232
-
#define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014
233
-
234
-
#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
235
-
236
-
#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
237
-
#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001
238
-
239
-
#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
240
-
241
-
#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
242
-
243
-
#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
244
-
245
-
#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010
246
-
#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002
247
-
248
-
#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
249
-
250
-
#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018
251
-
252
-
#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
253
-
254
-
#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020
255
-
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
256
-
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
257
-
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
258
-
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
259
-
260
-
#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
261
-
262
-
#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
263
-
264
-
#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
265
-
266
-
#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
267
-
268
-
#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
269
-
270
-
#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038
271
-
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f
272
-
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0
273
-
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
274
-
{
275
-
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK;
276
-
}
277
-
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040
278
-
279
-
#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
280
-
#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f
281
-
#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0
282
-
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
283
-
{
284
-
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
285
-
}
286
-
#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040
287
-
#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6
288
-
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
289
-
{
290
-
return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK;
291
-
}
292
-
293
-
#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040
294
-
#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff
295
-
#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0
296
-
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
297
-
{
298
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return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK;
299
-
}
300
-
301
-
#define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044
302
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#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff
303
-
#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0
304
-
static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
305
-
{
306
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return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK;
307
-
}
308
-
309
-
#define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048
310
-
311
-
#define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
312
-
313
-
#define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050
314
-
315
-
#define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054
316
-
317
-
#define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058
318
-
319
-
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
320
-
321
-
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
322
-
323
-
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
324
-
325
-
#define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068
326
-
#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
327
-
328
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
329
-
330
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070
331
-
332
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074
333
-
334
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078
335
-
336
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
337
-
338
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080
339
-
340
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084
341
-
342
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088
343
-
344
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
345
-
346
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090
347
-
348
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094
349
-
350
-
#define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098
351
-
352
-
#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
353
-
354
-
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
355
-
356
-
#define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4
357
-
358
-
#define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8
359
-
360
-
#define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac
361
-
362
-
#define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0
363
-
364
-
#define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4
365
-
366
-
#define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8
367
-
368
-
#define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc
369
-
370
-
#define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0
371
-
#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001
372
-
373
-
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4
374
-
375
-
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8
376
-
377
-
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc
378
-
379
-
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0
380
-
381
-
#define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4
382
-
383
-
384
-
#endif /* DSI_PHY_28NM_XML */
-286
drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h
-286
drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h
···
1
-
#ifndef DSI_PHY_28NM_8960_XML
2
-
#define DSI_PHY_28NM_8960_XML
3
-
4
-
/* Autogenerated file, DO NOT EDIT manually!
5
-
6
-
This file was generated by the rules-ng-ng headergen tool in this git repository:
7
-
http://github.com/freedreno/envytools/
8
-
git clone https://github.com/freedreno/envytools.git
9
-
10
-
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
12
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
13
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
14
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
15
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
16
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
17
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
18
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
19
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
20
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
21
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
22
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
23
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
24
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
25
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
26
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
27
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
28
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
29
-
30
-
Copyright (C) 2013-2022 by the following authors:
31
-
- Rob Clark <robdclark@gmail.com> (robclark)
32
-
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
33
-
34
-
Permission is hereby granted, free of charge, to any person obtaining
35
-
a copy of this software and associated documentation files (the
36
-
"Software"), to deal in the Software without restriction, including
37
-
without limitation the rights to use, copy, modify, merge, publish,
38
-
distribute, sublicense, and/or sell copies of the Software, and to
39
-
permit persons to whom the Software is furnished to do so, subject to
40
-
the following conditions:
41
-
42
-
The above copyright notice and this permission notice (including the
43
-
next paragraph) shall be included in all copies or substantial
44
-
portions of the Software.
45
-
46
-
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
47
-
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
48
-
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
49
-
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
50
-
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
51
-
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
52
-
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
53
-
*/
54
-
55
-
56
-
static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
57
-
58
-
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
59
-
60
-
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
61
-
62
-
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
63
-
64
-
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; }
65
-
66
-
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; }
67
-
68
-
static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; }
69
-
70
-
#define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
71
-
72
-
#define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
73
-
74
-
#define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
75
-
76
-
#define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c
77
-
78
-
#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114
79
-
80
-
#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118
81
-
82
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140
83
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
84
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
85
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
86
-
{
87
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
88
-
}
89
-
90
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144
91
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
92
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
93
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
94
-
{
95
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
96
-
}
97
-
98
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148
99
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
100
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
101
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
102
-
{
103
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
104
-
}
105
-
106
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c
107
-
108
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150
109
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
110
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
111
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
112
-
{
113
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
114
-
}
115
-
116
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154
117
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
118
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
119
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
120
-
{
121
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
122
-
}
123
-
124
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158
125
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
126
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
127
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
128
-
{
129
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
130
-
}
131
-
132
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c
133
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
134
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
135
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
136
-
{
137
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
138
-
}
139
-
140
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160
141
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
142
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
143
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
144
-
{
145
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK;
146
-
}
147
-
148
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164
149
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
150
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
151
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
152
-
{
153
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK;
154
-
}
155
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
156
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
157
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
158
-
{
159
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK;
160
-
}
161
-
162
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168
163
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
164
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
165
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
166
-
{
167
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK;
168
-
}
169
-
170
-
#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c
171
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
172
-
#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
173
-
static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
174
-
{
175
-
return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
176
-
}
177
-
178
-
#define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170
179
-
180
-
#define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174
181
-
182
-
#define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178
183
-
184
-
#define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c
185
-
186
-
#define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180
187
-
188
-
#define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184
189
-
190
-
#define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188
191
-
192
-
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c
193
-
194
-
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190
195
-
196
-
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194
197
-
198
-
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198
199
-
200
-
#define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c
201
-
202
-
#define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0
203
-
204
-
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000
205
-
206
-
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004
207
-
208
-
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008
209
-
210
-
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c
211
-
212
-
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010
213
-
214
-
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014
215
-
216
-
#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018
217
-
218
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#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028
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#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c
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#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030
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#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034
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#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038
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#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c
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#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040
231
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#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044
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#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048
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#define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050
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#define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000
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#define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001
241
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004
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244
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008
245
-
246
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c
247
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248
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010
249
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250
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014
251
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252
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018
253
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254
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c
255
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256
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020
257
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258
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024
259
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260
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028
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262
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c
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264
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030
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266
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034
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268
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038
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270
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c
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272
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048
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278
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c
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280
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#define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050
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282
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#define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080
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#define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001
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285
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#endif /* DSI_PHY_28NM_8960_XML */
-483
drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h
-483
drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h
···
1
-
#ifndef DSI_PHY_7NM_XML
2
-
#define DSI_PHY_7NM_XML
3
-
4
-
/* Autogenerated file, DO NOT EDIT manually!
5
-
6
-
This file was generated by the rules-ng-ng headergen tool in this git repository:
7
-
http://github.com/freedreno/envytools/
8
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git clone https://github.com/freedreno/envytools.git
9
-
10
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The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
12
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
13
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
14
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
15
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
16
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
17
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
18
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
19
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
20
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
21
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
22
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
23
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
24
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
25
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
26
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
27
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
28
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- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
29
-
30
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Copyright (C) 2013-2022 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
32
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
33
-
34
-
Permission is hereby granted, free of charge, to any person obtaining
35
-
a copy of this software and associated documentation files (the
36
-
"Software"), to deal in the Software without restriction, including
37
-
without limitation the rights to use, copy, modify, merge, publish,
38
-
distribute, sublicense, and/or sell copies of the Software, and to
39
-
permit persons to whom the Software is furnished to do so, subject to
40
-
the following conditions:
41
-
42
-
The above copyright notice and this permission notice (including the
43
-
next paragraph) shall be included in all copies or substantial
44
-
portions of the Software.
45
-
46
-
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
47
-
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
48
-
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
49
-
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
50
-
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
53
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*/
54
-
55
-
56
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#define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000
57
-
58
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#define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004
59
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60
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#define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008
61
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62
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#define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c
63
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64
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#define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010
65
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66
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#define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014
67
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68
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#define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018
69
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70
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#define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c
71
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72
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#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020
73
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74
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#define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024
75
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76
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#define REG_DSI_7nm_PHY_CMN_CTRL_1 0x00000028
77
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78
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#define REG_DSI_7nm_PHY_CMN_CTRL_2 0x0000002c
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80
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#define REG_DSI_7nm_PHY_CMN_CTRL_3 0x00000030
81
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82
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#define REG_DSI_7nm_PHY_CMN_LANE_CFG0 0x00000034
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84
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#define REG_DSI_7nm_PHY_CMN_LANE_CFG1 0x00000038
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86
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#define REG_DSI_7nm_PHY_CMN_PLL_CNTRL 0x0000003c
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#define REG_DSI_7nm_PHY_CMN_DPHY_SOT 0x00000040
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#define REG_DSI_7nm_PHY_CMN_LANE_CTRL0 0x000000a0
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#define REG_DSI_7nm_PHY_CMN_LANE_CTRL1 0x000000a4
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#define REG_DSI_7nm_PHY_CMN_LANE_CTRL2 0x000000a8
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#define REG_DSI_7nm_PHY_CMN_LANE_CTRL3 0x000000ac
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#define REG_DSI_7nm_PHY_CMN_LANE_CTRL4 0x000000b0
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#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0 0x000000b4
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#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1 0x000000b8
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#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2 0x000000bc
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#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 0x000000c0
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#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4 0x000000c4
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#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 0x000000c8
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#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6 0x000000cc
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#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7 0x000000d0
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#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8 0x000000d4
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#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9 0x000000d8
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#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10 0x000000dc
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#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11 0x000000e0
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#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12 0x000000e4
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#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13 0x000000e8
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#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec
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#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0
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#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4
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#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8
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#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc
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#define REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100
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#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104
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#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108
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#define REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c
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#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_1 0x00000110
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#define REG_DSI_7nm_PHY_CMN_CTRL_4 0x00000114
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#define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4 0x00000128
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#define REG_DSI_7nm_PHY_CMN_PHY_STATUS 0x00000140
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#define REG_DSI_7nm_PHY_CMN_LANE_STATUS0 0x00000148
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#define REG_DSI_7nm_PHY_CMN_LANE_STATUS1 0x0000014c
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#define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10 0x000001ac
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static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
161
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162
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static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
163
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static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
165
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static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
167
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static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; }
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static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }
171
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static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }
173
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static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
175
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#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
177
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#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
179
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#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008
181
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#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c
183
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#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
185
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186
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#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014
187
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188
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#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018
189
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#define REG_DSI_7nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c
191
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192
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#define REG_DSI_7nm_PHY_PLL_DSM_DIVIDER 0x00000020
193
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194
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#define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024
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196
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#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES 0x00000028
197
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198
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#define REG_DSI_7nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c
199
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200
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#define REG_DSI_7nm_PHY_PLL_CMODE 0x00000030
201
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202
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#define REG_DSI_7nm_PHY_PLL_PSM_CTRL 0x00000034
203
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204
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#define REG_DSI_7nm_PHY_PLL_RSM_CTRL 0x00000038
205
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206
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#define REG_DSI_7nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c
207
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208
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#define REG_DSI_7nm_PHY_PLL_PLL_CNTRL 0x00000040
209
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210
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#define REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044
211
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212
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#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048
213
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214
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#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c
215
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216
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#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050
217
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218
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#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MIN 0x00000054
219
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#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MAX 0x00000058
221
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#define REG_DSI_7nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c
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#define REG_DSI_7nm_PHY_PLL_BAND_SEL_IFILT 0x00000060
225
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#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064
227
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228
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#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068
229
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230
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#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c
231
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232
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#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070
233
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234
-
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074
235
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236
-
#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078
237
-
238
-
#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c
239
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240
-
#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080
241
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242
-
#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084
243
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244
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#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088
245
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246
-
#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c
247
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248
-
#define REG_DSI_7nm_PHY_PLL_PFILT 0x00000090
249
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250
-
#define REG_DSI_7nm_PHY_PLL_IFILT 0x00000094
251
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252
-
#define REG_DSI_7nm_PHY_PLL_PLL_GAIN 0x00000098
253
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254
-
#define REG_DSI_7nm_PHY_PLL_ICODE_LOW 0x0000009c
255
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256
-
#define REG_DSI_7nm_PHY_PLL_ICODE_HIGH 0x000000a0
257
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258
-
#define REG_DSI_7nm_PHY_PLL_LOCKDET 0x000000a4
259
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260
-
#define REG_DSI_7nm_PHY_PLL_OUTDIV 0x000000a8
261
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262
-
#define REG_DSI_7nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac
263
-
264
-
#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0
265
-
266
-
#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4
267
-
268
-
#define REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE 0x000000b8
269
-
270
-
#define REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc
271
-
272
-
#define REG_DSI_7nm_PHY_PLL_RATE_CHANGE 0x000000c0
273
-
274
-
#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4
275
-
276
-
#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8
277
-
278
-
#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc
279
-
280
-
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0
281
-
282
-
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4
283
-
284
-
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8
285
-
286
-
#define REG_DSI_7nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc
287
-
288
-
#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0
289
-
290
-
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4
291
-
292
-
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8
293
-
294
-
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec
295
-
296
-
#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0
297
-
298
-
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4
299
-
300
-
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8
301
-
302
-
#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc
303
-
304
-
#define REG_DSI_7nm_PHY_PLL_MASH_CONTROL 0x00000100
305
-
306
-
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104
307
-
308
-
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108
309
-
310
-
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c
311
-
312
-
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110
313
-
314
-
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114
315
-
316
-
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118
317
-
318
-
#define REG_DSI_7nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c
319
-
320
-
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120
321
-
322
-
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124
323
-
324
-
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128
325
-
326
-
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c
327
-
328
-
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130
329
-
330
-
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134
331
-
332
-
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138
333
-
334
-
#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c
335
-
336
-
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140
337
-
338
-
#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144
339
-
340
-
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148
341
-
342
-
#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c
343
-
344
-
#define REG_DSI_7nm_PHY_PLL_SSC_CONTROL 0x00000150
345
-
346
-
#define REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154
347
-
348
-
#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158
349
-
350
-
#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c
351
-
352
-
#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160
353
-
354
-
#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164
355
-
356
-
#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168
357
-
358
-
#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c
359
-
360
-
#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170
361
-
362
-
#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174
363
-
364
-
#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178
365
-
366
-
#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c
367
-
368
-
#define REG_DSI_7nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180
369
-
370
-
#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184
371
-
372
-
#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188
373
-
374
-
#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c
375
-
376
-
#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190
377
-
378
-
#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194
379
-
380
-
#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198
381
-
382
-
#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c
383
-
384
-
#define REG_DSI_7nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0
385
-
386
-
#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4
387
-
388
-
#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8
389
-
390
-
#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac
391
-
392
-
#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0
393
-
394
-
#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4
395
-
396
-
#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL 0x000001b8
397
-
398
-
#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc
399
-
400
-
#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0
401
-
402
-
#define REG_DSI_7nm_PHY_PLL_FD_OUT_LOW 0x000001c4
403
-
404
-
#define REG_DSI_7nm_PHY_PLL_FD_OUT_HIGH 0x000001c8
405
-
406
-
#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc
407
-
408
-
#define REG_DSI_7nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0
409
-
410
-
#define REG_DSI_7nm_PHY_PLL_FLL_CONFIG 0x000001d4
411
-
412
-
#define REG_DSI_7nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8
413
-
414
-
#define REG_DSI_7nm_PHY_PLL_FLL_CODE0 0x000001dc
415
-
416
-
#define REG_DSI_7nm_PHY_PLL_FLL_CODE1 0x000001e0
417
-
418
-
#define REG_DSI_7nm_PHY_PLL_FLL_GAIN0 0x000001e4
419
-
420
-
#define REG_DSI_7nm_PHY_PLL_FLL_GAIN1 0x000001e8
421
-
422
-
#define REG_DSI_7nm_PHY_PLL_SW_RESET 0x000001ec
423
-
424
-
#define REG_DSI_7nm_PHY_PLL_FAST_PWRUP 0x000001f0
425
-
426
-
#define REG_DSI_7nm_PHY_PLL_LOCKTIME0 0x000001f4
427
-
428
-
#define REG_DSI_7nm_PHY_PLL_LOCKTIME1 0x000001f8
429
-
430
-
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc
431
-
432
-
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS0 0x00000200
433
-
434
-
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS1 0x00000204
435
-
436
-
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS2 0x00000208
437
-
438
-
#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS3 0x0000020c
439
-
440
-
#define REG_DSI_7nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210
441
-
442
-
#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG 0x00000214
443
-
444
-
#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218
445
-
446
-
#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c
447
-
448
-
#define REG_DSI_7nm_PHY_PLL_RESET_SM_STATUS 0x00000220
449
-
450
-
#define REG_DSI_7nm_PHY_PLL_TDC_OFFSET 0x00000224
451
-
452
-
#define REG_DSI_7nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228
453
-
454
-
#define REG_DSI_7nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c
455
-
456
-
#define REG_DSI_7nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230
457
-
458
-
#define REG_DSI_7nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234
459
-
460
-
#define REG_DSI_7nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238
461
-
462
-
#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c
463
-
464
-
#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1 0x00000240
465
-
466
-
#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_2 0x00000244
467
-
468
-
#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248
469
-
470
-
#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c
471
-
472
-
#define REG_DSI_7nm_PHY_PLL_CMODE_1 0x00000250
473
-
474
-
#define REG_DSI_7nm_PHY_PLL_CMODE_2 0x00000254
475
-
476
-
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258
477
-
478
-
#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c
479
-
480
-
#define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE 0x00000260
481
-
482
-
483
-
#endif /* DSI_PHY_7NM_XML */
-70
drivers/gpu/drm/msm/dsi/sfpb.xml.h
-70
drivers/gpu/drm/msm/dsi/sfpb.xml.h
···
1
-
#ifndef SFPB_XML
2
-
#define SFPB_XML
3
-
4
-
/* Autogenerated file, DO NOT EDIT manually!
5
-
6
-
This file was generated by the rules-ng-ng headergen tool in this git repository:
7
-
http://github.com/freedreno/envytools/
8
-
git clone https://github.com/freedreno/envytools.git
9
-
10
-
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
12
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
13
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
14
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
15
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
16
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
17
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
18
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
19
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
20
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
21
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
22
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
23
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
24
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
25
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
26
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
27
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
28
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
29
-
30
-
Copyright (C) 2013-2022 by the following authors:
31
-
- Rob Clark <robdclark@gmail.com> (robclark)
32
-
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
33
-
34
-
Permission is hereby granted, free of charge, to any person obtaining
35
-
a copy of this software and associated documentation files (the
36
-
"Software"), to deal in the Software without restriction, including
37
-
without limitation the rights to use, copy, modify, merge, publish,
38
-
distribute, sublicense, and/or sell copies of the Software, and to
39
-
permit persons to whom the Software is furnished to do so, subject to
40
-
the following conditions:
41
-
42
-
The above copyright notice and this permission notice (including the
43
-
next paragraph) shall be included in all copies or substantial
44
-
portions of the Software.
45
-
46
-
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
47
-
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
48
-
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
49
-
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
50
-
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
51
-
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
52
-
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
53
-
*/
54
-
55
-
56
-
enum sfpb_ahb_arb_master_port_en {
57
-
SFPB_MASTER_PORT_ENABLE = 3,
58
-
SFPB_MASTER_PORT_DISABLE = 0,
59
-
};
60
-
61
-
#define REG_SFPB_GPREG 0x00000058
62
-
#define SFPB_GPREG_MASTER_PORT_EN__MASK 0x00001800
63
-
#define SFPB_GPREG_MASTER_PORT_EN__SHIFT 11
64
-
static inline uint32_t SFPB_GPREG_MASTER_PORT_EN(enum sfpb_ahb_arb_master_port_en val)
65
-
{
66
-
return ((val) << SFPB_GPREG_MASTER_PORT_EN__SHIFT) & SFPB_GPREG_MASTER_PORT_EN__MASK;
67
-
}
68
-
69
-
70
-
#endif /* SFPB_XML */
-1399
drivers/gpu/drm/msm/hdmi/hdmi.xml.h
-1399
drivers/gpu/drm/msm/hdmi/hdmi.xml.h
···
1
-
#ifndef HDMI_XML
2
-
#define HDMI_XML
3
-
4
-
/* Autogenerated file, DO NOT EDIT manually!
5
-
6
-
This file was generated by the rules-ng-ng headergen tool in this git repository:
7
-
http://github.com/freedreno/envytools/
8
-
git clone https://github.com/freedreno/envytools.git
9
-
10
-
The rules-ng-ng source files this header was generated from are:
11
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
12
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
13
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
14
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
15
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
16
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
17
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
18
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
19
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
20
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
21
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
22
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
23
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
24
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
25
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
26
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
27
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
28
-
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
29
-
30
-
Copyright (C) 2013-2022 by the following authors:
31
-
- Rob Clark <robdclark@gmail.com> (robclark)
32
-
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
33
-
34
-
Permission is hereby granted, free of charge, to any person obtaining
35
-
a copy of this software and associated documentation files (the
36
-
"Software"), to deal in the Software without restriction, including
37
-
without limitation the rights to use, copy, modify, merge, publish,
38
-
distribute, sublicense, and/or sell copies of the Software, and to
39
-
permit persons to whom the Software is furnished to do so, subject to
40
-
the following conditions:
41
-
42
-
The above copyright notice and this permission notice (including the
43
-
next paragraph) shall be included in all copies or substantial
44
-
portions of the Software.
45
-
46
-
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
47
-
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
48
-
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
49
-
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
50
-
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
51
-
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
52
-
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
53
-
*/
54
-
55
-
56
-
enum hdmi_hdcp_key_state {
57
-
HDCP_KEYS_STATE_NO_KEYS = 0,
58
-
HDCP_KEYS_STATE_NOT_CHECKED = 1,
59
-
HDCP_KEYS_STATE_CHECKING = 2,
60
-
HDCP_KEYS_STATE_VALID = 3,
61
-
HDCP_KEYS_STATE_AKSV_NOT_VALID = 4,
62
-
HDCP_KEYS_STATE_CHKSUM_MISMATCH = 5,
63
-
HDCP_KEYS_STATE_PROD_AKSV = 6,
64
-
HDCP_KEYS_STATE_RESERVED = 7,
65
-
};
66
-
67
-
enum hdmi_ddc_read_write {
68
-
DDC_WRITE = 0,
69
-
DDC_READ = 1,
70
-
};
71
-
72
-
enum hdmi_acr_cts {
73
-
ACR_NONE = 0,
74
-
ACR_32 = 1,
75
-
ACR_44 = 2,
76
-
ACR_48 = 3,
77
-
};
78
-
79
-
#define REG_HDMI_CTRL 0x00000000
80
-
#define HDMI_CTRL_ENABLE 0x00000001
81
-
#define HDMI_CTRL_HDMI 0x00000002
82
-
#define HDMI_CTRL_ENCRYPTED 0x00000004
83
-
84
-
#define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
85
-
#define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
86
-
87
-
#define REG_HDMI_ACR_PKT_CTRL 0x00000024
88
-
#define HDMI_ACR_PKT_CTRL_CONT 0x00000001
89
-
#define HDMI_ACR_PKT_CTRL_SEND 0x00000002
90
-
#define HDMI_ACR_PKT_CTRL_SELECT__MASK 0x00000030
91
-
#define HDMI_ACR_PKT_CTRL_SELECT__SHIFT 4
92
-
static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val)
93
-
{
94
-
return ((val) << HDMI_ACR_PKT_CTRL_SELECT__SHIFT) & HDMI_ACR_PKT_CTRL_SELECT__MASK;
95
-
}
96
-
#define HDMI_ACR_PKT_CTRL_SOURCE 0x00000100
97
-
#define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK 0x00070000
98
-
#define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT 16
99
-
static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val)
100
-
{
101
-
return ((val) << HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT) & HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK;
102
-
}
103
-
#define HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY 0x80000000
104
-
105
-
#define REG_HDMI_VBI_PKT_CTRL 0x00000028
106
-
#define HDMI_VBI_PKT_CTRL_GC_ENABLE 0x00000010
107
-
#define HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME 0x00000020
108
-
#define HDMI_VBI_PKT_CTRL_ISRC_SEND 0x00000100
109
-
#define HDMI_VBI_PKT_CTRL_ISRC_CONTINUOUS 0x00000200
110
-
#define HDMI_VBI_PKT_CTRL_ACP_SEND 0x00001000
111
-
#define HDMI_VBI_PKT_CTRL_ACP_SRC_SW 0x00002000
112
-
113
-
#define REG_HDMI_INFOFRAME_CTRL0 0x0000002c
114
-
#define HDMI_INFOFRAME_CTRL0_AVI_SEND 0x00000001
115
-
#define HDMI_INFOFRAME_CTRL0_AVI_CONT 0x00000002
116
-
#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND 0x00000010
117
-
#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT 0x00000020
118
-
#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE 0x00000040
119
-
#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE 0x00000080
120
-
121
-
#define REG_HDMI_INFOFRAME_CTRL1 0x00000030
122
-
#define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK 0x0000003f
123
-
#define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT 0
124
-
static inline uint32_t HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(uint32_t val)
125
-
{
126
-
return ((val) << HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK;
127
-
}
128
-
#define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK 0x00003f00
129
-
#define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT 8
130
-
static inline uint32_t HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE(uint32_t val)
131
-
{
132
-
return ((val) << HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK;
133
-
}
134
-
#define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK 0x003f0000
135
-
#define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT 16
136
-
static inline uint32_t HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE(uint32_t val)
137
-
{
138
-
return ((val) << HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK;
139
-
}
140
-
#define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK 0x3f000000
141
-
#define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT 24
142
-
static inline uint32_t HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE(uint32_t val)
143
-
{
144
-
return ((val) << HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK;
145
-
}
146
-
147
-
#define REG_HDMI_GEN_PKT_CTRL 0x00000034
148
-
#define HDMI_GEN_PKT_CTRL_GENERIC0_SEND 0x00000001
149
-
#define HDMI_GEN_PKT_CTRL_GENERIC0_CONT 0x00000002
150
-
#define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK 0x0000000c
151
-
#define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT 2
152
-
static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val)
153
-
{
154
-
return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK;
155
-
}
156
-
#define HDMI_GEN_PKT_CTRL_GENERIC1_SEND 0x00000010
157
-
#define HDMI_GEN_PKT_CTRL_GENERIC1_CONT 0x00000020
158
-
#define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK 0x003f0000
159
-
#define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT 16
160
-
static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val)
161
-
{
162
-
return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK;
163
-
}
164
-
#define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK 0x3f000000
165
-
#define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT 24
166
-
static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val)
167
-
{
168
-
return ((val) << HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK;
169
-
}
170
-
171
-
#define REG_HDMI_GC 0x00000040
172
-
#define HDMI_GC_MUTE 0x00000001
173
-
174
-
#define REG_HDMI_AUDIO_PKT_CTRL2 0x00000044
175
-
#define HDMI_AUDIO_PKT_CTRL2_OVERRIDE 0x00000001
176
-
#define HDMI_AUDIO_PKT_CTRL2_LAYOUT 0x00000002
177
-
178
-
static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; }
179
-
180
-
#define REG_HDMI_GENERIC0_HDR 0x00000084
181
-
182
-
static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; }
183
-
184
-
#define REG_HDMI_GENERIC1_HDR 0x000000a4
185
-
186
-
static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; }
187
-
188
-
static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
189
-
190
-
static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
191
-
#define HDMI_ACR_0_CTS__MASK 0xfffff000
192
-
#define HDMI_ACR_0_CTS__SHIFT 12
193
-
static inline uint32_t HDMI_ACR_0_CTS(uint32_t val)
194
-
{
195
-
return ((val) << HDMI_ACR_0_CTS__SHIFT) & HDMI_ACR_0_CTS__MASK;
196
-
}
197
-
198
-
static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; }
199
-
#define HDMI_ACR_1_N__MASK 0xffffffff
200
-
#define HDMI_ACR_1_N__SHIFT 0
201
-
static inline uint32_t HDMI_ACR_1_N(uint32_t val)
202
-
{
203
-
return ((val) << HDMI_ACR_1_N__SHIFT) & HDMI_ACR_1_N__MASK;
204
-
}
205
-
206
-
#define REG_HDMI_AUDIO_INFO0 0x000000e4
207
-
#define HDMI_AUDIO_INFO0_CHECKSUM__MASK 0x000000ff
208
-
#define HDMI_AUDIO_INFO0_CHECKSUM__SHIFT 0
209
-
static inline uint32_t HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val)
210
-
{
211
-
return ((val) << HDMI_AUDIO_INFO0_CHECKSUM__SHIFT) & HDMI_AUDIO_INFO0_CHECKSUM__MASK;
212
-
}
213
-
#define HDMI_AUDIO_INFO0_CC__MASK 0x00000700
214
-
#define HDMI_AUDIO_INFO0_CC__SHIFT 8
215
-
static inline uint32_t HDMI_AUDIO_INFO0_CC(uint32_t val)
216
-
{
217
-
return ((val) << HDMI_AUDIO_INFO0_CC__SHIFT) & HDMI_AUDIO_INFO0_CC__MASK;
218
-
}
219
-
220
-
#define REG_HDMI_AUDIO_INFO1 0x000000e8
221
-
#define HDMI_AUDIO_INFO1_CA__MASK 0x000000ff
222
-
#define HDMI_AUDIO_INFO1_CA__SHIFT 0
223
-
static inline uint32_t HDMI_AUDIO_INFO1_CA(uint32_t val)
224
-
{
225
-
return ((val) << HDMI_AUDIO_INFO1_CA__SHIFT) & HDMI_AUDIO_INFO1_CA__MASK;
226
-
}
227
-
#define HDMI_AUDIO_INFO1_LSV__MASK 0x00007800
228
-
#define HDMI_AUDIO_INFO1_LSV__SHIFT 11
229
-
static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val)
230
-
{
231
-
return ((val) << HDMI_AUDIO_INFO1_LSV__SHIFT) & HDMI_AUDIO_INFO1_LSV__MASK;
232
-
}
233
-
#define HDMI_AUDIO_INFO1_DM_INH 0x00008000
234
-
235
-
#define REG_HDMI_HDCP_CTRL 0x00000110
236
-
#define HDMI_HDCP_CTRL_ENABLE 0x00000001
237
-
#define HDMI_HDCP_CTRL_ENCRYPTION_ENABLE 0x00000100
238
-
239
-
#define REG_HDMI_HDCP_DEBUG_CTRL 0x00000114
240
-
#define HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER 0x00000004
241
-
242
-
#define REG_HDMI_HDCP_INT_CTRL 0x00000118
243
-
#define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT 0x00000001
244
-
#define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_ACK 0x00000002
245
-
#define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_MASK 0x00000004
246
-
#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT 0x00000010
247
-
#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_ACK 0x00000020
248
-
#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_MASK 0x00000040
249
-
#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK 0x00000080
250
-
#define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_INT 0x00000100
251
-
#define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_ACK 0x00000200
252
-
#define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_MASK 0x00000400
253
-
#define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_INT 0x00001000
254
-
#define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_ACK 0x00002000
255
-
#define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_MASK 0x00004000
256
-
257
-
#define REG_HDMI_HDCP_LINK0_STATUS 0x0000011c
258
-
#define HDMI_HDCP_LINK0_STATUS_AN_0_READY 0x00000100
259
-
#define HDMI_HDCP_LINK0_STATUS_AN_1_READY 0x00000200
260
-
#define HDMI_HDCP_LINK0_STATUS_RI_MATCHES 0x00001000
261
-
#define HDMI_HDCP_LINK0_STATUS_V_MATCHES 0x00100000
262
-
#define HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK 0x70000000
263
-
#define HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT 28
264
-
static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val)
265
-
{
266
-
return ((val) << HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT) & HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK;
267
-
}
268
-
269
-
#define REG_HDMI_HDCP_DDC_CTRL_0 0x00000120
270
-
#define HDMI_HDCP_DDC_CTRL_0_DISABLE 0x00000001
271
-
272
-
#define REG_HDMI_HDCP_DDC_CTRL_1 0x00000124
273
-
#define HDMI_HDCP_DDC_CTRL_1_FAILED_ACK 0x00000001
274
-
275
-
#define REG_HDMI_HDCP_DDC_STATUS 0x00000128
276
-
#define HDMI_HDCP_DDC_STATUS_XFER_REQ 0x00000010
277
-
#define HDMI_HDCP_DDC_STATUS_XFER_DONE 0x00000400
278
-
#define HDMI_HDCP_DDC_STATUS_ABORTED 0x00001000
279
-
#define HDMI_HDCP_DDC_STATUS_TIMEOUT 0x00002000
280
-
#define HDMI_HDCP_DDC_STATUS_NACK0 0x00004000
281
-
#define HDMI_HDCP_DDC_STATUS_NACK1 0x00008000
282
-
#define HDMI_HDCP_DDC_STATUS_FAILED 0x00010000
283
-
284
-
#define REG_HDMI_HDCP_ENTROPY_CTRL0 0x0000012c
285
-
286
-
#define REG_HDMI_HDCP_ENTROPY_CTRL1 0x0000025c
287
-
288
-
#define REG_HDMI_HDCP_RESET 0x00000130
289
-
#define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE 0x00000001
290
-
291
-
#define REG_HDMI_HDCP_RCVPORT_DATA0 0x00000134
292
-
293
-
#define REG_HDMI_HDCP_RCVPORT_DATA1 0x00000138
294
-
295
-
#define REG_HDMI_HDCP_RCVPORT_DATA2_0 0x0000013c
296
-
297
-
#define REG_HDMI_HDCP_RCVPORT_DATA2_1 0x00000140
298
-
299
-
#define REG_HDMI_HDCP_RCVPORT_DATA3 0x00000144
300
-
301
-
#define REG_HDMI_HDCP_RCVPORT_DATA4 0x00000148
302
-
303
-
#define REG_HDMI_HDCP_RCVPORT_DATA5 0x0000014c
304
-
305
-
#define REG_HDMI_HDCP_RCVPORT_DATA6 0x00000150
306
-
307
-
#define REG_HDMI_HDCP_RCVPORT_DATA7 0x00000154
308
-
309
-
#define REG_HDMI_HDCP_RCVPORT_DATA8 0x00000158
310
-
311
-
#define REG_HDMI_HDCP_RCVPORT_DATA9 0x0000015c
312
-
313
-
#define REG_HDMI_HDCP_RCVPORT_DATA10 0x00000160
314
-
315
-
#define REG_HDMI_HDCP_RCVPORT_DATA11 0x00000164
316
-
317
-
#define REG_HDMI_HDCP_RCVPORT_DATA12 0x00000168
318
-
319
-
#define REG_HDMI_VENSPEC_INFO0 0x0000016c
320
-
321
-
#define REG_HDMI_VENSPEC_INFO1 0x00000170
322
-
323
-
#define REG_HDMI_VENSPEC_INFO2 0x00000174
324
-
325
-
#define REG_HDMI_VENSPEC_INFO3 0x00000178
326
-
327
-
#define REG_HDMI_VENSPEC_INFO4 0x0000017c
328
-
329
-
#define REG_HDMI_VENSPEC_INFO5 0x00000180
330
-
331
-
#define REG_HDMI_VENSPEC_INFO6 0x00000184
332
-
333
-
#define REG_HDMI_AUDIO_CFG 0x000001d0
334
-
#define HDMI_AUDIO_CFG_ENGINE_ENABLE 0x00000001
335
-
#define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK 0x000000f0
336
-
#define HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT 4
337
-
static inline uint32_t HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val)
338
-
{
339
-
return ((val) << HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT) & HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK;
340
-
}
341
-
342
-
#define REG_HDMI_USEC_REFTIMER 0x00000208
343
-
344
-
#define REG_HDMI_DDC_CTRL 0x0000020c
345
-
#define HDMI_DDC_CTRL_GO 0x00000001
346
-
#define HDMI_DDC_CTRL_SOFT_RESET 0x00000002
347
-
#define HDMI_DDC_CTRL_SEND_RESET 0x00000004
348
-
#define HDMI_DDC_CTRL_SW_STATUS_RESET 0x00000008
349
-
#define HDMI_DDC_CTRL_TRANSACTION_CNT__MASK 0x00300000
350
-
#define HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT 20
351
-
static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val)
352
-
{
353
-
return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK;
354
-
}
355
-
356
-
#define REG_HDMI_DDC_ARBITRATION 0x00000210
357
-
#define HDMI_DDC_ARBITRATION_HW_ARBITRATION 0x00000010
358
-
359
-
#define REG_HDMI_DDC_INT_CTRL 0x00000214
360
-
#define HDMI_DDC_INT_CTRL_SW_DONE_INT 0x00000001
361
-
#define HDMI_DDC_INT_CTRL_SW_DONE_ACK 0x00000002
362
-
#define HDMI_DDC_INT_CTRL_SW_DONE_MASK 0x00000004
363
-
364
-
#define REG_HDMI_DDC_SW_STATUS 0x00000218
365
-
#define HDMI_DDC_SW_STATUS_NACK0 0x00001000
366
-
#define HDMI_DDC_SW_STATUS_NACK1 0x00002000
367
-
#define HDMI_DDC_SW_STATUS_NACK2 0x00004000
368
-
#define HDMI_DDC_SW_STATUS_NACK3 0x00008000
369
-
370
-
#define REG_HDMI_DDC_HW_STATUS 0x0000021c
371
-
#define HDMI_DDC_HW_STATUS_DONE 0x00000008
372
-
373
-
#define REG_HDMI_DDC_SPEED 0x00000220
374
-
#define HDMI_DDC_SPEED_THRESHOLD__MASK 0x00000003
375
-
#define HDMI_DDC_SPEED_THRESHOLD__SHIFT 0
376
-
static inline uint32_t HDMI_DDC_SPEED_THRESHOLD(uint32_t val)
377
-
{
378
-
return ((val) << HDMI_DDC_SPEED_THRESHOLD__SHIFT) & HDMI_DDC_SPEED_THRESHOLD__MASK;
379
-
}
380
-
#define HDMI_DDC_SPEED_PRESCALE__MASK 0xffff0000
381
-
#define HDMI_DDC_SPEED_PRESCALE__SHIFT 16
382
-
static inline uint32_t HDMI_DDC_SPEED_PRESCALE(uint32_t val)
383
-
{
384
-
return ((val) << HDMI_DDC_SPEED_PRESCALE__SHIFT) & HDMI_DDC_SPEED_PRESCALE__MASK;
385
-
}
386
-
387
-
#define REG_HDMI_DDC_SETUP 0x00000224
388
-
#define HDMI_DDC_SETUP_TIMEOUT__MASK 0xff000000
389
-
#define HDMI_DDC_SETUP_TIMEOUT__SHIFT 24
390
-
static inline uint32_t HDMI_DDC_SETUP_TIMEOUT(uint32_t val)
391
-
{
392
-
return ((val) << HDMI_DDC_SETUP_TIMEOUT__SHIFT) & HDMI_DDC_SETUP_TIMEOUT__MASK;
393
-
}
394
-
395
-
static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; }
396
-
397
-
static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; }
398
-
#define HDMI_I2C_TRANSACTION_REG_RW__MASK 0x00000001
399
-
#define HDMI_I2C_TRANSACTION_REG_RW__SHIFT 0
400
-
static inline uint32_t HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val)
401
-
{
402
-
return ((val) << HDMI_I2C_TRANSACTION_REG_RW__SHIFT) & HDMI_I2C_TRANSACTION_REG_RW__MASK;
403
-
}
404
-
#define HDMI_I2C_TRANSACTION_REG_STOP_ON_NACK 0x00000100
405
-
#define HDMI_I2C_TRANSACTION_REG_START 0x00001000
406
-
#define HDMI_I2C_TRANSACTION_REG_STOP 0x00002000
407
-
#define HDMI_I2C_TRANSACTION_REG_CNT__MASK 0x00ff0000
408
-
#define HDMI_I2C_TRANSACTION_REG_CNT__SHIFT 16
409
-
static inline uint32_t HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val)
410
-
{
411
-
return ((val) << HDMI_I2C_TRANSACTION_REG_CNT__SHIFT) & HDMI_I2C_TRANSACTION_REG_CNT__MASK;
412
-
}
413
-
414
-
#define REG_HDMI_DDC_DATA 0x00000238
415
-
#define HDMI_DDC_DATA_DATA_RW__MASK 0x00000001
416
-
#define HDMI_DDC_DATA_DATA_RW__SHIFT 0
417
-
static inline uint32_t HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val)
418
-
{
419
-
return ((val) << HDMI_DDC_DATA_DATA_RW__SHIFT) & HDMI_DDC_DATA_DATA_RW__MASK;
420
-
}
421
-
#define HDMI_DDC_DATA_DATA__MASK 0x0000ff00
422
-
#define HDMI_DDC_DATA_DATA__SHIFT 8
423
-
static inline uint32_t HDMI_DDC_DATA_DATA(uint32_t val)
424
-
{
425
-
return ((val) << HDMI_DDC_DATA_DATA__SHIFT) & HDMI_DDC_DATA_DATA__MASK;
426
-
}
427
-
#define HDMI_DDC_DATA_INDEX__MASK 0x00ff0000
428
-
#define HDMI_DDC_DATA_INDEX__SHIFT 16
429
-
static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val)
430
-
{
431
-
return ((val) << HDMI_DDC_DATA_INDEX__SHIFT) & HDMI_DDC_DATA_INDEX__MASK;
432
-
}
433
-
#define HDMI_DDC_DATA_INDEX_WRITE 0x80000000
434
-
435
-
#define REG_HDMI_HDCP_SHA_CTRL 0x0000023c
436
-
437
-
#define REG_HDMI_HDCP_SHA_STATUS 0x00000240
438
-
#define HDMI_HDCP_SHA_STATUS_BLOCK_DONE 0x00000001
439
-
#define HDMI_HDCP_SHA_STATUS_COMP_DONE 0x00000010
440
-
441
-
#define REG_HDMI_HDCP_SHA_DATA 0x00000244
442
-
#define HDMI_HDCP_SHA_DATA_DONE 0x00000001
443
-
444
-
#define REG_HDMI_HPD_INT_STATUS 0x00000250
445
-
#define HDMI_HPD_INT_STATUS_INT 0x00000001
446
-
#define HDMI_HPD_INT_STATUS_CABLE_DETECTED 0x00000002
447
-
448
-
#define REG_HDMI_HPD_INT_CTRL 0x00000254
449
-
#define HDMI_HPD_INT_CTRL_INT_ACK 0x00000001
450
-
#define HDMI_HPD_INT_CTRL_INT_CONNECT 0x00000002
451
-
#define HDMI_HPD_INT_CTRL_INT_EN 0x00000004
452
-
#define HDMI_HPD_INT_CTRL_RX_INT_ACK 0x00000010
453
-
#define HDMI_HPD_INT_CTRL_RX_INT_EN 0x00000020
454
-
#define HDMI_HPD_INT_CTRL_RCV_PLUGIN_DET_MASK 0x00000200
455
-
456
-
#define REG_HDMI_HPD_CTRL 0x00000258
457
-
#define HDMI_HPD_CTRL_TIMEOUT__MASK 0x00001fff
458
-
#define HDMI_HPD_CTRL_TIMEOUT__SHIFT 0
459
-
static inline uint32_t HDMI_HPD_CTRL_TIMEOUT(uint32_t val)
460
-
{
461
-
return ((val) << HDMI_HPD_CTRL_TIMEOUT__SHIFT) & HDMI_HPD_CTRL_TIMEOUT__MASK;
462
-
}
463
-
#define HDMI_HPD_CTRL_ENABLE 0x10000000
464
-
465
-
#define REG_HDMI_DDC_REF 0x0000027c
466
-
#define HDMI_DDC_REF_REFTIMER_ENABLE 0x00010000
467
-
#define HDMI_DDC_REF_REFTIMER__MASK 0x0000ffff
468
-
#define HDMI_DDC_REF_REFTIMER__SHIFT 0
469
-
static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val)
470
-
{
471
-
return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK;
472
-
}
473
-
474
-
#define REG_HDMI_HDCP_SW_UPPER_AKSV 0x00000284
475
-
476
-
#define REG_HDMI_HDCP_SW_LOWER_AKSV 0x00000288
477
-
478
-
#define REG_HDMI_CEC_CTRL 0x0000028c
479
-
480
-
#define REG_HDMI_CEC_WR_DATA 0x00000290
481
-
482
-
#define REG_HDMI_CEC_CEC_RETRANSMIT 0x00000294
483
-
484
-
#define REG_HDMI_CEC_STATUS 0x00000298
485
-
486
-
#define REG_HDMI_CEC_INT 0x0000029c
487
-
488
-
#define REG_HDMI_CEC_ADDR 0x000002a0
489
-
490
-
#define REG_HDMI_CEC_TIME 0x000002a4
491
-
492
-
#define REG_HDMI_CEC_REFTIMER 0x000002a8
493
-
494
-
#define REG_HDMI_CEC_RD_DATA 0x000002ac
495
-
496
-
#define REG_HDMI_CEC_RD_FILTER 0x000002b0
497
-
498
-
#define REG_HDMI_ACTIVE_HSYNC 0x000002b4
499
-
#define HDMI_ACTIVE_HSYNC_START__MASK 0x00001fff
500
-
#define HDMI_ACTIVE_HSYNC_START__SHIFT 0
501
-
static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val)
502
-
{
503
-
return ((val) << HDMI_ACTIVE_HSYNC_START__SHIFT) & HDMI_ACTIVE_HSYNC_START__MASK;
504
-
}
505
-
#define HDMI_ACTIVE_HSYNC_END__MASK 0x0fff0000
506
-
#define HDMI_ACTIVE_HSYNC_END__SHIFT 16
507
-
static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val)
508
-
{
509
-
return ((val) << HDMI_ACTIVE_HSYNC_END__SHIFT) & HDMI_ACTIVE_HSYNC_END__MASK;
510
-
}
511
-
512
-
#define REG_HDMI_ACTIVE_VSYNC 0x000002b8
513
-
#define HDMI_ACTIVE_VSYNC_START__MASK 0x00001fff
514
-
#define HDMI_ACTIVE_VSYNC_START__SHIFT 0
515
-
static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val)
516
-
{
517
-
return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK;
518
-
}
519
-
#define HDMI_ACTIVE_VSYNC_END__MASK 0x1fff0000
520
-
#define HDMI_ACTIVE_VSYNC_END__SHIFT 16
521
-
static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val)
522
-
{
523
-
return ((val) << HDMI_ACTIVE_VSYNC_END__SHIFT) & HDMI_ACTIVE_VSYNC_END__MASK;
524
-
}
525
-
526
-
#define REG_HDMI_VSYNC_ACTIVE_F2 0x000002bc
527
-
#define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00001fff
528
-
#define HDMI_VSYNC_ACTIVE_F2_START__SHIFT 0
529
-
static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val)
530
-
{
531
-
return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK;
532
-
}
533
-
#define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x1fff0000
534
-
#define HDMI_VSYNC_ACTIVE_F2_END__SHIFT 16
535
-
static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val)
536
-
{
537
-
return ((val) << HDMI_VSYNC_ACTIVE_F2_END__SHIFT) & HDMI_VSYNC_ACTIVE_F2_END__MASK;
538
-
}
539
-
540
-
#define REG_HDMI_TOTAL 0x000002c0
541
-
#define HDMI_TOTAL_H_TOTAL__MASK 0x00001fff
542
-
#define HDMI_TOTAL_H_TOTAL__SHIFT 0
543
-
static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val)
544
-
{
545
-
return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK;
546
-
}
547
-
#define HDMI_TOTAL_V_TOTAL__MASK 0x1fff0000
548
-
#define HDMI_TOTAL_V_TOTAL__SHIFT 16
549
-
static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val)
550
-
{
551
-
return ((val) << HDMI_TOTAL_V_TOTAL__SHIFT) & HDMI_TOTAL_V_TOTAL__MASK;
552
-
}
553
-
554
-
#define REG_HDMI_VSYNC_TOTAL_F2 0x000002c4
555
-
#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00001fff
556
-
#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT 0
557
-
static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)
558
-
{
559
-
return ((val) << HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT) & HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK;
560
-
}
561
-
562
-
#define REG_HDMI_FRAME_CTRL 0x000002c8
563
-
#define HDMI_FRAME_CTRL_RGB_MUX_SEL_BGR 0x00001000
564
-
#define HDMI_FRAME_CTRL_VSYNC_LOW 0x10000000
565
-
#define HDMI_FRAME_CTRL_HSYNC_LOW 0x20000000
566
-
#define HDMI_FRAME_CTRL_INTERLACED_EN 0x80000000
567
-
568
-
#define REG_HDMI_AUD_INT 0x000002cc
569
-
#define HDMI_AUD_INT_AUD_FIFO_URUN_INT 0x00000001
570
-
#define HDMI_AUD_INT_AUD_FIFO_URAN_MASK 0x00000002
571
-
#define HDMI_AUD_INT_AUD_SAM_DROP_INT 0x00000004
572
-
#define HDMI_AUD_INT_AUD_SAM_DROP_MASK 0x00000008
573
-
574
-
#define REG_HDMI_PHY_CTRL 0x000002d4
575
-
#define HDMI_PHY_CTRL_SW_RESET_PLL 0x00000001
576
-
#define HDMI_PHY_CTRL_SW_RESET_PLL_LOW 0x00000002
577
-
#define HDMI_PHY_CTRL_SW_RESET 0x00000004
578
-
#define HDMI_PHY_CTRL_SW_RESET_LOW 0x00000008
579
-
580
-
#define REG_HDMI_CEC_WR_RANGE 0x000002dc
581
-
582
-
#define REG_HDMI_CEC_RD_RANGE 0x000002e0
583
-
584
-
#define REG_HDMI_VERSION 0x000002e4
585
-
586
-
#define REG_HDMI_CEC_COMPL_CTL 0x00000360
587
-
588
-
#define REG_HDMI_CEC_RD_START_RANGE 0x00000364
589
-
590
-
#define REG_HDMI_CEC_RD_TOTAL_RANGE 0x00000368
591
-
592
-
#define REG_HDMI_CEC_RD_ERR_RESP_LO 0x0000036c
593
-
594
-
#define REG_HDMI_CEC_WR_CHECK_CONFIG 0x00000370
595
-
596
-
#define REG_HDMI_8x60_PHY_REG0 0x00000000
597
-
#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c
598
-
#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT 2
599
-
static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val)
600
-
{
601
-
return ((val) << HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT) & HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK;
602
-
}
603
-
604
-
#define REG_HDMI_8x60_PHY_REG1 0x00000004
605
-
#define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK 0x000000f0
606
-
#define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT 4
607
-
static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val)
608
-
{
609
-
return ((val) << HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT) & HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK;
610
-
}
611
-
#define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK 0x0000000f
612
-
#define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT 0
613
-
static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
614
-
{
615
-
return ((val) << HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT) & HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK;
616
-
}
617
-
618
-
#define REG_HDMI_8x60_PHY_REG2 0x00000008
619
-
#define HDMI_8x60_PHY_REG2_PD_DESER 0x00000001
620
-
#define HDMI_8x60_PHY_REG2_PD_DRIVE_1 0x00000002
621
-
#define HDMI_8x60_PHY_REG2_PD_DRIVE_2 0x00000004
622
-
#define HDMI_8x60_PHY_REG2_PD_DRIVE_3 0x00000008
623
-
#define HDMI_8x60_PHY_REG2_PD_DRIVE_4 0x00000010
624
-
#define HDMI_8x60_PHY_REG2_PD_PLL 0x00000020
625
-
#define HDMI_8x60_PHY_REG2_PD_PWRGEN 0x00000040
626
-
#define HDMI_8x60_PHY_REG2_RCV_SENSE_EN 0x00000080
627
-
628
-
#define REG_HDMI_8x60_PHY_REG3 0x0000000c
629
-
#define HDMI_8x60_PHY_REG3_PLL_ENABLE 0x00000001
630
-
631
-
#define REG_HDMI_8x60_PHY_REG4 0x00000010
632
-
633
-
#define REG_HDMI_8x60_PHY_REG5 0x00000014
634
-
635
-
#define REG_HDMI_8x60_PHY_REG6 0x00000018
636
-
637
-
#define REG_HDMI_8x60_PHY_REG7 0x0000001c
638
-
639
-
#define REG_HDMI_8x60_PHY_REG8 0x00000020
640
-
641
-
#define REG_HDMI_8x60_PHY_REG9 0x00000024
642
-
643
-
#define REG_HDMI_8x60_PHY_REG10 0x00000028
644
-
645
-
#define REG_HDMI_8x60_PHY_REG11 0x0000002c
646
-
647
-
#define REG_HDMI_8x60_PHY_REG12 0x00000030
648
-
#define HDMI_8x60_PHY_REG12_RETIMING_EN 0x00000001
649
-
#define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN 0x00000002
650
-
#define HDMI_8x60_PHY_REG12_FORCE_LOCK 0x00000010
651
-
652
-
#define REG_HDMI_8960_PHY_REG0 0x00000000
653
-
654
-
#define REG_HDMI_8960_PHY_REG1 0x00000004
655
-
656
-
#define REG_HDMI_8960_PHY_REG2 0x00000008
657
-
658
-
#define REG_HDMI_8960_PHY_REG3 0x0000000c
659
-
660
-
#define REG_HDMI_8960_PHY_REG4 0x00000010
661
-
662
-
#define REG_HDMI_8960_PHY_REG5 0x00000014
663
-
664
-
#define REG_HDMI_8960_PHY_REG6 0x00000018
665
-
666
-
#define REG_HDMI_8960_PHY_REG7 0x0000001c
667
-
668
-
#define REG_HDMI_8960_PHY_REG8 0x00000020
669
-
670
-
#define REG_HDMI_8960_PHY_REG9 0x00000024
671
-
672
-
#define REG_HDMI_8960_PHY_REG10 0x00000028
673
-
674
-
#define REG_HDMI_8960_PHY_REG11 0x0000002c
675
-
676
-
#define REG_HDMI_8960_PHY_REG12 0x00000030
677
-
#define HDMI_8960_PHY_REG12_SW_RESET 0x00000020
678
-
#define HDMI_8960_PHY_REG12_PWRDN_B 0x00000080
679
-
680
-
#define REG_HDMI_8960_PHY_REG_BIST_CFG 0x00000034
681
-
682
-
#define REG_HDMI_8960_PHY_DEBUG_BUS_SEL 0x00000038
683
-
684
-
#define REG_HDMI_8960_PHY_REG_MISC0 0x0000003c
685
-
686
-
#define REG_HDMI_8960_PHY_REG13 0x00000040
687
-
688
-
#define REG_HDMI_8960_PHY_REG14 0x00000044
689
-
690
-
#define REG_HDMI_8960_PHY_REG15 0x00000048
691
-
692
-
#define REG_HDMI_8960_PHY_PLL_REFCLK_CFG 0x00000000
693
-
694
-
#define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG 0x00000004
695
-
696
-
#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 0x00000008
697
-
698
-
#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 0x0000000c
699
-
700
-
#define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG 0x00000010
701
-
702
-
#define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG 0x00000014
703
-
704
-
#define REG_HDMI_8960_PHY_PLL_PWRDN_B 0x00000018
705
-
#define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL 0x00000002
706
-
#define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B 0x00000008
707
-
708
-
#define REG_HDMI_8960_PHY_PLL_SDM_CFG0 0x0000001c
709
-
710
-
#define REG_HDMI_8960_PHY_PLL_SDM_CFG1 0x00000020
711
-
712
-
#define REG_HDMI_8960_PHY_PLL_SDM_CFG2 0x00000024
713
-
714
-
#define REG_HDMI_8960_PHY_PLL_SDM_CFG3 0x00000028
715
-
716
-
#define REG_HDMI_8960_PHY_PLL_SDM_CFG4 0x0000002c
717
-
718
-
#define REG_HDMI_8960_PHY_PLL_SSC_CFG0 0x00000030
719
-
720
-
#define REG_HDMI_8960_PHY_PLL_SSC_CFG1 0x00000034
721
-
722
-
#define REG_HDMI_8960_PHY_PLL_SSC_CFG2 0x00000038
723
-
724
-
#define REG_HDMI_8960_PHY_PLL_SSC_CFG3 0x0000003c
725
-
726
-
#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 0x00000040
727
-
728
-
#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 0x00000044
729
-
730
-
#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 0x00000048
731
-
732
-
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 0x0000004c
733
-
734
-
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 0x00000050
735
-
736
-
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 0x00000054
737
-
738
-
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 0x00000058
739
-
740
-
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 0x0000005c
741
-
742
-
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 0x00000060
743
-
744
-
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 0x00000064
745
-
746
-
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 0x00000068
747
-
748
-
#define REG_HDMI_8960_PHY_PLL_DEBUG_SEL 0x0000006c
749
-
750
-
#define REG_HDMI_8960_PHY_PLL_MISC0 0x00000070
751
-
752
-
#define REG_HDMI_8960_PHY_PLL_MISC1 0x00000074
753
-
754
-
#define REG_HDMI_8960_PHY_PLL_MISC2 0x00000078
755
-
756
-
#define REG_HDMI_8960_PHY_PLL_MISC3 0x0000007c
757
-
758
-
#define REG_HDMI_8960_PHY_PLL_MISC4 0x00000080
759
-
760
-
#define REG_HDMI_8960_PHY_PLL_MISC5 0x00000084
761
-
762
-
#define REG_HDMI_8960_PHY_PLL_MISC6 0x00000088
763
-
764
-
#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0 0x0000008c
765
-
766
-
#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1 0x00000090
767
-
768
-
#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2 0x00000094
769
-
770
-
#define REG_HDMI_8960_PHY_PLL_STATUS0 0x00000098
771
-
#define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK 0x00000001
772
-
773
-
#define REG_HDMI_8960_PHY_PLL_STATUS1 0x0000009c
774
-
775
-
#define REG_HDMI_8x74_ANA_CFG0 0x00000000
776
-
777
-
#define REG_HDMI_8x74_ANA_CFG1 0x00000004
778
-
779
-
#define REG_HDMI_8x74_ANA_CFG2 0x00000008
780
-
781
-
#define REG_HDMI_8x74_ANA_CFG3 0x0000000c
782
-
783
-
#define REG_HDMI_8x74_PD_CTRL0 0x00000010
784
-
785
-
#define REG_HDMI_8x74_PD_CTRL1 0x00000014
786
-
787
-
#define REG_HDMI_8x74_GLB_CFG 0x00000018
788
-
789
-
#define REG_HDMI_8x74_DCC_CFG0 0x0000001c
790
-
791
-
#define REG_HDMI_8x74_DCC_CFG1 0x00000020
792
-
793
-
#define REG_HDMI_8x74_TXCAL_CFG0 0x00000024
794
-
795
-
#define REG_HDMI_8x74_TXCAL_CFG1 0x00000028
796
-
797
-
#define REG_HDMI_8x74_TXCAL_CFG2 0x0000002c
798
-
799
-
#define REG_HDMI_8x74_TXCAL_CFG3 0x00000030
800
-
801
-
#define REG_HDMI_8x74_BIST_CFG0 0x00000034
802
-
803
-
#define REG_HDMI_8x74_BIST_PATN0 0x0000003c
804
-
805
-
#define REG_HDMI_8x74_BIST_PATN1 0x00000040
806
-
807
-
#define REG_HDMI_8x74_BIST_PATN2 0x00000044
808
-
809
-
#define REG_HDMI_8x74_BIST_PATN3 0x00000048
810
-
811
-
#define REG_HDMI_8x74_STATUS 0x0000005c
812
-
813
-
#define REG_HDMI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
814
-
815
-
#define REG_HDMI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
816
-
817
-
#define REG_HDMI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
818
-
819
-
#define REG_HDMI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
820
-
821
-
#define REG_HDMI_28nm_PHY_PLL_VREG_CFG 0x00000010
822
-
823
-
#define REG_HDMI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
824
-
825
-
#define REG_HDMI_28nm_PHY_PLL_DMUX_CFG 0x00000018
826
-
827
-
#define REG_HDMI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
828
-
829
-
#define REG_HDMI_28nm_PHY_PLL_GLB_CFG 0x00000020
830
-
#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
831
-
#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
832
-
#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
833
-
#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
834
-
835
-
#define REG_HDMI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
836
-
837
-
#define REG_HDMI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
838
-
839
-
#define REG_HDMI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
840
-
841
-
#define REG_HDMI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
842
-
843
-
#define REG_HDMI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
844
-
845
-
#define REG_HDMI_28nm_PHY_PLL_SDM_CFG0 0x00000038
846
-
847
-
#define REG_HDMI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
848
-
849
-
#define REG_HDMI_28nm_PHY_PLL_SDM_CFG2 0x00000040
850
-
851
-
#define REG_HDMI_28nm_PHY_PLL_SDM_CFG3 0x00000044
852
-
853
-
#define REG_HDMI_28nm_PHY_PLL_SDM_CFG4 0x00000048
854
-
855
-
#define REG_HDMI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
856
-
857
-
#define REG_HDMI_28nm_PHY_PLL_SSC_CFG1 0x00000050
858
-
859
-
#define REG_HDMI_28nm_PHY_PLL_SSC_CFG2 0x00000054
860
-
861
-
#define REG_HDMI_28nm_PHY_PLL_SSC_CFG3 0x00000058
862
-
863
-
#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
864
-
865
-
#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
866
-
867
-
#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
868
-
869
-
#define REG_HDMI_28nm_PHY_PLL_TEST_CFG 0x00000068
870
-
#define HDMI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
871
-
872
-
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
873
-
874
-
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG1 0x00000070
875
-
876
-
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG2 0x00000074
877
-
878
-
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG3 0x00000078
879
-
880
-
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
881
-
882
-
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG5 0x00000080
883
-
884
-
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG6 0x00000084
885
-
886
-
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG7 0x00000088
887
-
888
-
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
889
-
890
-
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG9 0x00000090
891
-
892
-
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG10 0x00000094
893
-
894
-
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG11 0x00000098
895
-
896
-
#define REG_HDMI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
897
-
898
-
#define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
899
-
900
-
#define REG_HDMI_28nm_PHY_PLL_STATUS 0x000000c0
901
-
902
-
#define REG_HDMI_8996_PHY_CFG 0x00000000
903
-
904
-
#define REG_HDMI_8996_PHY_PD_CTL 0x00000004
905
-
906
-
#define REG_HDMI_8996_PHY_MODE 0x00000008
907
-
908
-
#define REG_HDMI_8996_PHY_MISR_CLEAR 0x0000000c
909
-
910
-
#define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG0 0x00000010
911
-
912
-
#define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG1 0x00000014
913
-
914
-
#define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE0 0x00000018
915
-
916
-
#define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE1 0x0000001c
917
-
918
-
#define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN0 0x00000020
919
-
920
-
#define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN1 0x00000024
921
-
922
-
#define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG0 0x00000028
923
-
924
-
#define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG1 0x0000002c
925
-
926
-
#define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE0 0x00000030
927
-
928
-
#define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE1 0x00000034
929
-
930
-
#define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN0 0x00000038
931
-
932
-
#define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN1 0x0000003c
933
-
934
-
#define REG_HDMI_8996_PHY_DEBUG_BUS_SEL 0x00000040
935
-
936
-
#define REG_HDMI_8996_PHY_TXCAL_CFG0 0x00000044
937
-
938
-
#define REG_HDMI_8996_PHY_TXCAL_CFG1 0x00000048
939
-
940
-
#define REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL 0x0000004c
941
-
942
-
#define REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL 0x00000050
943
-
944
-
#define REG_HDMI_8996_PHY_LANE_BIST_CONFIG 0x00000054
945
-
946
-
#define REG_HDMI_8996_PHY_CLOCK 0x00000058
947
-
948
-
#define REG_HDMI_8996_PHY_MISC1 0x0000005c
949
-
950
-
#define REG_HDMI_8996_PHY_MISC2 0x00000060
951
-
952
-
#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS0 0x00000064
953
-
954
-
#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS1 0x00000068
955
-
956
-
#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS2 0x0000006c
957
-
958
-
#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS0 0x00000070
959
-
960
-
#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS1 0x00000074
961
-
962
-
#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS2 0x00000078
963
-
964
-
#define REG_HDMI_8996_PHY_PRE_MISR_STATUS0 0x0000007c
965
-
966
-
#define REG_HDMI_8996_PHY_PRE_MISR_STATUS1 0x00000080
967
-
968
-
#define REG_HDMI_8996_PHY_PRE_MISR_STATUS2 0x00000084
969
-
970
-
#define REG_HDMI_8996_PHY_PRE_MISR_STATUS3 0x00000088
971
-
972
-
#define REG_HDMI_8996_PHY_POST_MISR_STATUS0 0x0000008c
973
-
974
-
#define REG_HDMI_8996_PHY_POST_MISR_STATUS1 0x00000090
975
-
976
-
#define REG_HDMI_8996_PHY_POST_MISR_STATUS2 0x00000094
977
-
978
-
#define REG_HDMI_8996_PHY_POST_MISR_STATUS3 0x00000098
979
-
980
-
#define REG_HDMI_8996_PHY_STATUS 0x0000009c
981
-
982
-
#define REG_HDMI_8996_PHY_MISC3_STATUS 0x000000a0
983
-
984
-
#define REG_HDMI_8996_PHY_MISC4_STATUS 0x000000a4
985
-
986
-
#define REG_HDMI_8996_PHY_DEBUG_BUS0 0x000000a8
987
-
988
-
#define REG_HDMI_8996_PHY_DEBUG_BUS1 0x000000ac
989
-
990
-
#define REG_HDMI_8996_PHY_DEBUG_BUS2 0x000000b0
991
-
992
-
#define REG_HDMI_8996_PHY_DEBUG_BUS3 0x000000b4
993
-
994
-
#define REG_HDMI_8996_PHY_PHY_REVISION_ID0 0x000000b8
995
-
996
-
#define REG_HDMI_8996_PHY_PHY_REVISION_ID1 0x000000bc
997
-
998
-
#define REG_HDMI_8996_PHY_PHY_REVISION_ID2 0x000000c0
999
-
1000
-
#define REG_HDMI_8996_PHY_PHY_REVISION_ID3 0x000000c4
1001
-
1002
-
#define REG_HDMI_PHY_QSERDES_COM_ATB_SEL1 0x00000000
1003
-
1004
-
#define REG_HDMI_PHY_QSERDES_COM_ATB_SEL2 0x00000004
1005
-
1006
-
#define REG_HDMI_PHY_QSERDES_COM_FREQ_UPDATE 0x00000008
1007
-
1008
-
#define REG_HDMI_PHY_QSERDES_COM_BG_TIMER 0x0000000c
1009
-
1010
-
#define REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER 0x00000010
1011
-
1012
-
#define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER1 0x00000014
1013
-
1014
-
#define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER2 0x00000018
1015
-
1016
-
#define REG_HDMI_PHY_QSERDES_COM_SSC_PER1 0x0000001c
1017
-
1018
-
#define REG_HDMI_PHY_QSERDES_COM_SSC_PER2 0x00000020
1019
-
1020
-
#define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1 0x00000024
1021
-
1022
-
#define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2 0x00000028
1023
-
1024
-
#define REG_HDMI_PHY_QSERDES_COM_POST_DIV 0x0000002c
1025
-
1026
-
#define REG_HDMI_PHY_QSERDES_COM_POST_DIV_MUX 0x00000030
1027
-
1028
-
#define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x00000034
1029
-
1030
-
#define REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1 0x00000038
1031
-
1032
-
#define REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL 0x0000003c
1033
-
1034
-
#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE 0x00000040
1035
-
1036
-
#define REG_HDMI_PHY_QSERDES_COM_PLL_EN 0x00000044
1037
-
1038
-
#define REG_HDMI_PHY_QSERDES_COM_PLL_IVCO 0x00000048
1039
-
1040
-
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x0000004c
1041
-
1042
-
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x00000050
1043
-
1044
-
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x00000054
1045
-
1046
-
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE1 0x00000058
1047
-
1048
-
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE1 0x0000005c
1049
-
1050
-
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE1 0x00000060
1051
-
1052
-
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE2 0x00000064
1053
-
1054
-
#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD0 0x00000064
1055
-
1056
-
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE2 0x00000068
1057
-
1058
-
#define REG_HDMI_PHY_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x00000068
1059
-
1060
-
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE2 0x0000006c
1061
-
1062
-
#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x0000006c
1063
-
1064
-
#define REG_HDMI_PHY_QSERDES_COM_BG_TRIM 0x00000070
1065
-
1066
-
#define REG_HDMI_PHY_QSERDES_COM_CLK_EP_DIV 0x00000074
1067
-
1068
-
#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0 0x00000078
1069
-
1070
-
#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE1 0x0000007c
1071
-
1072
-
#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE2 0x00000080
1073
-
1074
-
#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD1 0x00000080
1075
-
1076
-
#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x00000084
1077
-
1078
-
#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE1 0x00000088
1079
-
1080
-
#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE2 0x0000008c
1081
-
1082
-
#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD2 0x0000008c
1083
-
1084
-
#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x00000090
1085
-
1086
-
#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE1 0x00000094
1087
-
1088
-
#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE2 0x00000098
1089
-
1090
-
#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD3 0x00000098
1091
-
1092
-
#define REG_HDMI_PHY_QSERDES_COM_PLL_CNTRL 0x0000009c
1093
-
1094
-
#define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_CTRL 0x000000a0
1095
-
1096
-
#define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_DC 0x000000a4
1097
-
1098
-
#define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_IN_SYNC_SEL 0x000000a8
1099
-
1100
-
#define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x000000a8
1101
-
1102
-
#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL 0x000000ac
1103
-
1104
-
#define REG_HDMI_PHY_QSERDES_COM_CML_SYSCLK_SEL 0x000000b0
1105
-
1106
-
#define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL 0x000000b4
1107
-
1108
-
#define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL2 0x000000b8
1109
-
1110
-
#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL 0x000000bc
1111
-
1112
-
#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL2 0x000000c0
1113
-
1114
-
#define REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM 0x000000c4
1115
-
1116
-
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN 0x000000c8
1117
-
1118
-
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_CFG 0x000000cc
1119
-
1120
-
#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0 0x000000d0
1121
-
1122
-
#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE1 0x000000d4
1123
-
1124
-
#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE2 0x000000d8
1125
-
1126
-
#define REG_HDMI_PHY_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x000000d8
1127
-
1128
-
#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0x000000dc
1129
-
1130
-
#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0x000000e0
1131
-
1132
-
#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x000000e4
1133
-
1134
-
#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE1 0x000000e8
1135
-
1136
-
#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE1 0x000000ec
1137
-
1138
-
#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE1 0x000000f0
1139
-
1140
-
#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE2 0x000000f4
1141
-
1142
-
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL1 0x000000f4
1143
-
1144
-
#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE2 0x000000f8
1145
-
1146
-
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL2 0x000000f8
1147
-
1148
-
#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE2 0x000000fc
1149
-
1150
-
#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD4 0x000000fc
1151
-
1152
-
#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_INITVAL 0x00000100
1153
-
1154
-
#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_EN 0x00000104
1155
-
1156
-
#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x00000108
1157
-
1158
-
#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x0000010c
1159
-
1160
-
#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x00000110
1161
-
1162
-
#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x00000114
1163
-
1164
-
#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE2 0x00000118
1165
-
1166
-
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL1 0x00000118
1167
-
1168
-
#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE2 0x0000011c
1169
-
1170
-
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL2 0x0000011c
1171
-
1172
-
#define REG_HDMI_PHY_QSERDES_COM_RES_TRIM_CONTROL2 0x00000120
1173
-
1174
-
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL 0x00000124
1175
-
1176
-
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP 0x00000128
1177
-
1178
-
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE0 0x0000012c
1179
-
1180
-
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE0 0x00000130
1181
-
1182
-
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE1 0x00000134
1183
-
1184
-
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE1 0x00000138
1185
-
1186
-
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE2 0x0000013c
1187
-
1188
-
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL1 0x0000013c
1189
-
1190
-
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE2 0x00000140
1191
-
1192
-
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL2 0x00000140
1193
-
1194
-
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER1 0x00000144
1195
-
1196
-
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER2 0x00000148
1197
-
1198
-
#define REG_HDMI_PHY_QSERDES_COM_SAR 0x0000014c
1199
-
1200
-
#define REG_HDMI_PHY_QSERDES_COM_SAR_CLK 0x00000150
1201
-
1202
-
#define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_OUT_STATUS 0x00000154
1203
-
1204
-
#define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_READY_STATUS 0x00000158
1205
-
1206
-
#define REG_HDMI_PHY_QSERDES_COM_CMN_STATUS 0x0000015c
1207
-
1208
-
#define REG_HDMI_PHY_QSERDES_COM_RESET_SM_STATUS 0x00000160
1209
-
1210
-
#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CODE_STATUS 0x00000164
1211
-
1212
-
#define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE1_STATUS 0x00000168
1213
-
1214
-
#define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE2_STATUS 0x0000016c
1215
-
1216
-
#define REG_HDMI_PHY_QSERDES_COM_BG_CTRL 0x00000170
1217
-
1218
-
#define REG_HDMI_PHY_QSERDES_COM_CLK_SELECT 0x00000174
1219
-
1220
-
#define REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL 0x00000178
1221
-
1222
-
#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x0000017c
1223
-
1224
-
#define REG_HDMI_PHY_QSERDES_COM_PLL_ANALOG 0x00000180
1225
-
1226
-
#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV 0x00000184
1227
-
1228
-
#define REG_HDMI_PHY_QSERDES_COM_SW_RESET 0x00000188
1229
-
1230
-
#define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN 0x0000018c
1231
-
1232
-
#define REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS 0x00000190
1233
-
1234
-
#define REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG 0x00000194
1235
-
1236
-
#define REG_HDMI_PHY_QSERDES_COM_CMN_RATE_OVERRIDE 0x00000198
1237
-
1238
-
#define REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x0000019c
1239
-
1240
-
#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS0 0x000001a0
1241
-
1242
-
#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS1 0x000001a4
1243
-
1244
-
#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS2 0x000001a8
1245
-
1246
-
#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS3 0x000001ac
1247
-
1248
-
#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS_SEL 0x000001b0
1249
-
1250
-
#define REG_HDMI_PHY_QSERDES_COM_CMN_MISC1 0x000001b4
1251
-
1252
-
#define REG_HDMI_PHY_QSERDES_COM_CMN_MISC2 0x000001b8
1253
-
1254
-
#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE1 0x000001bc
1255
-
1256
-
#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE2 0x000001c0
1257
-
1258
-
#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD5 0x000001c4
1259
-
1260
-
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_MODE_LANENO 0x00000000
1261
-
1262
-
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_INVERT 0x00000004
1263
-
1264
-
#define REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE 0x00000008
1265
-
1266
-
#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_ONE 0x0000000c
1267
-
1268
-
#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_TWO 0x00000010
1269
-
1270
-
#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_THREE 0x00000014
1271
-
1272
-
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL 0x00000018
1273
-
1274
-
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_POST2_EMPH 0x0000001c
1275
-
1276
-
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_BOOST_LVL_UP_DN 0x00000020
1277
-
1278
-
#define REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES 0x00000024
1279
-
1280
-
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_IDLE_LVL_LARGE_AMP 0x00000028
1281
-
1282
-
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL 0x0000002c
1283
-
1284
-
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET 0x00000030
1285
-
1286
-
#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN 0x00000034
1287
-
1288
-
#define REG_HDMI_PHY_QSERDES_TX_LX_PRE_STALL_LDO_BOOST_EN 0x00000038
1289
-
1290
-
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND 0x0000003c
1291
-
1292
-
#define REG_HDMI_PHY_QSERDES_TX_LX_SLEW_CNTL 0x00000040
1293
-
1294
-
#define REG_HDMI_PHY_QSERDES_TX_LX_INTERFACE_SELECT 0x00000044
1295
-
1296
-
#define REG_HDMI_PHY_QSERDES_TX_LX_LPB_EN 0x00000048
1297
-
1298
-
#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_TX 0x0000004c
1299
-
1300
-
#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_RX 0x00000050
1301
-
1302
-
#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET 0x00000054
1303
-
1304
-
#define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH1 0x00000058
1305
-
1306
-
#define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH2 0x0000005c
1307
-
1308
-
#define REG_HDMI_PHY_QSERDES_TX_LX_SERDES_BYP_EN_OUT 0x00000060
1309
-
1310
-
#define REG_HDMI_PHY_QSERDES_TX_LX_DEBUG_BUS_SEL 0x00000064
1311
-
1312
-
#define REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x00000068
1313
-
1314
-
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_POL_INV 0x0000006c
1315
-
1316
-
#define REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN 0x00000070
1317
-
1318
-
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN1 0x00000074
1319
-
1320
-
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN2 0x00000078
1321
-
1322
-
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN3 0x0000007c
1323
-
1324
-
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN4 0x00000080
1325
-
1326
-
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN5 0x00000084
1327
-
1328
-
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN6 0x00000088
1329
-
1330
-
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN7 0x0000008c
1331
-
1332
-
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN8 0x00000090
1333
-
1334
-
#define REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE 0x00000094
1335
-
1336
-
#define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE 0x00000098
1337
-
1338
-
#define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE_CONFIGURATION 0x0000009c
1339
-
1340
-
#define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL1 0x000000a0
1341
-
1342
-
#define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL2 0x000000a4
1343
-
1344
-
#define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL 0x000000a8
1345
-
1346
-
#define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL_2 0x000000ac
1347
-
1348
-
#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED1 0x000000b0
1349
-
1350
-
#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED2 0x000000b4
1351
-
1352
-
#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED3 0x000000b8
1353
-
1354
-
#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED4 0x000000bc
1355
-
1356
-
#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN 0x000000c0
1357
-
1358
-
#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN_MUXES 0x000000c4
1359
-
1360
-
#define REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN 0x000000c8
1361
-
1362
-
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_INTERFACE_MODE 0x000000cc
1363
-
1364
-
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_CTRL 0x000000d0
1365
-
1366
-
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_ENCODED_OR_DATA 0x000000d4
1367
-
1368
-
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND2 0x000000d8
1369
-
1370
-
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND2 0x000000dc
1371
-
1372
-
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND2 0x000000e0
1373
-
1374
-
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND2 0x000000e4
1375
-
1376
-
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND0_1 0x000000e8
1377
-
1378
-
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND0_1 0x000000ec
1379
-
1380
-
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND0_1 0x000000f0
1381
-
1382
-
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND0_1 0x000000f4
1383
-
1384
-
#define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1 0x000000f8
1385
-
1386
-
#define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2 0x000000fc
1387
-
1388
-
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV_CNTL 0x00000100
1389
-
1390
-
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_STATUS 0x00000104
1391
-
1392
-
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT1 0x00000108
1393
-
1394
-
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT2 0x0000010c
1395
-
1396
-
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV 0x00000110
1397
-
1398
-
1399
-
#endif /* HDMI_XML */