tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

Pull kvm fixes from Paolo Bonzini:
"ARM:

- Fix the pKVM stage-1 walker erronously using the stage-2 accessor

- Correctly convert vcpu->kvm to a hyp pointer when generating an
exception in a nVHE+MTE configuration

- Check that KVM_CAP_DIRTY_LOG_* are valid before enabling them

- Fix SMPRI_EL1/TPIDR2_EL0 trapping on VHE

- Document the boot requirements for FGT when entering the kernel at
EL1

x86:

- Use SRCU to protect zap in __kvm_set_or_clear_apicv_inhibit()

- Make argument order consistent for kvcalloc()

- Userspace API fixes for DEBUGCTL and LBRs"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
KVM: x86: Fix a typo about the usage of kvcalloc()
KVM: x86: Use SRCU to protect zap in __kvm_set_or_clear_apicv_inhibit()
KVM: VMX: Ignore guest CPUID for host userspace writes to DEBUGCTL
KVM: VMX: Fold vmx_supported_debugctl() into vcpu_supported_debugctl()
KVM: VMX: Advertise PMU LBRs if and only if perf supports LBRs
arm64: booting: Document our requirements for fine grained traps with SME
KVM: arm64: Fix SMPRI_EL1/TPIDR2_EL0 trapping on VHE
KVM: Check KVM_CAP_DIRTY_LOG_{RING, RING_ACQ_REL} prior to enabling them
KVM: arm64: Fix bad dereference on MTE-enabled systems
KVM: arm64: Use correct accessor to parse stage-1 PTEs

Linus Torvalds 089d1c31 6e8c78d3

+52 -60
+8
Documentation/arm64/booting.rst
··· 340 340 - SMCR_EL2.LEN must be initialised to the same value for all CPUs the 341 341 kernel will execute on. 342 342 343 + - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01. 344 + 345 + - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01. 346 + 347 + - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01. 348 + 349 + - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01. 350 + 343 351 For CPUs with the Scalable Matrix Extension FA64 feature (FEAT_SME_FA64) 344 352 345 353 - If EL3 is present:
+2 -1
arch/arm64/kvm/hyp/exception.c
··· 13 13 #include <hyp/adjust_pc.h> 14 14 #include <linux/kvm_host.h> 15 15 #include <asm/kvm_emulate.h> 16 + #include <asm/kvm_mmu.h> 16 17 17 18 #if !defined (__KVM_NVHE_HYPERVISOR__) && !defined (__KVM_VHE_HYPERVISOR__) 18 19 #error Hypervisor code only! ··· 116 115 new |= (old & PSR_C_BIT); 117 116 new |= (old & PSR_V_BIT); 118 117 119 - if (kvm_has_mte(vcpu->kvm)) 118 + if (kvm_has_mte(kern_hyp_va(vcpu->kvm))) 120 119 new |= PSR_TCO_BIT; 121 120 122 121 new |= (old & PSR_DIT_BIT);
+20
arch/arm64/kvm/hyp/include/hyp/switch.h
··· 87 87 88 88 vcpu->arch.mdcr_el2_host = read_sysreg(mdcr_el2); 89 89 write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2); 90 + 91 + if (cpus_have_final_cap(ARM64_SME)) { 92 + sysreg_clear_set_s(SYS_HFGRTR_EL2, 93 + HFGxTR_EL2_nSMPRI_EL1_MASK | 94 + HFGxTR_EL2_nTPIDR2_EL0_MASK, 95 + 0); 96 + sysreg_clear_set_s(SYS_HFGWTR_EL2, 97 + HFGxTR_EL2_nSMPRI_EL1_MASK | 98 + HFGxTR_EL2_nTPIDR2_EL0_MASK, 99 + 0); 100 + } 90 101 } 91 102 92 103 static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu) ··· 107 96 write_sysreg(0, hstr_el2); 108 97 if (kvm_arm_support_pmu_v3()) 109 98 write_sysreg(0, pmuserenr_el0); 99 + 100 + if (cpus_have_final_cap(ARM64_SME)) { 101 + sysreg_clear_set_s(SYS_HFGRTR_EL2, 0, 102 + HFGxTR_EL2_nSMPRI_EL1_MASK | 103 + HFGxTR_EL2_nTPIDR2_EL0_MASK); 104 + sysreg_clear_set_s(SYS_HFGWTR_EL2, 0, 105 + HFGxTR_EL2_nSMPRI_EL1_MASK | 106 + HFGxTR_EL2_nTPIDR2_EL0_MASK); 107 + } 110 108 } 111 109 112 110 static inline void ___activate_traps(struct kvm_vcpu *vcpu)
+1 -1
arch/arm64/kvm/hyp/nvhe/mem_protect.c
··· 516 516 if (!kvm_pte_valid(pte)) 517 517 return PKVM_NOPAGE; 518 518 519 - return pkvm_getstate(kvm_pgtable_stage2_pte_prot(pte)); 519 + return pkvm_getstate(kvm_pgtable_hyp_pte_prot(pte)); 520 520 } 521 521 522 522 static int __hyp_check_page_state_range(u64 addr, u64 size,
-26
arch/arm64/kvm/hyp/nvhe/switch.c
··· 55 55 write_sysreg(val, cptr_el2); 56 56 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2); 57 57 58 - if (cpus_have_final_cap(ARM64_SME)) { 59 - val = read_sysreg_s(SYS_HFGRTR_EL2); 60 - val &= ~(HFGxTR_EL2_nTPIDR2_EL0_MASK | 61 - HFGxTR_EL2_nSMPRI_EL1_MASK); 62 - write_sysreg_s(val, SYS_HFGRTR_EL2); 63 - 64 - val = read_sysreg_s(SYS_HFGWTR_EL2); 65 - val &= ~(HFGxTR_EL2_nTPIDR2_EL0_MASK | 66 - HFGxTR_EL2_nSMPRI_EL1_MASK); 67 - write_sysreg_s(val, SYS_HFGWTR_EL2); 68 - } 69 - 70 58 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { 71 59 struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; 72 60 ··· 97 109 __deactivate_traps_common(vcpu); 98 110 99 111 write_sysreg(this_cpu_ptr(&kvm_init_params)->hcr_el2, hcr_el2); 100 - 101 - if (cpus_have_final_cap(ARM64_SME)) { 102 - u64 val; 103 - 104 - val = read_sysreg_s(SYS_HFGRTR_EL2); 105 - val |= HFGxTR_EL2_nTPIDR2_EL0_MASK | 106 - HFGxTR_EL2_nSMPRI_EL1_MASK; 107 - write_sysreg_s(val, SYS_HFGRTR_EL2); 108 - 109 - val = read_sysreg_s(SYS_HFGWTR_EL2); 110 - val |= HFGxTR_EL2_nTPIDR2_EL0_MASK | 111 - HFGxTR_EL2_nSMPRI_EL1_MASK; 112 - write_sysreg_s(val, SYS_HFGWTR_EL2); 113 - } 114 112 115 113 cptr = CPTR_EL2_DEFAULT; 116 114 if (vcpu_has_sve(vcpu) && (vcpu->arch.fp_state == FP_STATE_GUEST_OWNED))
-8
arch/arm64/kvm/hyp/vhe/switch.c
··· 63 63 __activate_traps_fpsimd32(vcpu); 64 64 } 65 65 66 - if (cpus_have_final_cap(ARM64_SME)) 67 - write_sysreg(read_sysreg(sctlr_el2) & ~SCTLR_ELx_ENTP2, 68 - sctlr_el2); 69 - 70 66 write_sysreg(val, cpacr_el1); 71 67 72 68 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1); ··· 83 87 * the host. 84 88 */ 85 89 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT)); 86 - 87 - if (cpus_have_final_cap(ARM64_SME)) 88 - write_sysreg(read_sysreg(sctlr_el2) | SCTLR_ELx_ENTP2, 89 - sctlr_el2); 90 90 91 91 write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1); 92 92
+1 -1
arch/x86/kvm/cpuid.c
··· 1338 1338 if (sanity_check_entries(entries, cpuid->nent, type)) 1339 1339 return -EINVAL; 1340 1340 1341 - array.entries = kvcalloc(sizeof(struct kvm_cpuid_entry2), cpuid->nent, GFP_KERNEL); 1341 + array.entries = kvcalloc(cpuid->nent, sizeof(struct kvm_cpuid_entry2), GFP_KERNEL); 1342 1342 if (!array.entries) 1343 1343 return -ENOMEM; 1344 1344
+3 -16
arch/x86/kvm/vmx/capabilities.h
··· 24 24 #define PMU_CAP_FW_WRITES (1ULL << 13) 25 25 #define PMU_CAP_LBR_FMT 0x3f 26 26 27 - #define DEBUGCTLMSR_LBR_MASK (DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI) 28 - 29 27 struct nested_vmx_msrs { 30 28 /* 31 29 * We only store the "true" versions of the VMX capability MSRs. We ··· 398 400 static inline u64 vmx_get_perf_capabilities(void) 399 401 { 400 402 u64 perf_cap = PMU_CAP_FW_WRITES; 403 + struct x86_pmu_lbr lbr; 401 404 u64 host_perf_cap = 0; 402 405 403 406 if (!enable_pmu) ··· 407 408 if (boot_cpu_has(X86_FEATURE_PDCM)) 408 409 rdmsrl(MSR_IA32_PERF_CAPABILITIES, host_perf_cap); 409 410 410 - perf_cap |= host_perf_cap & PMU_CAP_LBR_FMT; 411 + if (x86_perf_get_lbr(&lbr) >= 0 && lbr.nr) 412 + perf_cap |= host_perf_cap & PMU_CAP_LBR_FMT; 411 413 412 414 if (vmx_pebs_supported()) { 413 415 perf_cap |= host_perf_cap & PERF_CAP_PEBS_MASK; ··· 417 417 } 418 418 419 419 return perf_cap; 420 - } 421 - 422 - static inline u64 vmx_supported_debugctl(void) 423 - { 424 - u64 debugctl = 0; 425 - 426 - if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) 427 - debugctl |= DEBUGCTLMSR_BUS_LOCK_DETECT; 428 - 429 - if (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT) 430 - debugctl |= DEBUGCTLMSR_LBR_MASK; 431 - 432 - return debugctl; 433 420 } 434 421 435 422 static inline bool cpu_has_notify_vmexit(void)
+11 -7
arch/x86/kvm/vmx/vmx.c
··· 2021 2021 return (unsigned long)data; 2022 2022 } 2023 2023 2024 - static u64 vcpu_supported_debugctl(struct kvm_vcpu *vcpu) 2024 + static u64 vmx_get_supported_debugctl(struct kvm_vcpu *vcpu, bool host_initiated) 2025 2025 { 2026 - u64 debugctl = vmx_supported_debugctl(); 2026 + u64 debugctl = 0; 2027 2027 2028 - if (!intel_pmu_lbr_is_enabled(vcpu)) 2029 - debugctl &= ~DEBUGCTLMSR_LBR_MASK; 2028 + if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT) && 2029 + (host_initiated || guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))) 2030 + debugctl |= DEBUGCTLMSR_BUS_LOCK_DETECT; 2030 2031 2031 - if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) 2032 - debugctl &= ~DEBUGCTLMSR_BUS_LOCK_DETECT; 2032 + if ((vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT) && 2033 + (host_initiated || intel_pmu_lbr_is_enabled(vcpu))) 2034 + debugctl |= DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI; 2033 2035 2034 2036 return debugctl; 2035 2037 } ··· 2105 2103 vmcs_writel(GUEST_SYSENTER_ESP, data); 2106 2104 break; 2107 2105 case MSR_IA32_DEBUGCTLMSR: { 2108 - u64 invalid = data & ~vcpu_supported_debugctl(vcpu); 2106 + u64 invalid; 2107 + 2108 + invalid = data & ~vmx_get_supported_debugctl(vcpu, msr_info->host_initiated); 2109 2109 if (invalid & (DEBUGCTLMSR_BTF|DEBUGCTLMSR_LBR)) { 2110 2110 if (report_ignored_msrs) 2111 2111 vcpu_unimpl(vcpu, "%s: BTF|LBR in IA32_DEBUGCTLMSR 0x%llx, nop\n",
+3
arch/x86/kvm/x86.c
··· 10404 10404 kvm->arch.apicv_inhibit_reasons = new; 10405 10405 if (new) { 10406 10406 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE); 10407 + int idx = srcu_read_lock(&kvm->srcu); 10408 + 10407 10409 kvm_zap_gfn_range(kvm, gfn, gfn+1); 10410 + srcu_read_unlock(&kvm->srcu, idx); 10408 10411 } 10409 10412 } else { 10410 10413 kvm->arch.apicv_inhibit_reasons = new;
+3
virt/kvm/kvm_main.c
··· 4585 4585 } 4586 4586 case KVM_CAP_DIRTY_LOG_RING: 4587 4587 case KVM_CAP_DIRTY_LOG_RING_ACQ_REL: 4588 + if (!kvm_vm_ioctl_check_extension_generic(kvm, cap->cap)) 4589 + return -EINVAL; 4590 + 4588 4591 return kvm_vm_ioctl_enable_dirty_log_ring(kvm, cap->args[0]); 4589 4592 default: 4590 4593 return kvm_vm_ioctl_enable_cap(kvm, cap);