tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/i915/dp: Fix pipe BPP clamping due to HDR

The pipe BPP value shouldn't be set outside of the source's / sink's
valid pipe BPP range, ensure this when increasing the minimum pipe BPP
value to 30 due to HDR.

While at it debug print if the HDR mode was requested for a connector by
setting the corresponding HDR connector property. This indicates
if the requested HDR mode could not be enabled, since the selected
pipe BPP is below 30, due to a sink capability or link BW limit.

v2:
- Also handle the case where the sink could support the target 30 BPP
only in DSC mode due to a BW limit, but the sink doesn't support DSC
or 30 BPP as a DSC input BPP. (Chaitanya)
- Debug print the connector's HDR mode in the link config dump, to
indicate if a BPP >= 30 required by HDR couldn't be reached. (Ankit)
- Add Closes: trailer. (Ankit)
- Don't print the 30 BPP-outside of valid BPP range debug message if
the min BPP is already > 30 (and so a target BPP >= 30 required
for HDR is ensured).

Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/7052
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15503
Fixes: ba49a4643cf53 ("drm/i915/dp: Set min_bpp limit to 30 in HDR mode")
Cc: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Cc: <stable@vger.kernel.org> # v6.18+
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> # v1
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20260209133817.395823-1-imre.deak@intel.com

Imre Deak 08b7ef16 20df1466

+17 -3
+17 -3
drivers/gpu/drm/i915/display/intel_dp.c
··· 2703 2703 bool dsc, 2704 2704 struct link_config_limits *limits) 2705 2705 { 2706 + struct intel_display *display = to_intel_display(intel_dp); 2706 2707 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2707 2708 struct intel_connector *connector = 2708 2709 to_intel_connector(conn_state->connector); ··· 2716 2715 limits->min_lane_count = intel_dp_min_lane_count(intel_dp); 2717 2716 limits->max_lane_count = intel_dp_max_lane_count(intel_dp); 2718 2717 2719 - limits->pipe.min_bpp = intel_dp_in_hdr_mode(conn_state) ? 30 : 2720 - intel_dp_min_bpp(crtc_state->output_format); 2718 + limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format); 2721 2719 if (is_mst) { 2722 2720 /* 2723 2721 * FIXME: If all the streams can't fit into the link with their ··· 2730 2730 } else { 2731 2731 limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state, 2732 2732 respect_downstream_limits); 2733 + } 2734 + 2735 + if (!dsc && intel_dp_in_hdr_mode(conn_state)) { 2736 + if (intel_dp_supports_dsc(intel_dp, connector, crtc_state) && 2737 + limits->pipe.max_bpp >= 30) 2738 + limits->pipe.min_bpp = max(limits->pipe.min_bpp, 30); 2739 + else 2740 + drm_dbg_kms(display->drm, 2741 + "[CONNECTOR:%d:%s] Can't force 30 bpp for HDR (pipe bpp: %d-%d DSC-support: %s)\n", 2742 + connector->base.base.id, connector->base.name, 2743 + limits->pipe.min_bpp, limits->pipe.max_bpp, 2744 + str_yes_no(intel_dp_supports_dsc(intel_dp, connector, 2745 + crtc_state))); 2733 2746 } 2734 2747 2735 2748 if (dsc && !intel_dp_dsc_compute_pipe_bpp_limits(connector, limits)) ··· 2882 2869 } 2883 2870 2884 2871 drm_dbg_kms(display->drm, 2885 - "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n", 2872 + "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " HDR %s link rate required %d available %d\n", 2886 2873 pipe_config->lane_count, pipe_config->port_clock, 2887 2874 pipe_config->pipe_bpp, 2888 2875 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16), 2876 + str_yes_no(intel_dp_in_hdr_mode(conn_state)), 2889 2877 intel_dp_config_required_rate(pipe_config), 2890 2878 intel_dp_max_link_data_rate(intel_dp, 2891 2879 pipe_config->port_clock,