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Merge branch 'net-stmmac-report-active-phy-interface'

Russell King says:

====================
net: stmmac: report active phy interface

The original patch needs dwmac-thead fixed so the PHY_INTF* definitions
do not clash.
====================

Link: https://patch.msgid.link/aXnpTy6XckPGcmg0@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

+68 -5
+6
drivers/net/ethernet/stmicro/stmmac/common.h
··· 323 323 #define PHY_INTF_SEL_SMII 6 324 324 #define PHY_INTF_SEL_REVMII 7 325 325 326 + /* XGMAC uses a different encoding - from the AgileX5 documentation */ 327 + #define PHY_INTF_GMII 0 328 + #define PHY_INTF_RGMII 1 329 + 326 330 /* MSI defines */ 327 331 #define STMMAC_MSI_VEC_MAX 32 328 332 ··· 516 512 unsigned int dbgmem; 517 513 /* Number of Policing Counters */ 518 514 unsigned int pcsel; 515 + /* Active PHY interface, PHY_INTF_SEL_xxx */ 516 + u8 actphyif; 519 517 }; 520 518 521 519 /* RX Buffer size must be multiple of 4/8/16 bytes */
+5 -5
drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c
··· 37 37 #define GMAC_GTXCLK_SEL 0x18 38 38 #define GMAC_GTXCLK_SEL_PLL BIT(0) 39 39 #define GMAC_INTF_CTRL 0x1c 40 - #define PHY_INTF_MASK BIT(0) 41 - #define PHY_INTF_RGMII FIELD_PREP(PHY_INTF_MASK, 1) 42 - #define PHY_INTF_MII_GMII FIELD_PREP(PHY_INTF_MASK, 0) 40 + #define GMAC_INTF_MASK BIT(0) 41 + #define GMAC_INTF_RGMII FIELD_PREP(GMAC_INTF_MASK, 1) 42 + #define GMAC_INTF_MII_GMII FIELD_PREP(GMAC_INTF_MASK, 0) 43 43 #define GMAC_TXCLK_OEN 0x20 44 44 #define TXCLK_DIR_MASK BIT(0) 45 45 #define TXCLK_DIR_OUTPUT FIELD_PREP(TXCLK_DIR_MASK, 0) ··· 58 58 59 59 switch (plat->phy_interface) { 60 60 case PHY_INTERFACE_MODE_MII: 61 - phyif = PHY_INTF_MII_GMII; 61 + phyif = GMAC_INTF_MII_GMII; 62 62 break; 63 63 case PHY_INTERFACE_MODE_RGMII: 64 64 case PHY_INTERFACE_MODE_RGMII_ID: 65 65 case PHY_INTERFACE_MODE_RGMII_TXID: 66 66 case PHY_INTERFACE_MODE_RGMII_RXID: 67 - phyif = PHY_INTF_RGMII; 67 + phyif = GMAC_INTF_RGMII; 68 68 break; 69 69 default: 70 70 dev_err(dwmac->dev, "unsupported phy interface %s\n",
+2
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
··· 239 239 /* Alternate (enhanced) DESC mode */ 240 240 dma_cap->enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; 241 241 242 + dma_cap->actphyif = FIELD_GET(DMA_HW_FEAT_ACTPHYIF, hw_cap); 243 + 242 244 return 0; 243 245 } 244 246
+2
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
··· 382 382 dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27; 383 383 dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9; 384 384 385 + dma_cap->actphyif = FIELD_GET(DMA_HW_FEAT_ACTPHYIF, hw_cap); 386 + 385 387 /* MAC HW feature1 */ 386 388 hw_cap = readl(ioaddr + GMAC_HW_FEATURE1); 387 389 dma_cap->l3l4fnum = (hw_cap & GMAC_HW_FEAT_L3L4FNUM) >> 27;
+1
drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
··· 107 107 #define XGMAC_HWFEAT_VXN BIT(29) 108 108 #define XGMAC_HWFEAT_SAVLANINS BIT(27) 109 109 #define XGMAC_HWFEAT_TSSTSSEL GENMASK(26, 25) 110 + #define XGMAC_HWFEAT_PHYSEL GENMASK(24, 23) 110 111 #define XGMAC_HWFEAT_ADDMACADRSEL GENMASK(22, 18) 111 112 #define XGMAC_HWFEAT_RXCOESEL BIT(16) 112 113 #define XGMAC_HWFEAT_TXCOESEL BIT(14)
+1
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
··· 364 364 dma_cap->vxn = (hw_cap & XGMAC_HWFEAT_VXN) >> 29; 365 365 dma_cap->vlins = (hw_cap & XGMAC_HWFEAT_SAVLANINS) >> 27; 366 366 dma_cap->tssrc = (hw_cap & XGMAC_HWFEAT_TSSTSSEL) >> 25; 367 + dma_cap->actphyif = FIELD_GET(XGMAC_HWFEAT_PHYSEL, hw_cap); 367 368 dma_cap->multi_addr = (hw_cap & XGMAC_HWFEAT_ADDMACADRSEL) >> 18; 368 369 dma_cap->rx_coe = (hw_cap & XGMAC_HWFEAT_RXCOESEL) >> 16; 369 370 dma_cap->tx_coe = (hw_cap & XGMAC_HWFEAT_TXCOESEL) >> 14;
+51
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
··· 127 127 module_param(chain_mode, int, 0444); 128 128 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 129 129 130 + static const char *stmmac_dwmac_actphyif[8] = { 131 + [PHY_INTF_SEL_GMII_MII] = "GMII/MII", 132 + [PHY_INTF_SEL_RGMII] = "RGMII", 133 + [PHY_INTF_SEL_SGMII] = "SGMII", 134 + [PHY_INTF_SEL_TBI] = "TBI", 135 + [PHY_INTF_SEL_RMII] = "RMII", 136 + [PHY_INTF_SEL_RTBI] = "RTBI", 137 + [PHY_INTF_SEL_SMII] = "SMII", 138 + [PHY_INTF_SEL_REVMII] = "REVMII", 139 + }; 140 + 141 + static const char *stmmac_dwxgmac_phyif[4] = { 142 + [PHY_INTF_GMII] = "GMII", 143 + [PHY_INTF_RGMII] = "RGMII", 144 + }; 145 + 130 146 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 131 147 /* For MSI interrupts handling */ 132 148 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id); ··· 7286 7270 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 7287 7271 } 7288 7272 7273 + static void stmmac_print_actphyif(struct stmmac_priv *priv) 7274 + { 7275 + const char **phyif_table; 7276 + const char *actphyif_str; 7277 + size_t phyif_table_size; 7278 + 7279 + switch (priv->plat->core_type) { 7280 + case DWMAC_CORE_MAC100: 7281 + return; 7282 + 7283 + case DWMAC_CORE_GMAC: 7284 + case DWMAC_CORE_GMAC4: 7285 + phyif_table = stmmac_dwmac_actphyif; 7286 + phyif_table_size = ARRAY_SIZE(stmmac_dwmac_actphyif); 7287 + break; 7288 + 7289 + case DWMAC_CORE_XGMAC: 7290 + phyif_table = stmmac_dwxgmac_phyif; 7291 + phyif_table_size = ARRAY_SIZE(stmmac_dwxgmac_phyif); 7292 + break; 7293 + } 7294 + 7295 + if (priv->dma_cap.actphyif < phyif_table_size) 7296 + actphyif_str = phyif_table[priv->dma_cap.actphyif]; 7297 + else 7298 + actphyif_str = NULL; 7299 + 7300 + if (!actphyif_str) 7301 + actphyif_str = "unknown"; 7302 + 7303 + dev_info(priv->device, "Active PHY interface: %s (%u)\n", 7304 + actphyif_str, priv->dma_cap.actphyif); 7305 + } 7306 + 7289 7307 /** 7290 7308 * stmmac_hw_init - Init the MAC device 7291 7309 * @priv: driver private structure ··· 7376 7326 else if (priv->dma_cap.rx_coe_type1) 7377 7327 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 7378 7328 7329 + stmmac_print_actphyif(priv); 7379 7330 } else { 7380 7331 dev_info(priv->device, "No HW DMA feature register supported\n"); 7381 7332 }