Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mtd/for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull MTD updates from Miquel Raynal:
"MTD changes:
- There's been no major core change, just a bunch of driver related
improvements.
Amongst them the conversion to of_property_present() for
non-boolean properties, the addition of the support for Fujitsu
MB85RS128TY FRAM, a couple of improvements to the phram driver and
the usual load of misc changes.
Raw NAND changes:
- A new controller driver, from Nuvoton, has been merged
- Bastien Curutchet has contributed a series improving the Davinci
controller driver, both on the organization of the code, but also
on the performance side. The binding has also been converted to
yaml, received a new OOB layout and now supports on-die ECC engines
- The Qualcomm controller driver has been deeply cleaned to extract
some parts of the code into a shared file with the Qualcomm SPI
memory controller
- Aside from these main changes, the Cadence binding has been
converted to yaml, the brcmnand controller driver has received a
small fix, otherwise some more minor changes have also made their
way in
SPI NAND changes:
- The SPI NAND subsystem has seen a great improvement, with the
advent of DTR operations (DDR operations, which may be extended to
the address cycles). The first vendor driver to benefit from these
improvements is the Winbond driver
- A new manufacturer driver is added SkyHigh, with a new constraint
for the core, it is impossible to disable the on-die ECC engine
- A Foresee device is also now supported
SPI NOR changes:
- Several flash entries have been added: Atmel AT25SF321, Spansion
S28HL256T and S28HL02GT
- Support for vcc-supply regulators and their DT bindings has been
added
- The mx25u25635f entry has been dropped. The flash shares its ID
with mx25u25645g and both parts have an SFDP table. Removing their
entry lets them be driven by the generic SFDP-based driver"
* tag 'mtd/for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (47 commits)
mtd: spinand: skyhigh: Align with recent read from cache variant changes
mtd: spinand: winbond: Add support for DTR operations
mtd: spinand: winbond: Add comment about naming
mtd: spinand: winbond: Update the *JW chip definitions
mtd: spinand: Add support for read DTR operations
mtd: spinand: Enhance the logic when picking a variant
mtd: spinand: Add an optional frequency to read from cache macros
mtd: spinand: Create distinct fast and slow read from cache variants
mtd: hyperbus: Use of_property_present() for non-boolean properties
mtd: st_spi_fsm: Switch from CONFIG_PM_SLEEP guards to pm_sleep_ptr()
mtd: rawnand: davinci: add ROM supported OOB layout
mtd: spi-nor: sysfs: constify 'struct bin_attribute'
mtd: spi-nor: spansion: Add support for S28HL02GT
mtd: spi-nor: spansion: Add support for S28HL256T
mtd: spi-nor: extend description of size member of struct flash_info
mtd: rawnand: davinci: Reduce polling interval in NAND_OP_WAITRDY_INSTR
mtd: rawnand: qcom: Fix build issue on x86 architecture
mtd: rawnand: qcom: use FIELD_PREP and GENMASK
mtd: nand: Add qpic_common API file
mtd: rawnand: qcom: Add qcom prefix to common api
...
+3427
-1682
-53
Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt
-53
Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt
···
1
-
* Cadence NAND controller
2
-
3
-
Required properties:
4
-
- compatible : "cdns,hp-nfc"
5
-
- reg : Contains two entries, each of which is a tuple consisting of a
6
-
physical address and length. The first entry is the address and
7
-
length of the controller register set. The second entry is the
8
-
address and length of the Slave DMA data port.
9
-
- reg-names: should contain "reg" and "sdma"
10
-
- #address-cells: should be 1. The cell encodes the chip select connection.
11
-
- #size-cells : should be 0.
12
-
- interrupts : The interrupt number.
13
-
- clocks: phandle of the controller core clock (nf_clk).
14
-
15
-
Optional properties:
16
-
- dmas: shall reference DMA channel associated to the NAND controller
17
-
- cdns,board-delay-ps : Estimated Board delay. The value includes the total
18
-
round trip delay for the signals and is used for deciding on values
19
-
associated with data read capture. The example formula for SDR mode is
20
-
the following:
21
-
board delay = RE#PAD delay + PCB trace to device + PCB trace from device
22
-
+ DQ PAD delay
23
-
24
-
Child nodes represent the available NAND chips.
25
-
26
-
Required properties of NAND chips:
27
-
- reg: shall contain the native Chip Select ids from 0 to max supported by
28
-
the cadence nand flash controller
29
-
30
-
See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
31
-
generic bindings.
32
-
33
-
Example:
34
-
35
-
nand_controller: nand-controller@60000000 {
36
-
compatible = "cdns,hp-nfc";
37
-
#address-cells = <1>;
38
-
#size-cells = <0>;
39
-
reg = <0x60000000 0x10000>, <0x80000000 0x10000>;
40
-
reg-names = "reg", "sdma";
41
-
clocks = <&nf_clk>;
42
-
cdns,board-delay-ps = <4830>;
43
-
interrupts = <2 0>;
44
-
nand@0 {
45
-
reg = <0>;
46
-
label = "nand-1";
47
-
};
48
-
nand@1 {
49
-
reg = <1>;
50
-
label = "nand-2";
51
-
};
52
-
53
-
};
+75
Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
+75
Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mtd/cdns,hp-nfc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Cadence NAND controller
8
+
9
+
maintainers:
10
+
- Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
11
+
12
+
allOf:
13
+
- $ref: nand-controller.yaml
14
+
15
+
properties:
16
+
compatible:
17
+
items:
18
+
- const: cdns,hp-nfc
19
+
20
+
reg:
21
+
items:
22
+
- description: Controller register set
23
+
- description: Slave DMA data port register set
24
+
25
+
reg-names:
26
+
items:
27
+
- const: reg
28
+
- const: sdma
29
+
30
+
interrupts:
31
+
maxItems: 1
32
+
33
+
clocks:
34
+
maxItems: 1
35
+
36
+
dmas:
37
+
maxItems: 1
38
+
39
+
cdns,board-delay-ps:
40
+
description: |
41
+
Estimated Board delay. The value includes the total round trip
42
+
delay for the signals and is used for deciding on values associated
43
+
with data read capture. The example formula for SDR mode is the
44
+
following.
45
+
board delay = RE#PAD delay + PCB trace to device + PCB trace from device
46
+
+ DQ PAD delay
47
+
48
+
required:
49
+
- compatible
50
+
- reg
51
+
- reg-names
52
+
- interrupts
53
+
- clocks
54
+
55
+
unevaluatedProperties: false
56
+
57
+
examples:
58
+
- |
59
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
60
+
61
+
nand-controller@10b80000 {
62
+
compatible = "cdns,hp-nfc";
63
+
reg = <0x10b80000 0x10000>,
64
+
<0x10840000 0x10000>;
65
+
reg-names = "reg", "sdma";
66
+
#address-cells = <1>;
67
+
#size-cells = <0>;
68
+
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
69
+
clocks = <&nf_clk>;
70
+
cdns,board-delay-ps = <4830>;
71
+
72
+
nand@0 {
73
+
reg = <0>;
74
+
};
75
+
};
-94
Documentation/devicetree/bindings/mtd/davinci-nand.txt
-94
Documentation/devicetree/bindings/mtd/davinci-nand.txt
···
1
-
Device tree bindings for Texas instruments Davinci/Keystone NAND controller
2
-
3
-
This file provides information, what the device node for the davinci/keystone
4
-
NAND interface contains.
5
-
6
-
Documentation:
7
-
Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
8
-
Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
9
-
10
-
Required properties:
11
-
12
-
- compatible: "ti,davinci-nand"
13
-
"ti,keystone-nand"
14
-
15
-
- reg: Contains 2 offset/length values:
16
-
- offset and length for the access window.
17
-
- offset and length for accessing the AEMIF
18
-
control registers.
19
-
20
-
- ti,davinci-chipselect: number of chipselect. Indicates on the
21
-
davinci_nand driver which chipselect is used
22
-
for accessing the nand.
23
-
Can be in the range [0-3].
24
-
25
-
Recommended properties :
26
-
27
-
- ti,davinci-mask-ale: mask for ALE. Needed for executing address
28
-
phase. These offset will be added to the base
29
-
address for the chip select space the NAND Flash
30
-
device is connected to.
31
-
If not set equal to 0x08.
32
-
33
-
- ti,davinci-mask-cle: mask for CLE. Needed for executing command
34
-
phase. These offset will be added to the base
35
-
address for the chip select space the NAND Flash
36
-
device is connected to.
37
-
If not set equal to 0x10.
38
-
39
-
- ti,davinci-mask-chipsel: mask for chipselect address. Needed to mask
40
-
addresses for given chipselect.
41
-
42
-
- nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
43
-
valid values for davinci driver:
44
-
- "none"
45
-
- "soft"
46
-
- "hw"
47
-
48
-
- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
49
-
50
-
- nand-bus-width: buswidth 8 or 16. If not present 8.
51
-
52
-
- nand-on-flash-bbt: use flash based bad block table support. OOB
53
-
identifier is saved in OOB area. If not present
54
-
false.
55
-
56
-
Deprecated properties:
57
-
58
-
- ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
59
-
valid values for davinci driver:
60
-
- "none"
61
-
- "soft"
62
-
- "hw"
63
-
64
-
- ti,davinci-nand-buswidth: buswidth 8 or 16. If not present 8.
65
-
66
-
- ti,davinci-nand-use-bbt: use flash based bad block table support. OOB
67
-
identifier is saved in OOB area. If not present
68
-
false.
69
-
70
-
Nand device bindings may contain additional sub-nodes describing partitions of
71
-
the address space. See mtd.yaml for more detail. The NAND Flash timing
72
-
values must be programmed in the chip select’s node of AEMIF
73
-
memory-controller (see Documentation/devicetree/bindings/memory-controllers/
74
-
davinci-aemif.txt).
75
-
76
-
Example(da850 EVM ):
77
-
78
-
nand_cs3@62000000 {
79
-
compatible = "ti,davinci-nand";
80
-
reg = <0x62000000 0x807ff
81
-
0x68000000 0x8000>;
82
-
ti,davinci-chipselect = <1>;
83
-
ti,davinci-mask-ale = <0>;
84
-
ti,davinci-mask-cle = <0>;
85
-
ti,davinci-mask-chipsel = <0>;
86
-
nand-ecc-mode = "hw";
87
-
ti,davinci-ecc-bits = <4>;
88
-
nand-on-flash-bbt;
89
-
90
-
partition@180000 {
91
-
label = "ubifs";
92
-
reg = <0x180000 0x7e80000>;
93
-
};
94
-
};
+4
Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
+4
Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
+3
-2
Documentation/devicetree/bindings/mtd/microchip,mchp48l640.yaml
+3
-2
Documentation/devicetree/bindings/mtd/microchip,mchp48l640.yaml
+95
Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
+95
Documentation/devicetree/bindings/mtd/nuvoton,ma35d1-nand.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mtd/nuvoton,ma35d1-nand.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Nuvoton MA35D1 NAND Flash Interface (NFI) Controller
8
+
9
+
maintainers:
10
+
- Hui-Ping Chen <hpchen0nvt@gmail.com>
11
+
12
+
allOf:
13
+
- $ref: nand-controller.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
enum:
18
+
- nuvoton,ma35d1-nand-controller
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
interrupts:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
maxItems: 1
28
+
29
+
patternProperties:
30
+
"^nand@[a-f0-9]$":
31
+
type: object
32
+
$ref: raw-nand-chip.yaml
33
+
properties:
34
+
reg:
35
+
minimum: 0
36
+
maximum: 1
37
+
38
+
nand-ecc-step-size:
39
+
enum: [512, 1024]
40
+
41
+
nand-ecc-strength:
42
+
enum: [8, 12, 24]
43
+
44
+
required:
45
+
- reg
46
+
47
+
unevaluatedProperties: false
48
+
49
+
required:
50
+
- compatible
51
+
- reg
52
+
- interrupts
53
+
- clocks
54
+
55
+
unevaluatedProperties: false
56
+
57
+
examples:
58
+
- |
59
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
60
+
#include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
61
+
62
+
soc {
63
+
#address-cells = <2>;
64
+
#size-cells = <2>;
65
+
66
+
nand-controller@401A0000 {
67
+
compatible = "nuvoton,ma35d1-nand-controller";
68
+
reg = <0x0 0x401A0000 0x0 0x1000>;
69
+
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
70
+
clocks = <&clk NAND_GATE>;
71
+
#address-cells = <1>;
72
+
#size-cells = <0>;
73
+
74
+
nand@0 {
75
+
reg = <0>;
76
+
nand-on-flash-bbt;
77
+
nand-ecc-step-size = <512>;
78
+
nand-ecc-strength = <8>;
79
+
80
+
partitions {
81
+
compatible = "fixed-partitions";
82
+
#address-cells = <1>;
83
+
#size-cells = <1>;
84
+
85
+
uboot@0 {
86
+
label = "nand-uboot";
87
+
read-only;
88
+
reg = <0x0 0x300000>;
89
+
};
90
+
};
91
+
};
92
+
};
93
+
};
94
+
95
+
...
+124
Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml
+124
Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: TI DaVinci NAND controller
8
+
9
+
maintainers:
10
+
- Marcus Folkesson <marcus.folkesson@gmail.com>
11
+
12
+
allOf:
13
+
- $ref: nand-controller.yaml
14
+
15
+
properties:
16
+
compatible:
17
+
enum:
18
+
- ti,davinci-nand
19
+
- ti,keystone-nand
20
+
21
+
reg:
22
+
items:
23
+
- description: Access window.
24
+
- description: AEMIF control registers.
25
+
26
+
partitions:
27
+
$ref: /schemas/mtd/partitions/partitions.yaml
28
+
29
+
ti,davinci-chipselect:
30
+
description:
31
+
Number of chipselect. Indicate on the davinci_nand driver which
32
+
chipselect is used for accessing the nand.
33
+
$ref: /schemas/types.yaml#/definitions/uint32
34
+
enum: [0, 1, 2, 3]
35
+
36
+
ti,davinci-mask-ale:
37
+
description:
38
+
Mask for ALE. Needed for executing address phase. These offset will be
39
+
added to the base address for the chip select space the NAND Flash
40
+
device is connected to.
41
+
$ref: /schemas/types.yaml#/definitions/uint32
42
+
default: 0x08
43
+
44
+
ti,davinci-mask-cle:
45
+
description:
46
+
Mask for CLE. Needed for executing command phase. These offset will be
47
+
added to the base address for the chip select space the NAND Flash device
48
+
is connected to.
49
+
$ref: /schemas/types.yaml#/definitions/uint32
50
+
default: 0x10
51
+
52
+
ti,davinci-mask-chipsel:
53
+
description:
54
+
Mask for chipselect address. Needed to mask addresses for given
55
+
chipselect.
56
+
$ref: /schemas/types.yaml#/definitions/uint32
57
+
default: 0
58
+
59
+
ti,davinci-ecc-bits:
60
+
description: Used ECC bits.
61
+
enum: [1, 4]
62
+
63
+
ti,davinci-ecc-mode:
64
+
description: Operation mode of the NAND ECC mode.
65
+
$ref: /schemas/types.yaml#/definitions/string
66
+
enum: [none, soft, hw, on-die]
67
+
deprecated: true
68
+
69
+
ti,davinci-nand-buswidth:
70
+
description: Bus width to the NAND chip.
71
+
$ref: /schemas/types.yaml#/definitions/uint32
72
+
enum: [8, 16]
73
+
default: 8
74
+
deprecated: true
75
+
76
+
ti,davinci-nand-use-bbt:
77
+
type: boolean
78
+
description:
79
+
Use flash based bad block table support. OOB identifier is saved in OOB
80
+
area.
81
+
deprecated: true
82
+
83
+
required:
84
+
- compatible
85
+
- reg
86
+
- ti,davinci-chipselect
87
+
88
+
unevaluatedProperties: false
89
+
90
+
examples:
91
+
- |
92
+
bus {
93
+
#address-cells = <2>;
94
+
#size-cells = <1>;
95
+
96
+
nand-controller@2000000,0 {
97
+
compatible = "ti,davinci-nand";
98
+
#address-cells = <1>;
99
+
#size-cells = <0>;
100
+
reg = <0 0x02000000 0x02000000>,
101
+
<1 0x00000000 0x00008000>;
102
+
103
+
ti,davinci-chipselect = <1>;
104
+
ti,davinci-mask-ale = <0>;
105
+
ti,davinci-mask-cle = <0>;
106
+
ti,davinci-mask-chipsel = <0>;
107
+
108
+
ti,davinci-nand-buswidth = <16>;
109
+
ti,davinci-ecc-mode = "hw";
110
+
ti,davinci-ecc-bits = <4>;
111
+
ti,davinci-nand-use-bbt;
112
+
113
+
partitions {
114
+
compatible = "fixed-partitions";
115
+
#address-cells = <1>;
116
+
#size-cells = <1>;
117
+
118
+
partition@0 {
119
+
label = "u-boot env";
120
+
reg = <0 0x020000>;
121
+
};
122
+
};
123
+
};
124
+
};
+1
-1
MAINTAINERS
+1
-1
MAINTAINERS
···
5054
5054
CADENCE NAND DRIVER
5055
5055
L: linux-mtd@lists.infradead.org
5056
5056
S: Orphan
5057
-
F: Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt
5057
+
F: Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
5058
5058
F: drivers/mtd/nand/raw/cadence-nand-controller.c
5059
5059
5060
5060
CADENCE USB3 DRD IP DRIVER
+25
-3
drivers/mtd/devices/mchp48l640.c
+25
-3
drivers/mtd/devices/mchp48l640.c
···
27
27
struct mchp48_caps {
28
28
unsigned int size;
29
29
unsigned int page_size;
30
+
bool auto_disable_wel;
30
31
};
31
32
32
33
struct mchp48l640_flash {
···
195
194
else
196
195
goto fail;
197
196
198
-
ret = mchp48l640_waitforbit(flash, MCHP48L640_STATUS_WEL, false);
199
-
if (ret)
200
-
goto fail;
197
+
if (flash->caps->auto_disable_wel) {
198
+
ret = mchp48l640_waitforbit(flash, MCHP48L640_STATUS_WEL, false);
199
+
if (ret)
200
+
goto fail;
201
+
} else {
202
+
ret = mchp48l640_write_prepare(flash, false);
203
+
if (ret)
204
+
goto fail;
205
+
}
201
206
202
207
kfree(cmd);
203
208
return 0;
···
300
293
static const struct mchp48_caps mchp48l640_caps = {
301
294
.size = SZ_8K,
302
295
.page_size = 32,
296
+
.auto_disable_wel = true,
297
+
};
298
+
299
+
static const struct mchp48_caps mb85rs128ty_caps = {
300
+
.size = SZ_16K,
301
+
.page_size = 256,
302
+
.auto_disable_wel = false,
303
303
};
304
304
305
305
static int mchp48l640_probe(struct spi_device *spi)
···
367
353
.compatible = "microchip,48l640",
368
354
.data = &mchp48l640_caps,
369
355
},
356
+
{
357
+
.compatible = "fujitsu,mb85rs128ty",
358
+
.data = &mb85rs128ty_caps,
359
+
},
370
360
{}
371
361
};
372
362
MODULE_DEVICE_TABLE(of, mchp48l640_of_table);
···
379
361
{
380
362
.name = "48l640",
381
363
.driver_data = (kernel_ulong_t)&mchp48l640_caps,
364
+
},
365
+
{
366
+
.name = "mb85rs128ty",
367
+
.driver_data = (kernel_ulong_t)&mb85rs128ty_caps,
382
368
},
383
369
{}
384
370
};
+9
-4
drivers/mtd/devices/phram.c
+9
-4
drivers/mtd/devices/phram.c
···
30
30
#include <linux/platform_device.h>
31
31
#include <linux/of_address.h>
32
32
#include <linux/of.h>
33
+
#include <linux/security.h>
33
34
34
35
struct phram_mtd_list {
35
36
struct mtd_info mtd;
···
411
410
{
412
411
int ret;
413
412
413
+
ret = security_locked_down(LOCKDOWN_DEV_MEM);
414
+
if (ret)
415
+
return ret;
416
+
414
417
ret = platform_driver_register(&phram_driver);
415
418
if (ret)
416
419
return ret;
417
420
418
421
#ifndef MODULE
419
-
if (phram_paramline[0])
422
+
if (phram_paramline[0]) {
420
423
ret = phram_setup(phram_paramline);
424
+
if (ret)
425
+
platform_driver_unregister(&phram_driver);
426
+
}
421
427
phram_init_called = 1;
422
428
#endif
423
-
424
-
if (ret)
425
-
platform_driver_unregister(&phram_driver);
426
429
427
430
return ret;
428
431
}
+2
-4
drivers/mtd/devices/st_spi_fsm.c
+2
-4
drivers/mtd/devices/st_spi_fsm.c
···
2104
2104
WARN_ON(mtd_device_unregister(&fsm->mtd));
2105
2105
}
2106
2106
2107
-
#ifdef CONFIG_PM_SLEEP
2108
2107
static int stfsmfsm_suspend(struct device *dev)
2109
2108
{
2110
2109
struct stfsm *fsm = dev_get_drvdata(dev);
···
2119
2120
2120
2121
return clk_prepare_enable(fsm->clk);
2121
2122
}
2122
-
#endif
2123
2123
2124
-
static SIMPLE_DEV_PM_OPS(stfsm_pm_ops, stfsmfsm_suspend, stfsmfsm_resume);
2124
+
static DEFINE_SIMPLE_DEV_PM_OPS(stfsm_pm_ops, stfsmfsm_suspend, stfsmfsm_resume);
2125
2125
2126
2126
static const struct of_device_id stfsm_match[] = {
2127
2127
{ .compatible = "st,spi-fsm", },
···
2134
2136
.driver = {
2135
2137
.name = "st-spi-fsm",
2136
2138
.of_match_table = stfsm_match,
2137
-
.pm = &stfsm_pm_ops,
2139
+
.pm = pm_sleep_ptr(&stfsm_pm_ops),
2138
2140
},
2139
2141
};
2140
2142
module_platform_driver(stfsm_driver);
+14
-7
drivers/mtd/hyperbus/hbmc-am654.c
+14
-7
drivers/mtd/hyperbus/hbmc-am654.c
···
174
174
priv->hbdev.np = of_get_next_child(np, NULL);
175
175
ret = of_address_to_resource(priv->hbdev.np, 0, &res);
176
176
if (ret)
177
-
return ret;
177
+
goto put_node;
178
178
179
-
if (of_property_read_bool(dev->of_node, "mux-controls")) {
179
+
if (of_property_present(dev->of_node, "mux-controls")) {
180
180
struct mux_control *control = devm_mux_control_get(dev, NULL);
181
181
182
-
if (IS_ERR(control))
183
-
return PTR_ERR(control);
182
+
if (IS_ERR(control)) {
183
+
ret = PTR_ERR(control);
184
+
goto put_node;
185
+
}
184
186
185
187
ret = mux_control_select(control, 1);
186
188
if (ret) {
187
189
dev_err(dev, "Failed to select HBMC mux\n");
188
-
return ret;
190
+
goto put_node;
189
191
}
190
192
priv->mux_ctrl = control;
191
193
}
192
194
193
195
priv->hbdev.map.size = resource_size(&res);
194
196
priv->hbdev.map.virt = devm_ioremap_resource(dev, &res);
195
-
if (IS_ERR(priv->hbdev.map.virt))
196
-
return PTR_ERR(priv->hbdev.map.virt);
197
+
if (IS_ERR(priv->hbdev.map.virt)) {
198
+
ret = PTR_ERR(priv->hbdev.map.virt);
199
+
goto disable_mux;
200
+
}
197
201
198
202
priv->ctlr.dev = dev;
199
203
priv->ctlr.ops = &am654_hbmc_ops;
···
230
226
disable_mux:
231
227
if (priv->mux_ctrl)
232
228
mux_control_deselect(priv->mux_ctrl);
229
+
put_node:
230
+
of_node_put(priv->hbdev.np);
233
231
return ret;
234
232
}
235
233
···
247
241
248
242
if (dev_priv->rx_chan)
249
243
dma_release_channel(dev_priv->rx_chan);
244
+
of_node_put(priv->hbdev.np);
250
245
}
251
246
252
247
static const struct of_device_id am654_hbmc_dt_ids[] = {
+1
-1
drivers/mtd/nand/Makefile
+1
-1
drivers/mtd/nand/Makefile
+1
drivers/mtd/nand/onenand/onenand_base.c
+1
drivers/mtd/nand/onenand/onenand_base.c
+759
drivers/mtd/nand/qpic_common.c
+759
drivers/mtd/nand/qpic_common.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved
5
+
*/
6
+
#include <linux/clk.h>
7
+
#include <linux/delay.h>
8
+
#include <linux/dmaengine.h>
9
+
#include <linux/dma-mapping.h>
10
+
#include <linux/dma/qcom_adm.h>
11
+
#include <linux/dma/qcom_bam_dma.h>
12
+
#include <linux/module.h>
13
+
#include <linux/of.h>
14
+
#include <linux/platform_device.h>
15
+
#include <linux/slab.h>
16
+
#include <linux/mtd/nand-qpic-common.h>
17
+
18
+
/**
19
+
* qcom_free_bam_transaction() - Frees the BAM transaction memory
20
+
* @nandc: qpic nand controller
21
+
*
22
+
* This function frees the bam transaction memory
23
+
*/
24
+
void qcom_free_bam_transaction(struct qcom_nand_controller *nandc)
25
+
{
26
+
struct bam_transaction *bam_txn = nandc->bam_txn;
27
+
28
+
kfree(bam_txn);
29
+
}
30
+
EXPORT_SYMBOL(qcom_free_bam_transaction);
31
+
32
+
/**
33
+
* qcom_alloc_bam_transaction() - allocate BAM transaction
34
+
* @nandc: qpic nand controller
35
+
*
36
+
* This function will allocate and initialize the BAM transaction structure
37
+
*/
38
+
struct bam_transaction *
39
+
qcom_alloc_bam_transaction(struct qcom_nand_controller *nandc)
40
+
{
41
+
struct bam_transaction *bam_txn;
42
+
size_t bam_txn_size;
43
+
unsigned int num_cw = nandc->max_cwperpage;
44
+
void *bam_txn_buf;
45
+
46
+
bam_txn_size =
47
+
sizeof(*bam_txn) + num_cw *
48
+
((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
49
+
(sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
50
+
(sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
51
+
52
+
bam_txn_buf = kzalloc(bam_txn_size, GFP_KERNEL);
53
+
if (!bam_txn_buf)
54
+
return NULL;
55
+
56
+
bam_txn = bam_txn_buf;
57
+
bam_txn_buf += sizeof(*bam_txn);
58
+
59
+
bam_txn->bam_ce = bam_txn_buf;
60
+
bam_txn_buf +=
61
+
sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
62
+
63
+
bam_txn->cmd_sgl = bam_txn_buf;
64
+
bam_txn_buf +=
65
+
sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw;
66
+
67
+
bam_txn->data_sgl = bam_txn_buf;
68
+
69
+
init_completion(&bam_txn->txn_done);
70
+
71
+
return bam_txn;
72
+
}
73
+
EXPORT_SYMBOL(qcom_alloc_bam_transaction);
74
+
75
+
/**
76
+
* qcom_clear_bam_transaction() - Clears the BAM transaction
77
+
* @nandc: qpic nand controller
78
+
*
79
+
* This function will clear the BAM transaction indexes.
80
+
*/
81
+
void qcom_clear_bam_transaction(struct qcom_nand_controller *nandc)
82
+
{
83
+
struct bam_transaction *bam_txn = nandc->bam_txn;
84
+
85
+
if (!nandc->props->supports_bam)
86
+
return;
87
+
88
+
memset(&bam_txn->bam_positions, 0, sizeof(bam_txn->bam_positions));
89
+
bam_txn->last_data_desc = NULL;
90
+
91
+
sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
92
+
QPIC_PER_CW_CMD_SGL);
93
+
sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage *
94
+
QPIC_PER_CW_DATA_SGL);
95
+
96
+
reinit_completion(&bam_txn->txn_done);
97
+
}
98
+
EXPORT_SYMBOL(qcom_clear_bam_transaction);
99
+
100
+
/**
101
+
* qcom_qpic_bam_dma_done() - Callback for DMA descriptor completion
102
+
* @data: data pointer
103
+
*
104
+
* This function is a callback for DMA descriptor completion
105
+
*/
106
+
void qcom_qpic_bam_dma_done(void *data)
107
+
{
108
+
struct bam_transaction *bam_txn = data;
109
+
110
+
complete(&bam_txn->txn_done);
111
+
}
112
+
EXPORT_SYMBOL(qcom_qpic_bam_dma_done);
113
+
114
+
/**
115
+
* qcom_nandc_dev_to_mem() - Check for dma sync for cpu or device
116
+
* @nandc: qpic nand controller
117
+
* @is_cpu: cpu or Device
118
+
*
119
+
* This function will check for dma sync for cpu or device
120
+
*/
121
+
inline void qcom_nandc_dev_to_mem(struct qcom_nand_controller *nandc, bool is_cpu)
122
+
{
123
+
if (!nandc->props->supports_bam)
124
+
return;
125
+
126
+
if (is_cpu)
127
+
dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma,
128
+
MAX_REG_RD *
129
+
sizeof(*nandc->reg_read_buf),
130
+
DMA_FROM_DEVICE);
131
+
else
132
+
dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma,
133
+
MAX_REG_RD *
134
+
sizeof(*nandc->reg_read_buf),
135
+
DMA_FROM_DEVICE);
136
+
}
137
+
EXPORT_SYMBOL(qcom_nandc_dev_to_mem);
138
+
139
+
/**
140
+
* qcom_prepare_bam_async_desc() - Prepare DMA descriptor
141
+
* @nandc: qpic nand controller
142
+
* @chan: dma channel
143
+
* @flags: flags to control DMA descriptor preparation
144
+
*
145
+
* This function maps the scatter gather list for DMA transfer and forms the
146
+
* DMA descriptor for BAM.This descriptor will be added in the NAND DMA
147
+
* descriptor queue which will be submitted to DMA engine.
148
+
*/
149
+
int qcom_prepare_bam_async_desc(struct qcom_nand_controller *nandc,
150
+
struct dma_chan *chan, unsigned long flags)
151
+
{
152
+
struct desc_info *desc;
153
+
struct scatterlist *sgl;
154
+
unsigned int sgl_cnt;
155
+
int ret;
156
+
struct bam_transaction *bam_txn = nandc->bam_txn;
157
+
enum dma_transfer_direction dir_eng;
158
+
struct dma_async_tx_descriptor *dma_desc;
159
+
160
+
desc = kzalloc(sizeof(*desc), GFP_KERNEL);
161
+
if (!desc)
162
+
return -ENOMEM;
163
+
164
+
if (chan == nandc->cmd_chan) {
165
+
sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start];
166
+
sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
167
+
bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
168
+
dir_eng = DMA_MEM_TO_DEV;
169
+
desc->dir = DMA_TO_DEVICE;
170
+
} else if (chan == nandc->tx_chan) {
171
+
sgl = &bam_txn->data_sgl[bam_txn->tx_sgl_start];
172
+
sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
173
+
bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
174
+
dir_eng = DMA_MEM_TO_DEV;
175
+
desc->dir = DMA_TO_DEVICE;
176
+
} else {
177
+
sgl = &bam_txn->data_sgl[bam_txn->rx_sgl_start];
178
+
sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
179
+
bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
180
+
dir_eng = DMA_DEV_TO_MEM;
181
+
desc->dir = DMA_FROM_DEVICE;
182
+
}
183
+
184
+
sg_mark_end(sgl + sgl_cnt - 1);
185
+
ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
186
+
if (ret == 0) {
187
+
dev_err(nandc->dev, "failure in mapping desc\n");
188
+
kfree(desc);
189
+
return -ENOMEM;
190
+
}
191
+
192
+
desc->sgl_cnt = sgl_cnt;
193
+
desc->bam_sgl = sgl;
194
+
195
+
dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
196
+
flags);
197
+
198
+
if (!dma_desc) {
199
+
dev_err(nandc->dev, "failure in prep desc\n");
200
+
dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
201
+
kfree(desc);
202
+
return -EINVAL;
203
+
}
204
+
205
+
desc->dma_desc = dma_desc;
206
+
207
+
/* update last data/command descriptor */
208
+
if (chan == nandc->cmd_chan)
209
+
bam_txn->last_cmd_desc = dma_desc;
210
+
else
211
+
bam_txn->last_data_desc = dma_desc;
212
+
213
+
list_add_tail(&desc->node, &nandc->desc_list);
214
+
215
+
return 0;
216
+
}
217
+
EXPORT_SYMBOL(qcom_prepare_bam_async_desc);
218
+
219
+
/**
220
+
* qcom_prep_bam_dma_desc_cmd() - Prepares the command descriptor for BAM DMA
221
+
* @nandc: qpic nand controller
222
+
* @read: read or write type
223
+
* @reg_off: offset within the controller's data buffer
224
+
* @vaddr: virtual address of the buffer we want to write to
225
+
* @size: DMA transaction size in bytes
226
+
* @flags: flags to control DMA descriptor preparation
227
+
*
228
+
* This function will prepares the command descriptor for BAM DMA
229
+
* which will be used for NAND register reads and writes.
230
+
*/
231
+
int qcom_prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
232
+
int reg_off, const void *vaddr,
233
+
int size, unsigned int flags)
234
+
{
235
+
int bam_ce_size;
236
+
int i, ret;
237
+
struct bam_cmd_element *bam_ce_buffer;
238
+
struct bam_transaction *bam_txn = nandc->bam_txn;
239
+
240
+
bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
241
+
242
+
/* fill the command desc */
243
+
for (i = 0; i < size; i++) {
244
+
if (read)
245
+
bam_prep_ce(&bam_ce_buffer[i],
246
+
nandc_reg_phys(nandc, reg_off + 4 * i),
247
+
BAM_READ_COMMAND,
248
+
reg_buf_dma_addr(nandc,
249
+
(__le32 *)vaddr + i));
250
+
else
251
+
bam_prep_ce_le32(&bam_ce_buffer[i],
252
+
nandc_reg_phys(nandc, reg_off + 4 * i),
253
+
BAM_WRITE_COMMAND,
254
+
*((__le32 *)vaddr + i));
255
+
}
256
+
257
+
bam_txn->bam_ce_pos += size;
258
+
259
+
/* use the separate sgl after this command */
260
+
if (flags & NAND_BAM_NEXT_SGL) {
261
+
bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
262
+
bam_ce_size = (bam_txn->bam_ce_pos -
263
+
bam_txn->bam_ce_start) *
264
+
sizeof(struct bam_cmd_element);
265
+
sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
266
+
bam_ce_buffer, bam_ce_size);
267
+
bam_txn->cmd_sgl_pos++;
268
+
bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
269
+
270
+
if (flags & NAND_BAM_NWD) {
271
+
ret = qcom_prepare_bam_async_desc(nandc, nandc->cmd_chan,
272
+
DMA_PREP_FENCE | DMA_PREP_CMD);
273
+
if (ret)
274
+
return ret;
275
+
}
276
+
}
277
+
278
+
return 0;
279
+
}
280
+
EXPORT_SYMBOL(qcom_prep_bam_dma_desc_cmd);
281
+
282
+
/**
283
+
* qcom_prep_bam_dma_desc_data() - Prepares the data descriptor for BAM DMA
284
+
* @nandc: qpic nand controller
285
+
* @read: read or write type
286
+
* @vaddr: virtual address of the buffer we want to write to
287
+
* @size: DMA transaction size in bytes
288
+
* @flags: flags to control DMA descriptor preparation
289
+
*
290
+
* This function will prepares the data descriptor for BAM DMA which
291
+
* will be used for NAND data reads and writes.
292
+
*/
293
+
int qcom_prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
294
+
const void *vaddr, int size, unsigned int flags)
295
+
{
296
+
int ret;
297
+
struct bam_transaction *bam_txn = nandc->bam_txn;
298
+
299
+
if (read) {
300
+
sg_set_buf(&bam_txn->data_sgl[bam_txn->rx_sgl_pos],
301
+
vaddr, size);
302
+
bam_txn->rx_sgl_pos++;
303
+
} else {
304
+
sg_set_buf(&bam_txn->data_sgl[bam_txn->tx_sgl_pos],
305
+
vaddr, size);
306
+
bam_txn->tx_sgl_pos++;
307
+
308
+
/*
309
+
* BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
310
+
* is not set, form the DMA descriptor
311
+
*/
312
+
if (!(flags & NAND_BAM_NO_EOT)) {
313
+
ret = qcom_prepare_bam_async_desc(nandc, nandc->tx_chan,
314
+
DMA_PREP_INTERRUPT);
315
+
if (ret)
316
+
return ret;
317
+
}
318
+
}
319
+
320
+
return 0;
321
+
}
322
+
EXPORT_SYMBOL(qcom_prep_bam_dma_desc_data);
323
+
324
+
/**
325
+
* qcom_prep_adm_dma_desc() - Prepare descriptor for adma
326
+
* @nandc: qpic nand controller
327
+
* @read: read or write type
328
+
* @reg_off: offset within the controller's data buffer
329
+
* @vaddr: virtual address of the buffer we want to write to
330
+
* @size: adm dma transaction size in bytes
331
+
* @flow_control: flow controller
332
+
*
333
+
* This function will prepare descriptor for adma
334
+
*/
335
+
int qcom_prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
336
+
int reg_off, const void *vaddr, int size,
337
+
bool flow_control)
338
+
{
339
+
struct qcom_adm_peripheral_config periph_conf = {};
340
+
struct dma_async_tx_descriptor *dma_desc;
341
+
struct dma_slave_config slave_conf = {0};
342
+
enum dma_transfer_direction dir_eng;
343
+
struct desc_info *desc;
344
+
struct scatterlist *sgl;
345
+
int ret;
346
+
347
+
desc = kzalloc(sizeof(*desc), GFP_KERNEL);
348
+
if (!desc)
349
+
return -ENOMEM;
350
+
351
+
sgl = &desc->adm_sgl;
352
+
353
+
sg_init_one(sgl, vaddr, size);
354
+
355
+
if (read) {
356
+
dir_eng = DMA_DEV_TO_MEM;
357
+
desc->dir = DMA_FROM_DEVICE;
358
+
} else {
359
+
dir_eng = DMA_MEM_TO_DEV;
360
+
desc->dir = DMA_TO_DEVICE;
361
+
}
362
+
363
+
ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir);
364
+
if (!ret) {
365
+
ret = -ENOMEM;
366
+
goto err;
367
+
}
368
+
369
+
slave_conf.device_fc = flow_control;
370
+
if (read) {
371
+
slave_conf.src_maxburst = 16;
372
+
slave_conf.src_addr = nandc->base_dma + reg_off;
373
+
if (nandc->data_crci) {
374
+
periph_conf.crci = nandc->data_crci;
375
+
slave_conf.peripheral_config = &periph_conf;
376
+
slave_conf.peripheral_size = sizeof(periph_conf);
377
+
}
378
+
} else {
379
+
slave_conf.dst_maxburst = 16;
380
+
slave_conf.dst_addr = nandc->base_dma + reg_off;
381
+
if (nandc->cmd_crci) {
382
+
periph_conf.crci = nandc->cmd_crci;
383
+
slave_conf.peripheral_config = &periph_conf;
384
+
slave_conf.peripheral_size = sizeof(periph_conf);
385
+
}
386
+
}
387
+
388
+
ret = dmaengine_slave_config(nandc->chan, &slave_conf);
389
+
if (ret) {
390
+
dev_err(nandc->dev, "failed to configure dma channel\n");
391
+
goto err;
392
+
}
393
+
394
+
dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0);
395
+
if (!dma_desc) {
396
+
dev_err(nandc->dev, "failed to prepare desc\n");
397
+
ret = -EINVAL;
398
+
goto err;
399
+
}
400
+
401
+
desc->dma_desc = dma_desc;
402
+
403
+
list_add_tail(&desc->node, &nandc->desc_list);
404
+
405
+
return 0;
406
+
err:
407
+
kfree(desc);
408
+
409
+
return ret;
410
+
}
411
+
EXPORT_SYMBOL(qcom_prep_adm_dma_desc);
412
+
413
+
/**
414
+
* qcom_read_reg_dma() - read a given number of registers to the reg_read_buf pointer
415
+
* @nandc: qpic nand controller
416
+
* @first: offset of the first register in the contiguous block
417
+
* @num_regs: number of registers to read
418
+
* @flags: flags to control DMA descriptor preparation
419
+
*
420
+
* This function will prepares a descriptor to read a given number of
421
+
* contiguous registers to the reg_read_buf pointer.
422
+
*/
423
+
int qcom_read_reg_dma(struct qcom_nand_controller *nandc, int first,
424
+
int num_regs, unsigned int flags)
425
+
{
426
+
bool flow_control = false;
427
+
void *vaddr;
428
+
429
+
vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
430
+
nandc->reg_read_pos += num_regs;
431
+
432
+
if (first == NAND_DEV_CMD_VLD || first == NAND_DEV_CMD1)
433
+
first = dev_cmd_reg_addr(nandc, first);
434
+
435
+
if (nandc->props->supports_bam)
436
+
return qcom_prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
437
+
num_regs, flags);
438
+
439
+
if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
440
+
flow_control = true;
441
+
442
+
return qcom_prep_adm_dma_desc(nandc, true, first, vaddr,
443
+
num_regs * sizeof(u32), flow_control);
444
+
}
445
+
EXPORT_SYMBOL(qcom_read_reg_dma);
446
+
447
+
/**
448
+
* qcom_write_reg_dma() - write a given number of registers
449
+
* @nandc: qpic nand controller
450
+
* @vaddr: contiguous memory from where register value will
451
+
* be written
452
+
* @first: offset of the first register in the contiguous block
453
+
* @num_regs: number of registers to write
454
+
* @flags: flags to control DMA descriptor preparation
455
+
*
456
+
* This function will prepares a descriptor to write a given number of
457
+
* contiguous registers
458
+
*/
459
+
int qcom_write_reg_dma(struct qcom_nand_controller *nandc, __le32 *vaddr,
460
+
int first, int num_regs, unsigned int flags)
461
+
{
462
+
bool flow_control = false;
463
+
464
+
if (first == NAND_EXEC_CMD)
465
+
flags |= NAND_BAM_NWD;
466
+
467
+
if (first == NAND_DEV_CMD1_RESTORE || first == NAND_DEV_CMD1)
468
+
first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD1);
469
+
470
+
if (first == NAND_DEV_CMD_VLD_RESTORE || first == NAND_DEV_CMD_VLD)
471
+
first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD);
472
+
473
+
if (nandc->props->supports_bam)
474
+
return qcom_prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
475
+
num_regs, flags);
476
+
477
+
if (first == NAND_FLASH_CMD)
478
+
flow_control = true;
479
+
480
+
return qcom_prep_adm_dma_desc(nandc, false, first, vaddr,
481
+
num_regs * sizeof(u32), flow_control);
482
+
}
483
+
EXPORT_SYMBOL(qcom_write_reg_dma);
484
+
485
+
/**
486
+
* qcom_read_data_dma() - transfer data
487
+
* @nandc: qpic nand controller
488
+
* @reg_off: offset within the controller's data buffer
489
+
* @vaddr: virtual address of the buffer we want to write to
490
+
* @size: DMA transaction size in bytes
491
+
* @flags: flags to control DMA descriptor preparation
492
+
*
493
+
* This function will prepares a DMA descriptor to transfer data from the
494
+
* controller's internal buffer to the buffer 'vaddr'
495
+
*/
496
+
int qcom_read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
497
+
const u8 *vaddr, int size, unsigned int flags)
498
+
{
499
+
if (nandc->props->supports_bam)
500
+
return qcom_prep_bam_dma_desc_data(nandc, true, vaddr, size, flags);
501
+
502
+
return qcom_prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
503
+
}
504
+
EXPORT_SYMBOL(qcom_read_data_dma);
505
+
506
+
/**
507
+
* qcom_write_data_dma() - transfer data
508
+
* @nandc: qpic nand controller
509
+
* @reg_off: offset within the controller's data buffer
510
+
* @vaddr: virtual address of the buffer we want to read from
511
+
* @size: DMA transaction size in bytes
512
+
* @flags: flags to control DMA descriptor preparation
513
+
*
514
+
* This function will prepares a DMA descriptor to transfer data from
515
+
* 'vaddr' to the controller's internal buffer
516
+
*/
517
+
int qcom_write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
518
+
const u8 *vaddr, int size, unsigned int flags)
519
+
{
520
+
if (nandc->props->supports_bam)
521
+
return qcom_prep_bam_dma_desc_data(nandc, false, vaddr, size, flags);
522
+
523
+
return qcom_prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
524
+
}
525
+
EXPORT_SYMBOL(qcom_write_data_dma);
526
+
527
+
/**
528
+
* qcom_submit_descs() - submit dma descriptor
529
+
* @nandc: qpic nand controller
530
+
*
531
+
* This function will submit all the prepared dma descriptor
532
+
* cmd or data descriptor
533
+
*/
534
+
int qcom_submit_descs(struct qcom_nand_controller *nandc)
535
+
{
536
+
struct desc_info *desc, *n;
537
+
dma_cookie_t cookie = 0;
538
+
struct bam_transaction *bam_txn = nandc->bam_txn;
539
+
int ret = 0;
540
+
541
+
if (nandc->props->supports_bam) {
542
+
if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) {
543
+
ret = qcom_prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
544
+
if (ret)
545
+
goto err_unmap_free_desc;
546
+
}
547
+
548
+
if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) {
549
+
ret = qcom_prepare_bam_async_desc(nandc, nandc->tx_chan,
550
+
DMA_PREP_INTERRUPT);
551
+
if (ret)
552
+
goto err_unmap_free_desc;
553
+
}
554
+
555
+
if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) {
556
+
ret = qcom_prepare_bam_async_desc(nandc, nandc->cmd_chan,
557
+
DMA_PREP_CMD);
558
+
if (ret)
559
+
goto err_unmap_free_desc;
560
+
}
561
+
}
562
+
563
+
list_for_each_entry(desc, &nandc->desc_list, node)
564
+
cookie = dmaengine_submit(desc->dma_desc);
565
+
566
+
if (nandc->props->supports_bam) {
567
+
bam_txn->last_cmd_desc->callback = qcom_qpic_bam_dma_done;
568
+
bam_txn->last_cmd_desc->callback_param = bam_txn;
569
+
570
+
dma_async_issue_pending(nandc->tx_chan);
571
+
dma_async_issue_pending(nandc->rx_chan);
572
+
dma_async_issue_pending(nandc->cmd_chan);
573
+
574
+
if (!wait_for_completion_timeout(&bam_txn->txn_done,
575
+
QPIC_NAND_COMPLETION_TIMEOUT))
576
+
ret = -ETIMEDOUT;
577
+
} else {
578
+
if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
579
+
ret = -ETIMEDOUT;
580
+
}
581
+
582
+
err_unmap_free_desc:
583
+
/*
584
+
* Unmap the dma sg_list and free the desc allocated by both
585
+
* qcom_prepare_bam_async_desc() and qcom_prep_adm_dma_desc() functions.
586
+
*/
587
+
list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
588
+
list_del(&desc->node);
589
+
590
+
if (nandc->props->supports_bam)
591
+
dma_unmap_sg(nandc->dev, desc->bam_sgl,
592
+
desc->sgl_cnt, desc->dir);
593
+
else
594
+
dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1,
595
+
desc->dir);
596
+
597
+
kfree(desc);
598
+
}
599
+
600
+
return ret;
601
+
}
602
+
EXPORT_SYMBOL(qcom_submit_descs);
603
+
604
+
/**
605
+
* qcom_clear_read_regs() - reset the read register buffer
606
+
* @nandc: qpic nand controller
607
+
*
608
+
* This function reset the register read buffer for next NAND operation
609
+
*/
610
+
void qcom_clear_read_regs(struct qcom_nand_controller *nandc)
611
+
{
612
+
nandc->reg_read_pos = 0;
613
+
qcom_nandc_dev_to_mem(nandc, false);
614
+
}
615
+
EXPORT_SYMBOL(qcom_clear_read_regs);
616
+
617
+
/**
618
+
* qcom_nandc_unalloc() - unallocate qpic nand controller
619
+
* @nandc: qpic nand controller
620
+
*
621
+
* This function will unallocate memory alloacted for qpic nand controller
622
+
*/
623
+
void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
624
+
{
625
+
if (nandc->props->supports_bam) {
626
+
if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma))
627
+
dma_unmap_single(nandc->dev, nandc->reg_read_dma,
628
+
MAX_REG_RD *
629
+
sizeof(*nandc->reg_read_buf),
630
+
DMA_FROM_DEVICE);
631
+
632
+
if (nandc->tx_chan)
633
+
dma_release_channel(nandc->tx_chan);
634
+
635
+
if (nandc->rx_chan)
636
+
dma_release_channel(nandc->rx_chan);
637
+
638
+
if (nandc->cmd_chan)
639
+
dma_release_channel(nandc->cmd_chan);
640
+
} else {
641
+
if (nandc->chan)
642
+
dma_release_channel(nandc->chan);
643
+
}
644
+
}
645
+
EXPORT_SYMBOL(qcom_nandc_unalloc);
646
+
647
+
/**
648
+
* qcom_nandc_alloc() - Allocate qpic nand controller
649
+
* @nandc: qpic nand controller
650
+
*
651
+
* This function will allocate memory for qpic nand controller
652
+
*/
653
+
int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
654
+
{
655
+
int ret;
656
+
657
+
ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32));
658
+
if (ret) {
659
+
dev_err(nandc->dev, "failed to set DMA mask\n");
660
+
return ret;
661
+
}
662
+
663
+
/*
664
+
* we use the internal buffer for reading ONFI params, reading small
665
+
* data like ID and status, and preforming read-copy-write operations
666
+
* when writing to a codeword partially. 532 is the maximum possible
667
+
* size of a codeword for our nand controller
668
+
*/
669
+
nandc->buf_size = 532;
670
+
671
+
nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size, GFP_KERNEL);
672
+
if (!nandc->data_buffer)
673
+
return -ENOMEM;
674
+
675
+
nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs), GFP_KERNEL);
676
+
if (!nandc->regs)
677
+
return -ENOMEM;
678
+
679
+
nandc->reg_read_buf = devm_kcalloc(nandc->dev, MAX_REG_RD,
680
+
sizeof(*nandc->reg_read_buf),
681
+
GFP_KERNEL);
682
+
if (!nandc->reg_read_buf)
683
+
return -ENOMEM;
684
+
685
+
if (nandc->props->supports_bam) {
686
+
nandc->reg_read_dma =
687
+
dma_map_single(nandc->dev, nandc->reg_read_buf,
688
+
MAX_REG_RD *
689
+
sizeof(*nandc->reg_read_buf),
690
+
DMA_FROM_DEVICE);
691
+
if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) {
692
+
dev_err(nandc->dev, "failed to DMA MAP reg buffer\n");
693
+
return -EIO;
694
+
}
695
+
696
+
nandc->tx_chan = dma_request_chan(nandc->dev, "tx");
697
+
if (IS_ERR(nandc->tx_chan)) {
698
+
ret = PTR_ERR(nandc->tx_chan);
699
+
nandc->tx_chan = NULL;
700
+
dev_err_probe(nandc->dev, ret,
701
+
"tx DMA channel request failed\n");
702
+
goto unalloc;
703
+
}
704
+
705
+
nandc->rx_chan = dma_request_chan(nandc->dev, "rx");
706
+
if (IS_ERR(nandc->rx_chan)) {
707
+
ret = PTR_ERR(nandc->rx_chan);
708
+
nandc->rx_chan = NULL;
709
+
dev_err_probe(nandc->dev, ret,
710
+
"rx DMA channel request failed\n");
711
+
goto unalloc;
712
+
}
713
+
714
+
nandc->cmd_chan = dma_request_chan(nandc->dev, "cmd");
715
+
if (IS_ERR(nandc->cmd_chan)) {
716
+
ret = PTR_ERR(nandc->cmd_chan);
717
+
nandc->cmd_chan = NULL;
718
+
dev_err_probe(nandc->dev, ret,
719
+
"cmd DMA channel request failed\n");
720
+
goto unalloc;
721
+
}
722
+
723
+
/*
724
+
* Initially allocate BAM transaction to read ONFI param page.
725
+
* After detecting all the devices, this BAM transaction will
726
+
* be freed and the next BAM transaction will be allocated with
727
+
* maximum codeword size
728
+
*/
729
+
nandc->max_cwperpage = 1;
730
+
nandc->bam_txn = qcom_alloc_bam_transaction(nandc);
731
+
if (!nandc->bam_txn) {
732
+
dev_err(nandc->dev,
733
+
"failed to allocate bam transaction\n");
734
+
ret = -ENOMEM;
735
+
goto unalloc;
736
+
}
737
+
} else {
738
+
nandc->chan = dma_request_chan(nandc->dev, "rxtx");
739
+
if (IS_ERR(nandc->chan)) {
740
+
ret = PTR_ERR(nandc->chan);
741
+
nandc->chan = NULL;
742
+
dev_err_probe(nandc->dev, ret,
743
+
"rxtx DMA channel request failed\n");
744
+
return ret;
745
+
}
746
+
}
747
+
748
+
INIT_LIST_HEAD(&nandc->desc_list);
749
+
INIT_LIST_HEAD(&nandc->host_list);
750
+
751
+
return 0;
752
+
unalloc:
753
+
qcom_nandc_unalloc(nandc);
754
+
return ret;
755
+
}
756
+
EXPORT_SYMBOL(qcom_nandc_alloc);
757
+
758
+
MODULE_DESCRIPTION("QPIC controller common api");
759
+
MODULE_LICENSE("GPL");
+10
-2
drivers/mtd/nand/raw/Kconfig
+10
-2
drivers/mtd/nand/raw/Kconfig
···
279
279
280
280
config MTD_NAND_DAVINCI
281
281
tristate "DaVinci/Keystone NAND controller"
282
-
depends on ARCH_DAVINCI || (ARCH_KEYSTONE && TI_AEMIF) || COMPILE_TEST
283
-
depends on HAS_IOMEM
282
+
depends on COMPILE_TEST || ARCH_DAVINCI || ARCH_KEYSTONE
283
+
depends on HAS_IOMEM && TI_AEMIF
284
284
help
285
285
Enable the driver for NAND flash chips on Texas Instruments
286
286
DaVinci/Keystone processors.
···
453
453
depends on ARCH_EP93XX && HAS_IOMEM
454
454
help
455
455
Enables support for NAND controller on ts72xx SBCs.
456
+
457
+
config MTD_NAND_NUVOTON_MA35
458
+
tristate "Nuvoton MA35 SoC NAND controller"
459
+
depends on ARCH_MA35 || COMPILE_TEST
460
+
depends on OF
461
+
help
462
+
Enables support for the NAND controller found on
463
+
the Nuvoton MA35 series SoCs.
456
464
457
465
comment "Misc"
458
466
+1
drivers/mtd/nand/raw/Makefile
+1
drivers/mtd/nand/raw/Makefile
···
58
58
obj-$(CONFIG_MTD_NAND_ROCKCHIP) += rockchip-nand-controller.o
59
59
obj-$(CONFIG_MTD_NAND_PL35X) += pl35x-nand-controller.o
60
60
obj-$(CONFIG_MTD_NAND_RENESAS) += renesas-nand-controller.o
61
+
obj-$(CONFIG_MTD_NAND_NUVOTON_MA35) += nuvoton-ma35d1-nand-controller.o
61
62
62
63
nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o
63
64
nand-objs += nand_onfi.o
+5
drivers/mtd/nand/raw/brcmnand/brcmnand.c
+5
drivers/mtd/nand/raw/brcmnand/brcmnand.c
···
2342
2342
brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
2343
2343
status = brcmnand_waitfunc(chip);
2344
2344
2345
+
if (status < 0) {
2346
+
ret = status;
2347
+
goto out;
2348
+
}
2349
+
2345
2350
if (status & NAND_STATUS_FAIL) {
2346
2351
dev_info(ctrl->dev, "program failed at %llx\n",
2347
2352
(unsigned long long)addr);
+134
-3
drivers/mtd/nand/raw/davinci_nand.c
+134
-3
drivers/mtd/nand/raw/davinci_nand.c
···
10
10
* Dirk Behme <Dirk.Behme@gmail.com>
11
11
*/
12
12
13
+
#include <linux/clk.h>
13
14
#include <linux/err.h>
14
15
#include <linux/iopoll.h>
15
16
#include <linux/kernel.h>
17
+
#include <linux/memory/ti-aemif.h>
16
18
#include <linux/module.h>
17
19
#include <linux/mtd/partitions.h>
18
20
#include <linux/mtd/rawnand.h>
···
45
43
#define MASK_ALE 0x08
46
44
#define MASK_CLE 0x10
47
45
46
+
#define MAX_TSU_PS 3000 /* Input setup time in ps */
47
+
#define MAX_TH_PS 1600 /* Input hold time in ps */
48
+
48
49
struct davinci_nand_pdata {
49
50
uint32_t mask_ale;
50
51
uint32_t mask_cle;
···
71
66
72
67
/* none == NAND_ECC_ENGINE_TYPE_NONE (strongly *not* advised!!)
73
68
* soft == NAND_ECC_ENGINE_TYPE_SOFT
69
+
* on-die == NAND_ECC_ENGINE_TYPE_ON_DIE
74
70
* else == NAND_ECC_ENGINE_TYPE_ON_HOST, according to ecc_bits
75
71
*
76
72
* All DaVinci-family chips support 1-bit hardware ECC.
···
123
117
uint32_t mask_cle;
124
118
125
119
uint32_t core_chipsel;
120
+
121
+
struct clk *clk;
122
+
struct aemif_device *aemif;
126
123
};
127
124
128
125
static DEFINE_SPINLOCK(davinci_nand_lock);
···
488
479
.free = hwecc4_ooblayout_small_free,
489
480
};
490
481
482
+
static int hwecc4_ooblayout_large_ecc(struct mtd_info *mtd, int section,
483
+
struct mtd_oob_region *oobregion)
484
+
{
485
+
struct nand_device *nand = mtd_to_nanddev(mtd);
486
+
unsigned int total_ecc_bytes = nand->ecc.ctx.total;
487
+
int nregions = total_ecc_bytes / 10; /* 10 bytes per chunk */
488
+
489
+
if (section >= nregions)
490
+
return -ERANGE;
491
+
492
+
oobregion->offset = (section * 16) + 6;
493
+
oobregion->length = 10;
494
+
495
+
return 0;
496
+
}
497
+
498
+
static int hwecc4_ooblayout_large_free(struct mtd_info *mtd, int section,
499
+
struct mtd_oob_region *oobregion)
500
+
{
501
+
struct nand_device *nand = mtd_to_nanddev(mtd);
502
+
unsigned int total_ecc_bytes = nand->ecc.ctx.total;
503
+
int nregions = total_ecc_bytes / 10; /* 10 bytes per chunk */
504
+
505
+
/* First region is used for BBT */
506
+
if (section >= (nregions - 1))
507
+
return -ERANGE;
508
+
509
+
oobregion->offset = ((section + 1) * 16);
510
+
oobregion->length = 6;
511
+
512
+
return 0;
513
+
}
514
+
515
+
static const struct mtd_ooblayout_ops hwecc4_large_ooblayout_ops = {
516
+
.ecc = hwecc4_ooblayout_large_ecc,
517
+
.free = hwecc4_ooblayout_large_free,
518
+
};
519
+
491
520
#if defined(CONFIG_OF)
492
521
static const struct of_device_id davinci_nand_of_match[] = {
493
522
{.compatible = "ti,davinci-nand", },
···
572
525
pdata->engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
573
526
if (!strncmp("hw", mode, 2))
574
527
pdata->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
528
+
if (!strncmp("on-die", mode, 6))
529
+
pdata->engine_type = NAND_ECC_ENGINE_TYPE_ON_DIE;
575
530
}
576
531
if (!device_property_read_u32(&pdev->dev,
577
532
"ti,davinci-ecc-bits", &prop))
···
629
580
630
581
switch (chip->ecc.engine_type) {
631
582
case NAND_ECC_ENGINE_TYPE_NONE:
583
+
case NAND_ECC_ENGINE_TYPE_ON_DIE:
632
584
pdata->ecc_bits = 0;
633
585
break;
634
586
case NAND_ECC_ENGINE_TYPE_SOFT:
···
688
638
mtd_set_ooblayout(mtd,
689
639
&hwecc4_small_ooblayout_ops);
690
640
} else if (chunks == 4 || chunks == 8) {
691
-
mtd_set_ooblayout(mtd,
692
-
nand_get_large_page_ooblayout());
693
641
chip->ecc.read_page = nand_read_page_hwecc_oob_first;
642
+
643
+
if (chip->options & NAND_IS_BOOT_MEDIUM)
644
+
mtd_set_ooblayout(mtd, &hwecc4_large_ooblayout_ops);
645
+
else
646
+
mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());
694
647
} else {
695
648
return -EIO;
696
649
}
···
777
724
case NAND_OP_WAITRDY_INSTR:
778
725
timeout_us = instr->ctx.waitrdy.timeout_ms * 1000;
779
726
ret = readl_relaxed_poll_timeout(info->base + NANDFSR_OFFSET,
780
-
status, status & BIT(0), 100,
727
+
status, status & BIT(0), 5,
781
728
timeout_us);
782
729
if (ret)
783
730
return ret;
···
817
764
return 0;
818
765
}
819
766
767
+
#define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP((ps) / 1000, (period_ns)))
768
+
769
+
static int davinci_nand_setup_interface(struct nand_chip *chip, int chipnr,
770
+
const struct nand_interface_config *conf)
771
+
{
772
+
struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
773
+
const struct nand_sdr_timings *sdr;
774
+
struct aemif_cs_timings timings;
775
+
s32 cfg, min, cyc_ns;
776
+
int ret;
777
+
778
+
cyc_ns = 1000000000 / clk_get_rate(info->clk);
779
+
780
+
sdr = nand_get_sdr_timings(conf);
781
+
if (IS_ERR(sdr))
782
+
return PTR_ERR(sdr);
783
+
784
+
cfg = TO_CYCLES(sdr->tCLR_min, cyc_ns) - 1;
785
+
timings.rsetup = cfg > 0 ? cfg : 0;
786
+
787
+
cfg = max_t(s32, TO_CYCLES(sdr->tREA_max + MAX_TSU_PS, cyc_ns),
788
+
TO_CYCLES(sdr->tRP_min, cyc_ns)) - 1;
789
+
timings.rstrobe = cfg > 0 ? cfg : 0;
790
+
791
+
min = TO_CYCLES(sdr->tCEA_max + MAX_TSU_PS, cyc_ns) - 2;
792
+
while ((s32)(timings.rsetup + timings.rstrobe) < min)
793
+
timings.rstrobe++;
794
+
795
+
cfg = TO_CYCLES((s32)(MAX_TH_PS - sdr->tCHZ_max), cyc_ns) - 1;
796
+
timings.rhold = cfg > 0 ? cfg : 0;
797
+
798
+
min = TO_CYCLES(sdr->tRC_min, cyc_ns) - 3;
799
+
while ((s32)(timings.rsetup + timings.rstrobe + timings.rhold) < min)
800
+
timings.rhold++;
801
+
802
+
cfg = TO_CYCLES((s32)(sdr->tRHZ_max - (timings.rhold + 1) * cyc_ns * 1000), cyc_ns);
803
+
cfg = max_t(s32, cfg, TO_CYCLES(sdr->tCHZ_max, cyc_ns)) - 1;
804
+
timings.ta = cfg > 0 ? cfg : 0;
805
+
806
+
cfg = TO_CYCLES(sdr->tWP_min, cyc_ns) - 1;
807
+
timings.wstrobe = cfg > 0 ? cfg : 0;
808
+
809
+
cfg = max_t(s32, TO_CYCLES(sdr->tCLS_min, cyc_ns), TO_CYCLES(sdr->tALS_min, cyc_ns));
810
+
cfg = max_t(s32, cfg, TO_CYCLES(sdr->tCS_min, cyc_ns)) - 1;
811
+
timings.wsetup = cfg > 0 ? cfg : 0;
812
+
813
+
min = TO_CYCLES(sdr->tDS_min, cyc_ns) - 2;
814
+
while ((s32)(timings.wsetup + timings.wstrobe) < min)
815
+
timings.wstrobe++;
816
+
817
+
cfg = max_t(s32, TO_CYCLES(sdr->tCLH_min, cyc_ns), TO_CYCLES(sdr->tALH_min, cyc_ns));
818
+
cfg = max_t(s32, cfg, TO_CYCLES(sdr->tCH_min, cyc_ns));
819
+
cfg = max_t(s32, cfg, TO_CYCLES(sdr->tDH_min, cyc_ns)) - 1;
820
+
timings.whold = cfg > 0 ? cfg : 0;
821
+
822
+
min = TO_CYCLES(sdr->tWC_min, cyc_ns) - 2;
823
+
while ((s32)(timings.wsetup + timings.wstrobe + timings.whold) < min)
824
+
timings.whold++;
825
+
826
+
dev_dbg(&info->pdev->dev, "RSETUP %x RSTROBE %x RHOLD %x\n",
827
+
timings.rsetup, timings.rstrobe, timings.rhold);
828
+
dev_dbg(&info->pdev->dev, "TA %x\n", timings.ta);
829
+
dev_dbg(&info->pdev->dev, "WSETUP %x WSTROBE %x WHOLD %x\n",
830
+
timings.wsetup, timings.wstrobe, timings.whold);
831
+
832
+
ret = aemif_check_cs_timings(&timings);
833
+
if (ret || chipnr == NAND_DATA_IFACE_CHECK_ONLY)
834
+
return ret;
835
+
836
+
return aemif_set_cs_timings(info->aemif, info->core_chipsel, &timings);
837
+
}
838
+
820
839
static const struct nand_controller_ops davinci_nand_controller_ops = {
821
840
.attach_chip = davinci_nand_attach_chip,
822
841
.exec_op = davinci_nand_exec_op,
842
+
.setup_interface = davinci_nand_setup_interface,
823
843
};
824
844
825
845
static int nand_davinci_probe(struct platform_device *pdev)
···
948
822
return -EADDRNOTAVAIL;
949
823
}
950
824
825
+
info->clk = devm_clk_get_enabled(&pdev->dev, "aemif");
826
+
if (IS_ERR(info->clk))
827
+
return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), "failed to get clock");
828
+
951
829
info->pdev = pdev;
952
830
info->base = base;
953
831
info->vaddr = vaddr;
832
+
info->aemif = dev_get_drvdata(pdev->dev.parent);
954
833
955
834
mtd = nand_to_mtd(&info->chip);
956
835
mtd->dev.parent = &pdev->dev;
+1029
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
+1029
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (C) 2024 Nuvoton Technology Corp.
4
+
*/
5
+
#include <linux/clk.h>
6
+
#include <linux/dma-mapping.h>
7
+
#include <linux/err.h>
8
+
#include <linux/init.h>
9
+
#include <linux/interrupt.h>
10
+
#include <linux/io.h>
11
+
#include <linux/iopoll.h>
12
+
#include <linux/module.h>
13
+
#include <linux/mtd/mtd.h>
14
+
#include <linux/mtd/partitions.h>
15
+
#include <linux/mtd/rawnand.h>
16
+
#include <linux/of.h>
17
+
#include <linux/platform_device.h>
18
+
#include <linux/slab.h>
19
+
20
+
/* NFI Registers */
21
+
#define MA35_NFI_REG_DMACTL 0x400
22
+
#define DMA_EN BIT(0)
23
+
#define DMA_RST BIT(1)
24
+
#define DMA_BUSY BIT(9)
25
+
26
+
#define MA35_NFI_REG_DMASA 0x408
27
+
#define MA35_NFI_REG_GCTL 0x800
28
+
#define GRST BIT(0)
29
+
#define NAND_EN BIT(3)
30
+
31
+
#define MA35_NFI_REG_NANDCTL 0x8A0
32
+
#define SWRST BIT(0)
33
+
#define DMA_R_EN BIT(1)
34
+
#define DMA_W_EN BIT(2)
35
+
#define ECC_CHK BIT(7)
36
+
#define PROT3BEN BIT(8)
37
+
#define PSIZE_2K BIT(16)
38
+
#define PSIZE_4K BIT(17)
39
+
#define PSIZE_8K GENMASK(17, 16)
40
+
#define PSIZE_MASK GENMASK(17, 16)
41
+
#define BCH_T24 BIT(18)
42
+
#define BCH_T8 BIT(20)
43
+
#define BCH_T12 BIT(21)
44
+
#define BCH_NONE (0x0)
45
+
#define BCH_MASK GENMASK(22, 18)
46
+
#define ECC_EN BIT(23)
47
+
#define DISABLE_CS0 BIT(25)
48
+
49
+
#define MA35_NFI_REG_NANDINTEN 0x8A8
50
+
#define MA35_NFI_REG_NANDINTSTS 0x8AC
51
+
#define INT_DMA BIT(0)
52
+
#define INT_ECC BIT(2)
53
+
#define INT_RB0 BIT(10)
54
+
55
+
#define MA35_NFI_REG_NANDCMD 0x8B0
56
+
#define MA35_NFI_REG_NANDADDR 0x8B4
57
+
#define ENDADDR BIT(31)
58
+
59
+
#define MA35_NFI_REG_NANDDATA 0x8B8
60
+
#define MA35_NFI_REG_NANDRACTL 0x8BC
61
+
#define MA35_NFI_REG_NANDECTL 0x8C0
62
+
#define ENABLE_WP 0x0
63
+
#define DISABLE_WP BIT(0)
64
+
65
+
#define MA35_NFI_REG_NANDECCES0 0x8D0
66
+
#define ECC_STATUS_MASK GENMASK(1, 0)
67
+
#define ECC_ERR_CNT_MASK GENMASK(4, 0)
68
+
69
+
#define MA35_NFI_REG_NANDECCEA0 0x900
70
+
#define MA35_NFI_REG_NANDECCED0 0x960
71
+
#define MA35_NFI_REG_NANDRA0 0xA00
72
+
73
+
/* Define for the BCH hardware ECC engine */
74
+
/* define the total padding bytes for 512/1024 data segment */
75
+
#define MA35_BCH_PADDING_512 32
76
+
#define MA35_BCH_PADDING_1024 64
77
+
/* define the BCH parity code length for 512 bytes data pattern */
78
+
#define MA35_PARITY_BCH8 15
79
+
#define MA35_PARITY_BCH12 23
80
+
/* define the BCH parity code length for 1024 bytes data pattern */
81
+
#define MA35_PARITY_BCH24 45
82
+
83
+
#define MA35_MAX_NSELS (2)
84
+
#define PREFIX_RA_IS_EMPTY(reg) FIELD_GET(GENMASK(31, 16), (reg))
85
+
86
+
struct ma35_nand_chip {
87
+
struct list_head node;
88
+
struct nand_chip chip;
89
+
90
+
u32 eccstatus;
91
+
u8 nsels;
92
+
u8 sels[] __counted_by(nsels);
93
+
};
94
+
95
+
struct ma35_nand_info {
96
+
struct nand_controller controller;
97
+
struct device *dev;
98
+
void __iomem *regs;
99
+
int irq;
100
+
struct clk *clk;
101
+
struct completion complete;
102
+
struct list_head chips;
103
+
104
+
u8 *buffer;
105
+
unsigned long assigned_cs;
106
+
};
107
+
108
+
static inline struct ma35_nand_chip *to_ma35_nand(struct nand_chip *chip)
109
+
{
110
+
return container_of(chip, struct ma35_nand_chip, chip);
111
+
}
112
+
113
+
static int ma35_ooblayout_ecc(struct mtd_info *mtd, int section,
114
+
struct mtd_oob_region *oob_region)
115
+
{
116
+
struct nand_chip *chip = mtd_to_nand(mtd);
117
+
118
+
if (section)
119
+
return -ERANGE;
120
+
121
+
oob_region->length = chip->ecc.total;
122
+
oob_region->offset = mtd->oobsize - oob_region->length;
123
+
124
+
return 0;
125
+
}
126
+
127
+
static int ma35_ooblayout_free(struct mtd_info *mtd, int section,
128
+
struct mtd_oob_region *oob_region)
129
+
{
130
+
struct nand_chip *chip = mtd_to_nand(mtd);
131
+
132
+
if (section)
133
+
return -ERANGE;
134
+
135
+
oob_region->length = mtd->oobsize - chip->ecc.total - 2;
136
+
oob_region->offset = 2;
137
+
138
+
return 0;
139
+
}
140
+
141
+
static const struct mtd_ooblayout_ops ma35_ooblayout_ops = {
142
+
.free = ma35_ooblayout_free,
143
+
.ecc = ma35_ooblayout_ecc,
144
+
};
145
+
146
+
static inline void ma35_clear_spare(struct nand_chip *chip, int size)
147
+
{
148
+
struct ma35_nand_info *nand = nand_get_controller_data(chip);
149
+
int i;
150
+
151
+
for (i = 0; i < size / 4; i++)
152
+
writel(0xff, nand->regs + MA35_NFI_REG_NANDRA0);
153
+
}
154
+
155
+
static inline void read_remaining_bytes(struct ma35_nand_info *nand, u32 *buf,
156
+
u32 offset, int size, int swap)
157
+
{
158
+
u32 value = readl(nand->regs + MA35_NFI_REG_NANDRA0 + offset);
159
+
u8 *ptr = (u8 *)buf;
160
+
int i, shift;
161
+
162
+
for (i = 0; i < size; i++) {
163
+
shift = (swap ? 3 - i : i) * 8;
164
+
ptr[i] = (value >> shift) & 0xff;
165
+
}
166
+
}
167
+
168
+
static inline void ma35_read_spare(struct nand_chip *chip, int size, u32 *buf, u32 offset)
169
+
{
170
+
struct ma35_nand_info *nand = nand_get_controller_data(chip);
171
+
u32 off = round_down(offset, 4);
172
+
int len = offset % 4;
173
+
int i;
174
+
175
+
if (len) {
176
+
read_remaining_bytes(nand, buf, off, 4 - len, 1);
177
+
off += 4;
178
+
size -= (4 - len);
179
+
}
180
+
181
+
for (i = 0; i < size / 4; i++)
182
+
*buf++ = readl(nand->regs + MA35_NFI_REG_NANDRA0 + off + (i * 4));
183
+
184
+
read_remaining_bytes(nand, buf, off + (size & ~3), size % 4, 0);
185
+
}
186
+
187
+
static inline void ma35_write_spare(struct nand_chip *chip, int size, u32 *buf)
188
+
{
189
+
struct ma35_nand_info *nand = nand_get_controller_data(chip);
190
+
u32 value;
191
+
int i, j;
192
+
u8 *ptr;
193
+
194
+
for (i = 0, j = 0; i < size / 4; i++, j += 4)
195
+
writel(*buf++, nand->regs + MA35_NFI_REG_NANDRA0 + j);
196
+
197
+
ptr = (u8 *)buf;
198
+
switch (size % 4) {
199
+
case 1:
200
+
writel(*ptr, nand->regs + MA35_NFI_REG_NANDRA0 + j);
201
+
break;
202
+
case 2:
203
+
value = *ptr | (*(ptr + 1) << 8);
204
+
writel(value, nand->regs + MA35_NFI_REG_NANDRA0 + j);
205
+
break;
206
+
case 3:
207
+
value = *ptr | (*(ptr + 1) << 8) | (*(ptr + 2) << 16);
208
+
writel(value, nand->regs + MA35_NFI_REG_NANDRA0 + j);
209
+
break;
210
+
default:
211
+
break;
212
+
}
213
+
}
214
+
215
+
static void ma35_nand_target_enable(struct nand_chip *chip, unsigned int cs)
216
+
{
217
+
struct ma35_nand_info *nand = nand_get_controller_data(chip);
218
+
u32 reg;
219
+
220
+
switch (cs) {
221
+
case 0:
222
+
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
223
+
writel(reg & ~DISABLE_CS0, nand->regs + MA35_NFI_REG_NANDCTL);
224
+
225
+
reg = readl(nand->regs + MA35_NFI_REG_NANDINTSTS);
226
+
reg |= INT_RB0;
227
+
writel(reg, nand->regs + MA35_NFI_REG_NANDINTSTS);
228
+
break;
229
+
default:
230
+
break;
231
+
}
232
+
}
233
+
234
+
static int ma35_nand_hwecc_init(struct nand_chip *chip, struct ma35_nand_info *nand)
235
+
{
236
+
struct ma35_nand_chip *nvtnand = to_ma35_nand(chip);
237
+
struct mtd_info *mtd = nand_to_mtd(chip);
238
+
struct device *dev = mtd->dev.parent;
239
+
u32 reg;
240
+
241
+
nand->buffer = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
242
+
if (!nand->buffer)
243
+
return -ENOMEM;
244
+
245
+
/* Redundant area size */
246
+
writel(mtd->oobsize, nand->regs + MA35_NFI_REG_NANDRACTL);
247
+
248
+
/* Protect redundant 3 bytes and disable ECC engine */
249
+
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
250
+
reg |= (PROT3BEN | ECC_CHK);
251
+
reg &= ~ECC_EN;
252
+
253
+
if (chip->ecc.strength != 0) {
254
+
chip->ecc.steps = mtd->writesize / chip->ecc.size;
255
+
nvtnand->eccstatus = (chip->ecc.steps < 4) ? 1 : chip->ecc.steps / 4;
256
+
/* Set BCH algorithm */
257
+
reg &= ~BCH_MASK;
258
+
switch (chip->ecc.strength) {
259
+
case 8:
260
+
chip->ecc.total = chip->ecc.steps * MA35_PARITY_BCH8;
261
+
reg |= BCH_T8;
262
+
break;
263
+
case 12:
264
+
chip->ecc.total = chip->ecc.steps * MA35_PARITY_BCH12;
265
+
reg |= BCH_T12;
266
+
break;
267
+
case 24:
268
+
chip->ecc.total = chip->ecc.steps * MA35_PARITY_BCH24;
269
+
reg |= BCH_T24;
270
+
break;
271
+
default:
272
+
dev_err(nand->dev, "ECC strength unsupported\n");
273
+
return -EINVAL;
274
+
}
275
+
276
+
chip->ecc.bytes = chip->ecc.total / chip->ecc.steps;
277
+
}
278
+
writel(reg, nand->regs + MA35_NFI_REG_NANDCTL);
279
+
return 0;
280
+
}
281
+
282
+
/* Correct data by BCH alrogithm */
283
+
static void ma35_nfi_correct(struct nand_chip *chip, u8 index,
284
+
u8 err_cnt, u8 *addr)
285
+
{
286
+
struct ma35_nand_info *nand = nand_get_controller_data(chip);
287
+
u32 temp_data[24], temp_addr[24];
288
+
u32 padding_len, parity_len;
289
+
u32 value, offset, remain;
290
+
u32 err_data[6];
291
+
u8 i, j;
292
+
293
+
/* Configurations */
294
+
if (chip->ecc.strength <= 8) {
295
+
parity_len = MA35_PARITY_BCH8;
296
+
padding_len = MA35_BCH_PADDING_512;
297
+
} else if (chip->ecc.strength <= 12) {
298
+
parity_len = MA35_PARITY_BCH12;
299
+
padding_len = MA35_BCH_PADDING_512;
300
+
} else if (chip->ecc.strength <= 24) {
301
+
parity_len = MA35_PARITY_BCH24;
302
+
padding_len = MA35_BCH_PADDING_1024;
303
+
} else {
304
+
dev_err(nand->dev, "Invalid BCH_TSEL = 0x%lx\n",
305
+
readl(nand->regs + MA35_NFI_REG_NANDCTL) & BCH_MASK);
306
+
return;
307
+
}
308
+
309
+
/*
310
+
* got valid BCH_ECC_DATAx and parse them to temp_data[]
311
+
* got the valid register number of BCH_ECC_DATAx since
312
+
* one register include 4 error bytes
313
+
*/
314
+
j = (err_cnt + 3) / 4;
315
+
j = (j > 6) ? 6 : j;
316
+
for (i = 0; i < j; i++)
317
+
err_data[i] = readl(nand->regs + MA35_NFI_REG_NANDECCED0 + i * 4);
318
+
319
+
for (i = 0; i < j; i++) {
320
+
temp_data[i * 4 + 0] = err_data[i] & 0xff;
321
+
temp_data[i * 4 + 1] = (err_data[i] >> 8) & 0xff;
322
+
temp_data[i * 4 + 2] = (err_data[i] >> 16) & 0xff;
323
+
temp_data[i * 4 + 3] = (err_data[i] >> 24) & 0xff;
324
+
}
325
+
326
+
/*
327
+
* got valid REG_BCH_ECC_ADDRx and parse them to temp_addr[]
328
+
* got the valid register number of REG_BCH_ECC_ADDRx since
329
+
* one register include 2 error addresses
330
+
*/
331
+
j = (err_cnt + 1) / 2;
332
+
j = (j > 12) ? 12 : j;
333
+
for (i = 0; i < j; i++) {
334
+
temp_addr[i * 2 + 0] = readl(nand->regs + MA35_NFI_REG_NANDECCEA0 + i * 4)
335
+
& 0x07ff;
336
+
temp_addr[i * 2 + 1] = (readl(nand->regs + MA35_NFI_REG_NANDECCEA0 + i * 4)
337
+
>> 16) & 0x07ff;
338
+
}
339
+
340
+
/* pointer to begin address of field that with data error */
341
+
addr += index * chip->ecc.size;
342
+
343
+
/* correct each error bytes */
344
+
for (i = 0; i < err_cnt; i++) {
345
+
u32 corrected_index = temp_addr[i];
346
+
347
+
if (corrected_index < chip->ecc.size) {
348
+
/* for wrong data in field */
349
+
*(addr + corrected_index) ^= temp_data[i];
350
+
} else if (corrected_index < (chip->ecc.size + 3)) {
351
+
/* for wrong first-3-bytes in redundancy area */
352
+
corrected_index -= chip->ecc.size;
353
+
temp_addr[i] += (parity_len * index); /* field offset */
354
+
355
+
value = readl(nand->regs + MA35_NFI_REG_NANDRA0);
356
+
value ^= temp_data[i] << (8 * corrected_index);
357
+
writel(value, nand->regs + MA35_NFI_REG_NANDRA0);
358
+
} else {
359
+
/*
360
+
* for wrong parity code in redundancy area
361
+
* ERR_ADDRx = [data in field] + [3 bytes] + [xx] + [parity code]
362
+
* |<-- padding bytes -->|
363
+
* The ERR_ADDRx for last parity code always = field size + padding size.
364
+
* The first parity code = field size + padding size - parity code length.
365
+
* For example, for BCH T12, the first parity code = 512 + 32 - 23 = 521.
366
+
* That is, error byte address offset within field is
367
+
*/
368
+
corrected_index -= (chip->ecc.size + padding_len - parity_len);
369
+
370
+
/*
371
+
* final address = first parity code of first field +
372
+
* offset of fields +
373
+
* offset within field
374
+
*/
375
+
offset = (readl(nand->regs + MA35_NFI_REG_NANDRACTL) & 0x1ff) -
376
+
(parity_len * chip->ecc.steps) +
377
+
(parity_len * index) + corrected_index;
378
+
379
+
remain = offset % 4;
380
+
value = readl(nand->regs + MA35_NFI_REG_NANDRA0 + offset - remain);
381
+
value ^= temp_data[i] << (8 * remain);
382
+
writel(value, nand->regs + MA35_NFI_REG_NANDRA0 + offset - remain);
383
+
}
384
+
}
385
+
}
386
+
387
+
static int ma35_nfi_ecc_check(struct nand_chip *chip, u8 *addr)
388
+
{
389
+
struct ma35_nand_info *nand = nand_get_controller_data(chip);
390
+
struct ma35_nand_chip *nvtnand = to_ma35_nand(chip);
391
+
struct mtd_info *mtd = nand_to_mtd(chip);
392
+
int maxbitflips = 0;
393
+
int cnt = 0;
394
+
u32 status;
395
+
int i, j;
396
+
397
+
for (j = 0; j < nvtnand->eccstatus; j++) {
398
+
status = readl(nand->regs + MA35_NFI_REG_NANDECCES0 + j * 4);
399
+
if (!status)
400
+
continue;
401
+
402
+
for (i = 0; i < 4; i++) {
403
+
if ((status & ECC_STATUS_MASK) == 0x01) {
404
+
/* Correctable error */
405
+
cnt = (status >> 2) & ECC_ERR_CNT_MASK;
406
+
ma35_nfi_correct(chip, j * 4 + i, cnt, addr);
407
+
maxbitflips = max_t(u32, maxbitflips, cnt);
408
+
mtd->ecc_stats.corrected += cnt;
409
+
} else {
410
+
/* Uncorrectable error */
411
+
mtd->ecc_stats.failed++;
412
+
dev_err(nand->dev, "uncorrectable error! 0x%4x\n", status);
413
+
return -EBADMSG;
414
+
}
415
+
status >>= 8;
416
+
}
417
+
}
418
+
return maxbitflips;
419
+
}
420
+
421
+
static void ma35_nand_dmac_init(struct ma35_nand_info *nand)
422
+
{
423
+
/* DMAC reset and enable */
424
+
writel(DMA_RST | DMA_EN, nand->regs + MA35_NFI_REG_DMACTL);
425
+
writel(DMA_EN, nand->regs + MA35_NFI_REG_DMACTL);
426
+
427
+
/* Clear DMA finished flag and enable */
428
+
writel(INT_DMA | INT_ECC, nand->regs + MA35_NFI_REG_NANDINTSTS);
429
+
writel(INT_DMA, nand->regs + MA35_NFI_REG_NANDINTEN);
430
+
}
431
+
432
+
static int ma35_nand_do_write(struct nand_chip *chip, const u8 *addr, u32 len)
433
+
{
434
+
struct ma35_nand_info *nand = nand_get_controller_data(chip);
435
+
struct mtd_info *mtd = nand_to_mtd(chip);
436
+
dma_addr_t dma_addr;
437
+
int ret = 0, i;
438
+
u32 reg;
439
+
440
+
if (len != mtd->writesize) {
441
+
for (i = 0; i < len; i++)
442
+
writel(addr[i], nand->regs + MA35_NFI_REG_NANDDATA);
443
+
return 0;
444
+
}
445
+
446
+
ma35_nand_dmac_init(nand);
447
+
448
+
/* To mark this page as dirty. */
449
+
reg = readl(nand->regs + MA35_NFI_REG_NANDRA0);
450
+
if (reg & 0xffff0000)
451
+
writel(reg & 0xffff, nand->regs + MA35_NFI_REG_NANDRA0);
452
+
453
+
dma_addr = dma_map_single(nand->dev, (void *)addr, len, DMA_TO_DEVICE);
454
+
ret = dma_mapping_error(nand->dev, dma_addr);
455
+
if (ret) {
456
+
dev_err(nand->dev, "dma mapping error\n");
457
+
return -EINVAL;
458
+
}
459
+
dma_sync_single_for_device(nand->dev, dma_addr, len, DMA_TO_DEVICE);
460
+
461
+
reinit_completion(&nand->complete);
462
+
writel(dma_addr, nand->regs + MA35_NFI_REG_DMASA);
463
+
writel(readl(nand->regs + MA35_NFI_REG_NANDCTL) | DMA_W_EN,
464
+
nand->regs + MA35_NFI_REG_NANDCTL);
465
+
ret = wait_for_completion_timeout(&nand->complete, msecs_to_jiffies(1000));
466
+
if (!ret) {
467
+
dev_err(nand->dev, "write timeout\n");
468
+
ret = -ETIMEDOUT;
469
+
}
470
+
471
+
dma_unmap_single(nand->dev, dma_addr, len, DMA_TO_DEVICE);
472
+
473
+
return ret;
474
+
}
475
+
476
+
static int ma35_nand_do_read(struct nand_chip *chip, u8 *addr, u32 len)
477
+
{
478
+
struct ma35_nand_info *nand = nand_get_controller_data(chip);
479
+
struct mtd_info *mtd = nand_to_mtd(chip);
480
+
int ret = 0, cnt = 0, i;
481
+
dma_addr_t dma_addr;
482
+
u32 reg;
483
+
484
+
if (len != mtd->writesize) {
485
+
for (i = 0; i < len; i++)
486
+
addr[i] = readb(nand->regs + MA35_NFI_REG_NANDDATA);
487
+
return 0;
488
+
}
489
+
490
+
ma35_nand_dmac_init(nand);
491
+
492
+
/* Setup and start DMA using dma_addr */
493
+
dma_addr = dma_map_single(nand->dev, (void *)addr, len, DMA_FROM_DEVICE);
494
+
ret = dma_mapping_error(nand->dev, dma_addr);
495
+
if (ret) {
496
+
dev_err(nand->dev, "dma mapping error\n");
497
+
return -EINVAL;
498
+
}
499
+
500
+
reinit_completion(&nand->complete);
501
+
writel(dma_addr, nand->regs + MA35_NFI_REG_DMASA);
502
+
writel(readl(nand->regs + MA35_NFI_REG_NANDCTL) | DMA_R_EN,
503
+
nand->regs + MA35_NFI_REG_NANDCTL);
504
+
ret = wait_for_completion_timeout(&nand->complete, msecs_to_jiffies(1000));
505
+
if (!ret) {
506
+
dev_err(nand->dev, "read timeout\n");
507
+
ret = -ETIMEDOUT;
508
+
}
509
+
510
+
dma_unmap_single(nand->dev, dma_addr, len, DMA_FROM_DEVICE);
511
+
512
+
reg = readl(nand->regs + MA35_NFI_REG_NANDINTSTS);
513
+
if (reg & INT_ECC) {
514
+
cnt = ma35_nfi_ecc_check(chip, addr);
515
+
if (cnt < 0) {
516
+
writel(DMA_RST | DMA_EN, nand->regs + MA35_NFI_REG_DMACTL);
517
+
writel(readl(nand->regs + MA35_NFI_REG_NANDCTL) | SWRST,
518
+
nand->regs + MA35_NFI_REG_NANDCTL);
519
+
}
520
+
writel(INT_ECC, nand->regs + MA35_NFI_REG_NANDINTSTS);
521
+
}
522
+
523
+
ret = ret < 0 ? ret : cnt;
524
+
return ret;
525
+
}
526
+
527
+
static int ma35_nand_format_subpage(struct nand_chip *chip, u32 offset,
528
+
u32 len, const u8 *buf)
529
+
{
530
+
struct ma35_nand_info *nand = nand_get_controller_data(chip);
531
+
struct mtd_info *mtd = nand_to_mtd(chip);
532
+
u32 page_off = round_down(offset, chip->ecc.size);
533
+
u32 end = DIV_ROUND_UP(page_off + len, chip->ecc.size);
534
+
u32 start = page_off / chip->ecc.size;
535
+
u32 reg;
536
+
int i;
537
+
538
+
reg = readl(nand->regs + MA35_NFI_REG_NANDRACTL) | 0xffff0000;
539
+
memset(nand->buffer, 0xff, mtd->writesize);
540
+
for (i = start; i < end; i++) {
541
+
memcpy(nand->buffer + i * chip->ecc.size,
542
+
buf + i * chip->ecc.size, chip->ecc.size);
543
+
reg &= ~(1 << (i + 16));
544
+
}
545
+
writel(reg, nand->regs + MA35_NFI_REG_NANDRACTL);
546
+
547
+
return 0;
548
+
}
549
+
550
+
static int ma35_nand_write_subpage_hwecc(struct nand_chip *chip, u32 offset,
551
+
u32 data_len, const u8 *buf,
552
+
int oob_required, int page)
553
+
{
554
+
struct ma35_nand_info *nand = nand_get_controller_data(chip);
555
+
struct mtd_info *mtd = nand_to_mtd(chip);
556
+
u32 reg, oobpoi, index;
557
+
int i;
558
+
559
+
/* Enable HW ECC engine */
560
+
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
561
+
writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
562
+
563
+
ma35_nand_target_enable(chip, chip->cur_cs);
564
+
565
+
ma35_clear_spare(chip, mtd->oobsize);
566
+
ma35_write_spare(chip, mtd->oobsize - chip->ecc.total,
567
+
(u32 *)chip->oob_poi);
568
+
569
+
ma35_nand_format_subpage(chip, offset, data_len, buf);
570
+
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
571
+
ma35_nand_do_write(chip, nand->buffer, mtd->writesize);
572
+
nand_prog_page_end_op(chip);
573
+
574
+
oobpoi = mtd->oobsize - chip->ecc.total;
575
+
reg = readl(nand->regs + MA35_NFI_REG_NANDRACTL);
576
+
for (i = 0; i < chip->ecc.steps; i++) {
577
+
index = i * chip->ecc.bytes;
578
+
if (!(reg & (1 << (i + 16)))) {
579
+
ma35_read_spare(chip, chip->ecc.bytes,
580
+
(u32 *)(chip->oob_poi + oobpoi + index),
581
+
oobpoi + index);
582
+
}
583
+
}
584
+
585
+
writel(mtd->oobsize, nand->regs + MA35_NFI_REG_NANDRACTL);
586
+
/* Disable HW ECC engine */
587
+
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
588
+
writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
589
+
590
+
return 0;
591
+
}
592
+
593
+
static int ma35_nand_write_page_hwecc(struct nand_chip *chip, const u8 *buf,
594
+
int oob_required, int page)
595
+
{
596
+
struct ma35_nand_info *nand = nand_get_controller_data(chip);
597
+
struct mtd_info *mtd = nand_to_mtd(chip);
598
+
u32 reg;
599
+
600
+
/* Enable HW ECC engine */
601
+
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
602
+
writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
603
+
604
+
ma35_nand_target_enable(chip, chip->cur_cs);
605
+
606
+
ma35_clear_spare(chip, mtd->oobsize);
607
+
ma35_write_spare(chip, mtd->oobsize - chip->ecc.total,
608
+
(u32 *)chip->oob_poi);
609
+
610
+
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
611
+
ma35_nand_do_write(chip, buf, mtd->writesize);
612
+
nand_prog_page_end_op(chip);
613
+
614
+
ma35_read_spare(chip, chip->ecc.total,
615
+
(u32 *)(chip->oob_poi + (mtd->oobsize - chip->ecc.total)),
616
+
mtd->oobsize - chip->ecc.total);
617
+
618
+
/* Disable HW ECC engine */
619
+
writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
620
+
621
+
return 0;
622
+
}
623
+
624
+
static int ma35_nand_read_subpage_hwecc(struct nand_chip *chip, u32 offset,
625
+
u32 data_len, u8 *buf, int page)
626
+
{
627
+
struct ma35_nand_info *nand = nand_get_controller_data(chip);
628
+
struct mtd_info *mtd = nand_to_mtd(chip);
629
+
int bitflips = 0;
630
+
u32 reg;
631
+
632
+
/* Enable HW ECC engine */
633
+
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
634
+
writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
635
+
636
+
ma35_nand_target_enable(chip, chip->cur_cs);
637
+
nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
638
+
ma35_write_spare(chip, mtd->oobsize, (u32 *)chip->oob_poi);
639
+
640
+
reg = readl(nand->regs + MA35_NFI_REG_NANDRA0);
641
+
if (PREFIX_RA_IS_EMPTY(reg)) {
642
+
memset((void *)buf, 0xff, mtd->writesize);
643
+
} else {
644
+
nand_read_page_op(chip, page, offset, NULL, 0);
645
+
bitflips = ma35_nand_do_read(chip, buf + offset, data_len);
646
+
ma35_read_spare(chip, mtd->oobsize, (u32 *)chip->oob_poi, 0);
647
+
}
648
+
649
+
/* Disable HW ECC engine */
650
+
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
651
+
writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
652
+
653
+
return bitflips;
654
+
}
655
+
656
+
static int ma35_nand_read_page_hwecc(struct nand_chip *chip, u8 *buf,
657
+
int oob_required, int page)
658
+
{
659
+
struct ma35_nand_info *nand = nand_get_controller_data(chip);
660
+
struct mtd_info *mtd = nand_to_mtd(chip);
661
+
int bitflips = 0;
662
+
u32 reg;
663
+
664
+
/* Enable HW ECC engine */
665
+
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
666
+
writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
667
+
668
+
ma35_nand_target_enable(chip, chip->cur_cs);
669
+
nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
670
+
ma35_write_spare(chip, mtd->oobsize, (u32 *)chip->oob_poi);
671
+
672
+
reg = readl(nand->regs + MA35_NFI_REG_NANDRA0);
673
+
if (PREFIX_RA_IS_EMPTY(reg)) {
674
+
memset((void *)buf, 0xff, mtd->writesize);
675
+
} else {
676
+
nand_read_page_op(chip, page, 0, NULL, 0);
677
+
bitflips = ma35_nand_do_read(chip, buf, mtd->writesize);
678
+
ma35_read_spare(chip, mtd->oobsize, (u32 *)chip->oob_poi, 0);
679
+
}
680
+
681
+
/* Disable HW ECC engine */
682
+
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
683
+
writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
684
+
685
+
return bitflips;
686
+
}
687
+
688
+
static int ma35_nand_read_oob_hwecc(struct nand_chip *chip, int page)
689
+
{
690
+
struct ma35_nand_info *nand = nand_get_controller_data(chip);
691
+
struct mtd_info *mtd = nand_to_mtd(chip);
692
+
u32 reg;
693
+
694
+
ma35_nand_target_enable(chip, chip->cur_cs);
695
+
nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
696
+
697
+
/* copy OOB data to controller redundant area for page read */
698
+
ma35_write_spare(chip, mtd->oobsize, (u32 *)chip->oob_poi);
699
+
700
+
reg = readl(nand->regs + MA35_NFI_REG_NANDRA0);
701
+
if (PREFIX_RA_IS_EMPTY(reg))
702
+
memset((void *)chip->oob_poi, 0xff, mtd->oobsize);
703
+
704
+
return 0;
705
+
}
706
+
707
+
static inline void ma35_hw_init(struct ma35_nand_info *nand)
708
+
{
709
+
u32 reg;
710
+
711
+
/* Disable flash wp. */
712
+
writel(DISABLE_WP, nand->regs + MA35_NFI_REG_NANDECTL);
713
+
714
+
/* resets the internal state machine and counters */
715
+
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL);
716
+
reg |= SWRST;
717
+
writel(reg, nand->regs + MA35_NFI_REG_NANDCTL);
718
+
}
719
+
720
+
static irqreturn_t ma35_nand_irq(int irq, void *id)
721
+
{
722
+
struct ma35_nand_info *nand = (struct ma35_nand_info *)id;
723
+
u32 isr;
724
+
725
+
isr = readl(nand->regs + MA35_NFI_REG_NANDINTSTS);
726
+
if (isr & INT_DMA) {
727
+
writel(INT_DMA, nand->regs + MA35_NFI_REG_NANDINTSTS);
728
+
complete(&nand->complete);
729
+
return IRQ_HANDLED;
730
+
}
731
+
732
+
return IRQ_NONE;
733
+
}
734
+
735
+
static int ma35_nand_attach_chip(struct nand_chip *chip)
736
+
{
737
+
struct ma35_nand_info *nand = nand_get_controller_data(chip);
738
+
struct mtd_info *mtd = nand_to_mtd(chip);
739
+
struct device *dev = mtd->dev.parent;
740
+
u32 reg;
741
+
742
+
if (chip->options & NAND_BUSWIDTH_16) {
743
+
dev_err(dev, "16 bits bus width not supported");
744
+
return -EINVAL;
745
+
}
746
+
747
+
reg = readl(nand->regs + MA35_NFI_REG_NANDCTL) & (~PSIZE_MASK);
748
+
switch (mtd->writesize) {
749
+
case SZ_2K:
750
+
writel(reg | PSIZE_2K, nand->regs + MA35_NFI_REG_NANDCTL);
751
+
break;
752
+
case SZ_4K:
753
+
writel(reg | PSIZE_4K, nand->regs + MA35_NFI_REG_NANDCTL);
754
+
break;
755
+
case SZ_8K:
756
+
writel(reg | PSIZE_8K, nand->regs + MA35_NFI_REG_NANDCTL);
757
+
break;
758
+
default:
759
+
dev_err(dev, "Unsupported page size");
760
+
return -EINVAL;
761
+
}
762
+
763
+
switch (chip->ecc.engine_type) {
764
+
case NAND_ECC_ENGINE_TYPE_ON_HOST:
765
+
/* Do not store BBT bits in the OOB section as it is not protected */
766
+
if (chip->bbt_options & NAND_BBT_USE_FLASH)
767
+
chip->bbt_options |= NAND_BBT_NO_OOB;
768
+
chip->options |= NAND_USES_DMA | NAND_SUBPAGE_READ;
769
+
chip->ecc.write_subpage = ma35_nand_write_subpage_hwecc;
770
+
chip->ecc.write_page = ma35_nand_write_page_hwecc;
771
+
chip->ecc.read_subpage = ma35_nand_read_subpage_hwecc;
772
+
chip->ecc.read_page = ma35_nand_read_page_hwecc;
773
+
chip->ecc.read_oob = ma35_nand_read_oob_hwecc;
774
+
return ma35_nand_hwecc_init(chip, nand);
775
+
case NAND_ECC_ENGINE_TYPE_NONE:
776
+
case NAND_ECC_ENGINE_TYPE_SOFT:
777
+
case NAND_ECC_ENGINE_TYPE_ON_DIE:
778
+
break;
779
+
default:
780
+
return -EINVAL;
781
+
}
782
+
783
+
return 0;
784
+
}
785
+
786
+
static int ma35_nfc_exec_instr(struct nand_chip *chip,
787
+
const struct nand_op_instr *instr)
788
+
{
789
+
struct ma35_nand_info *nand = nand_get_controller_data(chip);
790
+
unsigned int i;
791
+
int ret = 0;
792
+
u32 status;
793
+
794
+
switch (instr->type) {
795
+
case NAND_OP_CMD_INSTR:
796
+
writel(instr->ctx.cmd.opcode, nand->regs + MA35_NFI_REG_NANDCMD);
797
+
break;
798
+
case NAND_OP_ADDR_INSTR:
799
+
for (i = 0; i < instr->ctx.addr.naddrs; i++) {
800
+
if (i == (instr->ctx.addr.naddrs - 1))
801
+
writel(instr->ctx.addr.addrs[i] | ENDADDR,
802
+
nand->regs + MA35_NFI_REG_NANDADDR);
803
+
else
804
+
writel(instr->ctx.addr.addrs[i],
805
+
nand->regs + MA35_NFI_REG_NANDADDR);
806
+
}
807
+
break;
808
+
case NAND_OP_DATA_IN_INSTR:
809
+
ret = ma35_nand_do_read(chip, instr->ctx.data.buf.in, instr->ctx.data.len);
810
+
break;
811
+
case NAND_OP_DATA_OUT_INSTR:
812
+
ret = ma35_nand_do_write(chip, instr->ctx.data.buf.out, instr->ctx.data.len);
813
+
break;
814
+
case NAND_OP_WAITRDY_INSTR:
815
+
return readl_poll_timeout(nand->regs + MA35_NFI_REG_NANDINTSTS, status,
816
+
status & INT_RB0, 20,
817
+
instr->ctx.waitrdy.timeout_ms * MSEC_PER_SEC);
818
+
default:
819
+
ret = -EINVAL;
820
+
break;
821
+
}
822
+
823
+
return ret;
824
+
}
825
+
826
+
static int ma35_nfc_exec_op(struct nand_chip *chip,
827
+
const struct nand_operation *op,
828
+
bool check_only)
829
+
{
830
+
int ret = 0;
831
+
u32 i;
832
+
833
+
if (check_only)
834
+
return 0;
835
+
836
+
ma35_nand_target_enable(chip, op->cs);
837
+
838
+
for (i = 0; i < op->ninstrs; i++) {
839
+
ret = ma35_nfc_exec_instr(chip, &op->instrs[i]);
840
+
if (ret)
841
+
break;
842
+
}
843
+
844
+
return ret;
845
+
}
846
+
847
+
static const struct nand_controller_ops ma35_nfc_ops = {
848
+
.attach_chip = ma35_nand_attach_chip,
849
+
.exec_op = ma35_nfc_exec_op,
850
+
};
851
+
852
+
static int ma35_nand_chip_init(struct device *dev, struct ma35_nand_info *nand,
853
+
struct device_node *np)
854
+
{
855
+
struct ma35_nand_chip *nvtnand;
856
+
struct nand_chip *chip;
857
+
struct mtd_info *mtd;
858
+
int nsels;
859
+
int ret;
860
+
u32 cs;
861
+
int i;
862
+
863
+
nsels = of_property_count_elems_of_size(np, "reg", sizeof(u32));
864
+
if (!nsels || nsels > MA35_MAX_NSELS) {
865
+
dev_err(dev, "invalid reg property size %d\n", nsels);
866
+
return -EINVAL;
867
+
}
868
+
869
+
nvtnand = devm_kzalloc(dev, struct_size(nvtnand, sels, nsels),
870
+
GFP_KERNEL);
871
+
if (!nvtnand)
872
+
return -ENOMEM;
873
+
874
+
nvtnand->nsels = nsels;
875
+
for (i = 0; i < nsels; i++) {
876
+
ret = of_property_read_u32_index(np, "reg", i, &cs);
877
+
if (ret) {
878
+
dev_err(dev, "reg property failure : %d\n", ret);
879
+
return ret;
880
+
}
881
+
882
+
if (cs >= MA35_MAX_NSELS) {
883
+
dev_err(dev, "invalid CS: %u\n", cs);
884
+
return -EINVAL;
885
+
}
886
+
887
+
if (test_and_set_bit(cs, &nand->assigned_cs)) {
888
+
dev_err(dev, "CS %u already assigned\n", cs);
889
+
return -EINVAL;
890
+
}
891
+
892
+
nvtnand->sels[i] = cs;
893
+
}
894
+
895
+
chip = &nvtnand->chip;
896
+
chip->controller = &nand->controller;
897
+
898
+
nand_set_flash_node(chip, np);
899
+
nand_set_controller_data(chip, nand);
900
+
901
+
mtd = nand_to_mtd(chip);
902
+
mtd->owner = THIS_MODULE;
903
+
mtd->dev.parent = dev;
904
+
905
+
mtd_set_ooblayout(mtd, &ma35_ooblayout_ops);
906
+
ret = nand_scan(chip, nsels);
907
+
if (ret)
908
+
return ret;
909
+
910
+
ret = mtd_device_register(mtd, NULL, 0);
911
+
if (ret) {
912
+
nand_cleanup(chip);
913
+
return ret;
914
+
}
915
+
916
+
list_add_tail(&nvtnand->node, &nand->chips);
917
+
918
+
return 0;
919
+
}
920
+
921
+
static void ma35_chips_cleanup(struct ma35_nand_info *nand)
922
+
{
923
+
struct ma35_nand_chip *nvtnand, *tmp;
924
+
struct nand_chip *chip;
925
+
int ret;
926
+
927
+
list_for_each_entry_safe(nvtnand, tmp, &nand->chips, node) {
928
+
chip = &nvtnand->chip;
929
+
ret = mtd_device_unregister(nand_to_mtd(chip));
930
+
WARN_ON(ret);
931
+
nand_cleanup(chip);
932
+
list_del(&nvtnand->node);
933
+
}
934
+
}
935
+
936
+
static int ma35_nand_chips_init(struct device *dev, struct ma35_nand_info *nand)
937
+
{
938
+
struct device_node *np = dev->of_node, *nand_np;
939
+
int ret;
940
+
941
+
for_each_child_of_node(np, nand_np) {
942
+
ret = ma35_nand_chip_init(dev, nand, nand_np);
943
+
if (ret) {
944
+
ma35_chips_cleanup(nand);
945
+
return ret;
946
+
}
947
+
}
948
+
return 0;
949
+
}
950
+
951
+
static int ma35_nand_probe(struct platform_device *pdev)
952
+
{
953
+
struct ma35_nand_info *nand;
954
+
int ret = 0;
955
+
956
+
nand = devm_kzalloc(&pdev->dev, sizeof(*nand), GFP_KERNEL);
957
+
if (!nand)
958
+
return -ENOMEM;
959
+
960
+
nand_controller_init(&nand->controller);
961
+
INIT_LIST_HEAD(&nand->chips);
962
+
nand->controller.ops = &ma35_nfc_ops;
963
+
964
+
init_completion(&nand->complete);
965
+
966
+
nand->regs = devm_platform_ioremap_resource(pdev, 0);
967
+
if (IS_ERR(nand->regs))
968
+
return PTR_ERR(nand->regs);
969
+
970
+
nand->dev = &pdev->dev;
971
+
972
+
nand->clk = devm_clk_get_enabled(&pdev->dev, "nand_gate");
973
+
if (IS_ERR(nand->clk))
974
+
return dev_err_probe(&pdev->dev, PTR_ERR(nand->clk),
975
+
"failed to find NAND clock\n");
976
+
977
+
nand->irq = platform_get_irq(pdev, 0);
978
+
if (nand->irq < 0)
979
+
return dev_err_probe(&pdev->dev, nand->irq,
980
+
"failed to get platform irq\n");
981
+
982
+
ret = devm_request_irq(&pdev->dev, nand->irq, ma35_nand_irq,
983
+
IRQF_TRIGGER_HIGH, "ma35d1-nand-controller", nand);
984
+
if (ret) {
985
+
dev_err(&pdev->dev, "failed to request NAND irq\n");
986
+
return -ENXIO;
987
+
}
988
+
989
+
platform_set_drvdata(pdev, nand);
990
+
991
+
writel(GRST | NAND_EN, nand->regs + MA35_NFI_REG_GCTL);
992
+
ma35_hw_init(nand);
993
+
ret = ma35_nand_chips_init(&pdev->dev, nand);
994
+
if (ret) {
995
+
dev_err(&pdev->dev, "failed to init NAND chips\n");
996
+
clk_disable(nand->clk);
997
+
return ret;
998
+
}
999
+
1000
+
return ret;
1001
+
}
1002
+
1003
+
static void ma35_nand_remove(struct platform_device *pdev)
1004
+
{
1005
+
struct ma35_nand_info *nand = platform_get_drvdata(pdev);
1006
+
1007
+
ma35_chips_cleanup(nand);
1008
+
}
1009
+
1010
+
static const struct of_device_id ma35_nand_of_match[] = {
1011
+
{ .compatible = "nuvoton,ma35d1-nand-controller" },
1012
+
{},
1013
+
};
1014
+
MODULE_DEVICE_TABLE(of, ma35_nand_of_match);
1015
+
1016
+
static struct platform_driver ma35_nand_driver = {
1017
+
.driver = {
1018
+
.name = "ma35d1-nand-controller",
1019
+
.of_match_table = ma35_nand_of_match,
1020
+
},
1021
+
.probe = ma35_nand_probe,
1022
+
.remove = ma35_nand_remove,
1023
+
};
1024
+
1025
+
module_platform_driver(ma35_nand_driver);
1026
+
1027
+
MODULE_DESCRIPTION("Nuvoton ma35 NAND driver");
1028
+
MODULE_AUTHOR("Hui-Ping Chen <hpchen0nvt@gmail.com>");
1029
+
MODULE_LICENSE("GPL");
+326
-1443
drivers/mtd/nand/raw/qcom_nandc.c
+326
-1443
drivers/mtd/nand/raw/qcom_nandc.c
···
15
15
#include <linux/of.h>
16
16
#include <linux/platform_device.h>
17
17
#include <linux/slab.h>
18
-
19
-
/* NANDc reg offsets */
20
-
#define NAND_FLASH_CMD 0x00
21
-
#define NAND_ADDR0 0x04
22
-
#define NAND_ADDR1 0x08
23
-
#define NAND_FLASH_CHIP_SELECT 0x0c
24
-
#define NAND_EXEC_CMD 0x10
25
-
#define NAND_FLASH_STATUS 0x14
26
-
#define NAND_BUFFER_STATUS 0x18
27
-
#define NAND_DEV0_CFG0 0x20
28
-
#define NAND_DEV0_CFG1 0x24
29
-
#define NAND_DEV0_ECC_CFG 0x28
30
-
#define NAND_AUTO_STATUS_EN 0x2c
31
-
#define NAND_DEV1_CFG0 0x30
32
-
#define NAND_DEV1_CFG1 0x34
33
-
#define NAND_READ_ID 0x40
34
-
#define NAND_READ_STATUS 0x44
35
-
#define NAND_DEV_CMD0 0xa0
36
-
#define NAND_DEV_CMD1 0xa4
37
-
#define NAND_DEV_CMD2 0xa8
38
-
#define NAND_DEV_CMD_VLD 0xac
39
-
#define SFLASHC_BURST_CFG 0xe0
40
-
#define NAND_ERASED_CW_DETECT_CFG 0xe8
41
-
#define NAND_ERASED_CW_DETECT_STATUS 0xec
42
-
#define NAND_EBI2_ECC_BUF_CFG 0xf0
43
-
#define FLASH_BUF_ACC 0x100
44
-
45
-
#define NAND_CTRL 0xf00
46
-
#define NAND_VERSION 0xf08
47
-
#define NAND_READ_LOCATION_0 0xf20
48
-
#define NAND_READ_LOCATION_1 0xf24
49
-
#define NAND_READ_LOCATION_2 0xf28
50
-
#define NAND_READ_LOCATION_3 0xf2c
51
-
#define NAND_READ_LOCATION_LAST_CW_0 0xf40
52
-
#define NAND_READ_LOCATION_LAST_CW_1 0xf44
53
-
#define NAND_READ_LOCATION_LAST_CW_2 0xf48
54
-
#define NAND_READ_LOCATION_LAST_CW_3 0xf4c
55
-
56
-
/* dummy register offsets, used by write_reg_dma */
57
-
#define NAND_DEV_CMD1_RESTORE 0xdead
58
-
#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
59
-
60
-
/* NAND_FLASH_CMD bits */
61
-
#define PAGE_ACC BIT(4)
62
-
#define LAST_PAGE BIT(5)
63
-
64
-
/* NAND_FLASH_CHIP_SELECT bits */
65
-
#define NAND_DEV_SEL 0
66
-
#define DM_EN BIT(2)
67
-
68
-
/* NAND_FLASH_STATUS bits */
69
-
#define FS_OP_ERR BIT(4)
70
-
#define FS_READY_BSY_N BIT(5)
71
-
#define FS_MPU_ERR BIT(8)
72
-
#define FS_DEVICE_STS_ERR BIT(16)
73
-
#define FS_DEVICE_WP BIT(23)
74
-
75
-
/* NAND_BUFFER_STATUS bits */
76
-
#define BS_UNCORRECTABLE_BIT BIT(8)
77
-
#define BS_CORRECTABLE_ERR_MSK 0x1f
78
-
79
-
/* NAND_DEVn_CFG0 bits */
80
-
#define DISABLE_STATUS_AFTER_WRITE 4
81
-
#define CW_PER_PAGE 6
82
-
#define UD_SIZE_BYTES 9
83
-
#define UD_SIZE_BYTES_MASK GENMASK(18, 9)
84
-
#define ECC_PARITY_SIZE_BYTES_RS 19
85
-
#define SPARE_SIZE_BYTES 23
86
-
#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23)
87
-
#define NUM_ADDR_CYCLES 27
88
-
#define STATUS_BFR_READ 30
89
-
#define SET_RD_MODE_AFTER_STATUS 31
90
-
91
-
/* NAND_DEVn_CFG0 bits */
92
-
#define DEV0_CFG1_ECC_DISABLE 0
93
-
#define WIDE_FLASH 1
94
-
#define NAND_RECOVERY_CYCLES 2
95
-
#define CS_ACTIVE_BSY 5
96
-
#define BAD_BLOCK_BYTE_NUM 6
97
-
#define BAD_BLOCK_IN_SPARE_AREA 16
98
-
#define WR_RD_BSY_GAP 17
99
-
#define ENABLE_BCH_ECC 27
100
-
101
-
/* NAND_DEV0_ECC_CFG bits */
102
-
#define ECC_CFG_ECC_DISABLE 0
103
-
#define ECC_SW_RESET 1
104
-
#define ECC_MODE 4
105
-
#define ECC_PARITY_SIZE_BYTES_BCH 8
106
-
#define ECC_NUM_DATA_BYTES 16
107
-
#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16)
108
-
#define ECC_FORCE_CLK_OPEN 30
109
-
110
-
/* NAND_DEV_CMD1 bits */
111
-
#define READ_ADDR 0
112
-
113
-
/* NAND_DEV_CMD_VLD bits */
114
-
#define READ_START_VLD BIT(0)
115
-
#define READ_STOP_VLD BIT(1)
116
-
#define WRITE_START_VLD BIT(2)
117
-
#define ERASE_START_VLD BIT(3)
118
-
#define SEQ_READ_START_VLD BIT(4)
119
-
120
-
/* NAND_EBI2_ECC_BUF_CFG bits */
121
-
#define NUM_STEPS 0
122
-
123
-
/* NAND_ERASED_CW_DETECT_CFG bits */
124
-
#define ERASED_CW_ECC_MASK 1
125
-
#define AUTO_DETECT_RES 0
126
-
#define MASK_ECC BIT(ERASED_CW_ECC_MASK)
127
-
#define RESET_ERASED_DET BIT(AUTO_DETECT_RES)
128
-
#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
129
-
#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
130
-
#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
131
-
132
-
/* NAND_ERASED_CW_DETECT_STATUS bits */
133
-
#define PAGE_ALL_ERASED BIT(7)
134
-
#define CODEWORD_ALL_ERASED BIT(6)
135
-
#define PAGE_ERASED BIT(5)
136
-
#define CODEWORD_ERASED BIT(4)
137
-
#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
138
-
#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
139
-
140
-
/* NAND_READ_LOCATION_n bits */
141
-
#define READ_LOCATION_OFFSET 0
142
-
#define READ_LOCATION_SIZE 16
143
-
#define READ_LOCATION_LAST 31
144
-
145
-
/* Version Mask */
146
-
#define NAND_VERSION_MAJOR_MASK 0xf0000000
147
-
#define NAND_VERSION_MAJOR_SHIFT 28
148
-
#define NAND_VERSION_MINOR_MASK 0x0fff0000
149
-
#define NAND_VERSION_MINOR_SHIFT 16
150
-
151
-
/* NAND OP_CMDs */
152
-
#define OP_PAGE_READ 0x2
153
-
#define OP_PAGE_READ_WITH_ECC 0x3
154
-
#define OP_PAGE_READ_WITH_ECC_SPARE 0x4
155
-
#define OP_PAGE_READ_ONFI_READ 0x5
156
-
#define OP_PROGRAM_PAGE 0x6
157
-
#define OP_PAGE_PROGRAM_WITH_ECC 0x7
158
-
#define OP_PROGRAM_PAGE_SPARE 0x9
159
-
#define OP_BLOCK_ERASE 0xa
160
-
#define OP_CHECK_STATUS 0xc
161
-
#define OP_FETCH_ID 0xb
162
-
#define OP_RESET_DEVICE 0xd
163
-
164
-
/* Default Value for NAND_DEV_CMD_VLD */
165
-
#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \
166
-
ERASE_START_VLD | SEQ_READ_START_VLD)
167
-
168
-
/* NAND_CTRL bits */
169
-
#define BAM_MODE_EN BIT(0)
170
-
171
-
/*
172
-
* the NAND controller performs reads/writes with ECC in 516 byte chunks.
173
-
* the driver calls the chunks 'step' or 'codeword' interchangeably
174
-
*/
175
-
#define NANDC_STEP_SIZE 512
176
-
177
-
/*
178
-
* the largest page size we support is 8K, this will have 16 steps/codewords
179
-
* of 512 bytes each
180
-
*/
181
-
#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
182
-
183
-
/* we read at most 3 registers per codeword scan */
184
-
#define MAX_REG_RD (3 * MAX_NUM_STEPS)
185
-
186
-
/* ECC modes supported by the controller */
187
-
#define ECC_NONE BIT(0)
188
-
#define ECC_RS_4BIT BIT(1)
189
-
#define ECC_BCH_4BIT BIT(2)
190
-
#define ECC_BCH_8BIT BIT(3)
191
-
192
-
#define nandc_set_read_loc_first(chip, reg, cw_offset, read_size, is_last_read_loc) \
193
-
nandc_set_reg(chip, reg, \
194
-
((cw_offset) << READ_LOCATION_OFFSET) | \
195
-
((read_size) << READ_LOCATION_SIZE) | \
196
-
((is_last_read_loc) << READ_LOCATION_LAST))
197
-
198
-
#define nandc_set_read_loc_last(chip, reg, cw_offset, read_size, is_last_read_loc) \
199
-
nandc_set_reg(chip, reg, \
200
-
((cw_offset) << READ_LOCATION_OFFSET) | \
201
-
((read_size) << READ_LOCATION_SIZE) | \
202
-
((is_last_read_loc) << READ_LOCATION_LAST))
203
-
/*
204
-
* Returns the actual register address for all NAND_DEV_ registers
205
-
* (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD)
206
-
*/
207
-
#define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
208
-
209
-
/* Returns the NAND register physical address */
210
-
#define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
211
-
212
-
/* Returns the dma address for reg read buffer */
213
-
#define reg_buf_dma_addr(chip, vaddr) \
214
-
((chip)->reg_read_dma + \
215
-
((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf))
216
-
217
-
#define QPIC_PER_CW_CMD_ELEMENTS 32
218
-
#define QPIC_PER_CW_CMD_SGL 32
219
-
#define QPIC_PER_CW_DATA_SGL 8
220
-
221
-
#define QPIC_NAND_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
222
-
223
-
/*
224
-
* Flags used in DMA descriptor preparation helper functions
225
-
* (i.e. read_reg_dma/write_reg_dma/read_data_dma/write_data_dma)
226
-
*/
227
-
/* Don't set the EOT in current tx BAM sgl */
228
-
#define NAND_BAM_NO_EOT BIT(0)
229
-
/* Set the NWD flag in current BAM sgl */
230
-
#define NAND_BAM_NWD BIT(1)
231
-
/* Finish writing in the current BAM sgl and start writing in another BAM sgl */
232
-
#define NAND_BAM_NEXT_SGL BIT(2)
233
-
/*
234
-
* Erased codeword status is being used two times in single transfer so this
235
-
* flag will determine the current value of erased codeword status register
236
-
*/
237
-
#define NAND_ERASED_CW_SET BIT(4)
238
-
239
-
#define MAX_ADDRESS_CYCLE 5
240
-
241
-
/*
242
-
* This data type corresponds to the BAM transaction which will be used for all
243
-
* NAND transfers.
244
-
* @bam_ce - the array of BAM command elements
245
-
* @cmd_sgl - sgl for NAND BAM command pipe
246
-
* @data_sgl - sgl for NAND BAM consumer/producer pipe
247
-
* @last_data_desc - last DMA desc in data channel (tx/rx).
248
-
* @last_cmd_desc - last DMA desc in command channel.
249
-
* @txn_done - completion for NAND transfer.
250
-
* @bam_ce_pos - the index in bam_ce which is available for next sgl
251
-
* @bam_ce_start - the index in bam_ce which marks the start position ce
252
-
* for current sgl. It will be used for size calculation
253
-
* for current sgl
254
-
* @cmd_sgl_pos - current index in command sgl.
255
-
* @cmd_sgl_start - start index in command sgl.
256
-
* @tx_sgl_pos - current index in data sgl for tx.
257
-
* @tx_sgl_start - start index in data sgl for tx.
258
-
* @rx_sgl_pos - current index in data sgl for rx.
259
-
* @rx_sgl_start - start index in data sgl for rx.
260
-
* @wait_second_completion - wait for second DMA desc completion before making
261
-
* the NAND transfer completion.
262
-
*/
263
-
struct bam_transaction {
264
-
struct bam_cmd_element *bam_ce;
265
-
struct scatterlist *cmd_sgl;
266
-
struct scatterlist *data_sgl;
267
-
struct dma_async_tx_descriptor *last_data_desc;
268
-
struct dma_async_tx_descriptor *last_cmd_desc;
269
-
struct completion txn_done;
270
-
u32 bam_ce_pos;
271
-
u32 bam_ce_start;
272
-
u32 cmd_sgl_pos;
273
-
u32 cmd_sgl_start;
274
-
u32 tx_sgl_pos;
275
-
u32 tx_sgl_start;
276
-
u32 rx_sgl_pos;
277
-
u32 rx_sgl_start;
278
-
bool wait_second_completion;
279
-
};
280
-
281
-
/*
282
-
* This data type corresponds to the nand dma descriptor
283
-
* @dma_desc - low level DMA engine descriptor
284
-
* @list - list for desc_info
285
-
*
286
-
* @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
287
-
* ADM
288
-
* @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
289
-
* @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
290
-
* @dir - DMA transfer direction
291
-
*/
292
-
struct desc_info {
293
-
struct dma_async_tx_descriptor *dma_desc;
294
-
struct list_head node;
295
-
296
-
union {
297
-
struct scatterlist adm_sgl;
298
-
struct {
299
-
struct scatterlist *bam_sgl;
300
-
int sgl_cnt;
301
-
};
302
-
};
303
-
enum dma_data_direction dir;
304
-
};
305
-
306
-
/*
307
-
* holds the current register values that we want to write. acts as a contiguous
308
-
* chunk of memory which we use to write the controller registers through DMA.
309
-
*/
310
-
struct nandc_regs {
311
-
__le32 cmd;
312
-
__le32 addr0;
313
-
__le32 addr1;
314
-
__le32 chip_sel;
315
-
__le32 exec;
316
-
317
-
__le32 cfg0;
318
-
__le32 cfg1;
319
-
__le32 ecc_bch_cfg;
320
-
321
-
__le32 clrflashstatus;
322
-
__le32 clrreadstatus;
323
-
324
-
__le32 cmd1;
325
-
__le32 vld;
326
-
327
-
__le32 orig_cmd1;
328
-
__le32 orig_vld;
329
-
330
-
__le32 ecc_buf_cfg;
331
-
__le32 read_location0;
332
-
__le32 read_location1;
333
-
__le32 read_location2;
334
-
__le32 read_location3;
335
-
__le32 read_location_last0;
336
-
__le32 read_location_last1;
337
-
__le32 read_location_last2;
338
-
__le32 read_location_last3;
339
-
340
-
__le32 erased_cw_detect_cfg_clr;
341
-
__le32 erased_cw_detect_cfg_set;
342
-
};
343
-
344
-
/*
345
-
* NAND controller data struct
346
-
*
347
-
* @dev: parent device
348
-
*
349
-
* @base: MMIO base
350
-
*
351
-
* @core_clk: controller clock
352
-
* @aon_clk: another controller clock
353
-
*
354
-
* @regs: a contiguous chunk of memory for DMA register
355
-
* writes. contains the register values to be
356
-
* written to controller
357
-
*
358
-
* @props: properties of current NAND controller,
359
-
* initialized via DT match data
360
-
*
361
-
* @controller: base controller structure
362
-
* @host_list: list containing all the chips attached to the
363
-
* controller
364
-
*
365
-
* @chan: dma channel
366
-
* @cmd_crci: ADM DMA CRCI for command flow control
367
-
* @data_crci: ADM DMA CRCI for data flow control
368
-
*
369
-
* @desc_list: DMA descriptor list (list of desc_infos)
370
-
*
371
-
* @data_buffer: our local DMA buffer for page read/writes,
372
-
* used when we can't use the buffer provided
373
-
* by upper layers directly
374
-
* @reg_read_buf: local buffer for reading back registers via DMA
375
-
*
376
-
* @base_phys: physical base address of controller registers
377
-
* @base_dma: dma base address of controller registers
378
-
* @reg_read_dma: contains dma address for register read buffer
379
-
*
380
-
* @buf_size/count/start: markers for chip->legacy.read_buf/write_buf
381
-
* functions
382
-
* @max_cwperpage: maximum QPIC codewords required. calculated
383
-
* from all connected NAND devices pagesize
384
-
*
385
-
* @reg_read_pos: marker for data read in reg_read_buf
386
-
*
387
-
* @cmd1/vld: some fixed controller register values
388
-
*
389
-
* @exec_opwrite: flag to select correct number of code word
390
-
* while reading status
391
-
*/
392
-
struct qcom_nand_controller {
393
-
struct device *dev;
394
-
395
-
void __iomem *base;
396
-
397
-
struct clk *core_clk;
398
-
struct clk *aon_clk;
399
-
400
-
struct nandc_regs *regs;
401
-
struct bam_transaction *bam_txn;
402
-
403
-
const struct qcom_nandc_props *props;
404
-
405
-
struct nand_controller controller;
406
-
struct list_head host_list;
407
-
408
-
union {
409
-
/* will be used only by QPIC for BAM DMA */
410
-
struct {
411
-
struct dma_chan *tx_chan;
412
-
struct dma_chan *rx_chan;
413
-
struct dma_chan *cmd_chan;
414
-
};
415
-
416
-
/* will be used only by EBI2 for ADM DMA */
417
-
struct {
418
-
struct dma_chan *chan;
419
-
unsigned int cmd_crci;
420
-
unsigned int data_crci;
421
-
};
422
-
};
423
-
424
-
struct list_head desc_list;
425
-
426
-
u8 *data_buffer;
427
-
__le32 *reg_read_buf;
428
-
429
-
phys_addr_t base_phys;
430
-
dma_addr_t base_dma;
431
-
dma_addr_t reg_read_dma;
432
-
433
-
int buf_size;
434
-
int buf_count;
435
-
int buf_start;
436
-
unsigned int max_cwperpage;
437
-
438
-
int reg_read_pos;
439
-
440
-
u32 cmd1, vld;
441
-
bool exec_opwrite;
442
-
};
18
+
#include <linux/mtd/nand-qpic-common.h>
443
19
444
20
/*
445
21
* NAND special boot partitions
···
47
471
unsigned int data_instr_idx;
48
472
unsigned int rdy_timeout_ms;
49
473
unsigned int rdy_delay_ns;
50
-
u32 addr1_reg;
51
-
u32 addr2_reg;
52
-
u32 cmd_reg;
474
+
__le32 addr1_reg;
475
+
__le32 addr2_reg;
476
+
__le32 cmd_reg;
53
477
u8 flag;
54
478
};
55
479
···
120
544
bool bch_enabled;
121
545
};
122
546
123
-
/*
124
-
* This data type corresponds to the NAND controller properties which varies
125
-
* among different NAND controllers.
126
-
* @ecc_modes - ecc mode for NAND
127
-
* @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
128
-
* @is_bam - whether NAND controller is using BAM
129
-
* @is_qpic - whether NAND CTRL is part of qpic IP
130
-
* @qpic_v2 - flag to indicate QPIC IP version 2
131
-
* @use_codeword_fixup - whether NAND has different layout for boot partitions
132
-
*/
133
-
struct qcom_nandc_props {
134
-
u32 ecc_modes;
135
-
u32 dev_cmd_reg_start;
136
-
bool is_bam;
137
-
bool is_qpic;
138
-
bool qpic_v2;
139
-
bool use_codeword_fixup;
140
-
};
141
-
142
-
/* Frees the BAM transaction memory */
143
-
static void free_bam_transaction(struct qcom_nand_controller *nandc)
144
-
{
145
-
struct bam_transaction *bam_txn = nandc->bam_txn;
146
-
147
-
devm_kfree(nandc->dev, bam_txn);
148
-
}
149
-
150
-
/* Allocates and Initializes the BAM transaction */
151
-
static struct bam_transaction *
152
-
alloc_bam_transaction(struct qcom_nand_controller *nandc)
153
-
{
154
-
struct bam_transaction *bam_txn;
155
-
size_t bam_txn_size;
156
-
unsigned int num_cw = nandc->max_cwperpage;
157
-
void *bam_txn_buf;
158
-
159
-
bam_txn_size =
160
-
sizeof(*bam_txn) + num_cw *
161
-
((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
162
-
(sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
163
-
(sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
164
-
165
-
bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
166
-
if (!bam_txn_buf)
167
-
return NULL;
168
-
169
-
bam_txn = bam_txn_buf;
170
-
bam_txn_buf += sizeof(*bam_txn);
171
-
172
-
bam_txn->bam_ce = bam_txn_buf;
173
-
bam_txn_buf +=
174
-
sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
175
-
176
-
bam_txn->cmd_sgl = bam_txn_buf;
177
-
bam_txn_buf +=
178
-
sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw;
179
-
180
-
bam_txn->data_sgl = bam_txn_buf;
181
-
182
-
init_completion(&bam_txn->txn_done);
183
-
184
-
return bam_txn;
185
-
}
186
-
187
-
/* Clears the BAM transaction indexes */
188
-
static void clear_bam_transaction(struct qcom_nand_controller *nandc)
189
-
{
190
-
struct bam_transaction *bam_txn = nandc->bam_txn;
191
-
192
-
if (!nandc->props->is_bam)
193
-
return;
194
-
195
-
bam_txn->bam_ce_pos = 0;
196
-
bam_txn->bam_ce_start = 0;
197
-
bam_txn->cmd_sgl_pos = 0;
198
-
bam_txn->cmd_sgl_start = 0;
199
-
bam_txn->tx_sgl_pos = 0;
200
-
bam_txn->tx_sgl_start = 0;
201
-
bam_txn->rx_sgl_pos = 0;
202
-
bam_txn->rx_sgl_start = 0;
203
-
bam_txn->last_data_desc = NULL;
204
-
bam_txn->wait_second_completion = false;
205
-
206
-
sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
207
-
QPIC_PER_CW_CMD_SGL);
208
-
sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage *
209
-
QPIC_PER_CW_DATA_SGL);
210
-
211
-
reinit_completion(&bam_txn->txn_done);
212
-
}
213
-
214
-
/* Callback for DMA descriptor completion */
215
-
static void qpic_bam_dma_done(void *data)
216
-
{
217
-
struct bam_transaction *bam_txn = data;
218
-
219
-
/*
220
-
* In case of data transfer with NAND, 2 callbacks will be generated.
221
-
* One for command channel and another one for data channel.
222
-
* If current transaction has data descriptors
223
-
* (i.e. wait_second_completion is true), then set this to false
224
-
* and wait for second DMA descriptor completion.
225
-
*/
226
-
if (bam_txn->wait_second_completion)
227
-
bam_txn->wait_second_completion = false;
228
-
else
229
-
complete(&bam_txn->txn_done);
230
-
}
231
-
232
-
static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
547
+
static struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
233
548
{
234
549
return container_of(chip, struct qcom_nand_host, chip);
235
550
}
236
551
237
-
static inline struct qcom_nand_controller *
552
+
static struct qcom_nand_controller *
238
553
get_qcom_nand_controller(struct nand_chip *chip)
239
554
{
240
-
return container_of(chip->controller, struct qcom_nand_controller,
241
-
controller);
555
+
return (struct qcom_nand_controller *)
556
+
((u8 *)chip->controller - sizeof(struct qcom_nand_controller));
242
557
}
243
558
244
-
static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset)
559
+
static u32 nandc_read(struct qcom_nand_controller *nandc, int offset)
245
560
{
246
561
return ioread32(nandc->base + offset);
247
562
}
248
563
249
-
static inline void nandc_write(struct qcom_nand_controller *nandc, int offset,
250
-
u32 val)
564
+
static void nandc_write(struct qcom_nand_controller *nandc, int offset,
565
+
u32 val)
251
566
{
252
567
iowrite32(val, nandc->base + offset);
253
568
}
254
569
255
-
static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,
256
-
bool is_cpu)
257
-
{
258
-
if (!nandc->props->is_bam)
259
-
return;
260
-
261
-
if (is_cpu)
262
-
dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma,
263
-
MAX_REG_RD *
264
-
sizeof(*nandc->reg_read_buf),
265
-
DMA_FROM_DEVICE);
266
-
else
267
-
dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma,
268
-
MAX_REG_RD *
269
-
sizeof(*nandc->reg_read_buf),
270
-
DMA_FROM_DEVICE);
271
-
}
272
-
273
-
static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
274
-
{
275
-
switch (offset) {
276
-
case NAND_FLASH_CMD:
277
-
return ®s->cmd;
278
-
case NAND_ADDR0:
279
-
return ®s->addr0;
280
-
case NAND_ADDR1:
281
-
return ®s->addr1;
282
-
case NAND_FLASH_CHIP_SELECT:
283
-
return ®s->chip_sel;
284
-
case NAND_EXEC_CMD:
285
-
return ®s->exec;
286
-
case NAND_FLASH_STATUS:
287
-
return ®s->clrflashstatus;
288
-
case NAND_DEV0_CFG0:
289
-
return ®s->cfg0;
290
-
case NAND_DEV0_CFG1:
291
-
return ®s->cfg1;
292
-
case NAND_DEV0_ECC_CFG:
293
-
return ®s->ecc_bch_cfg;
294
-
case NAND_READ_STATUS:
295
-
return ®s->clrreadstatus;
296
-
case NAND_DEV_CMD1:
297
-
return ®s->cmd1;
298
-
case NAND_DEV_CMD1_RESTORE:
299
-
return ®s->orig_cmd1;
300
-
case NAND_DEV_CMD_VLD:
301
-
return ®s->vld;
302
-
case NAND_DEV_CMD_VLD_RESTORE:
303
-
return ®s->orig_vld;
304
-
case NAND_EBI2_ECC_BUF_CFG:
305
-
return ®s->ecc_buf_cfg;
306
-
case NAND_READ_LOCATION_0:
307
-
return ®s->read_location0;
308
-
case NAND_READ_LOCATION_1:
309
-
return ®s->read_location1;
310
-
case NAND_READ_LOCATION_2:
311
-
return ®s->read_location2;
312
-
case NAND_READ_LOCATION_3:
313
-
return ®s->read_location3;
314
-
case NAND_READ_LOCATION_LAST_CW_0:
315
-
return ®s->read_location_last0;
316
-
case NAND_READ_LOCATION_LAST_CW_1:
317
-
return ®s->read_location_last1;
318
-
case NAND_READ_LOCATION_LAST_CW_2:
319
-
return ®s->read_location_last2;
320
-
case NAND_READ_LOCATION_LAST_CW_3:
321
-
return ®s->read_location_last3;
322
-
default:
323
-
return NULL;
324
-
}
325
-
}
326
-
327
-
static void nandc_set_reg(struct nand_chip *chip, int offset,
328
-
u32 val)
329
-
{
330
-
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
331
-
struct nandc_regs *regs = nandc->regs;
332
-
__le32 *reg;
333
-
334
-
reg = offset_to_nandc_reg(regs, offset);
335
-
336
-
if (reg)
337
-
*reg = cpu_to_le32(val);
338
-
}
339
-
340
-
/* Helper to check the code word, whether it is last cw or not */
570
+
/* Helper to check whether this is the last CW or not */
341
571
static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw)
342
572
{
343
573
return cw == (ecc->steps - 1);
344
574
}
345
575
576
+
/**
577
+
* nandc_set_read_loc_first() - to set read location first register
578
+
* @chip: NAND Private Flash Chip Data
579
+
* @reg_base: location register base
580
+
* @cw_offset: code word offset
581
+
* @read_size: code word read length
582
+
* @is_last_read_loc: is this the last read location
583
+
*
584
+
* This function will set location register value
585
+
*/
586
+
static void nandc_set_read_loc_first(struct nand_chip *chip,
587
+
int reg_base, u32 cw_offset,
588
+
u32 read_size, u32 is_last_read_loc)
589
+
{
590
+
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
591
+
__le32 locreg_val;
592
+
u32 val = (((cw_offset) << READ_LOCATION_OFFSET) |
593
+
((read_size) << READ_LOCATION_SIZE) |
594
+
((is_last_read_loc) << READ_LOCATION_LAST));
595
+
596
+
locreg_val = cpu_to_le32(val);
597
+
598
+
if (reg_base == NAND_READ_LOCATION_0)
599
+
nandc->regs->read_location0 = locreg_val;
600
+
else if (reg_base == NAND_READ_LOCATION_1)
601
+
nandc->regs->read_location1 = locreg_val;
602
+
else if (reg_base == NAND_READ_LOCATION_2)
603
+
nandc->regs->read_location2 = locreg_val;
604
+
else if (reg_base == NAND_READ_LOCATION_3)
605
+
nandc->regs->read_location3 = locreg_val;
606
+
}
607
+
608
+
/**
609
+
* nandc_set_read_loc_last - to set read location last register
610
+
* @chip: NAND Private Flash Chip Data
611
+
* @reg_base: location register base
612
+
* @cw_offset: code word offset
613
+
* @read_size: code word read length
614
+
* @is_last_read_loc: is this the last read location
615
+
*
616
+
* This function will set location last register value
617
+
*/
618
+
static void nandc_set_read_loc_last(struct nand_chip *chip,
619
+
int reg_base, u32 cw_offset,
620
+
u32 read_size, u32 is_last_read_loc)
621
+
{
622
+
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
623
+
__le32 locreg_val;
624
+
u32 val = (((cw_offset) << READ_LOCATION_OFFSET) |
625
+
((read_size) << READ_LOCATION_SIZE) |
626
+
((is_last_read_loc) << READ_LOCATION_LAST));
627
+
628
+
locreg_val = cpu_to_le32(val);
629
+
630
+
if (reg_base == NAND_READ_LOCATION_LAST_CW_0)
631
+
nandc->regs->read_location_last0 = locreg_val;
632
+
else if (reg_base == NAND_READ_LOCATION_LAST_CW_1)
633
+
nandc->regs->read_location_last1 = locreg_val;
634
+
else if (reg_base == NAND_READ_LOCATION_LAST_CW_2)
635
+
nandc->regs->read_location_last2 = locreg_val;
636
+
else if (reg_base == NAND_READ_LOCATION_LAST_CW_3)
637
+
nandc->regs->read_location_last3 = locreg_val;
638
+
}
639
+
346
640
/* helper to configure location register values */
347
641
static void nandc_set_read_loc(struct nand_chip *chip, int cw, int reg,
348
-
int cw_offset, int read_size, int is_last_read_loc)
642
+
u32 cw_offset, u32 read_size, u32 is_last_read_loc)
349
643
{
350
644
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
351
645
struct nand_ecc_ctrl *ecc = &chip->ecc;
352
646
int reg_base = NAND_READ_LOCATION_0;
353
647
354
-
if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw))
648
+
if (nandc->props->qpic_version2 && qcom_nandc_is_last_cw(ecc, cw))
355
649
reg_base = NAND_READ_LOCATION_LAST_CW_0;
356
650
357
651
reg_base += reg * 4;
358
652
359
-
if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw))
653
+
if (nandc->props->qpic_version2 && qcom_nandc_is_last_cw(ecc, cw))
360
654
return nandc_set_read_loc_last(chip, reg_base, cw_offset,
361
655
read_size, is_last_read_loc);
362
656
else
···
238
792
static void set_address(struct qcom_nand_host *host, u16 column, int page)
239
793
{
240
794
struct nand_chip *chip = &host->chip;
795
+
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
241
796
242
797
if (chip->options & NAND_BUSWIDTH_16)
243
798
column >>= 1;
244
799
245
-
nandc_set_reg(chip, NAND_ADDR0, page << 16 | column);
246
-
nandc_set_reg(chip, NAND_ADDR1, page >> 16 & 0xff);
800
+
nandc->regs->addr0 = cpu_to_le32(page << 16 | column);
801
+
nandc->regs->addr1 = cpu_to_le32(page >> 16 & 0xff);
247
802
}
248
803
249
804
/*
···
258
811
static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, int cw)
259
812
{
260
813
struct nand_chip *chip = &host->chip;
261
-
u32 cmd, cfg0, cfg1, ecc_bch_cfg;
814
+
__le32 cmd, cfg0, cfg1, ecc_bch_cfg;
262
815
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
263
816
264
817
if (read) {
265
818
if (host->use_ecc)
266
-
cmd = OP_PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
819
+
cmd = cpu_to_le32(OP_PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE);
267
820
else
268
-
cmd = OP_PAGE_READ | PAGE_ACC | LAST_PAGE;
821
+
cmd = cpu_to_le32(OP_PAGE_READ | PAGE_ACC | LAST_PAGE);
269
822
} else {
270
-
cmd = OP_PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
823
+
cmd = cpu_to_le32(OP_PROGRAM_PAGE | PAGE_ACC | LAST_PAGE);
271
824
}
272
825
273
826
if (host->use_ecc) {
274
-
cfg0 = (host->cfg0 & ~(7U << CW_PER_PAGE)) |
275
-
(num_cw - 1) << CW_PER_PAGE;
827
+
cfg0 = cpu_to_le32((host->cfg0 & ~(7U << CW_PER_PAGE)) |
828
+
(num_cw - 1) << CW_PER_PAGE);
276
829
277
-
cfg1 = host->cfg1;
278
-
ecc_bch_cfg = host->ecc_bch_cfg;
830
+
cfg1 = cpu_to_le32(host->cfg1);
831
+
ecc_bch_cfg = cpu_to_le32(host->ecc_bch_cfg);
279
832
} else {
280
-
cfg0 = (host->cfg0_raw & ~(7U << CW_PER_PAGE)) |
281
-
(num_cw - 1) << CW_PER_PAGE;
833
+
cfg0 = cpu_to_le32((host->cfg0_raw & ~(7U << CW_PER_PAGE)) |
834
+
(num_cw - 1) << CW_PER_PAGE);
282
835
283
-
cfg1 = host->cfg1_raw;
284
-
ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
836
+
cfg1 = cpu_to_le32(host->cfg1_raw);
837
+
ecc_bch_cfg = cpu_to_le32(ECC_CFG_ECC_DISABLE);
285
838
}
286
839
287
-
nandc_set_reg(chip, NAND_FLASH_CMD, cmd);
288
-
nandc_set_reg(chip, NAND_DEV0_CFG0, cfg0);
289
-
nandc_set_reg(chip, NAND_DEV0_CFG1, cfg1);
290
-
nandc_set_reg(chip, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
291
-
if (!nandc->props->qpic_v2)
292
-
nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
293
-
nandc_set_reg(chip, NAND_FLASH_STATUS, host->clrflashstatus);
294
-
nandc_set_reg(chip, NAND_READ_STATUS, host->clrreadstatus);
295
-
nandc_set_reg(chip, NAND_EXEC_CMD, 1);
840
+
nandc->regs->cmd = cmd;
841
+
nandc->regs->cfg0 = cfg0;
842
+
nandc->regs->cfg1 = cfg1;
843
+
nandc->regs->ecc_bch_cfg = ecc_bch_cfg;
844
+
845
+
if (!nandc->props->qpic_version2)
846
+
nandc->regs->ecc_buf_cfg = cpu_to_le32(host->ecc_buf_cfg);
847
+
848
+
nandc->regs->clrflashstatus = cpu_to_le32(host->clrflashstatus);
849
+
nandc->regs->clrreadstatus = cpu_to_le32(host->clrreadstatus);
850
+
nandc->regs->exec = cpu_to_le32(1);
296
851
297
852
if (read)
298
853
nandc_set_read_loc(chip, cw, 0, 0, host->use_ecc ?
299
854
host->cw_data : host->cw_size, 1);
300
-
}
301
-
302
-
/*
303
-
* Maps the scatter gather list for DMA transfer and forms the DMA descriptor
304
-
* for BAM. This descriptor will be added in the NAND DMA descriptor queue
305
-
* which will be submitted to DMA engine.
306
-
*/
307
-
static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
308
-
struct dma_chan *chan,
309
-
unsigned long flags)
310
-
{
311
-
struct desc_info *desc;
312
-
struct scatterlist *sgl;
313
-
unsigned int sgl_cnt;
314
-
int ret;
315
-
struct bam_transaction *bam_txn = nandc->bam_txn;
316
-
enum dma_transfer_direction dir_eng;
317
-
struct dma_async_tx_descriptor *dma_desc;
318
-
319
-
desc = kzalloc(sizeof(*desc), GFP_KERNEL);
320
-
if (!desc)
321
-
return -ENOMEM;
322
-
323
-
if (chan == nandc->cmd_chan) {
324
-
sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start];
325
-
sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
326
-
bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
327
-
dir_eng = DMA_MEM_TO_DEV;
328
-
desc->dir = DMA_TO_DEVICE;
329
-
} else if (chan == nandc->tx_chan) {
330
-
sgl = &bam_txn->data_sgl[bam_txn->tx_sgl_start];
331
-
sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
332
-
bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
333
-
dir_eng = DMA_MEM_TO_DEV;
334
-
desc->dir = DMA_TO_DEVICE;
335
-
} else {
336
-
sgl = &bam_txn->data_sgl[bam_txn->rx_sgl_start];
337
-
sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
338
-
bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
339
-
dir_eng = DMA_DEV_TO_MEM;
340
-
desc->dir = DMA_FROM_DEVICE;
341
-
}
342
-
343
-
sg_mark_end(sgl + sgl_cnt - 1);
344
-
ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
345
-
if (ret == 0) {
346
-
dev_err(nandc->dev, "failure in mapping desc\n");
347
-
kfree(desc);
348
-
return -ENOMEM;
349
-
}
350
-
351
-
desc->sgl_cnt = sgl_cnt;
352
-
desc->bam_sgl = sgl;
353
-
354
-
dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
355
-
flags);
356
-
357
-
if (!dma_desc) {
358
-
dev_err(nandc->dev, "failure in prep desc\n");
359
-
dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
360
-
kfree(desc);
361
-
return -EINVAL;
362
-
}
363
-
364
-
desc->dma_desc = dma_desc;
365
-
366
-
/* update last data/command descriptor */
367
-
if (chan == nandc->cmd_chan)
368
-
bam_txn->last_cmd_desc = dma_desc;
369
-
else
370
-
bam_txn->last_data_desc = dma_desc;
371
-
372
-
list_add_tail(&desc->node, &nandc->desc_list);
373
-
374
-
return 0;
375
-
}
376
-
377
-
/*
378
-
* Prepares the command descriptor for BAM DMA which will be used for NAND
379
-
* register reads and writes. The command descriptor requires the command
380
-
* to be formed in command element type so this function uses the command
381
-
* element from bam transaction ce array and fills the same with required
382
-
* data. A single SGL can contain multiple command elements so
383
-
* NAND_BAM_NEXT_SGL will be used for starting the separate SGL
384
-
* after the current command element.
385
-
*/
386
-
static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
387
-
int reg_off, const void *vaddr,
388
-
int size, unsigned int flags)
389
-
{
390
-
int bam_ce_size;
391
-
int i, ret;
392
-
struct bam_cmd_element *bam_ce_buffer;
393
-
struct bam_transaction *bam_txn = nandc->bam_txn;
394
-
395
-
bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
396
-
397
-
/* fill the command desc */
398
-
for (i = 0; i < size; i++) {
399
-
if (read)
400
-
bam_prep_ce(&bam_ce_buffer[i],
401
-
nandc_reg_phys(nandc, reg_off + 4 * i),
402
-
BAM_READ_COMMAND,
403
-
reg_buf_dma_addr(nandc,
404
-
(__le32 *)vaddr + i));
405
-
else
406
-
bam_prep_ce_le32(&bam_ce_buffer[i],
407
-
nandc_reg_phys(nandc, reg_off + 4 * i),
408
-
BAM_WRITE_COMMAND,
409
-
*((__le32 *)vaddr + i));
410
-
}
411
-
412
-
bam_txn->bam_ce_pos += size;
413
-
414
-
/* use the separate sgl after this command */
415
-
if (flags & NAND_BAM_NEXT_SGL) {
416
-
bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
417
-
bam_ce_size = (bam_txn->bam_ce_pos -
418
-
bam_txn->bam_ce_start) *
419
-
sizeof(struct bam_cmd_element);
420
-
sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
421
-
bam_ce_buffer, bam_ce_size);
422
-
bam_txn->cmd_sgl_pos++;
423
-
bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
424
-
425
-
if (flags & NAND_BAM_NWD) {
426
-
ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
427
-
DMA_PREP_FENCE |
428
-
DMA_PREP_CMD);
429
-
if (ret)
430
-
return ret;
431
-
}
432
-
}
433
-
434
-
return 0;
435
-
}
436
-
437
-
/*
438
-
* Prepares the data descriptor for BAM DMA which will be used for NAND
439
-
* data reads and writes.
440
-
*/
441
-
static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
442
-
const void *vaddr,
443
-
int size, unsigned int flags)
444
-
{
445
-
int ret;
446
-
struct bam_transaction *bam_txn = nandc->bam_txn;
447
-
448
-
if (read) {
449
-
sg_set_buf(&bam_txn->data_sgl[bam_txn->rx_sgl_pos],
450
-
vaddr, size);
451
-
bam_txn->rx_sgl_pos++;
452
-
} else {
453
-
sg_set_buf(&bam_txn->data_sgl[bam_txn->tx_sgl_pos],
454
-
vaddr, size);
455
-
bam_txn->tx_sgl_pos++;
456
-
457
-
/*
458
-
* BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
459
-
* is not set, form the DMA descriptor
460
-
*/
461
-
if (!(flags & NAND_BAM_NO_EOT)) {
462
-
ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
463
-
DMA_PREP_INTERRUPT);
464
-
if (ret)
465
-
return ret;
466
-
}
467
-
}
468
-
469
-
return 0;
470
-
}
471
-
472
-
static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
473
-
int reg_off, const void *vaddr, int size,
474
-
bool flow_control)
475
-
{
476
-
struct desc_info *desc;
477
-
struct dma_async_tx_descriptor *dma_desc;
478
-
struct scatterlist *sgl;
479
-
struct dma_slave_config slave_conf;
480
-
struct qcom_adm_peripheral_config periph_conf = {};
481
-
enum dma_transfer_direction dir_eng;
482
-
int ret;
483
-
484
-
desc = kzalloc(sizeof(*desc), GFP_KERNEL);
485
-
if (!desc)
486
-
return -ENOMEM;
487
-
488
-
sgl = &desc->adm_sgl;
489
-
490
-
sg_init_one(sgl, vaddr, size);
491
-
492
-
if (read) {
493
-
dir_eng = DMA_DEV_TO_MEM;
494
-
desc->dir = DMA_FROM_DEVICE;
495
-
} else {
496
-
dir_eng = DMA_MEM_TO_DEV;
497
-
desc->dir = DMA_TO_DEVICE;
498
-
}
499
-
500
-
ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir);
501
-
if (ret == 0) {
502
-
ret = -ENOMEM;
503
-
goto err;
504
-
}
505
-
506
-
memset(&slave_conf, 0x00, sizeof(slave_conf));
507
-
508
-
slave_conf.device_fc = flow_control;
509
-
if (read) {
510
-
slave_conf.src_maxburst = 16;
511
-
slave_conf.src_addr = nandc->base_dma + reg_off;
512
-
if (nandc->data_crci) {
513
-
periph_conf.crci = nandc->data_crci;
514
-
slave_conf.peripheral_config = &periph_conf;
515
-
slave_conf.peripheral_size = sizeof(periph_conf);
516
-
}
517
-
} else {
518
-
slave_conf.dst_maxburst = 16;
519
-
slave_conf.dst_addr = nandc->base_dma + reg_off;
520
-
if (nandc->cmd_crci) {
521
-
periph_conf.crci = nandc->cmd_crci;
522
-
slave_conf.peripheral_config = &periph_conf;
523
-
slave_conf.peripheral_size = sizeof(periph_conf);
524
-
}
525
-
}
526
-
527
-
ret = dmaengine_slave_config(nandc->chan, &slave_conf);
528
-
if (ret) {
529
-
dev_err(nandc->dev, "failed to configure dma channel\n");
530
-
goto err;
531
-
}
532
-
533
-
dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0);
534
-
if (!dma_desc) {
535
-
dev_err(nandc->dev, "failed to prepare desc\n");
536
-
ret = -EINVAL;
537
-
goto err;
538
-
}
539
-
540
-
desc->dma_desc = dma_desc;
541
-
542
-
list_add_tail(&desc->node, &nandc->desc_list);
543
-
544
-
return 0;
545
-
err:
546
-
kfree(desc);
547
-
548
-
return ret;
549
-
}
550
-
551
-
/*
552
-
* read_reg_dma: prepares a descriptor to read a given number of
553
-
* contiguous registers to the reg_read_buf pointer
554
-
*
555
-
* @first: offset of the first register in the contiguous block
556
-
* @num_regs: number of registers to read
557
-
* @flags: flags to control DMA descriptor preparation
558
-
*/
559
-
static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
560
-
int num_regs, unsigned int flags)
561
-
{
562
-
bool flow_control = false;
563
-
void *vaddr;
564
-
565
-
vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
566
-
nandc->reg_read_pos += num_regs;
567
-
568
-
if (first == NAND_DEV_CMD_VLD || first == NAND_DEV_CMD1)
569
-
first = dev_cmd_reg_addr(nandc, first);
570
-
571
-
if (nandc->props->is_bam)
572
-
return prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
573
-
num_regs, flags);
574
-
575
-
if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
576
-
flow_control = true;
577
-
578
-
return prep_adm_dma_desc(nandc, true, first, vaddr,
579
-
num_regs * sizeof(u32), flow_control);
580
-
}
581
-
582
-
/*
583
-
* write_reg_dma: prepares a descriptor to write a given number of
584
-
* contiguous registers
585
-
*
586
-
* @first: offset of the first register in the contiguous block
587
-
* @num_regs: number of registers to write
588
-
* @flags: flags to control DMA descriptor preparation
589
-
*/
590
-
static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
591
-
int num_regs, unsigned int flags)
592
-
{
593
-
bool flow_control = false;
594
-
struct nandc_regs *regs = nandc->regs;
595
-
void *vaddr;
596
-
597
-
vaddr = offset_to_nandc_reg(regs, first);
598
-
599
-
if (first == NAND_ERASED_CW_DETECT_CFG) {
600
-
if (flags & NAND_ERASED_CW_SET)
601
-
vaddr = ®s->erased_cw_detect_cfg_set;
602
-
else
603
-
vaddr = ®s->erased_cw_detect_cfg_clr;
604
-
}
605
-
606
-
if (first == NAND_EXEC_CMD)
607
-
flags |= NAND_BAM_NWD;
608
-
609
-
if (first == NAND_DEV_CMD1_RESTORE || first == NAND_DEV_CMD1)
610
-
first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD1);
611
-
612
-
if (first == NAND_DEV_CMD_VLD_RESTORE || first == NAND_DEV_CMD_VLD)
613
-
first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD);
614
-
615
-
if (nandc->props->is_bam)
616
-
return prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
617
-
num_regs, flags);
618
-
619
-
if (first == NAND_FLASH_CMD)
620
-
flow_control = true;
621
-
622
-
return prep_adm_dma_desc(nandc, false, first, vaddr,
623
-
num_regs * sizeof(u32), flow_control);
624
-
}
625
-
626
-
/*
627
-
* read_data_dma: prepares a DMA descriptor to transfer data from the
628
-
* controller's internal buffer to the buffer 'vaddr'
629
-
*
630
-
* @reg_off: offset within the controller's data buffer
631
-
* @vaddr: virtual address of the buffer we want to write to
632
-
* @size: DMA transaction size in bytes
633
-
* @flags: flags to control DMA descriptor preparation
634
-
*/
635
-
static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
636
-
const u8 *vaddr, int size, unsigned int flags)
637
-
{
638
-
if (nandc->props->is_bam)
639
-
return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags);
640
-
641
-
return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
642
-
}
643
-
644
-
/*
645
-
* write_data_dma: prepares a DMA descriptor to transfer data from
646
-
* 'vaddr' to the controller's internal buffer
647
-
*
648
-
* @reg_off: offset within the controller's data buffer
649
-
* @vaddr: virtual address of the buffer we want to read from
650
-
* @size: DMA transaction size in bytes
651
-
* @flags: flags to control DMA descriptor preparation
652
-
*/
653
-
static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
654
-
const u8 *vaddr, int size, unsigned int flags)
655
-
{
656
-
if (nandc->props->is_bam)
657
-
return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags);
658
-
659
-
return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
660
855
}
661
856
662
857
/*
···
309
1220
{
310
1221
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
311
1222
312
-
write_reg_dma(nandc, NAND_ADDR0, 2, 0);
313
-
write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
314
-
if (!nandc->props->qpic_v2)
315
-
write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
316
-
write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
317
-
write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
318
-
NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
1223
+
qcom_write_reg_dma(nandc, &nandc->regs->addr0, NAND_ADDR0, 2, 0);
1224
+
qcom_write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
1225
+
if (!nandc->props->qpic_version2)
1226
+
qcom_write_reg_dma(nandc, &nandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0);
1227
+
qcom_write_reg_dma(nandc, &nandc->regs->erased_cw_detect_cfg_clr,
1228
+
NAND_ERASED_CW_DETECT_CFG, 1, 0);
1229
+
qcom_write_reg_dma(nandc, &nandc->regs->erased_cw_detect_cfg_set,
1230
+
NAND_ERASED_CW_DETECT_CFG, 1, NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
319
1231
}
320
1232
321
1233
/*
···
329
1239
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
330
1240
struct nand_ecc_ctrl *ecc = &chip->ecc;
331
1241
332
-
int reg = NAND_READ_LOCATION_0;
1242
+
__le32 *reg = &nandc->regs->read_location0;
333
1243
334
-
if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw))
335
-
reg = NAND_READ_LOCATION_LAST_CW_0;
1244
+
if (nandc->props->qpic_version2 && qcom_nandc_is_last_cw(ecc, cw))
1245
+
reg = &nandc->regs->read_location_last0;
336
1246
337
-
if (nandc->props->is_bam)
338
-
write_reg_dma(nandc, reg, 4, NAND_BAM_NEXT_SGL);
1247
+
if (nandc->props->supports_bam)
1248
+
qcom_write_reg_dma(nandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SGL);
339
1249
340
-
write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
341
-
write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1250
+
qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
1251
+
qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
342
1252
343
1253
if (use_ecc) {
344
-
read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
345
-
read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
346
-
NAND_BAM_NEXT_SGL);
1254
+
qcom_read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
1255
+
qcom_read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
1256
+
NAND_BAM_NEXT_SGL);
347
1257
} else {
348
-
read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1258
+
qcom_read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
349
1259
}
350
1260
}
351
1261
···
369
1279
{
370
1280
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
371
1281
372
-
write_reg_dma(nandc, NAND_ADDR0, 2, 0);
373
-
write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
374
-
if (!nandc->props->qpic_v2)
375
-
write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
376
-
NAND_BAM_NEXT_SGL);
1282
+
qcom_write_reg_dma(nandc, &nandc->regs->addr0, NAND_ADDR0, 2, 0);
1283
+
qcom_write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
1284
+
if (!nandc->props->qpic_version2)
1285
+
qcom_write_reg_dma(nandc, &nandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1,
1286
+
NAND_BAM_NEXT_SGL);
377
1287
}
378
1288
379
1289
/*
···
384
1294
{
385
1295
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
386
1296
387
-
write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
388
-
write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1297
+
qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
1298
+
qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
389
1299
390
-
read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1300
+
qcom_read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
391
1301
392
-
write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
393
-
write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
394
-
}
395
-
396
-
/* helpers to submit/free our list of dma descriptors */
397
-
static int submit_descs(struct qcom_nand_controller *nandc)
398
-
{
399
-
struct desc_info *desc, *n;
400
-
dma_cookie_t cookie = 0;
401
-
struct bam_transaction *bam_txn = nandc->bam_txn;
402
-
int ret = 0;
403
-
404
-
if (nandc->props->is_bam) {
405
-
if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) {
406
-
ret = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
407
-
if (ret)
408
-
goto err_unmap_free_desc;
409
-
}
410
-
411
-
if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) {
412
-
ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
413
-
DMA_PREP_INTERRUPT);
414
-
if (ret)
415
-
goto err_unmap_free_desc;
416
-
}
417
-
418
-
if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) {
419
-
ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
420
-
DMA_PREP_CMD);
421
-
if (ret)
422
-
goto err_unmap_free_desc;
423
-
}
424
-
}
425
-
426
-
list_for_each_entry(desc, &nandc->desc_list, node)
427
-
cookie = dmaengine_submit(desc->dma_desc);
428
-
429
-
if (nandc->props->is_bam) {
430
-
bam_txn->last_cmd_desc->callback = qpic_bam_dma_done;
431
-
bam_txn->last_cmd_desc->callback_param = bam_txn;
432
-
if (bam_txn->last_data_desc) {
433
-
bam_txn->last_data_desc->callback = qpic_bam_dma_done;
434
-
bam_txn->last_data_desc->callback_param = bam_txn;
435
-
bam_txn->wait_second_completion = true;
436
-
}
437
-
438
-
dma_async_issue_pending(nandc->tx_chan);
439
-
dma_async_issue_pending(nandc->rx_chan);
440
-
dma_async_issue_pending(nandc->cmd_chan);
441
-
442
-
if (!wait_for_completion_timeout(&bam_txn->txn_done,
443
-
QPIC_NAND_COMPLETION_TIMEOUT))
444
-
ret = -ETIMEDOUT;
445
-
} else {
446
-
if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
447
-
ret = -ETIMEDOUT;
448
-
}
449
-
450
-
err_unmap_free_desc:
451
-
/*
452
-
* Unmap the dma sg_list and free the desc allocated by both
453
-
* prepare_bam_async_desc() and prep_adm_dma_desc() functions.
454
-
*/
455
-
list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
456
-
list_del(&desc->node);
457
-
458
-
if (nandc->props->is_bam)
459
-
dma_unmap_sg(nandc->dev, desc->bam_sgl,
460
-
desc->sgl_cnt, desc->dir);
461
-
else
462
-
dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1,
463
-
desc->dir);
464
-
465
-
kfree(desc);
466
-
}
467
-
468
-
return ret;
469
-
}
470
-
471
-
/* reset the register read buffer for next NAND operation */
472
-
static void clear_read_regs(struct qcom_nand_controller *nandc)
473
-
{
474
-
nandc->reg_read_pos = 0;
475
-
nandc_read_buffer_sync(nandc, false);
1302
+
qcom_write_reg_dma(nandc, &nandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0);
1303
+
qcom_write_reg_dma(nandc, &nandc->regs->clrreadstatus, NAND_READ_STATUS, 1,
1304
+
NAND_BAM_NEXT_SGL);
476
1305
}
477
1306
478
1307
/*
···
455
1446
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
456
1447
int i;
457
1448
458
-
nandc_read_buffer_sync(nandc, true);
1449
+
qcom_nandc_dev_to_mem(nandc, true);
459
1450
460
1451
for (i = 0; i < cw_cnt; i++) {
461
1452
u32 flash = le32_to_cpu(nandc->reg_read_buf[i]);
···
482
1473
nand_read_page_op(chip, page, 0, NULL, 0);
483
1474
nandc->buf_count = 0;
484
1475
nandc->buf_start = 0;
485
-
clear_read_regs(nandc);
1476
+
qcom_clear_read_regs(nandc);
486
1477
host->use_ecc = false;
487
1478
488
-
if (nandc->props->qpic_v2)
1479
+
if (nandc->props->qpic_version2)
489
1480
raw_cw = ecc->steps - 1;
490
1481
491
-
clear_bam_transaction(nandc);
1482
+
qcom_clear_bam_transaction(nandc);
492
1483
set_address(host, host->cw_size * cw, page);
493
1484
update_rw_regs(host, 1, true, raw_cw);
494
1485
config_nand_page_read(chip);
···
506
1497
oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
507
1498
}
508
1499
509
-
if (nandc->props->is_bam) {
1500
+
if (nandc->props->supports_bam) {
510
1501
nandc_set_read_loc(chip, cw, 0, read_loc, data_size1, 0);
511
1502
read_loc += data_size1;
512
1503
···
521
1512
522
1513
config_nand_cw_read(chip, false, raw_cw);
523
1514
524
-
read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
1515
+
qcom_read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
525
1516
reg_off += data_size1;
526
1517
527
-
read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
1518
+
qcom_read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
528
1519
reg_off += oob_size1;
529
1520
530
-
read_data_dma(nandc, reg_off, data_buf + data_size1, data_size2, 0);
1521
+
qcom_read_data_dma(nandc, reg_off, data_buf + data_size1, data_size2, 0);
531
1522
reg_off += data_size2;
532
1523
533
-
read_data_dma(nandc, reg_off, oob_buf + oob_size1, oob_size2, 0);
1524
+
qcom_read_data_dma(nandc, reg_off, oob_buf + oob_size1, oob_size2, 0);
534
1525
535
-
ret = submit_descs(nandc);
1526
+
ret = qcom_submit_descs(nandc);
536
1527
if (ret) {
537
1528
dev_err(nandc->dev, "failure to read raw cw %d\n", cw);
538
1529
return ret;
···
630
1621
u8 *data_buf_start = data_buf, *oob_buf_start = oob_buf;
631
1622
632
1623
buf = (struct read_stats *)nandc->reg_read_buf;
633
-
nandc_read_buffer_sync(nandc, true);
1624
+
qcom_nandc_dev_to_mem(nandc, true);
634
1625
635
1626
for (i = 0; i < ecc->steps; i++, buf++) {
636
1627
u32 flash, buffer, erased_cw;
···
743
1734
oob_size = host->ecc_bytes_hw + host->spare_bytes;
744
1735
}
745
1736
746
-
if (nandc->props->is_bam) {
1737
+
if (nandc->props->supports_bam) {
747
1738
if (data_buf && oob_buf) {
748
1739
nandc_set_read_loc(chip, i, 0, 0, data_size, 0);
749
1740
nandc_set_read_loc(chip, i, 1, data_size,
···
759
1750
config_nand_cw_read(chip, true, i);
760
1751
761
1752
if (data_buf)
762
-
read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
763
-
data_size, 0);
1753
+
qcom_read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
1754
+
data_size, 0);
764
1755
765
1756
/*
766
1757
* when ecc is enabled, the controller doesn't read the real
···
775
1766
for (j = 0; j < host->bbm_size; j++)
776
1767
*oob_buf++ = 0xff;
777
1768
778
-
read_data_dma(nandc, FLASH_BUF_ACC + data_size,
779
-
oob_buf, oob_size, 0);
1769
+
qcom_read_data_dma(nandc, FLASH_BUF_ACC + data_size,
1770
+
oob_buf, oob_size, 0);
780
1771
}
781
1772
782
1773
if (data_buf)
···
785
1776
oob_buf += oob_size;
786
1777
}
787
1778
788
-
ret = submit_descs(nandc);
1779
+
ret = qcom_submit_descs(nandc);
789
1780
if (ret) {
790
1781
dev_err(nandc->dev, "failure to read page/oob\n");
791
1782
return ret;
···
806
1797
int size;
807
1798
int ret;
808
1799
809
-
clear_read_regs(nandc);
1800
+
qcom_clear_read_regs(nandc);
810
1801
811
1802
size = host->use_ecc ? host->cw_data : host->cw_size;
812
1803
···
818
1809
819
1810
config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - 1);
820
1811
821
-
read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
1812
+
qcom_read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
822
1813
823
-
ret = submit_descs(nandc);
1814
+
ret = qcom_submit_descs(nandc);
824
1815
if (ret)
825
1816
dev_err(nandc->dev, "failed to copy last codeword\n");
826
1817
···
906
1897
nandc->buf_count = 0;
907
1898
nandc->buf_start = 0;
908
1899
host->use_ecc = true;
909
-
clear_read_regs(nandc);
1900
+
qcom_clear_read_regs(nandc);
910
1901
set_address(host, 0, page);
911
1902
update_rw_regs(host, ecc->steps, true, 0);
912
1903
913
1904
data_buf = buf;
914
1905
oob_buf = oob_required ? chip->oob_poi : NULL;
915
1906
916
-
clear_bam_transaction(nandc);
1907
+
qcom_clear_bam_transaction(nandc);
917
1908
918
1909
return read_page_ecc(host, data_buf, oob_buf, page);
919
1910
}
···
954
1945
if (host->nr_boot_partitions)
955
1946
qcom_nandc_codeword_fixup(host, page);
956
1947
957
-
clear_read_regs(nandc);
958
-
clear_bam_transaction(nandc);
1948
+
qcom_clear_read_regs(nandc);
1949
+
qcom_clear_bam_transaction(nandc);
959
1950
960
1951
host->use_ecc = true;
961
1952
set_address(host, 0, page);
···
982
1973
set_address(host, 0, page);
983
1974
nandc->buf_count = 0;
984
1975
nandc->buf_start = 0;
985
-
clear_read_regs(nandc);
986
-
clear_bam_transaction(nandc);
1976
+
qcom_clear_read_regs(nandc);
1977
+
qcom_clear_bam_transaction(nandc);
987
1978
988
1979
data_buf = (u8 *)buf;
989
1980
oob_buf = chip->oob_poi;
···
1004
1995
oob_size = ecc->bytes;
1005
1996
}
1006
1997
1007
-
write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size,
1008
-
i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0);
1998
+
qcom_write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size,
1999
+
i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0);
1009
2000
1010
2001
/*
1011
2002
* when ECC is enabled, we don't really need to write anything
···
1017
2008
if (qcom_nandc_is_last_cw(ecc, i)) {
1018
2009
oob_buf += host->bbm_size;
1019
2010
1020
-
write_data_dma(nandc, FLASH_BUF_ACC + data_size,
1021
-
oob_buf, oob_size, 0);
2011
+
qcom_write_data_dma(nandc, FLASH_BUF_ACC + data_size,
2012
+
oob_buf, oob_size, 0);
1022
2013
}
1023
2014
1024
2015
config_nand_cw_write(chip);
···
1027
2018
oob_buf += oob_size;
1028
2019
}
1029
2020
1030
-
ret = submit_descs(nandc);
2021
+
ret = qcom_submit_descs(nandc);
1031
2022
if (ret) {
1032
2023
dev_err(nandc->dev, "failure to write page\n");
1033
2024
return ret;
···
1052
2043
qcom_nandc_codeword_fixup(host, page);
1053
2044
1054
2045
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1055
-
clear_read_regs(nandc);
1056
-
clear_bam_transaction(nandc);
2046
+
qcom_clear_read_regs(nandc);
2047
+
qcom_clear_bam_transaction(nandc);
1057
2048
1058
2049
data_buf = (u8 *)buf;
1059
2050
oob_buf = chip->oob_poi;
···
1079
2070
oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
1080
2071
}
1081
2072
1082
-
write_data_dma(nandc, reg_off, data_buf, data_size1,
1083
-
NAND_BAM_NO_EOT);
2073
+
qcom_write_data_dma(nandc, reg_off, data_buf, data_size1,
2074
+
NAND_BAM_NO_EOT);
1084
2075
reg_off += data_size1;
1085
2076
data_buf += data_size1;
1086
2077
1087
-
write_data_dma(nandc, reg_off, oob_buf, oob_size1,
1088
-
NAND_BAM_NO_EOT);
2078
+
qcom_write_data_dma(nandc, reg_off, oob_buf, oob_size1,
2079
+
NAND_BAM_NO_EOT);
1089
2080
reg_off += oob_size1;
1090
2081
oob_buf += oob_size1;
1091
2082
1092
-
write_data_dma(nandc, reg_off, data_buf, data_size2,
1093
-
NAND_BAM_NO_EOT);
2083
+
qcom_write_data_dma(nandc, reg_off, data_buf, data_size2,
2084
+
NAND_BAM_NO_EOT);
1094
2085
reg_off += data_size2;
1095
2086
data_buf += data_size2;
1096
2087
1097
-
write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
2088
+
qcom_write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
1098
2089
oob_buf += oob_size2;
1099
2090
1100
2091
config_nand_cw_write(chip);
1101
2092
}
1102
2093
1103
-
ret = submit_descs(nandc);
2094
+
ret = qcom_submit_descs(nandc);
1104
2095
if (ret) {
1105
2096
dev_err(nandc->dev, "failure to write raw page\n");
1106
2097
return ret;
···
1130
2121
qcom_nandc_codeword_fixup(host, page);
1131
2122
1132
2123
host->use_ecc = true;
1133
-
clear_bam_transaction(nandc);
2124
+
qcom_clear_bam_transaction(nandc);
1134
2125
1135
2126
/* calculate the data and oob size for the last codeword/step */
1136
2127
data_size = ecc->size - ((ecc->steps - 1) << 2);
···
1145
2136
update_rw_regs(host, 1, false, 0);
1146
2137
1147
2138
config_nand_page_write(chip);
1148
-
write_data_dma(nandc, FLASH_BUF_ACC,
1149
-
nandc->data_buffer, data_size + oob_size, 0);
2139
+
qcom_write_data_dma(nandc, FLASH_BUF_ACC,
2140
+
nandc->data_buffer, data_size + oob_size, 0);
1150
2141
config_nand_cw_write(chip);
1151
2142
1152
-
ret = submit_descs(nandc);
2143
+
ret = qcom_submit_descs(nandc);
1153
2144
if (ret) {
1154
2145
dev_err(nandc->dev, "failure to write oob\n");
1155
2146
return ret;
···
1176
2167
*/
1177
2168
host->use_ecc = false;
1178
2169
1179
-
clear_bam_transaction(nandc);
2170
+
qcom_clear_bam_transaction(nandc);
1180
2171
ret = copy_last_cw(host, page);
1181
2172
if (ret)
1182
2173
goto err;
···
1203
2194
struct nand_ecc_ctrl *ecc = &chip->ecc;
1204
2195
int page, ret;
1205
2196
1206
-
clear_read_regs(nandc);
1207
-
clear_bam_transaction(nandc);
2197
+
qcom_clear_read_regs(nandc);
2198
+
qcom_clear_bam_transaction(nandc);
1208
2199
1209
2200
/*
1210
2201
* to mark the BBM as bad, we flash the entire last codeword with 0s.
···
1221
2212
update_rw_regs(host, 1, false, ecc->steps - 1);
1222
2213
1223
2214
config_nand_page_write(chip);
1224
-
write_data_dma(nandc, FLASH_BUF_ACC,
1225
-
nandc->data_buffer, host->cw_size, 0);
2215
+
qcom_write_data_dma(nandc, FLASH_BUF_ACC,
2216
+
nandc->data_buffer, host->cw_size, 0);
1226
2217
config_nand_cw_write(chip);
1227
2218
1228
-
ret = submit_descs(nandc);
2219
+
ret = qcom_submit_descs(nandc);
1229
2220
if (ret) {
1230
2221
dev_err(nandc->dev, "failure to update BBM\n");
1231
2222
return ret;
···
1464
2455
1465
2456
mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops);
1466
2457
/* Free the initially allocated BAM transaction for reading the ONFI params */
1467
-
if (nandc->props->is_bam)
1468
-
free_bam_transaction(nandc);
2458
+
if (nandc->props->supports_bam)
2459
+
qcom_free_bam_transaction(nandc);
1469
2460
1470
2461
nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage,
1471
2462
cwperpage);
1472
2463
1473
2464
/* Now allocate the BAM transaction based on updated max_cwperpage */
1474
-
if (nandc->props->is_bam) {
1475
-
nandc->bam_txn = alloc_bam_transaction(nandc);
2465
+
if (nandc->props->supports_bam) {
2466
+
nandc->bam_txn = qcom_alloc_bam_transaction(nandc);
1476
2467
if (!nandc->bam_txn) {
1477
2468
dev_err(nandc->dev,
1478
2469
"failed to allocate bam transaction\n");
···
1494
2485
host->cw_size = host->cw_data + ecc->bytes;
1495
2486
bad_block_byte = mtd->writesize - host->cw_size * (cwperpage - 1) + 1;
1496
2487
1497
-
host->cfg0 = (cwperpage - 1) << CW_PER_PAGE
1498
-
| host->cw_data << UD_SIZE_BYTES
1499
-
| 0 << DISABLE_STATUS_AFTER_WRITE
1500
-
| 5 << NUM_ADDR_CYCLES
1501
-
| host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_RS
1502
-
| 0 << STATUS_BFR_READ
1503
-
| 1 << SET_RD_MODE_AFTER_STATUS
1504
-
| host->spare_bytes << SPARE_SIZE_BYTES;
2488
+
host->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
2489
+
FIELD_PREP(UD_SIZE_BYTES_MASK, host->cw_data) |
2490
+
FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 0) |
2491
+
FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) |
2492
+
FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, host->ecc_bytes_hw) |
2493
+
FIELD_PREP(STATUS_BFR_READ, 0) |
2494
+
FIELD_PREP(SET_RD_MODE_AFTER_STATUS, 1) |
2495
+
FIELD_PREP(SPARE_SIZE_BYTES_MASK, host->spare_bytes);
1505
2496
1506
-
host->cfg1 = 7 << NAND_RECOVERY_CYCLES
1507
-
| 0 << CS_ACTIVE_BSY
1508
-
| bad_block_byte << BAD_BLOCK_BYTE_NUM
1509
-
| 0 << BAD_BLOCK_IN_SPARE_AREA
1510
-
| 2 << WR_RD_BSY_GAP
1511
-
| wide_bus << WIDE_FLASH
1512
-
| host->bch_enabled << ENABLE_BCH_ECC;
2497
+
host->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) |
2498
+
FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, bad_block_byte) |
2499
+
FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 0) |
2500
+
FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) |
2501
+
FIELD_PREP(WIDE_FLASH, wide_bus) |
2502
+
FIELD_PREP(ENABLE_BCH_ECC, host->bch_enabled);
1513
2503
1514
-
host->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE
1515
-
| host->cw_size << UD_SIZE_BYTES
1516
-
| 5 << NUM_ADDR_CYCLES
1517
-
| 0 << SPARE_SIZE_BYTES;
2504
+
host->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
2505
+
FIELD_PREP(UD_SIZE_BYTES_MASK, host->cw_size) |
2506
+
FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) |
2507
+
FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
1518
2508
1519
-
host->cfg1_raw = 7 << NAND_RECOVERY_CYCLES
1520
-
| 0 << CS_ACTIVE_BSY
1521
-
| 17 << BAD_BLOCK_BYTE_NUM
1522
-
| 1 << BAD_BLOCK_IN_SPARE_AREA
1523
-
| 2 << WR_RD_BSY_GAP
1524
-
| wide_bus << WIDE_FLASH
1525
-
| 1 << DEV0_CFG1_ECC_DISABLE;
2509
+
host->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) |
2510
+
FIELD_PREP(CS_ACTIVE_BSY, 0) |
2511
+
FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
2512
+
FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
2513
+
FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) |
2514
+
FIELD_PREP(WIDE_FLASH, wide_bus) |
2515
+
FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
1526
2516
1527
-
host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
1528
-
| 0 << ECC_SW_RESET
1529
-
| host->cw_data << ECC_NUM_DATA_BYTES
1530
-
| 1 << ECC_FORCE_CLK_OPEN
1531
-
| ecc_mode << ECC_MODE
1532
-
| host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
2517
+
host->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !host->bch_enabled) |
2518
+
FIELD_PREP(ECC_SW_RESET, 0) |
2519
+
FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, host->cw_data) |
2520
+
FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
2521
+
FIELD_PREP(ECC_MODE_MASK, ecc_mode) |
2522
+
FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, host->ecc_bytes_hw);
1533
2523
1534
-
if (!nandc->props->qpic_v2)
2524
+
if (!nandc->props->qpic_version2)
1535
2525
host->ecc_buf_cfg = 0x203 << NUM_STEPS;
1536
2526
1537
2527
host->clrflashstatus = FS_READY_BSY_N;
···
1564
2556
cmd = OP_FETCH_ID;
1565
2557
break;
1566
2558
case NAND_CMD_PARAM:
1567
-
if (nandc->props->qpic_v2)
2559
+
if (nandc->props->qpic_version2)
1568
2560
cmd = OP_PAGE_READ_ONFI_READ;
1569
2561
else
1570
2562
cmd = OP_PAGE_READ;
···
1617
2609
if (ret < 0)
1618
2610
return ret;
1619
2611
1620
-
q_op->cmd_reg = ret;
2612
+
q_op->cmd_reg = cpu_to_le32(ret);
1621
2613
q_op->rdy_delay_ns = instr->delay_ns;
1622
2614
break;
1623
2615
···
1627
2619
addrs = &instr->ctx.addr.addrs[offset];
1628
2620
1629
2621
for (i = 0; i < min_t(unsigned int, 4, naddrs); i++)
1630
-
q_op->addr1_reg |= addrs[i] << (i * 8);
2622
+
q_op->addr1_reg |= cpu_to_le32(addrs[i] << (i * 8));
1631
2623
1632
2624
if (naddrs > 4)
1633
-
q_op->addr2_reg |= addrs[4];
2625
+
q_op->addr2_reg |= cpu_to_le32(addrs[4]);
1634
2626
1635
2627
q_op->rdy_delay_ns = instr->delay_ns;
1636
2628
break;
···
1671
2663
unsigned long start = jiffies + msecs_to_jiffies(time_ms);
1672
2664
u32 flash;
1673
2665
1674
-
nandc_read_buffer_sync(nandc, true);
2666
+
qcom_nandc_dev_to_mem(nandc, true);
1675
2667
1676
2668
do {
1677
2669
flash = le32_to_cpu(nandc->reg_read_buf[0]);
···
1711
2703
nandc->buf_start = 0;
1712
2704
host->use_ecc = false;
1713
2705
1714
-
clear_read_regs(nandc);
1715
-
clear_bam_transaction(nandc);
2706
+
qcom_clear_read_regs(nandc);
2707
+
qcom_clear_bam_transaction(nandc);
1716
2708
1717
-
nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg);
1718
-
nandc_set_reg(chip, NAND_EXEC_CMD, 1);
2709
+
nandc->regs->cmd = q_op.cmd_reg;
2710
+
nandc->regs->exec = cpu_to_le32(1);
1719
2711
1720
-
write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
1721
-
write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1722
-
read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
2712
+
qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
2713
+
qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
2714
+
qcom_read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1723
2715
1724
-
ret = submit_descs(nandc);
2716
+
ret = qcom_submit_descs(nandc);
1725
2717
if (ret) {
1726
2718
dev_err(nandc->dev, "failure in submitting status descriptor\n");
1727
2719
goto err_out;
1728
2720
}
1729
2721
1730
-
nandc_read_buffer_sync(nandc, true);
2722
+
qcom_nandc_dev_to_mem(nandc, true);
1731
2723
1732
2724
for (i = 0; i < num_cw; i++) {
1733
2725
flash_status = le32_to_cpu(nandc->reg_read_buf[i]);
···
1768
2760
nandc->buf_start = 0;
1769
2761
host->use_ecc = false;
1770
2762
1771
-
clear_read_regs(nandc);
1772
-
clear_bam_transaction(nandc);
2763
+
qcom_clear_read_regs(nandc);
2764
+
qcom_clear_bam_transaction(nandc);
1773
2765
1774
-
nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg);
1775
-
nandc_set_reg(chip, NAND_ADDR0, q_op.addr1_reg);
1776
-
nandc_set_reg(chip, NAND_ADDR1, q_op.addr2_reg);
1777
-
nandc_set_reg(chip, NAND_FLASH_CHIP_SELECT,
1778
-
nandc->props->is_bam ? 0 : DM_EN);
2766
+
nandc->regs->cmd = q_op.cmd_reg;
2767
+
nandc->regs->addr0 = q_op.addr1_reg;
2768
+
nandc->regs->addr1 = q_op.addr2_reg;
2769
+
nandc->regs->chip_sel = cpu_to_le32(nandc->props->supports_bam ? 0 : DM_EN);
2770
+
nandc->regs->exec = cpu_to_le32(1);
1779
2771
1780
-
nandc_set_reg(chip, NAND_EXEC_CMD, 1);
2772
+
qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
2773
+
qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1781
2774
1782
-
write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
1783
-
write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
2775
+
qcom_read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
1784
2776
1785
-
read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
1786
-
1787
-
ret = submit_descs(nandc);
2777
+
ret = qcom_submit_descs(nandc);
1788
2778
if (ret) {
1789
2779
dev_err(nandc->dev, "failure in submitting read id descriptor\n");
1790
2780
goto err_out;
···
1792
2786
op_id = q_op.data_instr_idx;
1793
2787
len = nand_subop_get_data_len(subop, op_id);
1794
2788
1795
-
nandc_read_buffer_sync(nandc, true);
2789
+
qcom_nandc_dev_to_mem(nandc, true);
1796
2790
memcpy(instr->ctx.data.buf.in, nandc->reg_read_buf, len);
1797
2791
1798
2792
err_out:
···
1813
2807
1814
2808
if (q_op.flag == OP_PROGRAM_PAGE) {
1815
2809
goto wait_rdy;
1816
-
} else if (q_op.cmd_reg == OP_BLOCK_ERASE) {
1817
-
q_op.cmd_reg |= PAGE_ACC | LAST_PAGE;
1818
-
nandc_set_reg(chip, NAND_ADDR0, q_op.addr1_reg);
1819
-
nandc_set_reg(chip, NAND_ADDR1, q_op.addr2_reg);
1820
-
nandc_set_reg(chip, NAND_DEV0_CFG0,
1821
-
host->cfg0_raw & ~(7 << CW_PER_PAGE));
1822
-
nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw);
2810
+
} else if (q_op.cmd_reg == cpu_to_le32(OP_BLOCK_ERASE)) {
2811
+
q_op.cmd_reg |= cpu_to_le32(PAGE_ACC | LAST_PAGE);
2812
+
nandc->regs->addr0 = q_op.addr1_reg;
2813
+
nandc->regs->addr1 = q_op.addr2_reg;
2814
+
nandc->regs->cfg0 = cpu_to_le32(host->cfg0_raw & ~(7 << CW_PER_PAGE));
2815
+
nandc->regs->cfg1 = cpu_to_le32(host->cfg1_raw);
1823
2816
instrs = 3;
1824
-
} else if (q_op.cmd_reg != OP_RESET_DEVICE) {
2817
+
} else if (q_op.cmd_reg != cpu_to_le32(OP_RESET_DEVICE)) {
1825
2818
return 0;
1826
2819
}
1827
2820
···
1828
2823
nandc->buf_start = 0;
1829
2824
host->use_ecc = false;
1830
2825
1831
-
clear_read_regs(nandc);
1832
-
clear_bam_transaction(nandc);
2826
+
qcom_clear_read_regs(nandc);
2827
+
qcom_clear_bam_transaction(nandc);
1833
2828
1834
-
nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg);
1835
-
nandc_set_reg(chip, NAND_EXEC_CMD, 1);
2829
+
nandc->regs->cmd = q_op.cmd_reg;
2830
+
nandc->regs->exec = cpu_to_le32(1);
1836
2831
1837
-
write_reg_dma(nandc, NAND_FLASH_CMD, instrs, NAND_BAM_NEXT_SGL);
1838
-
if (q_op.cmd_reg == OP_BLOCK_ERASE)
1839
-
write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
2832
+
qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, instrs, NAND_BAM_NEXT_SGL);
2833
+
if (q_op.cmd_reg == cpu_to_le32(OP_BLOCK_ERASE))
2834
+
qcom_write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
1840
2835
1841
-
write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1842
-
read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
2836
+
qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
2837
+
qcom_read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1843
2838
1844
-
ret = submit_descs(nandc);
2839
+
ret = qcom_submit_descs(nandc);
1845
2840
if (ret) {
1846
2841
dev_err(nandc->dev, "failure in submitting misc descriptor\n");
1847
2842
goto err_out;
···
1869
2864
if (ret)
1870
2865
return ret;
1871
2866
1872
-
q_op.cmd_reg |= PAGE_ACC | LAST_PAGE;
2867
+
q_op.cmd_reg |= cpu_to_le32(PAGE_ACC | LAST_PAGE);
1873
2868
1874
2869
nandc->buf_count = 0;
1875
2870
nandc->buf_start = 0;
1876
2871
host->use_ecc = false;
1877
-
clear_read_regs(nandc);
1878
-
clear_bam_transaction(nandc);
2872
+
qcom_clear_read_regs(nandc);
2873
+
qcom_clear_bam_transaction(nandc);
1879
2874
1880
-
nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg);
2875
+
nandc->regs->cmd = q_op.cmd_reg;
2876
+
nandc->regs->addr0 = 0;
2877
+
nandc->regs->addr1 = 0;
1881
2878
1882
-
nandc_set_reg(chip, NAND_ADDR0, 0);
1883
-
nandc_set_reg(chip, NAND_ADDR1, 0);
1884
-
nandc_set_reg(chip, NAND_DEV0_CFG0, 0 << CW_PER_PAGE
1885
-
| 512 << UD_SIZE_BYTES
1886
-
| 5 << NUM_ADDR_CYCLES
1887
-
| 0 << SPARE_SIZE_BYTES);
1888
-
nandc_set_reg(chip, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES
1889
-
| 0 << CS_ACTIVE_BSY
1890
-
| 17 << BAD_BLOCK_BYTE_NUM
1891
-
| 1 << BAD_BLOCK_IN_SPARE_AREA
1892
-
| 2 << WR_RD_BSY_GAP
1893
-
| 0 << WIDE_FLASH
1894
-
| 1 << DEV0_CFG1_ECC_DISABLE);
1895
-
if (!nandc->props->qpic_v2)
1896
-
nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
2879
+
host->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, 0) |
2880
+
FIELD_PREP(UD_SIZE_BYTES_MASK, 512) |
2881
+
FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) |
2882
+
FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
2883
+
2884
+
host->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) |
2885
+
FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
2886
+
FIELD_PREP(CS_ACTIVE_BSY, 0) |
2887
+
FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
2888
+
FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) |
2889
+
FIELD_PREP(WIDE_FLASH, 0) |
2890
+
FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
2891
+
2892
+
if (!nandc->props->qpic_version2)
2893
+
nandc->regs->ecc_buf_cfg = cpu_to_le32(ECC_CFG_ECC_DISABLE);
1897
2894
1898
2895
/* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
1899
-
if (!nandc->props->qpic_v2) {
1900
-
nandc_set_reg(chip, NAND_DEV_CMD_VLD,
1901
-
(nandc->vld & ~READ_START_VLD));
1902
-
nandc_set_reg(chip, NAND_DEV_CMD1,
1903
-
(nandc->cmd1 & ~(0xFF << READ_ADDR))
1904
-
| NAND_CMD_PARAM << READ_ADDR);
2896
+
if (!nandc->props->qpic_version2) {
2897
+
nandc->regs->vld = cpu_to_le32((nandc->vld & ~READ_START_VLD));
2898
+
nandc->regs->cmd1 = cpu_to_le32((nandc->cmd1 & ~(0xFF << READ_ADDR))
2899
+
| NAND_CMD_PARAM << READ_ADDR);
1905
2900
}
1906
2901
1907
-
nandc_set_reg(chip, NAND_EXEC_CMD, 1);
2902
+
nandc->regs->exec = cpu_to_le32(1);
1908
2903
1909
-
if (!nandc->props->qpic_v2) {
1910
-
nandc_set_reg(chip, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
1911
-
nandc_set_reg(chip, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
2904
+
if (!nandc->props->qpic_version2) {
2905
+
nandc->regs->orig_cmd1 = cpu_to_le32(nandc->cmd1);
2906
+
nandc->regs->orig_vld = cpu_to_le32(nandc->vld);
1912
2907
}
1913
2908
1914
2909
instr = q_op.data_instr;
···
1917
2912
1918
2913
nandc_set_read_loc(chip, 0, 0, 0, len, 1);
1919
2914
1920
-
if (!nandc->props->qpic_v2) {
1921
-
write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
1922
-
write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
2915
+
if (!nandc->props->qpic_version2) {
2916
+
qcom_write_reg_dma(nandc, &nandc->regs->vld, NAND_DEV_CMD_VLD, 1, 0);
2917
+
qcom_write_reg_dma(nandc, &nandc->regs->cmd1, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
1923
2918
}
1924
2919
1925
2920
nandc->buf_count = len;
···
1927
2922
1928
2923
config_nand_single_cw_page_read(chip, false, 0);
1929
2924
1930
-
read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
1931
-
nandc->buf_count, 0);
2925
+
qcom_read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
2926
+
nandc->buf_count, 0);
1932
2927
1933
2928
/* restore CMD1 and VLD regs */
1934
-
if (!nandc->props->qpic_v2) {
1935
-
write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0);
1936
-
write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL);
2929
+
if (!nandc->props->qpic_version2) {
2930
+
qcom_write_reg_dma(nandc, &nandc->regs->orig_cmd1, NAND_DEV_CMD1_RESTORE, 1, 0);
2931
+
qcom_write_reg_dma(nandc, &nandc->regs->orig_vld, NAND_DEV_CMD_VLD_RESTORE, 1,
2932
+
NAND_BAM_NEXT_SGL);
1937
2933
}
1938
2934
1939
-
ret = submit_descs(nandc);
2935
+
ret = qcom_submit_descs(nandc);
1940
2936
if (ret) {
1941
2937
dev_err(nandc->dev, "failure in submitting param page descriptor\n");
1942
2938
goto err_out;
···
2021
3015
.exec_op = qcom_nand_exec_op,
2022
3016
};
2023
3017
2024
-
static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
2025
-
{
2026
-
if (nandc->props->is_bam) {
2027
-
if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma))
2028
-
dma_unmap_single(nandc->dev, nandc->reg_read_dma,
2029
-
MAX_REG_RD *
2030
-
sizeof(*nandc->reg_read_buf),
2031
-
DMA_FROM_DEVICE);
2032
-
2033
-
if (nandc->tx_chan)
2034
-
dma_release_channel(nandc->tx_chan);
2035
-
2036
-
if (nandc->rx_chan)
2037
-
dma_release_channel(nandc->rx_chan);
2038
-
2039
-
if (nandc->cmd_chan)
2040
-
dma_release_channel(nandc->cmd_chan);
2041
-
} else {
2042
-
if (nandc->chan)
2043
-
dma_release_channel(nandc->chan);
2044
-
}
2045
-
}
2046
-
2047
-
static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
2048
-
{
2049
-
int ret;
2050
-
2051
-
ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32));
2052
-
if (ret) {
2053
-
dev_err(nandc->dev, "failed to set DMA mask\n");
2054
-
return ret;
2055
-
}
2056
-
2057
-
/*
2058
-
* we use the internal buffer for reading ONFI params, reading small
2059
-
* data like ID and status, and preforming read-copy-write operations
2060
-
* when writing to a codeword partially. 532 is the maximum possible
2061
-
* size of a codeword for our nand controller
2062
-
*/
2063
-
nandc->buf_size = 532;
2064
-
2065
-
nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size, GFP_KERNEL);
2066
-
if (!nandc->data_buffer)
2067
-
return -ENOMEM;
2068
-
2069
-
nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs), GFP_KERNEL);
2070
-
if (!nandc->regs)
2071
-
return -ENOMEM;
2072
-
2073
-
nandc->reg_read_buf = devm_kcalloc(nandc->dev, MAX_REG_RD,
2074
-
sizeof(*nandc->reg_read_buf),
2075
-
GFP_KERNEL);
2076
-
if (!nandc->reg_read_buf)
2077
-
return -ENOMEM;
2078
-
2079
-
if (nandc->props->is_bam) {
2080
-
nandc->reg_read_dma =
2081
-
dma_map_single(nandc->dev, nandc->reg_read_buf,
2082
-
MAX_REG_RD *
2083
-
sizeof(*nandc->reg_read_buf),
2084
-
DMA_FROM_DEVICE);
2085
-
if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) {
2086
-
dev_err(nandc->dev, "failed to DMA MAP reg buffer\n");
2087
-
return -EIO;
2088
-
}
2089
-
2090
-
nandc->tx_chan = dma_request_chan(nandc->dev, "tx");
2091
-
if (IS_ERR(nandc->tx_chan)) {
2092
-
ret = PTR_ERR(nandc->tx_chan);
2093
-
nandc->tx_chan = NULL;
2094
-
dev_err_probe(nandc->dev, ret,
2095
-
"tx DMA channel request failed\n");
2096
-
goto unalloc;
2097
-
}
2098
-
2099
-
nandc->rx_chan = dma_request_chan(nandc->dev, "rx");
2100
-
if (IS_ERR(nandc->rx_chan)) {
2101
-
ret = PTR_ERR(nandc->rx_chan);
2102
-
nandc->rx_chan = NULL;
2103
-
dev_err_probe(nandc->dev, ret,
2104
-
"rx DMA channel request failed\n");
2105
-
goto unalloc;
2106
-
}
2107
-
2108
-
nandc->cmd_chan = dma_request_chan(nandc->dev, "cmd");
2109
-
if (IS_ERR(nandc->cmd_chan)) {
2110
-
ret = PTR_ERR(nandc->cmd_chan);
2111
-
nandc->cmd_chan = NULL;
2112
-
dev_err_probe(nandc->dev, ret,
2113
-
"cmd DMA channel request failed\n");
2114
-
goto unalloc;
2115
-
}
2116
-
2117
-
/*
2118
-
* Initially allocate BAM transaction to read ONFI param page.
2119
-
* After detecting all the devices, this BAM transaction will
2120
-
* be freed and the next BAM transaction will be allocated with
2121
-
* maximum codeword size
2122
-
*/
2123
-
nandc->max_cwperpage = 1;
2124
-
nandc->bam_txn = alloc_bam_transaction(nandc);
2125
-
if (!nandc->bam_txn) {
2126
-
dev_err(nandc->dev,
2127
-
"failed to allocate bam transaction\n");
2128
-
ret = -ENOMEM;
2129
-
goto unalloc;
2130
-
}
2131
-
} else {
2132
-
nandc->chan = dma_request_chan(nandc->dev, "rxtx");
2133
-
if (IS_ERR(nandc->chan)) {
2134
-
ret = PTR_ERR(nandc->chan);
2135
-
nandc->chan = NULL;
2136
-
dev_err_probe(nandc->dev, ret,
2137
-
"rxtx DMA channel request failed\n");
2138
-
return ret;
2139
-
}
2140
-
}
2141
-
2142
-
INIT_LIST_HEAD(&nandc->desc_list);
2143
-
INIT_LIST_HEAD(&nandc->host_list);
2144
-
2145
-
nand_controller_init(&nandc->controller);
2146
-
nandc->controller.ops = &qcom_nandc_ops;
2147
-
2148
-
return 0;
2149
-
unalloc:
2150
-
qcom_nandc_unalloc(nandc);
2151
-
return ret;
2152
-
}
2153
-
2154
3018
/* one time setup of a few nand controller registers */
2155
3019
static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
2156
3020
{
2157
3021
u32 nand_ctrl;
2158
3022
3023
+
nand_controller_init(nandc->controller);
3024
+
nandc->controller->ops = &qcom_nandc_ops;
3025
+
2159
3026
/* kill onenand */
2160
-
if (!nandc->props->is_qpic)
3027
+
if (!nandc->props->nandc_part_of_qpic)
2161
3028
nandc_write(nandc, SFLASHC_BURST_CFG, 0);
2162
3029
2163
-
if (!nandc->props->qpic_v2)
3030
+
if (!nandc->props->qpic_version2)
2164
3031
nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD),
2165
3032
NAND_DEV_CMD_VLD_VAL);
2166
3033
2167
3034
/* enable ADM or BAM DMA */
2168
-
if (nandc->props->is_bam) {
3035
+
if (nandc->props->supports_bam) {
2169
3036
nand_ctrl = nandc_read(nandc, NAND_CTRL);
2170
3037
2171
3038
/*
···
2055
3176
}
2056
3177
2057
3178
/* save the original values of these registers */
2058
-
if (!nandc->props->qpic_v2) {
3179
+
if (!nandc->props->qpic_version2) {
2059
3180
nandc->cmd1 = nandc_read(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD1));
2060
3181
nandc->vld = NAND_DEV_CMD_VLD_VAL;
2061
3182
}
···
2167
3288
chip->legacy.block_bad = qcom_nandc_block_bad;
2168
3289
chip->legacy.block_markbad = qcom_nandc_block_markbad;
2169
3290
2170
-
chip->controller = &nandc->controller;
3291
+
chip->controller = nandc->controller;
2171
3292
chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA |
2172
3293
NAND_SKIP_BBTSCAN;
2173
3294
···
2228
3349
struct device_node *np = nandc->dev->of_node;
2229
3350
int ret;
2230
3351
2231
-
if (!nandc->props->is_bam) {
3352
+
if (!nandc->props->supports_bam) {
2232
3353
ret = of_property_read_u32(np, "qcom,cmd-crci",
2233
3354
&nandc->cmd_crci);
2234
3355
if (ret) {
···
2250
3371
static int qcom_nandc_probe(struct platform_device *pdev)
2251
3372
{
2252
3373
struct qcom_nand_controller *nandc;
3374
+
struct nand_controller *controller;
2253
3375
const void *dev_data;
2254
3376
struct device *dev = &pdev->dev;
2255
3377
struct resource *res;
2256
3378
int ret;
2257
3379
2258
-
nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
3380
+
nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc) + sizeof(*controller),
3381
+
GFP_KERNEL);
2259
3382
if (!nandc)
2260
3383
return -ENOMEM;
3384
+
controller = (struct nand_controller *)&nandc[1];
2261
3385
2262
3386
platform_set_drvdata(pdev, nandc);
2263
3387
nandc->dev = dev;
3388
+
nandc->controller = controller;
2264
3389
2265
3390
dev_data = of_device_get_match_data(dev);
2266
3391
if (!dev_data) {
···
2357
3474
2358
3475
static const struct qcom_nandc_props ipq806x_nandc_props = {
2359
3476
.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
2360
-
.is_bam = false,
3477
+
.supports_bam = false,
2361
3478
.use_codeword_fixup = true,
2362
3479
.dev_cmd_reg_start = 0x0,
2363
3480
};
2364
3481
2365
3482
static const struct qcom_nandc_props ipq4019_nandc_props = {
2366
3483
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
2367
-
.is_bam = true,
2368
-
.is_qpic = true,
3484
+
.supports_bam = true,
3485
+
.nandc_part_of_qpic = true,
2369
3486
.dev_cmd_reg_start = 0x0,
2370
3487
};
2371
3488
2372
3489
static const struct qcom_nandc_props ipq8074_nandc_props = {
2373
3490
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
2374
-
.is_bam = true,
2375
-
.is_qpic = true,
3491
+
.supports_bam = true,
3492
+
.nandc_part_of_qpic = true,
2376
3493
.dev_cmd_reg_start = 0x7000,
2377
3494
};
2378
3495
2379
3496
static const struct qcom_nandc_props sdx55_nandc_props = {
2380
3497
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
2381
-
.is_bam = true,
2382
-
.is_qpic = true,
2383
-
.qpic_v2 = true,
3498
+
.supports_bam = true,
3499
+
.nandc_part_of_qpic = true,
3500
+
.qpic_version2 = true,
2384
3501
.dev_cmd_reg_start = 0x7000,
2385
3502
};
2386
3503
+1
-1
drivers/mtd/nand/spi/Makefile
+1
-1
drivers/mtd/nand/spi/Makefile
···
1
1
# SPDX-License-Identifier: GPL-2.0
2
2
spinand-objs := core.o alliancememory.o ato.o esmt.o foresee.o gigadevice.o macronix.o
3
-
spinand-objs += micron.o paragon.o toshiba.o winbond.o xtx.o
3
+
spinand-objs += micron.o paragon.o skyhigh.o toshiba.o winbond.o xtx.o
4
4
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
+2
-2
drivers/mtd/nand/spi/alliancememory.c
+2
-2
drivers/mtd/nand/spi/alliancememory.c
···
21
21
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
22
22
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
23
23
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
24
-
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
25
-
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
24
+
SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
25
+
SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0));
26
26
27
27
static SPINAND_OP_VARIANTS(write_cache_variants,
28
28
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+2
-2
drivers/mtd/nand/spi/ato.c
+2
-2
drivers/mtd/nand/spi/ato.c
···
15
15
16
16
static SPINAND_OP_VARIANTS(read_cache_variants,
17
17
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
18
-
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
19
-
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
18
+
SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
19
+
SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0));
20
20
21
21
static SPINAND_OP_VARIANTS(write_cache_variants,
22
22
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+30
-8
drivers/mtd/nand/spi/core.c
+30
-8
drivers/mtd/nand/spi/core.c
···
294
294
struct spinand_device *spinand = nand_to_spinand(nand);
295
295
bool enable = (req->mode != MTD_OPS_RAW);
296
296
297
+
if (!enable && spinand->flags & SPINAND_NO_RAW_ACCESS)
298
+
return -EOPNOTSUPP;
299
+
297
300
memset(spinand->oobbuf, 0xff, nanddev_per_page_oobsize(nand));
298
301
299
302
/* Only enable or disable the engine */
···
904
901
.oobbuf.in = marker,
905
902
.mode = MTD_OPS_RAW,
906
903
};
904
+
int ret;
907
905
908
906
spinand_select_target(spinand, pos->target);
909
-
spinand_read_page(spinand, &req);
907
+
908
+
ret = spinand_read_page(spinand, &req);
909
+
if (ret == -EOPNOTSUPP) {
910
+
/* Retry with ECC in case raw access is not supported */
911
+
req.mode = MTD_OPS_PLACE_OOB;
912
+
spinand_read_page(spinand, &req);
913
+
}
914
+
910
915
if (marker[0] != 0xff || marker[1] != 0xff)
911
916
return true;
912
917
···
953
942
if (ret)
954
943
return ret;
955
944
956
-
ret = spinand_write_enable_op(spinand);
957
-
if (ret)
958
-
return ret;
945
+
ret = spinand_write_page(spinand, &req);
946
+
if (ret == -EOPNOTSUPP) {
947
+
/* Retry with ECC in case raw access is not supported */
948
+
req.mode = MTD_OPS_PLACE_OOB;
949
+
ret = spinand_write_page(spinand, &req);
950
+
}
959
951
960
-
return spinand_write_page(spinand, &req);
952
+
return ret;
961
953
}
962
954
963
955
static int spinand_mtd_block_markbad(struct mtd_info *mtd, loff_t offs)
···
1131
1117
¯onix_spinand_manufacturer,
1132
1118
µn_spinand_manufacturer,
1133
1119
¶gon_spinand_manufacturer,
1120
+
&skyhigh_spinand_manufacturer,
1134
1121
&toshiba_spinand_manufacturer,
1135
1122
&winbond_spinand_manufacturer,
1136
1123
&xtx_spinand_manufacturer,
···
1213
1198
const struct spinand_op_variants *variants)
1214
1199
{
1215
1200
struct nand_device *nand = spinand_to_nand(spinand);
1201
+
const struct spi_mem_op *best_variant = NULL;
1202
+
u64 best_op_duration_ns = ULLONG_MAX;
1216
1203
unsigned int i;
1217
1204
1218
1205
for (i = 0; i < variants->nops; i++) {
1219
1206
struct spi_mem_op op = variants->ops[i];
1207
+
u64 op_duration_ns = 0;
1220
1208
unsigned int nbytes;
1221
1209
int ret;
1222
1210
···
1238
1220
break;
1239
1221
1240
1222
nbytes -= op.data.nbytes;
1223
+
1224
+
op_duration_ns += spi_mem_calc_op_duration(&op);
1241
1225
}
1242
1226
1243
-
if (!nbytes)
1244
-
return &variants->ops[i];
1227
+
if (!nbytes && op_duration_ns < best_op_duration_ns) {
1228
+
best_op_duration_ns = op_duration_ns;
1229
+
best_variant = &variants->ops[i];
1230
+
}
1245
1231
}
1246
1232
1247
-
return NULL;
1233
+
return best_variant;
1248
1234
}
1249
1235
1250
1236
/**
+2
-2
drivers/mtd/nand/spi/esmt.c
+2
-2
drivers/mtd/nand/spi/esmt.c
···
15
15
static SPINAND_OP_VARIANTS(read_cache_variants,
16
16
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
17
17
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
18
-
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
19
-
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
18
+
SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
19
+
SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0));
20
20
21
21
static SPINAND_OP_VARIANTS(write_cache_variants,
22
22
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+12
-2
drivers/mtd/nand/spi/foresee.c
+12
-2
drivers/mtd/nand/spi/foresee.c
···
14
14
static SPINAND_OP_VARIANTS(read_cache_variants,
15
15
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
16
16
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
17
-
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
18
-
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
17
+
SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
18
+
SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0));
19
19
20
20
static SPINAND_OP_VARIANTS(write_cache_variants,
21
21
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
···
74
74
SPINAND_INFO("F35SQA002G",
75
75
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x72, 0x72),
76
76
NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
77
+
NAND_ECCREQ(1, 512),
78
+
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
79
+
&write_cache_variants,
80
+
&update_cache_variants),
81
+
SPINAND_HAS_QE_BIT,
82
+
SPINAND_ECCINFO(&f35sqa002g_ooblayout,
83
+
f35sqa002g_ecc_get_status)),
84
+
SPINAND_INFO("F35SQA001G",
85
+
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71, 0x71),
86
+
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
77
87
NAND_ECCREQ(1, 512),
78
88
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
79
89
&write_cache_variants,
+8
-8
drivers/mtd/nand/spi/gigadevice.c
+8
-8
drivers/mtd/nand/spi/gigadevice.c
···
28
28
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
29
29
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
30
30
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
31
-
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
32
-
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
31
+
SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
32
+
SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0));
33
33
34
34
static SPINAND_OP_VARIANTS(read_cache_variants_f,
35
35
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
36
36
SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(0, 1, NULL, 0),
37
37
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
38
38
SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(0, 1, NULL, 0),
39
-
SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
40
-
SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
39
+
SPINAND_PAGE_READ_FROM_CACHE_FAST_OP_3A(0, 1, NULL, 0),
40
+
SPINAND_PAGE_READ_FROM_CACHE_OP_3A(0, 0, NULL, 0));
41
41
42
42
static SPINAND_OP_VARIANTS(read_cache_variants_1gq5,
43
43
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
44
44
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
45
45
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
46
46
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
47
-
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
48
-
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
47
+
SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
48
+
SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0));
49
49
50
50
static SPINAND_OP_VARIANTS(read_cache_variants_2gq5,
51
51
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
52
52
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
53
53
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
54
54
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
55
-
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
56
-
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
55
+
SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
56
+
SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0));
57
57
58
58
static SPINAND_OP_VARIANTS(write_cache_variants,
59
59
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+2
-2
drivers/mtd/nand/spi/macronix.c
+2
-2
drivers/mtd/nand/spi/macronix.c
···
28
28
static SPINAND_OP_VARIANTS(read_cache_variants,
29
29
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
30
30
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
31
-
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
32
-
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
31
+
SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
32
+
SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0));
33
33
34
34
static SPINAND_OP_VARIANTS(write_cache_variants,
35
35
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+4
-4
drivers/mtd/nand/spi/micron.c
+4
-4
drivers/mtd/nand/spi/micron.c
···
33
33
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
34
34
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
35
35
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
36
-
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
37
-
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
36
+
SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
37
+
SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0));
38
38
39
39
static SPINAND_OP_VARIANTS(x4_write_cache_variants,
40
40
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
···
48
48
static SPINAND_OP_VARIANTS(x4_read_cache_variants,
49
49
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
50
50
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
51
-
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
52
-
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
51
+
SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
52
+
SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0));
53
53
54
54
static SPINAND_OP_VARIANTS(x1_write_cache_variants,
55
55
SPINAND_PROG_LOAD(true, 0, NULL, 0));
+2
-2
drivers/mtd/nand/spi/paragon.c
+2
-2
drivers/mtd/nand/spi/paragon.c
···
26
26
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
27
27
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
28
28
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
29
-
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
30
-
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
29
+
SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
30
+
SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0));
31
31
32
32
static SPINAND_OP_VARIANTS(write_cache_variants,
33
33
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+147
drivers/mtd/nand/spi/skyhigh.c
+147
drivers/mtd/nand/spi/skyhigh.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2024 SkyHigh Memory Limited
4
+
*
5
+
* Author: Takahiro Kuwano <takahiro.kuwano@infineon.com>
6
+
* Co-Author: KR Kim <kr.kim@skyhighmemory.com>
7
+
*/
8
+
9
+
#include <linux/device.h>
10
+
#include <linux/kernel.h>
11
+
#include <linux/mtd/spinand.h>
12
+
13
+
#define SPINAND_MFR_SKYHIGH 0x01
14
+
#define SKYHIGH_STATUS_ECC_1TO2_BITFLIPS (1 << 4)
15
+
#define SKYHIGH_STATUS_ECC_3TO6_BITFLIPS (2 << 4)
16
+
#define SKYHIGH_STATUS_ECC_UNCOR_ERROR (3 << 4)
17
+
#define SKYHIGH_CONFIG_PROTECT_EN BIT(1)
18
+
19
+
static SPINAND_OP_VARIANTS(read_cache_variants,
20
+
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
21
+
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
22
+
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
23
+
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
24
+
SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
25
+
SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0));
26
+
27
+
static SPINAND_OP_VARIANTS(write_cache_variants,
28
+
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
29
+
SPINAND_PROG_LOAD(true, 0, NULL, 0));
30
+
31
+
static SPINAND_OP_VARIANTS(update_cache_variants,
32
+
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
33
+
SPINAND_PROG_LOAD(false, 0, NULL, 0));
34
+
35
+
static int skyhigh_spinand_ooblayout_ecc(struct mtd_info *mtd, int section,
36
+
struct mtd_oob_region *region)
37
+
{
38
+
/* ECC bytes are stored in hidden area. */
39
+
return -ERANGE;
40
+
}
41
+
42
+
static int skyhigh_spinand_ooblayout_free(struct mtd_info *mtd, int section,
43
+
struct mtd_oob_region *region)
44
+
{
45
+
if (section)
46
+
return -ERANGE;
47
+
48
+
/* ECC bytes are stored in hidden area. Reserve 2 bytes for the BBM. */
49
+
region->offset = 2;
50
+
region->length = mtd->oobsize - 2;
51
+
52
+
return 0;
53
+
}
54
+
55
+
static const struct mtd_ooblayout_ops skyhigh_spinand_ooblayout = {
56
+
.ecc = skyhigh_spinand_ooblayout_ecc,
57
+
.free = skyhigh_spinand_ooblayout_free,
58
+
};
59
+
60
+
static int skyhigh_spinand_ecc_get_status(struct spinand_device *spinand,
61
+
u8 status)
62
+
{
63
+
switch (status & STATUS_ECC_MASK) {
64
+
case STATUS_ECC_NO_BITFLIPS:
65
+
return 0;
66
+
67
+
case SKYHIGH_STATUS_ECC_UNCOR_ERROR:
68
+
return -EBADMSG;
69
+
70
+
case SKYHIGH_STATUS_ECC_1TO2_BITFLIPS:
71
+
return 2;
72
+
73
+
case SKYHIGH_STATUS_ECC_3TO6_BITFLIPS:
74
+
return 6;
75
+
76
+
default:
77
+
break;
78
+
}
79
+
80
+
return -EINVAL;
81
+
}
82
+
83
+
static const struct spinand_info skyhigh_spinand_table[] = {
84
+
SPINAND_INFO("S35ML01G301",
85
+
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
86
+
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
87
+
NAND_ECCREQ(6, 32),
88
+
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
89
+
&write_cache_variants,
90
+
&update_cache_variants),
91
+
SPINAND_NO_RAW_ACCESS,
92
+
SPINAND_ECCINFO(&skyhigh_spinand_ooblayout,
93
+
skyhigh_spinand_ecc_get_status)),
94
+
SPINAND_INFO("S35ML01G300",
95
+
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
96
+
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
97
+
NAND_ECCREQ(6, 32),
98
+
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
99
+
&write_cache_variants,
100
+
&update_cache_variants),
101
+
SPINAND_NO_RAW_ACCESS,
102
+
SPINAND_ECCINFO(&skyhigh_spinand_ooblayout,
103
+
skyhigh_spinand_ecc_get_status)),
104
+
SPINAND_INFO("S35ML02G300",
105
+
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
106
+
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
107
+
NAND_ECCREQ(6, 32),
108
+
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
109
+
&write_cache_variants,
110
+
&update_cache_variants),
111
+
SPINAND_NO_RAW_ACCESS,
112
+
SPINAND_ECCINFO(&skyhigh_spinand_ooblayout,
113
+
skyhigh_spinand_ecc_get_status)),
114
+
SPINAND_INFO("S35ML04G300",
115
+
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
116
+
NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 2, 1, 1),
117
+
NAND_ECCREQ(6, 32),
118
+
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
119
+
&write_cache_variants,
120
+
&update_cache_variants),
121
+
SPINAND_NO_RAW_ACCESS,
122
+
SPINAND_ECCINFO(&skyhigh_spinand_ooblayout,
123
+
skyhigh_spinand_ecc_get_status)),
124
+
};
125
+
126
+
static int skyhigh_spinand_init(struct spinand_device *spinand)
127
+
{
128
+
/*
129
+
* Config_Protect_En (bit 1 in Block Lock register) must be set to 1
130
+
* before writing other bits. Do it here before core unlocks all blocks
131
+
* by writing block protection bits.
132
+
*/
133
+
return spinand_write_reg_op(spinand, REG_BLOCK_LOCK,
134
+
SKYHIGH_CONFIG_PROTECT_EN);
135
+
}
136
+
137
+
static const struct spinand_manufacturer_ops skyhigh_spinand_manuf_ops = {
138
+
.init = skyhigh_spinand_init,
139
+
};
140
+
141
+
const struct spinand_manufacturer skyhigh_spinand_manufacturer = {
142
+
.id = SPINAND_MFR_SKYHIGH,
143
+
.name = "SkyHigh",
144
+
.chips = skyhigh_spinand_table,
145
+
.nchips = ARRAY_SIZE(skyhigh_spinand_table),
146
+
.ops = &skyhigh_spinand_manuf_ops,
147
+
};
+2
-2
drivers/mtd/nand/spi/toshiba.c
+2
-2
drivers/mtd/nand/spi/toshiba.c
···
17
17
static SPINAND_OP_VARIANTS(read_cache_variants,
18
18
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
19
19
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
20
-
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
21
-
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
20
+
SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
21
+
SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0));
22
22
23
23
static SPINAND_OP_VARIANTS(write_cache_x4_variants,
24
24
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+23
-4
drivers/mtd/nand/spi/winbond.c
+23
-4
drivers/mtd/nand/spi/winbond.c
···
10
10
#include <linux/device.h>
11
11
#include <linux/kernel.h>
12
12
#include <linux/mtd/spinand.h>
13
+
#include <linux/units.h>
13
14
14
15
#define SPINAND_MFR_WINBOND 0xEF
15
16
···
18
17
19
18
#define W25N04KV_STATUS_ECC_5_8_BITFLIPS (3 << 4)
20
19
20
+
/*
21
+
* "X2" in the core is equivalent to "dual output" in the datasheets,
22
+
* "X4" in the core is equivalent to "quad output" in the datasheets.
23
+
*/
24
+
25
+
static SPINAND_OP_VARIANTS(read_cache_dtr_variants,
26
+
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_DTR_OP(0, 8, NULL, 0, 80 * HZ_PER_MHZ),
27
+
SPINAND_PAGE_READ_FROM_CACHE_X4_DTR_OP(0, 2, NULL, 0, 80 * HZ_PER_MHZ),
28
+
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
29
+
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
30
+
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_DTR_OP(0, 4, NULL, 0, 80 * HZ_PER_MHZ),
31
+
SPINAND_PAGE_READ_FROM_CACHE_X2_DTR_OP(0, 2, NULL, 0, 80 * HZ_PER_MHZ),
32
+
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
33
+
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
34
+
SPINAND_PAGE_READ_FROM_CACHE_DTR_OP(0, 2, NULL, 0, 80 * HZ_PER_MHZ),
35
+
SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
36
+
SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0, 54 * HZ_PER_MHZ));
37
+
21
38
static SPINAND_OP_VARIANTS(read_cache_variants,
22
39
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
23
40
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
24
41
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
25
42
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
26
-
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
27
-
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
43
+
SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
44
+
SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0));
28
45
29
46
static SPINAND_OP_VARIANTS(write_cache_variants,
30
47
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
···
213
194
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbc, 0x21),
214
195
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
215
196
NAND_ECCREQ(1, 512),
216
-
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
197
+
SPINAND_INFO_OP_VARIANTS(&read_cache_dtr_variants,
217
198
&write_cache_variants,
218
199
&update_cache_variants),
219
200
0,
···
242
223
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbf, 0x22),
243
224
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 2, 1),
244
225
NAND_ECCREQ(1, 512),
245
-
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
226
+
SPINAND_INFO_OP_VARIANTS(&read_cache_dtr_variants,
246
227
&write_cache_variants,
247
228
&update_cache_variants),
248
229
0,
+2
-2
drivers/mtd/nand/spi/xtx.c
+2
-2
drivers/mtd/nand/spi/xtx.c
···
27
27
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
28
28
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
29
29
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
30
-
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
31
-
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
30
+
SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
31
+
SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0));
32
32
33
33
static SPINAND_OP_VARIANTS(write_cache_variants,
34
34
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+4
drivers/mtd/spi-nor/atmel.c
+4
drivers/mtd/spi-nor/atmel.c
+12
-7
drivers/mtd/spi-nor/core.c
+12
-7
drivers/mtd/spi-nor/core.c
···
17
17
#include <linux/mtd/spi-nor.h>
18
18
#include <linux/mutex.h>
19
19
#include <linux/of_platform.h>
20
+
#include <linux/regulator/consumer.h>
20
21
#include <linux/sched/task_stack.h>
21
22
#include <linux/sizes.h>
22
23
#include <linux/slab.h>
···
3577
3576
static int spi_nor_probe(struct spi_mem *spimem)
3578
3577
{
3579
3578
struct spi_device *spi = spimem->spi;
3580
-
struct flash_platform_data *data = dev_get_platdata(&spi->dev);
3579
+
struct device *dev = &spi->dev;
3580
+
struct flash_platform_data *data = dev_get_platdata(dev);
3581
3581
struct spi_nor *nor;
3582
3582
/*
3583
3583
* Enable all caps by default. The core will mask them after
···
3588
3586
char *flash_name;
3589
3587
int ret;
3590
3588
3591
-
nor = devm_kzalloc(&spi->dev, sizeof(*nor), GFP_KERNEL);
3589
+
ret = devm_regulator_get_enable(dev, "vcc");
3590
+
if (ret)
3591
+
return ret;
3592
+
3593
+
nor = devm_kzalloc(dev, sizeof(*nor), GFP_KERNEL);
3592
3594
if (!nor)
3593
3595
return -ENOMEM;
3594
3596
3595
3597
nor->spimem = spimem;
3596
-
nor->dev = &spi->dev;
3597
-
spi_nor_set_flash_node(nor, spi->dev.of_node);
3598
+
nor->dev = dev;
3599
+
spi_nor_set_flash_node(nor, dev->of_node);
3598
3600
3599
3601
spi_mem_set_drvdata(spimem, nor);
3600
3602
···
3634
3628
*/
3635
3629
if (nor->params->page_size > PAGE_SIZE) {
3636
3630
nor->bouncebuf_size = nor->params->page_size;
3637
-
devm_kfree(nor->dev, nor->bouncebuf);
3638
-
nor->bouncebuf = devm_kmalloc(nor->dev,
3639
-
nor->bouncebuf_size,
3631
+
devm_kfree(dev, nor->bouncebuf);
3632
+
nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size,
3640
3633
GFP_KERNEL);
3641
3634
if (!nor->bouncebuf)
3642
3635
return -ENOMEM;
+5
-1
drivers/mtd/spi-nor/core.h
+5
-1
drivers/mtd/spi-nor/core.h
···
448
448
* @id: pointer to struct spi_nor_id or NULL, which means "no ID" (mostly
449
449
* older chips).
450
450
* @name: (obsolete) the name of the flash. Do not set it for new additions.
451
-
* @size: the size of the flash in bytes.
451
+
* @size: the size of the flash in bytes. The flash size is one
452
+
* property parsed by the SFDP. We use it as an indicator
453
+
* whether we need SFDP parsing for a particular flash.
454
+
* I.e. non-legacy flash entries in flash_info will have
455
+
* a size of zero iff SFDP should be used.
452
456
* @sector_size: (optional) the size listed here is what works with
453
457
* SPINOR_OP_SE, which isn't necessarily called a "sector" by
454
458
* the vendor. Defaults to 64k.
+2
-7
drivers/mtd/spi-nor/macronix.c
+2
-7
drivers/mtd/spi-nor/macronix.c
···
143
143
.size = SZ_16M,
144
144
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
145
145
}, {
146
-
.id = SNOR_ID(0xc2, 0x25, 0x39),
147
-
.name = "mx25u25635f",
148
-
.size = SZ_32M,
149
-
.no_sfdp_flags = SECT_4K,
150
-
.fixup_flags = SPI_NOR_4B_OPCODES,
151
-
}, {
152
146
.id = SNOR_ID(0xc2, 0x25, 0x3a),
153
147
.name = "mx25u51245g",
154
148
.size = SZ_64M,
···
224
230
return ret;
225
231
226
232
/* Read flash ID to make sure the switch was successful. */
227
-
ret = spi_nor_read_id(nor, 4, 4, buf, SNOR_PROTO_8_8_8_DTR);
233
+
ret = spi_nor_read_id(nor, nor->addr_nbytes, 4, buf,
234
+
SNOR_PROTO_8_8_8_DTR);
228
235
if (ret) {
229
236
dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret);
230
237
return ret;
+10
drivers/mtd/spi-nor/spansion.c
+10
drivers/mtd/spi-nor/spansion.c
···
958
958
.mfr_flags = USE_CLPEF,
959
959
.fixups = &s25hx_t_fixups
960
960
}, {
961
+
/* S28HL256T */
962
+
.id = SNOR_ID(0x34, 0x5a, 0x19),
963
+
.mfr_flags = USE_CLPEF,
964
+
.fixups = &s28hx_t_fixups,
965
+
}, {
961
966
.id = SNOR_ID(0x34, 0x5a, 0x1a),
962
967
.name = "s28hl512t",
963
968
.mfr_flags = USE_CLPEF,
···
970
965
}, {
971
966
.id = SNOR_ID(0x34, 0x5a, 0x1b),
972
967
.name = "s28hl01gt",
968
+
.mfr_flags = USE_CLPEF,
969
+
.fixups = &s28hx_t_fixups,
970
+
}, {
971
+
/* S28HL02GT */
972
+
.id = SNOR_ID(0x34, 0x5a, 0x1c),
973
973
.mfr_flags = USE_CLPEF,
974
974
.fixups = &s28hx_t_fixups,
975
975
}, {
+4
-4
drivers/mtd/spi-nor/sysfs.c
+4
-4
drivers/mtd/spi-nor/sysfs.c
···
50
50
};
51
51
52
52
static ssize_t sfdp_read(struct file *filp, struct kobject *kobj,
53
-
struct bin_attribute *bin_attr, char *buf,
53
+
const struct bin_attribute *bin_attr, char *buf,
54
54
loff_t off, size_t count)
55
55
{
56
56
struct spi_device *spi = to_spi_device(kobj_to_dev(kobj));
···
62
62
return memory_read_from_buffer(buf, count, &off, nor->sfdp->dwords,
63
63
sfdp_size);
64
64
}
65
-
static BIN_ATTR_RO(sfdp, 0);
65
+
static const BIN_ATTR_RO(sfdp, 0);
66
66
67
-
static struct bin_attribute *spi_nor_sysfs_bin_entries[] = {
67
+
static const struct bin_attribute *const spi_nor_sysfs_bin_entries[] = {
68
68
&bin_attr_sfdp,
69
69
NULL
70
70
};
···
104
104
.is_visible = spi_nor_sysfs_is_visible,
105
105
.is_bin_visible = spi_nor_sysfs_is_bin_visible,
106
106
.attrs = spi_nor_sysfs_entries,
107
-
.bin_attrs = spi_nor_sysfs_bin_entries,
107
+
.bin_attrs_new = spi_nor_sysfs_bin_entries,
108
108
};
109
109
110
110
const struct attribute_group *spi_nor_sysfs_groups[] = {
+478
include/linux/mtd/nand-qpic-common.h
+478
include/linux/mtd/nand-qpic-common.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* QCOM QPIC common APIs header file
4
+
*
5
+
* Copyright (c) 2023 Qualcomm Inc.
6
+
* Authors: Md sadre Alam <quic_mdalam@quicinc.com>
7
+
*
8
+
*/
9
+
#ifndef __MTD_NAND_QPIC_COMMON_H__
10
+
#define __MTD_NAND_QPIC_COMMON_H__
11
+
12
+
/* NANDc reg offsets */
13
+
#define NAND_FLASH_CMD 0x00
14
+
#define NAND_ADDR0 0x04
15
+
#define NAND_ADDR1 0x08
16
+
#define NAND_FLASH_CHIP_SELECT 0x0c
17
+
#define NAND_EXEC_CMD 0x10
18
+
#define NAND_FLASH_STATUS 0x14
19
+
#define NAND_BUFFER_STATUS 0x18
20
+
#define NAND_DEV0_CFG0 0x20
21
+
#define NAND_DEV0_CFG1 0x24
22
+
#define NAND_DEV0_ECC_CFG 0x28
23
+
#define NAND_AUTO_STATUS_EN 0x2c
24
+
#define NAND_DEV1_CFG0 0x30
25
+
#define NAND_DEV1_CFG1 0x34
26
+
#define NAND_READ_ID 0x40
27
+
#define NAND_READ_STATUS 0x44
28
+
#define NAND_DEV_CMD0 0xa0
29
+
#define NAND_DEV_CMD1 0xa4
30
+
#define NAND_DEV_CMD2 0xa8
31
+
#define NAND_DEV_CMD_VLD 0xac
32
+
#define SFLASHC_BURST_CFG 0xe0
33
+
#define NAND_ERASED_CW_DETECT_CFG 0xe8
34
+
#define NAND_ERASED_CW_DETECT_STATUS 0xec
35
+
#define NAND_EBI2_ECC_BUF_CFG 0xf0
36
+
#define FLASH_BUF_ACC 0x100
37
+
38
+
#define NAND_CTRL 0xf00
39
+
#define NAND_VERSION 0xf08
40
+
#define NAND_READ_LOCATION_0 0xf20
41
+
#define NAND_READ_LOCATION_1 0xf24
42
+
#define NAND_READ_LOCATION_2 0xf28
43
+
#define NAND_READ_LOCATION_3 0xf2c
44
+
#define NAND_READ_LOCATION_LAST_CW_0 0xf40
45
+
#define NAND_READ_LOCATION_LAST_CW_1 0xf44
46
+
#define NAND_READ_LOCATION_LAST_CW_2 0xf48
47
+
#define NAND_READ_LOCATION_LAST_CW_3 0xf4c
48
+
49
+
/* dummy register offsets, used by qcom_write_reg_dma */
50
+
#define NAND_DEV_CMD1_RESTORE 0xdead
51
+
#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
52
+
53
+
/* NAND_FLASH_CMD bits */
54
+
#define PAGE_ACC BIT(4)
55
+
#define LAST_PAGE BIT(5)
56
+
57
+
/* NAND_FLASH_CHIP_SELECT bits */
58
+
#define NAND_DEV_SEL 0
59
+
#define DM_EN BIT(2)
60
+
61
+
/* NAND_FLASH_STATUS bits */
62
+
#define FS_OP_ERR BIT(4)
63
+
#define FS_READY_BSY_N BIT(5)
64
+
#define FS_MPU_ERR BIT(8)
65
+
#define FS_DEVICE_STS_ERR BIT(16)
66
+
#define FS_DEVICE_WP BIT(23)
67
+
68
+
/* NAND_BUFFER_STATUS bits */
69
+
#define BS_UNCORRECTABLE_BIT BIT(8)
70
+
#define BS_CORRECTABLE_ERR_MSK 0x1f
71
+
72
+
/* NAND_DEVn_CFG0 bits */
73
+
#define DISABLE_STATUS_AFTER_WRITE BIT(4)
74
+
#define CW_PER_PAGE 6
75
+
#define CW_PER_PAGE_MASK GENMASK(8, 6)
76
+
#define UD_SIZE_BYTES 9
77
+
#define UD_SIZE_BYTES_MASK GENMASK(18, 9)
78
+
#define ECC_PARITY_SIZE_BYTES_RS GENMASK(22, 19)
79
+
#define SPARE_SIZE_BYTES 23
80
+
#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23)
81
+
#define NUM_ADDR_CYCLES 27
82
+
#define NUM_ADDR_CYCLES_MASK GENMASK(29, 27)
83
+
#define STATUS_BFR_READ BIT(30)
84
+
#define SET_RD_MODE_AFTER_STATUS BIT(31)
85
+
86
+
/* NAND_DEVn_CFG0 bits */
87
+
#define DEV0_CFG1_ECC_DISABLE BIT(0)
88
+
#define WIDE_FLASH BIT(1)
89
+
#define NAND_RECOVERY_CYCLES 2
90
+
#define NAND_RECOVERY_CYCLES_MASK GENMASK(4, 2)
91
+
#define CS_ACTIVE_BSY BIT(5)
92
+
#define BAD_BLOCK_BYTE_NUM 6
93
+
#define BAD_BLOCK_BYTE_NUM_MASK GENMASK(15, 6)
94
+
#define BAD_BLOCK_IN_SPARE_AREA BIT(16)
95
+
#define WR_RD_BSY_GAP 17
96
+
#define WR_RD_BSY_GAP_MASK GENMASK(22, 17)
97
+
#define ENABLE_BCH_ECC BIT(27)
98
+
99
+
/* NAND_DEV0_ECC_CFG bits */
100
+
#define ECC_CFG_ECC_DISABLE BIT(0)
101
+
#define ECC_SW_RESET BIT(1)
102
+
#define ECC_MODE 4
103
+
#define ECC_MODE_MASK GENMASK(5, 4)
104
+
#define ECC_PARITY_SIZE_BYTES_BCH 8
105
+
#define ECC_PARITY_SIZE_BYTES_BCH_MASK GENMASK(12, 8)
106
+
#define ECC_NUM_DATA_BYTES 16
107
+
#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16)
108
+
#define ECC_FORCE_CLK_OPEN BIT(30)
109
+
110
+
/* NAND_DEV_CMD1 bits */
111
+
#define READ_ADDR 0
112
+
113
+
/* NAND_DEV_CMD_VLD bits */
114
+
#define READ_START_VLD BIT(0)
115
+
#define READ_STOP_VLD BIT(1)
116
+
#define WRITE_START_VLD BIT(2)
117
+
#define ERASE_START_VLD BIT(3)
118
+
#define SEQ_READ_START_VLD BIT(4)
119
+
120
+
/* NAND_EBI2_ECC_BUF_CFG bits */
121
+
#define NUM_STEPS 0
122
+
123
+
/* NAND_ERASED_CW_DETECT_CFG bits */
124
+
#define ERASED_CW_ECC_MASK 1
125
+
#define AUTO_DETECT_RES 0
126
+
#define MASK_ECC BIT(ERASED_CW_ECC_MASK)
127
+
#define RESET_ERASED_DET BIT(AUTO_DETECT_RES)
128
+
#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
129
+
#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
130
+
#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
131
+
132
+
/* NAND_ERASED_CW_DETECT_STATUS bits */
133
+
#define PAGE_ALL_ERASED BIT(7)
134
+
#define CODEWORD_ALL_ERASED BIT(6)
135
+
#define PAGE_ERASED BIT(5)
136
+
#define CODEWORD_ERASED BIT(4)
137
+
#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
138
+
#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
139
+
140
+
/* NAND_READ_LOCATION_n bits */
141
+
#define READ_LOCATION_OFFSET 0
142
+
#define READ_LOCATION_SIZE 16
143
+
#define READ_LOCATION_LAST 31
144
+
145
+
/* Version Mask */
146
+
#define NAND_VERSION_MAJOR_MASK 0xf0000000
147
+
#define NAND_VERSION_MAJOR_SHIFT 28
148
+
#define NAND_VERSION_MINOR_MASK 0x0fff0000
149
+
#define NAND_VERSION_MINOR_SHIFT 16
150
+
151
+
/* NAND OP_CMDs */
152
+
#define OP_PAGE_READ 0x2
153
+
#define OP_PAGE_READ_WITH_ECC 0x3
154
+
#define OP_PAGE_READ_WITH_ECC_SPARE 0x4
155
+
#define OP_PAGE_READ_ONFI_READ 0x5
156
+
#define OP_PROGRAM_PAGE 0x6
157
+
#define OP_PAGE_PROGRAM_WITH_ECC 0x7
158
+
#define OP_PROGRAM_PAGE_SPARE 0x9
159
+
#define OP_BLOCK_ERASE 0xa
160
+
#define OP_CHECK_STATUS 0xc
161
+
#define OP_FETCH_ID 0xb
162
+
#define OP_RESET_DEVICE 0xd
163
+
164
+
/* Default Value for NAND_DEV_CMD_VLD */
165
+
#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \
166
+
ERASE_START_VLD | SEQ_READ_START_VLD)
167
+
168
+
/* NAND_CTRL bits */
169
+
#define BAM_MODE_EN BIT(0)
170
+
171
+
/*
172
+
* the NAND controller performs reads/writes with ECC in 516 byte chunks.
173
+
* the driver calls the chunks 'step' or 'codeword' interchangeably
174
+
*/
175
+
#define NANDC_STEP_SIZE 512
176
+
177
+
/*
178
+
* the largest page size we support is 8K, this will have 16 steps/codewords
179
+
* of 512 bytes each
180
+
*/
181
+
#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
182
+
183
+
/* we read at most 3 registers per codeword scan */
184
+
#define MAX_REG_RD (3 * MAX_NUM_STEPS)
185
+
186
+
/* ECC modes supported by the controller */
187
+
#define ECC_NONE BIT(0)
188
+
#define ECC_RS_4BIT BIT(1)
189
+
#define ECC_BCH_4BIT BIT(2)
190
+
#define ECC_BCH_8BIT BIT(3)
191
+
192
+
/*
193
+
* Returns the actual register address for all NAND_DEV_ registers
194
+
* (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD)
195
+
*/
196
+
#define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
197
+
198
+
/* Returns the NAND register physical address */
199
+
#define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
200
+
201
+
/* Returns the dma address for reg read buffer */
202
+
#define reg_buf_dma_addr(chip, vaddr) \
203
+
((chip)->reg_read_dma + \
204
+
((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf))
205
+
206
+
#define QPIC_PER_CW_CMD_ELEMENTS 32
207
+
#define QPIC_PER_CW_CMD_SGL 32
208
+
#define QPIC_PER_CW_DATA_SGL 8
209
+
210
+
#define QPIC_NAND_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
211
+
212
+
/*
213
+
* Flags used in DMA descriptor preparation helper functions
214
+
* (i.e. qcom_read_reg_dma/qcom_write_reg_dma/qcom_read_data_dma/qcom_write_data_dma)
215
+
*/
216
+
/* Don't set the EOT in current tx BAM sgl */
217
+
#define NAND_BAM_NO_EOT BIT(0)
218
+
/* Set the NWD flag in current BAM sgl */
219
+
#define NAND_BAM_NWD BIT(1)
220
+
/* Finish writing in the current BAM sgl and start writing in another BAM sgl */
221
+
#define NAND_BAM_NEXT_SGL BIT(2)
222
+
/*
223
+
* Erased codeword status is being used two times in single transfer so this
224
+
* flag will determine the current value of erased codeword status register
225
+
*/
226
+
#define NAND_ERASED_CW_SET BIT(4)
227
+
228
+
#define MAX_ADDRESS_CYCLE 5
229
+
230
+
/*
231
+
* This data type corresponds to the BAM transaction which will be used for all
232
+
* NAND transfers.
233
+
* @bam_ce - the array of BAM command elements
234
+
* @cmd_sgl - sgl for NAND BAM command pipe
235
+
* @data_sgl - sgl for NAND BAM consumer/producer pipe
236
+
* @last_data_desc - last DMA desc in data channel (tx/rx).
237
+
* @last_cmd_desc - last DMA desc in command channel.
238
+
* @txn_done - completion for NAND transfer.
239
+
* @bam_ce_pos - the index in bam_ce which is available for next sgl
240
+
* @bam_ce_start - the index in bam_ce which marks the start position ce
241
+
* for current sgl. It will be used for size calculation
242
+
* for current sgl
243
+
* @cmd_sgl_pos - current index in command sgl.
244
+
* @cmd_sgl_start - start index in command sgl.
245
+
* @tx_sgl_pos - current index in data sgl for tx.
246
+
* @tx_sgl_start - start index in data sgl for tx.
247
+
* @rx_sgl_pos - current index in data sgl for rx.
248
+
* @rx_sgl_start - start index in data sgl for rx.
249
+
*/
250
+
struct bam_transaction {
251
+
struct bam_cmd_element *bam_ce;
252
+
struct scatterlist *cmd_sgl;
253
+
struct scatterlist *data_sgl;
254
+
struct dma_async_tx_descriptor *last_data_desc;
255
+
struct dma_async_tx_descriptor *last_cmd_desc;
256
+
struct completion txn_done;
257
+
struct_group(bam_positions,
258
+
u32 bam_ce_pos;
259
+
u32 bam_ce_start;
260
+
u32 cmd_sgl_pos;
261
+
u32 cmd_sgl_start;
262
+
u32 tx_sgl_pos;
263
+
u32 tx_sgl_start;
264
+
u32 rx_sgl_pos;
265
+
u32 rx_sgl_start;
266
+
267
+
);
268
+
};
269
+
270
+
/*
271
+
* This data type corresponds to the nand dma descriptor
272
+
* @dma_desc - low level DMA engine descriptor
273
+
* @list - list for desc_info
274
+
*
275
+
* @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
276
+
* ADM
277
+
* @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
278
+
* @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
279
+
* @dir - DMA transfer direction
280
+
*/
281
+
struct desc_info {
282
+
struct dma_async_tx_descriptor *dma_desc;
283
+
struct list_head node;
284
+
285
+
union {
286
+
struct scatterlist adm_sgl;
287
+
struct {
288
+
struct scatterlist *bam_sgl;
289
+
int sgl_cnt;
290
+
};
291
+
};
292
+
enum dma_data_direction dir;
293
+
};
294
+
295
+
/*
296
+
* holds the current register values that we want to write. acts as a contiguous
297
+
* chunk of memory which we use to write the controller registers through DMA.
298
+
*/
299
+
struct nandc_regs {
300
+
__le32 cmd;
301
+
__le32 addr0;
302
+
__le32 addr1;
303
+
__le32 chip_sel;
304
+
__le32 exec;
305
+
306
+
__le32 cfg0;
307
+
__le32 cfg1;
308
+
__le32 ecc_bch_cfg;
309
+
310
+
__le32 clrflashstatus;
311
+
__le32 clrreadstatus;
312
+
313
+
__le32 cmd1;
314
+
__le32 vld;
315
+
316
+
__le32 orig_cmd1;
317
+
__le32 orig_vld;
318
+
319
+
__le32 ecc_buf_cfg;
320
+
__le32 read_location0;
321
+
__le32 read_location1;
322
+
__le32 read_location2;
323
+
__le32 read_location3;
324
+
__le32 read_location_last0;
325
+
__le32 read_location_last1;
326
+
__le32 read_location_last2;
327
+
__le32 read_location_last3;
328
+
329
+
__le32 erased_cw_detect_cfg_clr;
330
+
__le32 erased_cw_detect_cfg_set;
331
+
};
332
+
333
+
/*
334
+
* NAND controller data struct
335
+
*
336
+
* @dev: parent device
337
+
*
338
+
* @base: MMIO base
339
+
*
340
+
* @core_clk: controller clock
341
+
* @aon_clk: another controller clock
342
+
*
343
+
* @regs: a contiguous chunk of memory for DMA register
344
+
* writes. contains the register values to be
345
+
* written to controller
346
+
*
347
+
* @props: properties of current NAND controller,
348
+
* initialized via DT match data
349
+
*
350
+
* @controller: base controller structure
351
+
* @host_list: list containing all the chips attached to the
352
+
* controller
353
+
*
354
+
* @chan: dma channel
355
+
* @cmd_crci: ADM DMA CRCI for command flow control
356
+
* @data_crci: ADM DMA CRCI for data flow control
357
+
*
358
+
* @desc_list: DMA descriptor list (list of desc_infos)
359
+
*
360
+
* @data_buffer: our local DMA buffer for page read/writes,
361
+
* used when we can't use the buffer provided
362
+
* by upper layers directly
363
+
* @reg_read_buf: local buffer for reading back registers via DMA
364
+
*
365
+
* @base_phys: physical base address of controller registers
366
+
* @base_dma: dma base address of controller registers
367
+
* @reg_read_dma: contains dma address for register read buffer
368
+
*
369
+
* @buf_size/count/start: markers for chip->legacy.read_buf/write_buf
370
+
* functions
371
+
* @max_cwperpage: maximum QPIC codewords required. calculated
372
+
* from all connected NAND devices pagesize
373
+
*
374
+
* @reg_read_pos: marker for data read in reg_read_buf
375
+
*
376
+
* @cmd1/vld: some fixed controller register values
377
+
*
378
+
* @exec_opwrite: flag to select correct number of code word
379
+
* while reading status
380
+
*/
381
+
struct qcom_nand_controller {
382
+
struct device *dev;
383
+
384
+
void __iomem *base;
385
+
386
+
struct clk *core_clk;
387
+
struct clk *aon_clk;
388
+
389
+
struct nandc_regs *regs;
390
+
struct bam_transaction *bam_txn;
391
+
392
+
const struct qcom_nandc_props *props;
393
+
394
+
struct nand_controller *controller;
395
+
struct list_head host_list;
396
+
397
+
union {
398
+
/* will be used only by QPIC for BAM DMA */
399
+
struct {
400
+
struct dma_chan *tx_chan;
401
+
struct dma_chan *rx_chan;
402
+
struct dma_chan *cmd_chan;
403
+
};
404
+
405
+
/* will be used only by EBI2 for ADM DMA */
406
+
struct {
407
+
struct dma_chan *chan;
408
+
unsigned int cmd_crci;
409
+
unsigned int data_crci;
410
+
};
411
+
};
412
+
413
+
struct list_head desc_list;
414
+
415
+
u8 *data_buffer;
416
+
__le32 *reg_read_buf;
417
+
418
+
phys_addr_t base_phys;
419
+
dma_addr_t base_dma;
420
+
dma_addr_t reg_read_dma;
421
+
422
+
int buf_size;
423
+
int buf_count;
424
+
int buf_start;
425
+
unsigned int max_cwperpage;
426
+
427
+
int reg_read_pos;
428
+
429
+
u32 cmd1, vld;
430
+
bool exec_opwrite;
431
+
};
432
+
433
+
/*
434
+
* This data type corresponds to the NAND controller properties which varies
435
+
* among different NAND controllers.
436
+
* @ecc_modes - ecc mode for NAND
437
+
* @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
438
+
* @supports_bam - whether NAND controller is using BAM
439
+
* @nandc_part_of_qpic - whether NAND controller is part of qpic IP
440
+
* @qpic_version2 - flag to indicate QPIC IP version 2
441
+
* @use_codeword_fixup - whether NAND has different layout for boot partitions
442
+
*/
443
+
struct qcom_nandc_props {
444
+
u32 ecc_modes;
445
+
u32 dev_cmd_reg_start;
446
+
bool supports_bam;
447
+
bool nandc_part_of_qpic;
448
+
bool qpic_version2;
449
+
bool use_codeword_fixup;
450
+
};
451
+
452
+
void qcom_free_bam_transaction(struct qcom_nand_controller *nandc);
453
+
struct bam_transaction *qcom_alloc_bam_transaction(struct qcom_nand_controller *nandc);
454
+
void qcom_clear_bam_transaction(struct qcom_nand_controller *nandc);
455
+
void qcom_qpic_bam_dma_done(void *data);
456
+
void qcom_nandc_dev_to_mem(struct qcom_nand_controller *nandc, bool is_cpu);
457
+
int qcom_prepare_bam_async_desc(struct qcom_nand_controller *nandc,
458
+
struct dma_chan *chan, unsigned long flags);
459
+
int qcom_prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
460
+
int reg_off, const void *vaddr, int size, unsigned int flags);
461
+
int qcom_prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
462
+
const void *vaddr, int size, unsigned int flags);
463
+
int qcom_prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read, int reg_off,
464
+
const void *vaddr, int size, bool flow_control);
465
+
int qcom_read_reg_dma(struct qcom_nand_controller *nandc, int first, int num_regs,
466
+
unsigned int flags);
467
+
int qcom_write_reg_dma(struct qcom_nand_controller *nandc, __le32 *vaddr, int first,
468
+
int num_regs, unsigned int flags);
469
+
int qcom_read_data_dma(struct qcom_nand_controller *nandc, int reg_off, const u8 *vaddr,
470
+
int size, unsigned int flags);
471
+
int qcom_write_data_dma(struct qcom_nand_controller *nandc, int reg_off, const u8 *vaddr,
472
+
int size, unsigned int flags);
473
+
int qcom_submit_descs(struct qcom_nand_controller *nandc);
474
+
void qcom_clear_read_regs(struct qcom_nand_controller *nandc);
475
+
void qcom_nandc_unalloc(struct qcom_nand_controller *nandc);
476
+
int qcom_nandc_alloc(struct qcom_nand_controller *nandc);
477
+
#endif
478
+
+55
-5
include/linux/mtd/spinand.h
+55
-5
include/linux/mtd/spinand.h
···
62
62
SPI_MEM_OP_NO_DUMMY, \
63
63
SPI_MEM_OP_NO_DATA)
64
64
65
-
#define SPINAND_PAGE_READ_FROM_CACHE_OP(fast, addr, ndummy, buf, len) \
66
-
SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \
65
+
#define SPINAND_PAGE_READ_FROM_CACHE_OP(addr, ndummy, buf, len, ...) \
66
+
SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \
67
67
SPI_MEM_OP_ADDR(2, addr, 1), \
68
68
SPI_MEM_OP_DUMMY(ndummy, 1), \
69
-
SPI_MEM_OP_DATA_IN(len, buf, 1))
69
+
SPI_MEM_OP_DATA_IN(len, buf, 1), \
70
+
__VA_OPT__(SPI_MEM_OP_MAX_FREQ(__VA_ARGS__)))
70
71
71
-
#define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(fast, addr, ndummy, buf, len) \
72
-
SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \
72
+
#define SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(addr, ndummy, buf, len) \
73
+
SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \
74
+
SPI_MEM_OP_ADDR(2, addr, 1), \
75
+
SPI_MEM_OP_DUMMY(ndummy, 1), \
76
+
SPI_MEM_OP_DATA_IN(len, buf, 1))
77
+
78
+
#define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(addr, ndummy, buf, len) \
79
+
SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \
73
80
SPI_MEM_OP_ADDR(3, addr, 1), \
74
81
SPI_MEM_OP_DUMMY(ndummy, 1), \
75
82
SPI_MEM_OP_DATA_IN(len, buf, 1))
83
+
84
+
#define SPINAND_PAGE_READ_FROM_CACHE_FAST_OP_3A(addr, ndummy, buf, len) \
85
+
SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \
86
+
SPI_MEM_OP_ADDR(3, addr, 1), \
87
+
SPI_MEM_OP_DUMMY(ndummy, 1), \
88
+
SPI_MEM_OP_DATA_IN(len, buf, 1))
89
+
90
+
#define SPINAND_PAGE_READ_FROM_CACHE_DTR_OP(addr, ndummy, buf, len, freq) \
91
+
SPI_MEM_OP(SPI_MEM_OP_CMD(0x0d, 1), \
92
+
SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
93
+
SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
94
+
SPI_MEM_DTR_OP_DATA_IN(len, buf, 1), \
95
+
SPI_MEM_OP_MAX_FREQ(freq))
76
96
77
97
#define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \
78
98
SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
···
106
86
SPI_MEM_OP_DUMMY(ndummy, 1), \
107
87
SPI_MEM_OP_DATA_IN(len, buf, 2))
108
88
89
+
#define SPINAND_PAGE_READ_FROM_CACHE_X2_DTR_OP(addr, ndummy, buf, len, freq) \
90
+
SPI_MEM_OP(SPI_MEM_OP_CMD(0x3d, 1), \
91
+
SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
92
+
SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
93
+
SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \
94
+
SPI_MEM_OP_MAX_FREQ(freq))
95
+
109
96
#define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \
110
97
SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
111
98
SPI_MEM_OP_ADDR(2, addr, 1), \
···
124
97
SPI_MEM_OP_ADDR(3, addr, 1), \
125
98
SPI_MEM_OP_DUMMY(ndummy, 1), \
126
99
SPI_MEM_OP_DATA_IN(len, buf, 4))
100
+
101
+
#define SPINAND_PAGE_READ_FROM_CACHE_X4_DTR_OP(addr, ndummy, buf, len, freq) \
102
+
SPI_MEM_OP(SPI_MEM_OP_CMD(0x6d, 1), \
103
+
SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
104
+
SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
105
+
SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \
106
+
SPI_MEM_OP_MAX_FREQ(freq))
127
107
128
108
#define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \
129
109
SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
···
144
110
SPI_MEM_OP_DUMMY(ndummy, 2), \
145
111
SPI_MEM_OP_DATA_IN(len, buf, 2))
146
112
113
+
#define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_DTR_OP(addr, ndummy, buf, len, freq) \
114
+
SPI_MEM_OP(SPI_MEM_OP_CMD(0xbd, 1), \
115
+
SPI_MEM_DTR_OP_ADDR(2, addr, 2), \
116
+
SPI_MEM_DTR_OP_DUMMY(ndummy, 2), \
117
+
SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \
118
+
SPI_MEM_OP_MAX_FREQ(freq))
119
+
147
120
#define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len) \
148
121
SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
149
122
SPI_MEM_OP_ADDR(2, addr, 4), \
···
162
121
SPI_MEM_OP_ADDR(3, addr, 4), \
163
122
SPI_MEM_OP_DUMMY(ndummy, 4), \
164
123
SPI_MEM_OP_DATA_IN(len, buf, 4))
124
+
125
+
#define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_DTR_OP(addr, ndummy, buf, len, freq) \
126
+
SPI_MEM_OP(SPI_MEM_OP_CMD(0xed, 1), \
127
+
SPI_MEM_DTR_OP_ADDR(2, addr, 4), \
128
+
SPI_MEM_DTR_OP_DUMMY(ndummy, 4), \
129
+
SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \
130
+
SPI_MEM_OP_MAX_FREQ(freq))
165
131
166
132
#define SPINAND_PROG_EXEC_OP(addr) \
167
133
SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \
···
316
268
extern const struct spinand_manufacturer macronix_spinand_manufacturer;
317
269
extern const struct spinand_manufacturer micron_spinand_manufacturer;
318
270
extern const struct spinand_manufacturer paragon_spinand_manufacturer;
271
+
extern const struct spinand_manufacturer skyhigh_spinand_manufacturer;
319
272
extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
320
273
extern const struct spinand_manufacturer winbond_spinand_manufacturer;
321
274
extern const struct spinand_manufacturer xtx_spinand_manufacturer;
···
363
314
#define SPINAND_HAS_CR_FEAT_BIT BIT(1)
364
315
#define SPINAND_HAS_PROG_PLANE_SELECT_BIT BIT(2)
365
316
#define SPINAND_HAS_READ_PLANE_SELECT_BIT BIT(3)
317
+
#define SPINAND_NO_RAW_ACCESS BIT(4)
366
318
367
319
/**
368
320
* struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure