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dt-bindings: spmi: add support for glymur-spmi-pmic-arb (arbiter v8)

SPMI PMIC Arbiter version 8 builds upon version 7 with support for
up to four SPMI buses. To achieve this, the register map was
slightly rearranged. Add a new binding file and compatible string
for version 8 using the name 'glymur' as the Qualcomm Technologies,
Inc. Glymur SoC is the first one to use PMIC arbiter version 8. This
specifies the new register ranges needed only for version 8.

Also document SPMI PMIC Arbiter for Qualcomm Kaanapali SoC, by adding
fallback to Glymur compatible string, as it too has version 8
functionality.

Signed-off-by: David Collins <david.collins@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://patch.msgid.link/20260123182039.224314-9-sboyd@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Jishnu Prakash and committed by
Greg Kroah-Hartman 09144981 e9ae440c

+150
+150
Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/spmi/qcom,glymur-spmi-pmic-arb.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Technologies, Inc. Glymur SPMI Controller (PMIC Arbiter v8) 8 + 9 + maintainers: 10 + - David Collins <david.collins@oss.qualcomm.com> 11 + 12 + description: | 13 + The Glymur SPMI PMIC Arbiter implements HW version 8 and it's an SPMI 14 + controller with wrapping arbitration logic to allow for multiple on-chip 15 + devices to control up to 4 SPMI separate buses. 16 + 17 + The PMIC Arbiter can also act as an interrupt controller, providing interrupts 18 + to slave devices. 19 + 20 + allOf: 21 + - $ref: /schemas/spmi/qcom,spmi-pmic-arb-common.yaml 22 + 23 + properties: 24 + compatible: 25 + oneOf: 26 + - items: 27 + - enum: 28 + - qcom,kaanapali-spmi-pmic-arb 29 + - const: qcom,glymur-spmi-pmic-arb 30 + - enum: 31 + - qcom,glymur-spmi-pmic-arb 32 + 33 + reg: 34 + items: 35 + - description: core registers 36 + - description: tx-channel per virtual slave registers 37 + - description: rx-channel (called observer) per virtual slave registers 38 + - description: channel to PMIC peripheral mapping registers 39 + 40 + reg-names: 41 + items: 42 + - const: core 43 + - const: chnls 44 + - const: obsrvr 45 + - const: chnl_map 46 + 47 + ranges: true 48 + 49 + '#address-cells': 50 + const: 2 51 + 52 + '#size-cells': 53 + const: 2 54 + 55 + patternProperties: 56 + "^spmi@[a-f0-9]+$": 57 + type: object 58 + $ref: /schemas/spmi/spmi.yaml 59 + unevaluatedProperties: false 60 + 61 + properties: 62 + reg: 63 + items: 64 + - description: configuration registers 65 + - description: interrupt controller registers 66 + - description: channel owner EE mapping registers 67 + 68 + reg-names: 69 + items: 70 + - const: cnfg 71 + - const: intr 72 + - const: chnl_owner 73 + 74 + interrupts: 75 + maxItems: 1 76 + 77 + interrupt-names: 78 + const: periph_irq 79 + 80 + interrupt-controller: true 81 + 82 + '#interrupt-cells': 83 + const: 4 84 + description: | 85 + cell 1: slave ID for the requested interrupt (0-15) 86 + cell 2: peripheral ID for requested interrupt (0-255) 87 + cell 3: the requested peripheral interrupt (0-7) 88 + cell 4: interrupt flags indicating level-sense information, 89 + as defined in dt-bindings/interrupt-controller/irq.h 90 + 91 + required: 92 + - compatible 93 + - reg-names 94 + 95 + unevaluatedProperties: false 96 + 97 + examples: 98 + - | 99 + #include <dt-bindings/interrupt-controller/arm-gic.h> 100 + 101 + soc { 102 + #address-cells = <2>; 103 + #size-cells = <2>; 104 + 105 + arbiter@c400000 { 106 + compatible = "qcom,glymur-spmi-pmic-arb"; 107 + reg = <0x0 0xc400000 0x0 0x3000>, 108 + <0x0 0xc900000 0x0 0x400000>, 109 + <0x0 0xc4c0000 0x0 0x400000>, 110 + <0x0 0xc403000 0x0 0x8000>; 111 + reg-names = "core", "chnls", "obsrvr", "chnl_map"; 112 + 113 + qcom,ee = <0>; 114 + qcom,channel = <0>; 115 + 116 + #address-cells = <2>; 117 + #size-cells = <2>; 118 + ranges; 119 + 120 + spmi@c426000 { 121 + reg = <0x0 0xc426000 0x0 0x4000>, 122 + <0x0 0xc8c0000 0x0 0x10000>, 123 + <0x0 0xc42a000 0x0 0x8000>; 124 + reg-names = "cnfg", "intr", "chnl_owner"; 125 + 126 + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 127 + interrupt-names = "periph_irq"; 128 + interrupt-controller; 129 + #interrupt-cells = <4>; 130 + 131 + #address-cells = <2>; 132 + #size-cells = <0>; 133 + }; 134 + 135 + spmi@c437000 { 136 + reg = <0x0 0xc437000 0x0 0x4000>, 137 + <0x0 0xc8d0000 0x0 0x10000>, 138 + <0x0 0xc43b000 0x0 0x8000>; 139 + reg-names = "cnfg", "intr", "chnl_owner"; 140 + 141 + interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 142 + interrupt-names = "periph_irq"; 143 + interrupt-controller; 144 + #interrupt-cells = <4>; 145 + 146 + #address-cells = <2>; 147 + #size-cells = <0>; 148 + }; 149 + }; 150 + };