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Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue

Tony Nguyen says:

====================
Intel Wired LAN Driver Updates 2024-03-29 (net: intel)

This series contains updates to most Intel drivers.

Jesse moves declaration of pci_driver struct to remove need for forward
declarations in igb and converts Intel drivers to user newer power
management ops.

Sasha reworks power management flow on igc to avoid using rtnl_lock()
during those flows.

Maciej reorganizes i40e_nvm file to avoid forward declarations.

* '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue:
i40e: avoid forward declarations in i40e_nvm.c
igc: Refactor runtime power management flow
net: intel: implement modern PM ops declarations
igb: simplify pci ops declaration
====================

Link: https://lore.kernel.org/r/20240329175632.211340-1-anthony.l.nguyen@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

+657 -724
+4 -4
drivers/net/ethernet/intel/e100.c
··· 3037 3037 return 0; 3038 3038 } 3039 3039 3040 - static int __maybe_unused e100_suspend(struct device *dev_d) 3040 + static int e100_suspend(struct device *dev_d) 3041 3041 { 3042 3042 bool wake; 3043 3043 ··· 3046 3046 return 0; 3047 3047 } 3048 3048 3049 - static int __maybe_unused e100_resume(struct device *dev_d) 3049 + static int e100_resume(struct device *dev_d) 3050 3050 { 3051 3051 struct net_device *netdev = dev_get_drvdata(dev_d); 3052 3052 struct nic *nic = netdev_priv(netdev); ··· 3163 3163 .resume = e100_io_resume, 3164 3164 }; 3165 3165 3166 - static SIMPLE_DEV_PM_OPS(e100_pm_ops, e100_suspend, e100_resume); 3166 + static DEFINE_SIMPLE_DEV_PM_OPS(e100_pm_ops, e100_suspend, e100_resume); 3167 3167 3168 3168 static struct pci_driver e100_driver = { 3169 3169 .name = DRV_NAME, ··· 3172 3172 .remove = e100_remove, 3173 3173 3174 3174 /* Power Management hooks */ 3175 - .driver.pm = &e100_pm_ops, 3175 + .driver.pm = pm_sleep_ptr(&e100_pm_ops), 3176 3176 3177 3177 .shutdown = e100_shutdown, 3178 3178 .err_handler = &e100_err_handler,
+6 -8
drivers/net/ethernet/intel/e1000/e1000_main.c
··· 149 149 __be16 proto, u16 vid); 150 150 static void e1000_restore_vlan(struct e1000_adapter *adapter); 151 151 152 - static int __maybe_unused e1000_suspend(struct device *dev); 153 - static int __maybe_unused e1000_resume(struct device *dev); 152 + static int e1000_suspend(struct device *dev); 153 + static int e1000_resume(struct device *dev); 154 154 static void e1000_shutdown(struct pci_dev *pdev); 155 155 156 156 #ifdef CONFIG_NET_POLL_CONTROLLER ··· 175 175 .resume = e1000_io_resume, 176 176 }; 177 177 178 - static SIMPLE_DEV_PM_OPS(e1000_pm_ops, e1000_suspend, e1000_resume); 178 + static DEFINE_SIMPLE_DEV_PM_OPS(e1000_pm_ops, e1000_suspend, e1000_resume); 179 179 180 180 static struct pci_driver e1000_driver = { 181 181 .name = e1000_driver_name, 182 182 .id_table = e1000_pci_tbl, 183 183 .probe = e1000_probe, 184 184 .remove = e1000_remove, 185 - .driver = { 186 - .pm = &e1000_pm_ops, 187 - }, 185 + .driver.pm = pm_sleep_ptr(&e1000_pm_ops), 188 186 .shutdown = e1000_shutdown, 189 187 .err_handler = &e1000_err_handler 190 188 }; ··· 5133 5135 return 0; 5134 5136 } 5135 5137 5136 - static int __maybe_unused e1000_suspend(struct device *dev) 5138 + static int e1000_suspend(struct device *dev) 5137 5139 { 5138 5140 int retval; 5139 5141 struct pci_dev *pdev = to_pci_dev(dev); ··· 5145 5147 return retval; 5146 5148 } 5147 5149 5148 - static int __maybe_unused e1000_resume(struct device *dev) 5150 + static int e1000_resume(struct device *dev) 5149 5151 { 5150 5152 struct pci_dev *pdev = to_pci_dev(dev); 5151 5153 struct net_device *netdev = pci_get_drvdata(pdev);
+9 -13
drivers/net/ethernet/intel/e1000e/netdev.c
··· 6950 6950 return 0; 6951 6951 } 6952 6952 6953 - static __maybe_unused int e1000e_pm_prepare(struct device *dev) 6953 + static int e1000e_pm_prepare(struct device *dev) 6954 6954 { 6955 6955 return pm_runtime_suspended(dev) && 6956 6956 pm_suspend_via_firmware(); 6957 6957 } 6958 6958 6959 - static __maybe_unused int e1000e_pm_suspend(struct device *dev) 6959 + static int e1000e_pm_suspend(struct device *dev) 6960 6960 { 6961 6961 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6962 6962 struct e1000_adapter *adapter = netdev_priv(netdev); ··· 6979 6979 return rc; 6980 6980 } 6981 6981 6982 - static __maybe_unused int e1000e_pm_resume(struct device *dev) 6982 + static int e1000e_pm_resume(struct device *dev) 6983 6983 { 6984 6984 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); 6985 6985 struct e1000_adapter *adapter = netdev_priv(netdev); ··· 7013 7013 return -EBUSY; 7014 7014 } 7015 7015 7016 - static __maybe_unused int e1000e_pm_runtime_resume(struct device *dev) 7016 + static int e1000e_pm_runtime_resume(struct device *dev) 7017 7017 { 7018 7018 struct pci_dev *pdev = to_pci_dev(dev); 7019 7019 struct net_device *netdev = pci_get_drvdata(pdev); ··· 7032 7032 return rc; 7033 7033 } 7034 7034 7035 - static __maybe_unused int e1000e_pm_runtime_suspend(struct device *dev) 7035 + static int e1000e_pm_runtime_suspend(struct device *dev) 7036 7036 { 7037 7037 struct pci_dev *pdev = to_pci_dev(dev); 7038 7038 struct net_device *netdev = pci_get_drvdata(pdev); ··· 7919 7919 }; 7920 7920 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); 7921 7921 7922 - static const struct dev_pm_ops e1000_pm_ops = { 7923 - #ifdef CONFIG_PM_SLEEP 7922 + static const struct dev_pm_ops e1000e_pm_ops = { 7924 7923 .prepare = e1000e_pm_prepare, 7925 7924 .suspend = e1000e_pm_suspend, 7926 7925 .resume = e1000e_pm_resume, ··· 7927 7928 .thaw = e1000e_pm_thaw, 7928 7929 .poweroff = e1000e_pm_suspend, 7929 7930 .restore = e1000e_pm_resume, 7930 - #endif 7931 - SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume, 7932 - e1000e_pm_runtime_idle) 7931 + RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume, 7932 + e1000e_pm_runtime_idle) 7933 7933 }; 7934 7934 7935 7935 /* PCI Device API Driver */ ··· 7937 7939 .id_table = e1000_pci_tbl, 7938 7940 .probe = e1000_probe, 7939 7941 .remove = e1000_remove, 7940 - .driver = { 7941 - .pm = &e1000_pm_ops, 7942 - }, 7942 + .driver.pm = pm_ptr(&e1000e_pm_ops), 7943 7943 .shutdown = e1000_shutdown, 7944 7944 .err_handler = &e1000_err_handler 7945 7945 };
+4 -6
drivers/net/ethernet/intel/fm10k/fm10k_pci.c
··· 2342 2342 * suspend or hibernation. This function does not need to handle lower PCIe 2343 2343 * device state as the stack takes care of that for us. 2344 2344 **/ 2345 - static int __maybe_unused fm10k_resume(struct device *dev) 2345 + static int fm10k_resume(struct device *dev) 2346 2346 { 2347 2347 struct fm10k_intfc *interface = dev_get_drvdata(dev); 2348 2348 struct net_device *netdev = interface->netdev; ··· 2369 2369 * system suspend or hibernation. This function does not need to handle lower 2370 2370 * PCIe device state as the stack takes care of that for us. 2371 2371 **/ 2372 - static int __maybe_unused fm10k_suspend(struct device *dev) 2372 + static int fm10k_suspend(struct device *dev) 2373 2373 { 2374 2374 struct fm10k_intfc *interface = dev_get_drvdata(dev); 2375 2375 struct net_device *netdev = interface->netdev; ··· 2502 2502 .reset_done = fm10k_io_reset_done, 2503 2503 }; 2504 2504 2505 - static SIMPLE_DEV_PM_OPS(fm10k_pm_ops, fm10k_suspend, fm10k_resume); 2505 + static DEFINE_SIMPLE_DEV_PM_OPS(fm10k_pm_ops, fm10k_suspend, fm10k_resume); 2506 2506 2507 2507 static struct pci_driver fm10k_driver = { 2508 2508 .name = fm10k_driver_name, 2509 2509 .id_table = fm10k_pci_tbl, 2510 2510 .probe = fm10k_probe, 2511 2511 .remove = fm10k_remove, 2512 - .driver = { 2513 - .pm = &fm10k_pm_ops, 2514 - }, 2512 + .driver.pm = pm_sleep_ptr(&fm10k_pm_ops), 2515 2513 .sriov_configure = fm10k_iov_configure, 2516 2514 .err_handler = &fm10k_err_handler 2517 2515 };
+4 -6
drivers/net/ethernet/intel/i40e/i40e_main.c
··· 16505 16505 * i40e_suspend - PM callback for moving to D3 16506 16506 * @dev: generic device information structure 16507 16507 **/ 16508 - static int __maybe_unused i40e_suspend(struct device *dev) 16508 + static int i40e_suspend(struct device *dev) 16509 16509 { 16510 16510 struct i40e_pf *pf = dev_get_drvdata(dev); 16511 16511 struct i40e_hw *hw = &pf->hw; ··· 16556 16556 * i40e_resume - PM callback for waking up from D3 16557 16557 * @dev: generic device information structure 16558 16558 **/ 16559 - static int __maybe_unused i40e_resume(struct device *dev) 16559 + static int i40e_resume(struct device *dev) 16560 16560 { 16561 16561 struct i40e_pf *pf = dev_get_drvdata(dev); 16562 16562 int err; ··· 16602 16602 .resume = i40e_pci_error_resume, 16603 16603 }; 16604 16604 16605 - static SIMPLE_DEV_PM_OPS(i40e_pm_ops, i40e_suspend, i40e_resume); 16605 + static DEFINE_SIMPLE_DEV_PM_OPS(i40e_pm_ops, i40e_suspend, i40e_resume); 16606 16606 16607 16607 static struct pci_driver i40e_driver = { 16608 16608 .name = i40e_driver_name, 16609 16609 .id_table = i40e_pci_tbl, 16610 16610 .probe = i40e_probe, 16611 16611 .remove = i40e_remove, 16612 - .driver = { 16613 - .pm = &i40e_pm_ops, 16614 - }, 16612 + .driver.pm = pm_sleep_ptr(&i40e_pm_ops), 16615 16613 .shutdown = i40e_shutdown, 16616 16614 .err_handler = &i40e_err_handler, 16617 16615 .sriov_configure = i40e_pci_sriov_configure,
+564 -596
drivers/net/ethernet/intel/i40e/i40e_nvm.c
··· 734 734 return ret_code; 735 735 } 736 736 737 - static int i40e_nvmupd_state_init(struct i40e_hw *hw, 738 - struct i40e_nvm_access *cmd, 739 - u8 *bytes, int *perrno); 740 - static int i40e_nvmupd_state_reading(struct i40e_hw *hw, 741 - struct i40e_nvm_access *cmd, 742 - u8 *bytes, int *perrno); 743 - static int i40e_nvmupd_state_writing(struct i40e_hw *hw, 744 - struct i40e_nvm_access *cmd, 745 - u8 *bytes, int *errno); 746 - static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw, 747 - struct i40e_nvm_access *cmd, 748 - int *perrno); 749 - static int i40e_nvmupd_nvm_erase(struct i40e_hw *hw, 750 - struct i40e_nvm_access *cmd, 751 - int *perrno); 752 - static int i40e_nvmupd_nvm_write(struct i40e_hw *hw, 753 - struct i40e_nvm_access *cmd, 754 - u8 *bytes, int *perrno); 755 - static int i40e_nvmupd_nvm_read(struct i40e_hw *hw, 756 - struct i40e_nvm_access *cmd, 757 - u8 *bytes, int *perrno); 758 - static int i40e_nvmupd_exec_aq(struct i40e_hw *hw, 759 - struct i40e_nvm_access *cmd, 760 - u8 *bytes, int *perrno); 761 - static int i40e_nvmupd_get_aq_result(struct i40e_hw *hw, 762 - struct i40e_nvm_access *cmd, 763 - u8 *bytes, int *perrno); 764 - static int i40e_nvmupd_get_aq_event(struct i40e_hw *hw, 765 - struct i40e_nvm_access *cmd, 766 - u8 *bytes, int *perrno); 767 - static inline u8 i40e_nvmupd_get_module(u32 val) 737 + static u8 i40e_nvmupd_get_module(u32 val) 768 738 { 769 739 return (u8)(val & I40E_NVM_MOD_PNT_MASK); 770 740 } ··· 769 799 }; 770 800 771 801 /** 772 - * i40e_nvmupd_command - Process an NVM update command 773 - * @hw: pointer to hardware structure 774 - * @cmd: pointer to nvm update command 775 - * @bytes: pointer to the data buffer 776 - * @perrno: pointer to return error code 777 - * 778 - * Dispatches command depending on what update state is current 779 - **/ 780 - int i40e_nvmupd_command(struct i40e_hw *hw, 781 - struct i40e_nvm_access *cmd, 782 - u8 *bytes, int *perrno) 783 - { 784 - enum i40e_nvmupd_cmd upd_cmd; 785 - int status; 786 - 787 - /* assume success */ 788 - *perrno = 0; 789 - 790 - /* early check for status command and debug msgs */ 791 - upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 792 - 793 - i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d opc 0x%04x cmd 0x%08x config 0x%08x offset 0x%08x data_size 0x%08x\n", 794 - i40e_nvm_update_state_str[upd_cmd], 795 - hw->nvmupd_state, 796 - hw->nvm_release_on_done, hw->nvm_wait_opcode, 797 - cmd->command, cmd->config, cmd->offset, cmd->data_size); 798 - 799 - if (upd_cmd == I40E_NVMUPD_INVALID) { 800 - *perrno = -EFAULT; 801 - i40e_debug(hw, I40E_DEBUG_NVM, 802 - "i40e_nvmupd_validate_command returns %d errno %d\n", 803 - upd_cmd, *perrno); 804 - } 805 - 806 - /* a status request returns immediately rather than 807 - * going into the state machine 808 - */ 809 - if (upd_cmd == I40E_NVMUPD_STATUS) { 810 - if (!cmd->data_size) { 811 - *perrno = -EFAULT; 812 - return -EINVAL; 813 - } 814 - 815 - bytes[0] = hw->nvmupd_state; 816 - 817 - if (cmd->data_size >= 4) { 818 - bytes[1] = 0; 819 - *((u16 *)&bytes[2]) = hw->nvm_wait_opcode; 820 - } 821 - 822 - /* Clear error status on read */ 823 - if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) 824 - hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 825 - 826 - return 0; 827 - } 828 - 829 - /* Clear status even it is not read and log */ 830 - if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) { 831 - i40e_debug(hw, I40E_DEBUG_NVM, 832 - "Clearing I40E_NVMUPD_STATE_ERROR state without reading\n"); 833 - hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 834 - } 835 - 836 - /* Acquire lock to prevent race condition where adminq_task 837 - * can execute after i40e_nvmupd_nvm_read/write but before state 838 - * variables (nvm_wait_opcode, nvm_release_on_done) are updated. 839 - * 840 - * During NVMUpdate, it is observed that lock could be held for 841 - * ~5ms for most commands. However lock is held for ~60ms for 842 - * NVMUPD_CSUM_LCB command. 843 - */ 844 - mutex_lock(&hw->aq.arq_mutex); 845 - switch (hw->nvmupd_state) { 846 - case I40E_NVMUPD_STATE_INIT: 847 - status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno); 848 - break; 849 - 850 - case I40E_NVMUPD_STATE_READING: 851 - status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno); 852 - break; 853 - 854 - case I40E_NVMUPD_STATE_WRITING: 855 - status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno); 856 - break; 857 - 858 - case I40E_NVMUPD_STATE_INIT_WAIT: 859 - case I40E_NVMUPD_STATE_WRITE_WAIT: 860 - /* if we need to stop waiting for an event, clear 861 - * the wait info and return before doing anything else 862 - */ 863 - if (cmd->offset == 0xffff) { 864 - i40e_nvmupd_clear_wait_state(hw); 865 - status = 0; 866 - break; 867 - } 868 - 869 - status = -EBUSY; 870 - *perrno = -EBUSY; 871 - break; 872 - 873 - default: 874 - /* invalid state, should never happen */ 875 - i40e_debug(hw, I40E_DEBUG_NVM, 876 - "NVMUPD: no such state %d\n", hw->nvmupd_state); 877 - status = -EOPNOTSUPP; 878 - *perrno = -ESRCH; 879 - break; 880 - } 881 - 882 - mutex_unlock(&hw->aq.arq_mutex); 883 - return status; 884 - } 885 - 886 - /** 887 - * i40e_nvmupd_state_init - Handle NVM update state Init 888 - * @hw: pointer to hardware structure 889 - * @cmd: pointer to nvm update command buffer 890 - * @bytes: pointer to the data buffer 891 - * @perrno: pointer to return error code 892 - * 893 - * Process legitimate commands of the Init state and conditionally set next 894 - * state. Reject all other commands. 895 - **/ 896 - static int i40e_nvmupd_state_init(struct i40e_hw *hw, 897 - struct i40e_nvm_access *cmd, 898 - u8 *bytes, int *perrno) 899 - { 900 - enum i40e_nvmupd_cmd upd_cmd; 901 - int status = 0; 902 - 903 - upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 904 - 905 - switch (upd_cmd) { 906 - case I40E_NVMUPD_READ_SA: 907 - status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 908 - if (status) { 909 - *perrno = i40e_aq_rc_to_posix(status, 910 - hw->aq.asq_last_status); 911 - } else { 912 - status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 913 - i40e_release_nvm(hw); 914 - } 915 - break; 916 - 917 - case I40E_NVMUPD_READ_SNT: 918 - status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 919 - if (status) { 920 - *perrno = i40e_aq_rc_to_posix(status, 921 - hw->aq.asq_last_status); 922 - } else { 923 - status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 924 - if (status) 925 - i40e_release_nvm(hw); 926 - else 927 - hw->nvmupd_state = I40E_NVMUPD_STATE_READING; 928 - } 929 - break; 930 - 931 - case I40E_NVMUPD_WRITE_ERA: 932 - status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 933 - if (status) { 934 - *perrno = i40e_aq_rc_to_posix(status, 935 - hw->aq.asq_last_status); 936 - } else { 937 - status = i40e_nvmupd_nvm_erase(hw, cmd, perrno); 938 - if (status) { 939 - i40e_release_nvm(hw); 940 - } else { 941 - hw->nvm_release_on_done = true; 942 - hw->nvm_wait_opcode = i40e_aqc_opc_nvm_erase; 943 - hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 944 - } 945 - } 946 - break; 947 - 948 - case I40E_NVMUPD_WRITE_SA: 949 - status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 950 - if (status) { 951 - *perrno = i40e_aq_rc_to_posix(status, 952 - hw->aq.asq_last_status); 953 - } else { 954 - status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 955 - if (status) { 956 - i40e_release_nvm(hw); 957 - } else { 958 - hw->nvm_release_on_done = true; 959 - hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 960 - hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 961 - } 962 - } 963 - break; 964 - 965 - case I40E_NVMUPD_WRITE_SNT: 966 - status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 967 - if (status) { 968 - *perrno = i40e_aq_rc_to_posix(status, 969 - hw->aq.asq_last_status); 970 - } else { 971 - status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 972 - if (status) { 973 - i40e_release_nvm(hw); 974 - } else { 975 - hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 976 - hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; 977 - } 978 - } 979 - break; 980 - 981 - case I40E_NVMUPD_CSUM_SA: 982 - status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 983 - if (status) { 984 - *perrno = i40e_aq_rc_to_posix(status, 985 - hw->aq.asq_last_status); 986 - } else { 987 - status = i40e_update_nvm_checksum(hw); 988 - if (status) { 989 - *perrno = hw->aq.asq_last_status ? 990 - i40e_aq_rc_to_posix(status, 991 - hw->aq.asq_last_status) : 992 - -EIO; 993 - i40e_release_nvm(hw); 994 - } else { 995 - hw->nvm_release_on_done = true; 996 - hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 997 - hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 998 - } 999 - } 1000 - break; 1001 - 1002 - case I40E_NVMUPD_EXEC_AQ: 1003 - status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno); 1004 - break; 1005 - 1006 - case I40E_NVMUPD_GET_AQ_RESULT: 1007 - status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno); 1008 - break; 1009 - 1010 - case I40E_NVMUPD_GET_AQ_EVENT: 1011 - status = i40e_nvmupd_get_aq_event(hw, cmd, bytes, perrno); 1012 - break; 1013 - 1014 - default: 1015 - i40e_debug(hw, I40E_DEBUG_NVM, 1016 - "NVMUPD: bad cmd %s in init state\n", 1017 - i40e_nvm_update_state_str[upd_cmd]); 1018 - status = -EIO; 1019 - *perrno = -ESRCH; 1020 - break; 1021 - } 1022 - return status; 1023 - } 1024 - 1025 - /** 1026 - * i40e_nvmupd_state_reading - Handle NVM update state Reading 1027 - * @hw: pointer to hardware structure 1028 - * @cmd: pointer to nvm update command buffer 1029 - * @bytes: pointer to the data buffer 1030 - * @perrno: pointer to return error code 1031 - * 1032 - * NVM ownership is already held. Process legitimate commands and set any 1033 - * change in state; reject all other commands. 1034 - **/ 1035 - static int i40e_nvmupd_state_reading(struct i40e_hw *hw, 1036 - struct i40e_nvm_access *cmd, 1037 - u8 *bytes, int *perrno) 1038 - { 1039 - enum i40e_nvmupd_cmd upd_cmd; 1040 - int status = 0; 1041 - 1042 - upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 1043 - 1044 - switch (upd_cmd) { 1045 - case I40E_NVMUPD_READ_SA: 1046 - case I40E_NVMUPD_READ_CON: 1047 - status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 1048 - break; 1049 - 1050 - case I40E_NVMUPD_READ_LCB: 1051 - status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 1052 - i40e_release_nvm(hw); 1053 - hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1054 - break; 1055 - 1056 - default: 1057 - i40e_debug(hw, I40E_DEBUG_NVM, 1058 - "NVMUPD: bad cmd %s in reading state.\n", 1059 - i40e_nvm_update_state_str[upd_cmd]); 1060 - status = -EOPNOTSUPP; 1061 - *perrno = -ESRCH; 1062 - break; 1063 - } 1064 - return status; 1065 - } 1066 - 1067 - /** 1068 - * i40e_nvmupd_state_writing - Handle NVM update state Writing 1069 - * @hw: pointer to hardware structure 1070 - * @cmd: pointer to nvm update command buffer 1071 - * @bytes: pointer to the data buffer 1072 - * @perrno: pointer to return error code 1073 - * 1074 - * NVM ownership is already held. Process legitimate commands and set any 1075 - * change in state; reject all other commands 1076 - **/ 1077 - static int i40e_nvmupd_state_writing(struct i40e_hw *hw, 1078 - struct i40e_nvm_access *cmd, 1079 - u8 *bytes, int *perrno) 1080 - { 1081 - enum i40e_nvmupd_cmd upd_cmd; 1082 - bool retry_attempt = false; 1083 - int status = 0; 1084 - 1085 - upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 1086 - 1087 - retry: 1088 - switch (upd_cmd) { 1089 - case I40E_NVMUPD_WRITE_CON: 1090 - status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 1091 - if (!status) { 1092 - hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 1093 - hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; 1094 - } 1095 - break; 1096 - 1097 - case I40E_NVMUPD_WRITE_LCB: 1098 - status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 1099 - if (status) { 1100 - *perrno = hw->aq.asq_last_status ? 1101 - i40e_aq_rc_to_posix(status, 1102 - hw->aq.asq_last_status) : 1103 - -EIO; 1104 - hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1105 - } else { 1106 - hw->nvm_release_on_done = true; 1107 - hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 1108 - hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 1109 - } 1110 - break; 1111 - 1112 - case I40E_NVMUPD_CSUM_CON: 1113 - /* Assumes the caller has acquired the nvm */ 1114 - status = i40e_update_nvm_checksum(hw); 1115 - if (status) { 1116 - *perrno = hw->aq.asq_last_status ? 1117 - i40e_aq_rc_to_posix(status, 1118 - hw->aq.asq_last_status) : 1119 - -EIO; 1120 - hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1121 - } else { 1122 - hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 1123 - hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; 1124 - } 1125 - break; 1126 - 1127 - case I40E_NVMUPD_CSUM_LCB: 1128 - /* Assumes the caller has acquired the nvm */ 1129 - status = i40e_update_nvm_checksum(hw); 1130 - if (status) { 1131 - *perrno = hw->aq.asq_last_status ? 1132 - i40e_aq_rc_to_posix(status, 1133 - hw->aq.asq_last_status) : 1134 - -EIO; 1135 - hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1136 - } else { 1137 - hw->nvm_release_on_done = true; 1138 - hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 1139 - hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 1140 - } 1141 - break; 1142 - 1143 - default: 1144 - i40e_debug(hw, I40E_DEBUG_NVM, 1145 - "NVMUPD: bad cmd %s in writing state.\n", 1146 - i40e_nvm_update_state_str[upd_cmd]); 1147 - status = -EOPNOTSUPP; 1148 - *perrno = -ESRCH; 1149 - break; 1150 - } 1151 - 1152 - /* In some circumstances, a multi-write transaction takes longer 1153 - * than the default 3 minute timeout on the write semaphore. If 1154 - * the write failed with an EBUSY status, this is likely the problem, 1155 - * so here we try to reacquire the semaphore then retry the write. 1156 - * We only do one retry, then give up. 1157 - */ 1158 - if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) && 1159 - !retry_attempt) { 1160 - u32 old_asq_status = hw->aq.asq_last_status; 1161 - int old_status = status; 1162 - u32 gtime; 1163 - 1164 - gtime = rd32(hw, I40E_GLVFGEN_TIMER); 1165 - if (gtime >= hw->nvm.hw_semaphore_timeout) { 1166 - i40e_debug(hw, I40E_DEBUG_ALL, 1167 - "NVMUPD: write semaphore expired (%d >= %lld), retrying\n", 1168 - gtime, hw->nvm.hw_semaphore_timeout); 1169 - i40e_release_nvm(hw); 1170 - status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 1171 - if (status) { 1172 - i40e_debug(hw, I40E_DEBUG_ALL, 1173 - "NVMUPD: write semaphore reacquire failed aq_err = %d\n", 1174 - hw->aq.asq_last_status); 1175 - status = old_status; 1176 - hw->aq.asq_last_status = old_asq_status; 1177 - } else { 1178 - retry_attempt = true; 1179 - goto retry; 1180 - } 1181 - } 1182 - } 1183 - 1184 - return status; 1185 - } 1186 - 1187 - /** 1188 - * i40e_nvmupd_clear_wait_state - clear wait state on hw 1189 - * @hw: pointer to the hardware structure 1190 - **/ 1191 - void i40e_nvmupd_clear_wait_state(struct i40e_hw *hw) 1192 - { 1193 - i40e_debug(hw, I40E_DEBUG_NVM, 1194 - "NVMUPD: clearing wait on opcode 0x%04x\n", 1195 - hw->nvm_wait_opcode); 1196 - 1197 - if (hw->nvm_release_on_done) { 1198 - i40e_release_nvm(hw); 1199 - hw->nvm_release_on_done = false; 1200 - } 1201 - hw->nvm_wait_opcode = 0; 1202 - 1203 - if (hw->aq.arq_last_status) { 1204 - hw->nvmupd_state = I40E_NVMUPD_STATE_ERROR; 1205 - return; 1206 - } 1207 - 1208 - switch (hw->nvmupd_state) { 1209 - case I40E_NVMUPD_STATE_INIT_WAIT: 1210 - hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1211 - break; 1212 - 1213 - case I40E_NVMUPD_STATE_WRITE_WAIT: 1214 - hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING; 1215 - break; 1216 - 1217 - default: 1218 - break; 1219 - } 1220 - } 1221 - 1222 - /** 1223 - * i40e_nvmupd_check_wait_event - handle NVM update operation events 1224 - * @hw: pointer to the hardware structure 1225 - * @opcode: the event that just happened 1226 - * @desc: AdminQ descriptor 1227 - **/ 1228 - void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode, 1229 - struct i40e_aq_desc *desc) 1230 - { 1231 - u32 aq_desc_len = sizeof(struct i40e_aq_desc); 1232 - 1233 - if (opcode == hw->nvm_wait_opcode) { 1234 - memcpy(&hw->nvm_aq_event_desc, desc, aq_desc_len); 1235 - i40e_nvmupd_clear_wait_state(hw); 1236 - } 1237 - } 1238 - 1239 - /** 1240 802 * i40e_nvmupd_validate_command - Validate given command 1241 803 * @hw: pointer to hardware structure 1242 804 * @cmd: pointer to nvm update command buffer ··· 776 1274 * 777 1275 * Return one of the valid command types or I40E_NVMUPD_INVALID 778 1276 **/ 779 - static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw, 780 - struct i40e_nvm_access *cmd, 781 - int *perrno) 1277 + static enum i40e_nvmupd_cmd 1278 + i40e_nvmupd_validate_command(struct i40e_hw *hw, struct i40e_nvm_access *cmd, 1279 + int *perrno) 782 1280 { 783 1281 enum i40e_nvmupd_cmd upd_cmd; 784 1282 u8 module, transaction; ··· 790 1288 module = i40e_nvmupd_get_module(cmd->config); 791 1289 792 1290 /* limits on data size */ 793 - if ((cmd->data_size < 1) || 794 - (cmd->data_size > I40E_NVMUPD_MAX_DATA)) { 1291 + if (cmd->data_size < 1 || cmd->data_size > I40E_NVMUPD_MAX_DATA) { 795 1292 i40e_debug(hw, I40E_DEBUG_NVM, 796 - "i40e_nvmupd_validate_command data_size %d\n", 797 - cmd->data_size); 1293 + "%s data_size %d\n", __func__, cmd->data_size); 798 1294 *perrno = -EFAULT; 799 1295 return I40E_NVMUPD_INVALID; 800 1296 } ··· 844 1344 case I40E_NVM_CSUM: 845 1345 upd_cmd = I40E_NVMUPD_CSUM_CON; 846 1346 break; 847 - case (I40E_NVM_CSUM|I40E_NVM_SA): 1347 + case (I40E_NVM_CSUM | I40E_NVM_SA): 848 1348 upd_cmd = I40E_NVMUPD_CSUM_SA; 849 1349 break; 850 - case (I40E_NVM_CSUM|I40E_NVM_LCB): 1350 + case (I40E_NVM_CSUM | I40E_NVM_LCB): 851 1351 upd_cmd = I40E_NVMUPD_CSUM_LCB; 852 1352 break; 853 1353 case I40E_NVM_EXEC: ··· 859 1359 } 860 1360 861 1361 return upd_cmd; 1362 + } 1363 + 1364 + /** 1365 + * i40e_nvmupd_nvm_erase - Erase an NVM module 1366 + * @hw: pointer to hardware structure 1367 + * @cmd: pointer to nvm update command buffer 1368 + * @perrno: pointer to return error code 1369 + * 1370 + * module, offset, data_size and data are in cmd structure 1371 + **/ 1372 + static int i40e_nvmupd_nvm_erase(struct i40e_hw *hw, 1373 + struct i40e_nvm_access *cmd, 1374 + int *perrno) 1375 + { 1376 + struct i40e_asq_cmd_details cmd_details; 1377 + u8 module, transaction; 1378 + int status = 0; 1379 + bool last; 1380 + 1381 + transaction = i40e_nvmupd_get_transaction(cmd->config); 1382 + module = i40e_nvmupd_get_module(cmd->config); 1383 + last = (transaction & I40E_NVM_LCB); 1384 + 1385 + memset(&cmd_details, 0, sizeof(cmd_details)); 1386 + cmd_details.wb_desc = &hw->nvm_wb_desc; 1387 + 1388 + status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size, 1389 + last, &cmd_details); 1390 + if (status) { 1391 + i40e_debug(hw, I40E_DEBUG_NVM, 1392 + "%s mod 0x%x off 0x%x len 0x%x\n", 1393 + __func__, module, cmd->offset, cmd->data_size); 1394 + i40e_debug(hw, I40E_DEBUG_NVM, 1395 + "%s status %d aq %d\n", 1396 + __func__, status, hw->aq.asq_last_status); 1397 + *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1398 + } 1399 + 1400 + return status; 1401 + } 1402 + 1403 + /** 1404 + * i40e_nvmupd_nvm_write - Write NVM 1405 + * @hw: pointer to hardware structure 1406 + * @cmd: pointer to nvm update command buffer 1407 + * @bytes: pointer to the data buffer 1408 + * @perrno: pointer to return error code 1409 + * 1410 + * module, offset, data_size and data are in cmd structure 1411 + **/ 1412 + static int i40e_nvmupd_nvm_write(struct i40e_hw *hw, 1413 + struct i40e_nvm_access *cmd, 1414 + u8 *bytes, int *perrno) 1415 + { 1416 + struct i40e_asq_cmd_details cmd_details; 1417 + u8 module, transaction; 1418 + u8 preservation_flags; 1419 + int status = 0; 1420 + bool last; 1421 + 1422 + transaction = i40e_nvmupd_get_transaction(cmd->config); 1423 + module = i40e_nvmupd_get_module(cmd->config); 1424 + last = (transaction & I40E_NVM_LCB); 1425 + preservation_flags = i40e_nvmupd_get_preservation_flags(cmd->config); 1426 + 1427 + memset(&cmd_details, 0, sizeof(cmd_details)); 1428 + cmd_details.wb_desc = &hw->nvm_wb_desc; 1429 + 1430 + status = i40e_aq_update_nvm(hw, module, cmd->offset, 1431 + (u16)cmd->data_size, bytes, last, 1432 + preservation_flags, &cmd_details); 1433 + if (status) { 1434 + i40e_debug(hw, I40E_DEBUG_NVM, 1435 + "%s mod 0x%x off 0x%x len 0x%x\n", 1436 + __func__, module, cmd->offset, cmd->data_size); 1437 + i40e_debug(hw, I40E_DEBUG_NVM, 1438 + "%s status %d aq %d\n", 1439 + __func__, status, hw->aq.asq_last_status); 1440 + *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1441 + } 1442 + 1443 + return status; 1444 + } 1445 + 1446 + /** 1447 + * i40e_nvmupd_nvm_read - Read NVM 1448 + * @hw: pointer to hardware structure 1449 + * @cmd: pointer to nvm update command buffer 1450 + * @bytes: pointer to the data buffer 1451 + * @perrno: pointer to return error code 1452 + * 1453 + * cmd structure contains identifiers and data buffer 1454 + **/ 1455 + static int i40e_nvmupd_nvm_read(struct i40e_hw *hw, 1456 + struct i40e_nvm_access *cmd, 1457 + u8 *bytes, int *perrno) 1458 + { 1459 + struct i40e_asq_cmd_details cmd_details; 1460 + u8 module, transaction; 1461 + int status; 1462 + bool last; 1463 + 1464 + transaction = i40e_nvmupd_get_transaction(cmd->config); 1465 + module = i40e_nvmupd_get_module(cmd->config); 1466 + last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA); 1467 + 1468 + memset(&cmd_details, 0, sizeof(cmd_details)); 1469 + cmd_details.wb_desc = &hw->nvm_wb_desc; 1470 + 1471 + status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size, 1472 + bytes, last, &cmd_details); 1473 + if (status) { 1474 + i40e_debug(hw, I40E_DEBUG_NVM, 1475 + "%s mod 0x%x off 0x%x len 0x%x\n", 1476 + __func__, module, cmd->offset, cmd->data_size); 1477 + i40e_debug(hw, I40E_DEBUG_NVM, 1478 + "%s status %d aq %d\n", 1479 + __func__, status, hw->aq.asq_last_status); 1480 + *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1481 + } 1482 + 1483 + return status; 862 1484 } 863 1485 864 1486 /** ··· 1171 1549 } 1172 1550 1173 1551 /** 1174 - * i40e_nvmupd_nvm_read - Read NVM 1552 + * i40e_nvmupd_state_init - Handle NVM update state Init 1175 1553 * @hw: pointer to hardware structure 1176 1554 * @cmd: pointer to nvm update command buffer 1177 1555 * @bytes: pointer to the data buffer 1178 1556 * @perrno: pointer to return error code 1179 1557 * 1180 - * cmd structure contains identifiers and data buffer 1558 + * Process legitimate commands of the Init state and conditionally set next 1559 + * state. Reject all other commands. 1181 1560 **/ 1182 - static int i40e_nvmupd_nvm_read(struct i40e_hw *hw, 1183 - struct i40e_nvm_access *cmd, 1184 - u8 *bytes, int *perrno) 1561 + static int i40e_nvmupd_state_init(struct i40e_hw *hw, 1562 + struct i40e_nvm_access *cmd, 1563 + u8 *bytes, int *perrno) 1185 1564 { 1186 - struct i40e_asq_cmd_details cmd_details; 1187 - u8 module, transaction; 1565 + enum i40e_nvmupd_cmd upd_cmd; 1566 + int status = 0; 1567 + 1568 + upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 1569 + 1570 + switch (upd_cmd) { 1571 + case I40E_NVMUPD_READ_SA: 1572 + status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 1573 + if (status) { 1574 + *perrno = i40e_aq_rc_to_posix(status, 1575 + hw->aq.asq_last_status); 1576 + } else { 1577 + status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 1578 + i40e_release_nvm(hw); 1579 + } 1580 + break; 1581 + 1582 + case I40E_NVMUPD_READ_SNT: 1583 + status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 1584 + if (status) { 1585 + *perrno = i40e_aq_rc_to_posix(status, 1586 + hw->aq.asq_last_status); 1587 + } else { 1588 + status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 1589 + if (status) 1590 + i40e_release_nvm(hw); 1591 + else 1592 + hw->nvmupd_state = I40E_NVMUPD_STATE_READING; 1593 + } 1594 + break; 1595 + 1596 + case I40E_NVMUPD_WRITE_ERA: 1597 + status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 1598 + if (status) { 1599 + *perrno = i40e_aq_rc_to_posix(status, 1600 + hw->aq.asq_last_status); 1601 + } else { 1602 + status = i40e_nvmupd_nvm_erase(hw, cmd, perrno); 1603 + if (status) { 1604 + i40e_release_nvm(hw); 1605 + } else { 1606 + hw->nvm_release_on_done = true; 1607 + hw->nvm_wait_opcode = i40e_aqc_opc_nvm_erase; 1608 + hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 1609 + } 1610 + } 1611 + break; 1612 + 1613 + case I40E_NVMUPD_WRITE_SA: 1614 + status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 1615 + if (status) { 1616 + *perrno = i40e_aq_rc_to_posix(status, 1617 + hw->aq.asq_last_status); 1618 + } else { 1619 + status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 1620 + if (status) { 1621 + i40e_release_nvm(hw); 1622 + } else { 1623 + hw->nvm_release_on_done = true; 1624 + hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 1625 + hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 1626 + } 1627 + } 1628 + break; 1629 + 1630 + case I40E_NVMUPD_WRITE_SNT: 1631 + status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 1632 + if (status) { 1633 + *perrno = i40e_aq_rc_to_posix(status, 1634 + hw->aq.asq_last_status); 1635 + } else { 1636 + status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 1637 + if (status) { 1638 + i40e_release_nvm(hw); 1639 + } else { 1640 + hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 1641 + hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; 1642 + } 1643 + } 1644 + break; 1645 + 1646 + case I40E_NVMUPD_CSUM_SA: 1647 + status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 1648 + if (status) { 1649 + *perrno = i40e_aq_rc_to_posix(status, 1650 + hw->aq.asq_last_status); 1651 + } else { 1652 + status = i40e_update_nvm_checksum(hw); 1653 + if (status) { 1654 + *perrno = hw->aq.asq_last_status ? 1655 + i40e_aq_rc_to_posix(status, 1656 + hw->aq.asq_last_status) : 1657 + -EIO; 1658 + i40e_release_nvm(hw); 1659 + } else { 1660 + hw->nvm_release_on_done = true; 1661 + hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 1662 + hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 1663 + } 1664 + } 1665 + break; 1666 + 1667 + case I40E_NVMUPD_EXEC_AQ: 1668 + status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno); 1669 + break; 1670 + 1671 + case I40E_NVMUPD_GET_AQ_RESULT: 1672 + status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno); 1673 + break; 1674 + 1675 + case I40E_NVMUPD_GET_AQ_EVENT: 1676 + status = i40e_nvmupd_get_aq_event(hw, cmd, bytes, perrno); 1677 + break; 1678 + 1679 + default: 1680 + i40e_debug(hw, I40E_DEBUG_NVM, 1681 + "NVMUPD: bad cmd %s in init state\n", 1682 + i40e_nvm_update_state_str[upd_cmd]); 1683 + status = -EIO; 1684 + *perrno = -ESRCH; 1685 + break; 1686 + } 1687 + return status; 1688 + } 1689 + 1690 + /** 1691 + * i40e_nvmupd_state_reading - Handle NVM update state Reading 1692 + * @hw: pointer to hardware structure 1693 + * @cmd: pointer to nvm update command buffer 1694 + * @bytes: pointer to the data buffer 1695 + * @perrno: pointer to return error code 1696 + * 1697 + * NVM ownership is already held. Process legitimate commands and set any 1698 + * change in state; reject all other commands. 1699 + **/ 1700 + static int i40e_nvmupd_state_reading(struct i40e_hw *hw, 1701 + struct i40e_nvm_access *cmd, 1702 + u8 *bytes, int *perrno) 1703 + { 1704 + enum i40e_nvmupd_cmd upd_cmd; 1705 + int status = 0; 1706 + 1707 + upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 1708 + 1709 + switch (upd_cmd) { 1710 + case I40E_NVMUPD_READ_SA: 1711 + case I40E_NVMUPD_READ_CON: 1712 + status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 1713 + break; 1714 + 1715 + case I40E_NVMUPD_READ_LCB: 1716 + status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 1717 + i40e_release_nvm(hw); 1718 + hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1719 + break; 1720 + 1721 + default: 1722 + i40e_debug(hw, I40E_DEBUG_NVM, 1723 + "NVMUPD: bad cmd %s in reading state.\n", 1724 + i40e_nvm_update_state_str[upd_cmd]); 1725 + status = -EOPNOTSUPP; 1726 + *perrno = -ESRCH; 1727 + break; 1728 + } 1729 + return status; 1730 + } 1731 + 1732 + /** 1733 + * i40e_nvmupd_state_writing - Handle NVM update state Writing 1734 + * @hw: pointer to hardware structure 1735 + * @cmd: pointer to nvm update command buffer 1736 + * @bytes: pointer to the data buffer 1737 + * @perrno: pointer to return error code 1738 + * 1739 + * NVM ownership is already held. Process legitimate commands and set any 1740 + * change in state; reject all other commands 1741 + **/ 1742 + static int i40e_nvmupd_state_writing(struct i40e_hw *hw, 1743 + struct i40e_nvm_access *cmd, 1744 + u8 *bytes, int *perrno) 1745 + { 1746 + enum i40e_nvmupd_cmd upd_cmd; 1747 + bool retry_attempt = false; 1748 + int status = 0; 1749 + 1750 + upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 1751 + 1752 + retry: 1753 + switch (upd_cmd) { 1754 + case I40E_NVMUPD_WRITE_CON: 1755 + status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 1756 + if (!status) { 1757 + hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 1758 + hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; 1759 + } 1760 + break; 1761 + 1762 + case I40E_NVMUPD_WRITE_LCB: 1763 + status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 1764 + if (status) { 1765 + *perrno = hw->aq.asq_last_status ? 1766 + i40e_aq_rc_to_posix(status, 1767 + hw->aq.asq_last_status) : 1768 + -EIO; 1769 + hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1770 + } else { 1771 + hw->nvm_release_on_done = true; 1772 + hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 1773 + hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 1774 + } 1775 + break; 1776 + 1777 + case I40E_NVMUPD_CSUM_CON: 1778 + /* Assumes the caller has acquired the nvm */ 1779 + status = i40e_update_nvm_checksum(hw); 1780 + if (status) { 1781 + *perrno = hw->aq.asq_last_status ? 1782 + i40e_aq_rc_to_posix(status, 1783 + hw->aq.asq_last_status) : 1784 + -EIO; 1785 + hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1786 + } else { 1787 + hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 1788 + hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; 1789 + } 1790 + break; 1791 + 1792 + case I40E_NVMUPD_CSUM_LCB: 1793 + /* Assumes the caller has acquired the nvm */ 1794 + status = i40e_update_nvm_checksum(hw); 1795 + if (status) { 1796 + *perrno = hw->aq.asq_last_status ? 1797 + i40e_aq_rc_to_posix(status, 1798 + hw->aq.asq_last_status) : 1799 + -EIO; 1800 + hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1801 + } else { 1802 + hw->nvm_release_on_done = true; 1803 + hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 1804 + hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 1805 + } 1806 + break; 1807 + 1808 + default: 1809 + i40e_debug(hw, I40E_DEBUG_NVM, 1810 + "NVMUPD: bad cmd %s in writing state.\n", 1811 + i40e_nvm_update_state_str[upd_cmd]); 1812 + status = -EOPNOTSUPP; 1813 + *perrno = -ESRCH; 1814 + break; 1815 + } 1816 + 1817 + /* In some circumstances, a multi-write transaction takes longer 1818 + * than the default 3 minute timeout on the write semaphore. If 1819 + * the write failed with an EBUSY status, this is likely the problem, 1820 + * so here we try to reacquire the semaphore then retry the write. 1821 + * We only do one retry, then give up. 1822 + */ 1823 + if (status && hw->aq.asq_last_status == I40E_AQ_RC_EBUSY && 1824 + !retry_attempt) { 1825 + u32 old_asq_status = hw->aq.asq_last_status; 1826 + int old_status = status; 1827 + u32 gtime; 1828 + 1829 + gtime = rd32(hw, I40E_GLVFGEN_TIMER); 1830 + if (gtime >= hw->nvm.hw_semaphore_timeout) { 1831 + i40e_debug(hw, I40E_DEBUG_ALL, 1832 + "NVMUPD: write semaphore expired (%d >= %lld), retrying\n", 1833 + gtime, hw->nvm.hw_semaphore_timeout); 1834 + i40e_release_nvm(hw); 1835 + status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 1836 + if (status) { 1837 + i40e_debug(hw, I40E_DEBUG_ALL, 1838 + "NVMUPD: write semaphore reacquire failed aq_err = %d\n", 1839 + hw->aq.asq_last_status); 1840 + status = old_status; 1841 + hw->aq.asq_last_status = old_asq_status; 1842 + } else { 1843 + retry_attempt = true; 1844 + goto retry; 1845 + } 1846 + } 1847 + } 1848 + 1849 + return status; 1850 + } 1851 + 1852 + /** 1853 + * i40e_nvmupd_command - Process an NVM update command 1854 + * @hw: pointer to hardware structure 1855 + * @cmd: pointer to nvm update command 1856 + * @bytes: pointer to the data buffer 1857 + * @perrno: pointer to return error code 1858 + * 1859 + * Dispatches command depending on what update state is current 1860 + **/ 1861 + int i40e_nvmupd_command(struct i40e_hw *hw, 1862 + struct i40e_nvm_access *cmd, 1863 + u8 *bytes, int *perrno) 1864 + { 1865 + enum i40e_nvmupd_cmd upd_cmd; 1188 1866 int status; 1189 - bool last; 1190 1867 1191 - transaction = i40e_nvmupd_get_transaction(cmd->config); 1192 - module = i40e_nvmupd_get_module(cmd->config); 1193 - last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA); 1868 + /* assume success */ 1869 + *perrno = 0; 1194 1870 1195 - memset(&cmd_details, 0, sizeof(cmd_details)); 1196 - cmd_details.wb_desc = &hw->nvm_wb_desc; 1871 + /* early check for status command and debug msgs */ 1872 + upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 1197 1873 1198 - status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size, 1199 - bytes, last, &cmd_details); 1200 - if (status) { 1874 + i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d opc 0x%04x cmd 0x%08x config 0x%08x offset 0x%08x data_size 0x%08x\n", 1875 + i40e_nvm_update_state_str[upd_cmd], 1876 + hw->nvmupd_state, 1877 + hw->nvm_release_on_done, hw->nvm_wait_opcode, 1878 + cmd->command, cmd->config, cmd->offset, cmd->data_size); 1879 + 1880 + if (upd_cmd == I40E_NVMUPD_INVALID) { 1881 + *perrno = -EFAULT; 1201 1882 i40e_debug(hw, I40E_DEBUG_NVM, 1202 - "i40e_nvmupd_nvm_read mod 0x%x off 0x%x len 0x%x\n", 1203 - module, cmd->offset, cmd->data_size); 1204 - i40e_debug(hw, I40E_DEBUG_NVM, 1205 - "i40e_nvmupd_nvm_read status %d aq %d\n", 1206 - status, hw->aq.asq_last_status); 1207 - *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1883 + "i40e_nvmupd_validate_command returns %d errno %d\n", 1884 + upd_cmd, *perrno); 1208 1885 } 1209 1886 1887 + /* a status request returns immediately rather than 1888 + * going into the state machine 1889 + */ 1890 + if (upd_cmd == I40E_NVMUPD_STATUS) { 1891 + if (!cmd->data_size) { 1892 + *perrno = -EFAULT; 1893 + return -EINVAL; 1894 + } 1895 + 1896 + bytes[0] = hw->nvmupd_state; 1897 + 1898 + if (cmd->data_size >= 4) { 1899 + bytes[1] = 0; 1900 + *((u16 *)&bytes[2]) = hw->nvm_wait_opcode; 1901 + } 1902 + 1903 + /* Clear error status on read */ 1904 + if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) 1905 + hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1906 + 1907 + return 0; 1908 + } 1909 + 1910 + /* Clear status even it is not read and log */ 1911 + if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) { 1912 + i40e_debug(hw, I40E_DEBUG_NVM, 1913 + "Clearing I40E_NVMUPD_STATE_ERROR state without reading\n"); 1914 + hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1915 + } 1916 + 1917 + /* Acquire lock to prevent race condition where adminq_task 1918 + * can execute after i40e_nvmupd_nvm_read/write but before state 1919 + * variables (nvm_wait_opcode, nvm_release_on_done) are updated. 1920 + * 1921 + * During NVMUpdate, it is observed that lock could be held for 1922 + * ~5ms for most commands. However lock is held for ~60ms for 1923 + * NVMUPD_CSUM_LCB command. 1924 + */ 1925 + mutex_lock(&hw->aq.arq_mutex); 1926 + switch (hw->nvmupd_state) { 1927 + case I40E_NVMUPD_STATE_INIT: 1928 + status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno); 1929 + break; 1930 + 1931 + case I40E_NVMUPD_STATE_READING: 1932 + status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno); 1933 + break; 1934 + 1935 + case I40E_NVMUPD_STATE_WRITING: 1936 + status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno); 1937 + break; 1938 + 1939 + case I40E_NVMUPD_STATE_INIT_WAIT: 1940 + case I40E_NVMUPD_STATE_WRITE_WAIT: 1941 + /* if we need to stop waiting for an event, clear 1942 + * the wait info and return before doing anything else 1943 + */ 1944 + if (cmd->offset == 0xffff) { 1945 + i40e_nvmupd_clear_wait_state(hw); 1946 + status = 0; 1947 + break; 1948 + } 1949 + 1950 + status = -EBUSY; 1951 + *perrno = -EBUSY; 1952 + break; 1953 + 1954 + default: 1955 + /* invalid state, should never happen */ 1956 + i40e_debug(hw, I40E_DEBUG_NVM, 1957 + "NVMUPD: no such state %d\n", hw->nvmupd_state); 1958 + status = -EOPNOTSUPP; 1959 + *perrno = -ESRCH; 1960 + break; 1961 + } 1962 + 1963 + mutex_unlock(&hw->aq.arq_mutex); 1210 1964 return status; 1211 1965 } 1212 1966 1213 1967 /** 1214 - * i40e_nvmupd_nvm_erase - Erase an NVM module 1215 - * @hw: pointer to hardware structure 1216 - * @cmd: pointer to nvm update command buffer 1217 - * @perrno: pointer to return error code 1218 - * 1219 - * module, offset, data_size and data are in cmd structure 1968 + * i40e_nvmupd_clear_wait_state - clear wait state on hw 1969 + * @hw: pointer to the hardware structure 1220 1970 **/ 1221 - static int i40e_nvmupd_nvm_erase(struct i40e_hw *hw, 1222 - struct i40e_nvm_access *cmd, 1223 - int *perrno) 1971 + void i40e_nvmupd_clear_wait_state(struct i40e_hw *hw) 1224 1972 { 1225 - struct i40e_asq_cmd_details cmd_details; 1226 - u8 module, transaction; 1227 - int status = 0; 1228 - bool last; 1973 + i40e_debug(hw, I40E_DEBUG_NVM, 1974 + "NVMUPD: clearing wait on opcode 0x%04x\n", 1975 + hw->nvm_wait_opcode); 1229 1976 1230 - transaction = i40e_nvmupd_get_transaction(cmd->config); 1231 - module = i40e_nvmupd_get_module(cmd->config); 1232 - last = (transaction & I40E_NVM_LCB); 1977 + if (hw->nvm_release_on_done) { 1978 + i40e_release_nvm(hw); 1979 + hw->nvm_release_on_done = false; 1980 + } 1981 + hw->nvm_wait_opcode = 0; 1233 1982 1234 - memset(&cmd_details, 0, sizeof(cmd_details)); 1235 - cmd_details.wb_desc = &hw->nvm_wb_desc; 1236 - 1237 - status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size, 1238 - last, &cmd_details); 1239 - if (status) { 1240 - i40e_debug(hw, I40E_DEBUG_NVM, 1241 - "i40e_nvmupd_nvm_erase mod 0x%x off 0x%x len 0x%x\n", 1242 - module, cmd->offset, cmd->data_size); 1243 - i40e_debug(hw, I40E_DEBUG_NVM, 1244 - "i40e_nvmupd_nvm_erase status %d aq %d\n", 1245 - status, hw->aq.asq_last_status); 1246 - *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1983 + if (hw->aq.arq_last_status) { 1984 + hw->nvmupd_state = I40E_NVMUPD_STATE_ERROR; 1985 + return; 1247 1986 } 1248 1987 1249 - return status; 1988 + switch (hw->nvmupd_state) { 1989 + case I40E_NVMUPD_STATE_INIT_WAIT: 1990 + hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1991 + break; 1992 + 1993 + case I40E_NVMUPD_STATE_WRITE_WAIT: 1994 + hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING; 1995 + break; 1996 + 1997 + default: 1998 + break; 1999 + } 1250 2000 } 1251 2001 1252 2002 /** 1253 - * i40e_nvmupd_nvm_write - Write NVM 1254 - * @hw: pointer to hardware structure 1255 - * @cmd: pointer to nvm update command buffer 1256 - * @bytes: pointer to the data buffer 1257 - * @perrno: pointer to return error code 1258 - * 1259 - * module, offset, data_size and data are in cmd structure 2003 + * i40e_nvmupd_check_wait_event - handle NVM update operation events 2004 + * @hw: pointer to the hardware structure 2005 + * @opcode: the event that just happened 2006 + * @desc: AdminQ descriptor 1260 2007 **/ 1261 - static int i40e_nvmupd_nvm_write(struct i40e_hw *hw, 1262 - struct i40e_nvm_access *cmd, 1263 - u8 *bytes, int *perrno) 2008 + void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode, 2009 + struct i40e_aq_desc *desc) 1264 2010 { 1265 - struct i40e_asq_cmd_details cmd_details; 1266 - u8 module, transaction; 1267 - u8 preservation_flags; 1268 - int status = 0; 1269 - bool last; 2011 + u32 aq_desc_len = sizeof(struct i40e_aq_desc); 1270 2012 1271 - transaction = i40e_nvmupd_get_transaction(cmd->config); 1272 - module = i40e_nvmupd_get_module(cmd->config); 1273 - last = (transaction & I40E_NVM_LCB); 1274 - preservation_flags = i40e_nvmupd_get_preservation_flags(cmd->config); 1275 - 1276 - memset(&cmd_details, 0, sizeof(cmd_details)); 1277 - cmd_details.wb_desc = &hw->nvm_wb_desc; 1278 - 1279 - status = i40e_aq_update_nvm(hw, module, cmd->offset, 1280 - (u16)cmd->data_size, bytes, last, 1281 - preservation_flags, &cmd_details); 1282 - if (status) { 1283 - i40e_debug(hw, I40E_DEBUG_NVM, 1284 - "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n", 1285 - module, cmd->offset, cmd->data_size); 1286 - i40e_debug(hw, I40E_DEBUG_NVM, 1287 - "i40e_nvmupd_nvm_write status %d aq %d\n", 1288 - status, hw->aq.asq_last_status); 1289 - *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 2013 + if (opcode == hw->nvm_wait_opcode) { 2014 + memcpy(&hw->nvm_aq_event_desc, desc, aq_desc_len); 2015 + i40e_nvmupd_clear_wait_state(hw); 1290 2016 } 1291 - 1292 - return status; 1293 2017 }
+4 -4
drivers/net/ethernet/intel/iavf/iavf_main.c
··· 5023 5023 * 5024 5024 * Called when the system (VM) is entering sleep/suspend. 5025 5025 **/ 5026 - static int __maybe_unused iavf_suspend(struct device *dev_d) 5026 + static int iavf_suspend(struct device *dev_d) 5027 5027 { 5028 5028 struct net_device *netdev = dev_get_drvdata(dev_d); 5029 5029 struct iavf_adapter *adapter = netdev_priv(netdev); ··· 5051 5051 * 5052 5052 * Called when the system (VM) is resumed from sleep/suspend. 5053 5053 **/ 5054 - static int __maybe_unused iavf_resume(struct device *dev_d) 5054 + static int iavf_resume(struct device *dev_d) 5055 5055 { 5056 5056 struct pci_dev *pdev = to_pci_dev(dev_d); 5057 5057 struct iavf_adapter *adapter; ··· 5238 5238 pci_set_power_state(pdev, PCI_D3hot); 5239 5239 } 5240 5240 5241 - static SIMPLE_DEV_PM_OPS(iavf_pm_ops, iavf_suspend, iavf_resume); 5241 + static DEFINE_SIMPLE_DEV_PM_OPS(iavf_pm_ops, iavf_suspend, iavf_resume); 5242 5242 5243 5243 static struct pci_driver iavf_driver = { 5244 5244 .name = iavf_driver_name, 5245 5245 .id_table = iavf_pci_tbl, 5246 5246 .probe = iavf_probe, 5247 5247 .remove = iavf_remove, 5248 - .driver.pm = &iavf_pm_ops, 5248 + .driver.pm = pm_sleep_ptr(&iavf_pm_ops), 5249 5249 .shutdown = iavf_shutdown, 5250 5250 }; 5251 5251
+4 -8
drivers/net/ethernet/intel/ice/ice_main.c
··· 5321 5321 } 5322 5322 } 5323 5323 5324 - #ifdef CONFIG_PM 5325 5324 /** 5326 5325 * ice_prepare_for_shutdown - prep for PCI shutdown 5327 5326 * @pf: board private structure ··· 5409 5410 * Power Management callback to quiesce the device and prepare 5410 5411 * for D3 transition. 5411 5412 */ 5412 - static int __maybe_unused ice_suspend(struct device *dev) 5413 + static int ice_suspend(struct device *dev) 5413 5414 { 5414 5415 struct pci_dev *pdev = to_pci_dev(dev); 5415 5416 struct ice_pf *pf; ··· 5476 5477 * ice_resume - PM callback for waking up from D3 5477 5478 * @dev: generic device information structure 5478 5479 */ 5479 - static int __maybe_unused ice_resume(struct device *dev) 5480 + static int ice_resume(struct device *dev) 5480 5481 { 5481 5482 struct pci_dev *pdev = to_pci_dev(dev); 5482 5483 enum ice_reset_req reset_type; ··· 5527 5528 5528 5529 return 0; 5529 5530 } 5530 - #endif /* CONFIG_PM */ 5531 5531 5532 5532 /** 5533 5533 * ice_pci_err_detected - warning that PCI error has been detected ··· 5700 5702 }; 5701 5703 MODULE_DEVICE_TABLE(pci, ice_pci_tbl); 5702 5704 5703 - static __maybe_unused SIMPLE_DEV_PM_OPS(ice_pm_ops, ice_suspend, ice_resume); 5705 + static DEFINE_SIMPLE_DEV_PM_OPS(ice_pm_ops, ice_suspend, ice_resume); 5704 5706 5705 5707 static const struct pci_error_handlers ice_pci_err_handler = { 5706 5708 .error_detected = ice_pci_err_detected, ··· 5715 5717 .id_table = ice_pci_tbl, 5716 5718 .probe = ice_probe, 5717 5719 .remove = ice_remove, 5718 - #ifdef CONFIG_PM 5719 - .driver.pm = &ice_pm_ops, 5720 - #endif /* CONFIG_PM */ 5720 + .driver.pm = pm_sleep_ptr(&ice_pm_ops), 5721 5721 .shutdown = ice_shutdown, 5722 5722 .sriov_configure = ice_sriov_configure, 5723 5723 .sriov_get_vf_total_msix = ice_sriov_get_vf_total_msix,
+24 -35
drivers/net/ethernet/intel/igb/igb_main.c
··· 106 106 static void igb_free_all_tx_resources(struct igb_adapter *); 107 107 static void igb_free_all_rx_resources(struct igb_adapter *); 108 108 static void igb_setup_mrqc(struct igb_adapter *); 109 - static int igb_probe(struct pci_dev *, const struct pci_device_id *); 110 - static void igb_remove(struct pci_dev *pdev); 111 109 static void igb_init_queue_configuration(struct igb_adapter *adapter); 112 110 static int igb_sw_init(struct igb_adapter *); 113 111 int igb_open(struct net_device *); ··· 176 178 static int igb_disable_sriov(struct pci_dev *dev, bool reinit); 177 179 #endif 178 180 179 - static int igb_suspend(struct device *); 180 - static int igb_resume(struct device *); 181 - static int igb_runtime_suspend(struct device *dev); 182 - static int igb_runtime_resume(struct device *dev); 183 - static int igb_runtime_idle(struct device *dev); 184 - #ifdef CONFIG_PM 185 - static const struct dev_pm_ops igb_pm_ops = { 186 - SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 187 - SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 188 - igb_runtime_idle) 189 - }; 190 - #endif 191 - static void igb_shutdown(struct pci_dev *); 192 - static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 193 181 #ifdef CONFIG_IGB_DCA 194 182 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 195 183 static struct notifier_block dca_notifier = { ··· 202 218 }; 203 219 204 220 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 205 - 206 - static struct pci_driver igb_driver = { 207 - .name = igb_driver_name, 208 - .id_table = igb_pci_tbl, 209 - .probe = igb_probe, 210 - .remove = igb_remove, 211 - #ifdef CONFIG_PM 212 - .driver.pm = &igb_pm_ops, 213 - #endif 214 - .shutdown = igb_shutdown, 215 - .sriov_configure = igb_pci_sriov_configure, 216 - .err_handler = &igb_err_handler 217 - }; 218 221 219 222 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 220 223 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); ··· 617 646 struct igb_adapter *adapter = hw->back; 618 647 return adapter->netdev; 619 648 } 649 + 650 + static struct pci_driver igb_driver; 620 651 621 652 /** 622 653 * igb_init_module - Driver Registration Routine ··· 9426 9453 netif_rx(skb); 9427 9454 } 9428 9455 9429 - static int __maybe_unused igb_suspend(struct device *dev) 9456 + static int igb_suspend(struct device *dev) 9430 9457 { 9431 9458 return __igb_shutdown(to_pci_dev(dev), NULL, 0); 9432 9459 } 9433 9460 9434 - static int __maybe_unused __igb_resume(struct device *dev, bool rpm) 9461 + static int __igb_resume(struct device *dev, bool rpm) 9435 9462 { 9436 9463 struct pci_dev *pdev = to_pci_dev(dev); 9437 9464 struct net_device *netdev = pci_get_drvdata(pdev); ··· 9487 9514 return err; 9488 9515 } 9489 9516 9490 - static int __maybe_unused igb_resume(struct device *dev) 9517 + static int igb_resume(struct device *dev) 9491 9518 { 9492 9519 return __igb_resume(dev, false); 9493 9520 } 9494 9521 9495 - static int __maybe_unused igb_runtime_idle(struct device *dev) 9522 + static int igb_runtime_idle(struct device *dev) 9496 9523 { 9497 9524 struct net_device *netdev = dev_get_drvdata(dev); 9498 9525 struct igb_adapter *adapter = netdev_priv(netdev); ··· 9503 9530 return -EBUSY; 9504 9531 } 9505 9532 9506 - static int __maybe_unused igb_runtime_suspend(struct device *dev) 9533 + static int igb_runtime_suspend(struct device *dev) 9507 9534 { 9508 9535 return __igb_shutdown(to_pci_dev(dev), NULL, 1); 9509 9536 } 9510 9537 9511 - static int __maybe_unused igb_runtime_resume(struct device *dev) 9538 + static int igb_runtime_resume(struct device *dev) 9512 9539 { 9513 9540 return __igb_resume(dev, true); 9514 9541 } ··· 10130 10157 10131 10158 spin_unlock(&adapter->nfc_lock); 10132 10159 } 10160 + 10161 + static _DEFINE_DEV_PM_OPS(igb_pm_ops, igb_suspend, igb_resume, 10162 + igb_runtime_suspend, igb_runtime_resume, 10163 + igb_runtime_idle); 10164 + 10165 + static struct pci_driver igb_driver = { 10166 + .name = igb_driver_name, 10167 + .id_table = igb_pci_tbl, 10168 + .probe = igb_probe, 10169 + .remove = igb_remove, 10170 + .driver.pm = pm_ptr(&igb_pm_ops), 10171 + .shutdown = igb_shutdown, 10172 + .sriov_configure = igb_pci_sriov_configure, 10173 + .err_handler = &igb_err_handler 10174 + }; 10175 + 10133 10176 /* igb_main.c */
+3 -3
drivers/net/ethernet/intel/igbvf/netdev.c
··· 2470 2470 return 0; 2471 2471 } 2472 2472 2473 - static int __maybe_unused igbvf_resume(struct device *dev_d) 2473 + static int igbvf_resume(struct device *dev_d) 2474 2474 { 2475 2475 struct pci_dev *pdev = to_pci_dev(dev_d); 2476 2476 struct net_device *netdev = pci_get_drvdata(pdev); ··· 2957 2957 }; 2958 2958 MODULE_DEVICE_TABLE(pci, igbvf_pci_tbl); 2959 2959 2960 - static SIMPLE_DEV_PM_OPS(igbvf_pm_ops, igbvf_suspend, igbvf_resume); 2960 + static DEFINE_SIMPLE_DEV_PM_OPS(igbvf_pm_ops, igbvf_suspend, igbvf_resume); 2961 2961 2962 2962 /* PCI Device API Driver */ 2963 2963 static struct pci_driver igbvf_driver = { ··· 2965 2965 .id_table = igbvf_pci_tbl, 2966 2966 .probe = igbvf_probe, 2967 2967 .remove = igbvf_remove, 2968 - .driver.pm = &igbvf_pm_ops, 2968 + .driver.pm = pm_sleep_ptr(&igbvf_pm_ops), 2969 2969 .shutdown = igbvf_shutdown, 2970 2970 .err_handler = &igbvf_err_handler 2971 2971 };
+23 -33
drivers/net/ethernet/intel/igc/igc_main.c
··· 5929 5929 if (err) 5930 5930 goto err_req_irq; 5931 5931 5932 - /* Notify the stack of the actual queue counts. */ 5933 - err = netif_set_real_num_tx_queues(netdev, adapter->num_tx_queues); 5934 - if (err) 5935 - goto err_set_queues; 5936 - 5937 - err = netif_set_real_num_rx_queues(netdev, adapter->num_rx_queues); 5938 - if (err) 5939 - goto err_set_queues; 5940 - 5941 5932 clear_bit(__IGC_DOWN, &adapter->state); 5942 5933 5943 5934 for (i = 0; i < adapter->num_q_vectors; i++) ··· 5949 5958 5950 5959 return IGC_SUCCESS; 5951 5960 5952 - err_set_queues: 5953 - igc_free_irq(adapter); 5954 5961 err_req_irq: 5955 5962 igc_release_hw_control(adapter); 5956 5963 igc_power_down_phy_copper_base(&adapter->hw); ··· 5965 5976 5966 5977 int igc_open(struct net_device *netdev) 5967 5978 { 5979 + struct igc_adapter *adapter = netdev_priv(netdev); 5980 + int err; 5981 + 5982 + /* Notify the stack of the actual queue counts. */ 5983 + err = netif_set_real_num_queues(netdev, adapter->num_tx_queues, 5984 + adapter->num_rx_queues); 5985 + if (err) { 5986 + netdev_err(netdev, "error setting real queue count\n"); 5987 + return err; 5988 + } 5989 + 5968 5990 return __igc_open(netdev, false); 5969 5991 } 5970 5992 ··· 7104 7104 return 0; 7105 7105 } 7106 7106 7107 - #ifdef CONFIG_PM 7108 - static int __maybe_unused igc_runtime_suspend(struct device *dev) 7107 + static int igc_runtime_suspend(struct device *dev) 7109 7108 { 7110 7109 return __igc_shutdown(to_pci_dev(dev), NULL, 1); 7111 7110 } ··· 7139 7140 netif_rx(skb); 7140 7141 } 7141 7142 7142 - static int __maybe_unused igc_resume(struct device *dev) 7143 + static int igc_resume(struct device *dev) 7143 7144 { 7144 7145 struct pci_dev *pdev = to_pci_dev(dev); 7145 7146 struct net_device *netdev = pci_get_drvdata(pdev); ··· 7181 7182 7182 7183 wr32(IGC_WUS, ~0); 7183 7184 7184 - rtnl_lock(); 7185 - if (!err && netif_running(netdev)) 7185 + if (netif_running(netdev)) { 7186 7186 err = __igc_open(netdev, true); 7187 - 7188 - if (!err) 7189 - netif_device_attach(netdev); 7190 - rtnl_unlock(); 7187 + if (!err) 7188 + netif_device_attach(netdev); 7189 + } 7191 7190 7192 7191 return err; 7193 7192 } 7194 7193 7195 - static int __maybe_unused igc_runtime_resume(struct device *dev) 7194 + static int igc_runtime_resume(struct device *dev) 7196 7195 { 7197 7196 return igc_resume(dev); 7198 7197 } 7199 7198 7200 - static int __maybe_unused igc_suspend(struct device *dev) 7199 + static int igc_suspend(struct device *dev) 7201 7200 { 7202 7201 return __igc_shutdown(to_pci_dev(dev), NULL, 0); 7203 7202 } ··· 7210 7213 7211 7214 return -EBUSY; 7212 7215 } 7213 - #endif /* CONFIG_PM */ 7214 7216 7215 7217 static void igc_shutdown(struct pci_dev *pdev) 7216 7218 { ··· 7324 7328 .resume = igc_io_resume, 7325 7329 }; 7326 7330 7327 - #ifdef CONFIG_PM 7328 - static const struct dev_pm_ops igc_pm_ops = { 7329 - SET_SYSTEM_SLEEP_PM_OPS(igc_suspend, igc_resume) 7330 - SET_RUNTIME_PM_OPS(igc_runtime_suspend, igc_runtime_resume, 7331 - igc_runtime_idle) 7332 - }; 7333 - #endif 7331 + static _DEFINE_DEV_PM_OPS(igc_pm_ops, igc_suspend, igc_resume, 7332 + igc_runtime_suspend, igc_runtime_resume, 7333 + igc_runtime_idle); 7334 7334 7335 7335 static struct pci_driver igc_driver = { 7336 7336 .name = igc_driver_name, 7337 7337 .id_table = igc_pci_tbl, 7338 7338 .probe = igc_probe, 7339 7339 .remove = igc_remove, 7340 - #ifdef CONFIG_PM 7341 - .driver.pm = &igc_pm_ops, 7342 - #endif 7340 + .driver.pm = pm_ptr(&igc_pm_ops), 7343 7341 .shutdown = igc_shutdown, 7344 7342 .err_handler = &igc_err_handler, 7345 7343 };
+4 -4
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
··· 6974 6974 return 0; 6975 6975 } 6976 6976 6977 - static int __maybe_unused ixgbe_resume(struct device *dev_d) 6977 + static int ixgbe_resume(struct device *dev_d) 6978 6978 { 6979 6979 struct pci_dev *pdev = to_pci_dev(dev_d); 6980 6980 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); ··· 7082 7082 return 0; 7083 7083 } 7084 7084 7085 - static int __maybe_unused ixgbe_suspend(struct device *dev_d) 7085 + static int ixgbe_suspend(struct device *dev_d) 7086 7086 { 7087 7087 struct pci_dev *pdev = to_pci_dev(dev_d); 7088 7088 int retval; ··· 11583 11583 .resume = ixgbe_io_resume, 11584 11584 }; 11585 11585 11586 - static SIMPLE_DEV_PM_OPS(ixgbe_pm_ops, ixgbe_suspend, ixgbe_resume); 11586 + static DEFINE_SIMPLE_DEV_PM_OPS(ixgbe_pm_ops, ixgbe_suspend, ixgbe_resume); 11587 11587 11588 11588 static struct pci_driver ixgbe_driver = { 11589 11589 .name = ixgbe_driver_name, 11590 11590 .id_table = ixgbe_pci_tbl, 11591 11591 .probe = ixgbe_probe, 11592 11592 .remove = ixgbe_remove, 11593 - .driver.pm = &ixgbe_pm_ops, 11593 + .driver.pm = pm_sleep_ptr(&ixgbe_pm_ops), 11594 11594 .shutdown = ixgbe_shutdown, 11595 11595 .sriov_configure = ixgbe_pci_sriov_configure, 11596 11596 .err_handler = &ixgbe_err_handler
+4 -4
drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c
··· 4300 4300 return 0; 4301 4301 } 4302 4302 4303 - static int __maybe_unused ixgbevf_suspend(struct device *dev_d) 4303 + static int ixgbevf_suspend(struct device *dev_d) 4304 4304 { 4305 4305 struct net_device *netdev = dev_get_drvdata(dev_d); 4306 4306 struct ixgbevf_adapter *adapter = netdev_priv(netdev); ··· 4317 4317 return 0; 4318 4318 } 4319 4319 4320 - static int __maybe_unused ixgbevf_resume(struct device *dev_d) 4320 + static int ixgbevf_resume(struct device *dev_d) 4321 4321 { 4322 4322 struct pci_dev *pdev = to_pci_dev(dev_d); 4323 4323 struct net_device *netdev = pci_get_drvdata(pdev); ··· 4854 4854 .resume = ixgbevf_io_resume, 4855 4855 }; 4856 4856 4857 - static SIMPLE_DEV_PM_OPS(ixgbevf_pm_ops, ixgbevf_suspend, ixgbevf_resume); 4857 + static DEFINE_SIMPLE_DEV_PM_OPS(ixgbevf_pm_ops, ixgbevf_suspend, ixgbevf_resume); 4858 4858 4859 4859 static struct pci_driver ixgbevf_driver = { 4860 4860 .name = ixgbevf_driver_name, ··· 4863 4863 .remove = ixgbevf_remove, 4864 4864 4865 4865 /* Power Management Hooks */ 4866 - .driver.pm = &ixgbevf_pm_ops, 4866 + .driver.pm = pm_sleep_ptr(&ixgbevf_pm_ops), 4867 4867 4868 4868 .shutdown = ixgbevf_shutdown, 4869 4869 .err_handler = &ixgbevf_err_handler