Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
misc: microchip: pci1xxxx: Add support to read and write into PCI1XXXX OTP via NVMEM sysfs
Microchip's pci1xxxx is an unmanaged PCIe3.1a switch for consumer,
industrial, and automotive applications. This switch integrates OTP
and EEPROM to enable customization of the part in the field. This
patch adds support to read and write into PCI1XXXX OTP via NVMEM sysfs.
Signed-off-by: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>
Co-developed-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
Signed-off-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
Co-developed-by: Vaibhaav Ram T.L <vaibhaavram.tl@microchip.com>
Signed-off-by: Vaibhaav Ram T.L <vaibhaavram.tl@microchip.com>
Link: https://lore.kernel.org/r/20230620143520.858-2-vaibhaavram.tl@microchip.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Kumaravel Thiagarajan
and committed by
Greg Kroah-Hartman
09690015
31ed379b
+307
-1
+2
MAINTAINERS
+2
MAINTAINERS
···
13931
13931
F: include/dt-bindings/nvmem/microchip,sama7g5-otpc.h
13932
13932
13933
13933
MICROCHIP PCI1XXXX GP DRIVER
13934
+
M: Vaibhaav Ram T.L <vaibhaavram.tl@microchip.com>
13934
13935
M: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>
13935
13936
L: linux-gpio@vger.kernel.org
13936
13937
S: Supported
13937
13938
F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gp.c
13938
13939
F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gp.h
13939
13940
F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c
13941
+
F: drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
13940
13942
13941
13943
MICROCHIP PCI1XXXX I2C DRIVER
13942
13944
M: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
+1
drivers/misc/mchp_pci1xxxx/Kconfig
+1
drivers/misc/mchp_pci1xxxx/Kconfig
+1
-1
drivers/misc/mchp_pci1xxxx/Makefile
+1
-1
drivers/misc/mchp_pci1xxxx/Makefile
+303
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
+303
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
// Copyright (C) 2022-2023 Microchip Technology Inc.
3
+
// PCI1xxxx OTP/EEPROM driver
4
+
5
+
#include <linux/auxiliary_bus.h>
6
+
#include <linux/device.h>
7
+
#include <linux/iopoll.h>
8
+
#include <linux/module.h>
9
+
#include <linux/nvmem-provider.h>
10
+
11
+
#include "mchp_pci1xxxx_gp.h"
12
+
13
+
#define AUX_DRIVER_NAME "PCI1xxxxOTPE2P"
14
+
#define OTP_NAME "pci1xxxx_otp"
15
+
16
+
#define PERI_PF3_SYSTEM_REG_ADDR_BASE 0x2000
17
+
#define PERI_PF3_SYSTEM_REG_LENGTH 0x4000
18
+
19
+
#define OTP_SIZE_BYTES 8192
20
+
21
+
#define CONFIG_REG_ADDR_BASE 0
22
+
#define OTP_REG_ADDR_BASE 0x1000
23
+
24
+
#define MMAP_OTP_OFFSET(x) (OTP_REG_ADDR_BASE + (x))
25
+
#define MMAP_CFG_OFFSET(x) (CONFIG_REG_ADDR_BASE + (x))
26
+
27
+
#define STATUS_READ_DELAY_US 1
28
+
#define STATUS_READ_TIMEOUT_US 20000
29
+
30
+
#define OTP_ADDR_HIGH_OFFSET 0x04
31
+
#define OTP_ADDR_LOW_OFFSET 0x08
32
+
#define OTP_PRGM_DATA_OFFSET 0x10
33
+
#define OTP_PRGM_MODE_OFFSET 0x14
34
+
#define OTP_RD_DATA_OFFSET 0x18
35
+
#define OTP_FUNC_CMD_OFFSET 0x20
36
+
#define OTP_CMD_GO_OFFSET 0x28
37
+
#define OTP_PASS_FAIL_OFFSET 0x2C
38
+
#define OTP_STATUS_OFFSET 0x30
39
+
40
+
#define OTP_FUNC_RD_BIT BIT(0)
41
+
#define OTP_FUNC_PGM_BIT BIT(1)
42
+
#define OTP_CMD_GO_BIT BIT(0)
43
+
#define OTP_STATUS_BUSY_BIT BIT(0)
44
+
#define OTP_PGM_MODE_BYTE_BIT BIT(0)
45
+
#define OTP_FAIL_BIT BIT(0)
46
+
47
+
#define OTP_PWR_DN_BIT BIT(0)
48
+
#define OTP_PWR_DN_OFFSET 0x00
49
+
50
+
#define CFG_SYS_LOCK_OFFSET 0xA0
51
+
#define CFG_SYS_LOCK_PF3 BIT(5)
52
+
53
+
#define BYTE_LOW (GENMASK(7, 0))
54
+
#define BYTE_HIGH (GENMASK(12, 8))
55
+
56
+
struct pci1xxxx_otp_eeprom_device {
57
+
struct auxiliary_device *pdev;
58
+
void __iomem *reg_base;
59
+
struct nvmem_config nvmem_config_otp;
60
+
struct nvmem_device *nvmem_otp;
61
+
};
62
+
63
+
static int set_sys_lock(struct pci1xxxx_otp_eeprom_device *priv)
64
+
{
65
+
void __iomem *sys_lock = priv->reg_base +
66
+
MMAP_CFG_OFFSET(CFG_SYS_LOCK_OFFSET);
67
+
u8 data;
68
+
69
+
writel(CFG_SYS_LOCK_PF3, sys_lock);
70
+
data = readl(sys_lock);
71
+
if (data != CFG_SYS_LOCK_PF3)
72
+
return -EPERM;
73
+
74
+
return 0;
75
+
}
76
+
77
+
static void release_sys_lock(struct pci1xxxx_otp_eeprom_device *priv)
78
+
{
79
+
void __iomem *sys_lock = priv->reg_base +
80
+
MMAP_CFG_OFFSET(CFG_SYS_LOCK_OFFSET);
81
+
writel(0, sys_lock);
82
+
}
83
+
84
+
static void otp_device_set_address(struct pci1xxxx_otp_eeprom_device *priv,
85
+
u16 address)
86
+
{
87
+
u16 lo, hi;
88
+
89
+
lo = address & BYTE_LOW;
90
+
hi = (address & BYTE_HIGH) >> 8;
91
+
writew(lo, priv->reg_base + MMAP_OTP_OFFSET(OTP_ADDR_LOW_OFFSET));
92
+
writew(hi, priv->reg_base + MMAP_OTP_OFFSET(OTP_ADDR_HIGH_OFFSET));
93
+
}
94
+
95
+
static int pci1xxxx_otp_read(void *priv_t, unsigned int off,
96
+
void *buf_t, size_t count)
97
+
{
98
+
struct pci1xxxx_otp_eeprom_device *priv = priv_t;
99
+
void __iomem *rb = priv->reg_base;
100
+
char *buf = buf_t;
101
+
u32 regval;
102
+
u32 byte;
103
+
int ret;
104
+
u8 data;
105
+
106
+
if (off >= priv->nvmem_config_otp.size)
107
+
return -EFAULT;
108
+
109
+
if ((off + count) > priv->nvmem_config_otp.size)
110
+
count = priv->nvmem_config_otp.size - off;
111
+
112
+
ret = set_sys_lock(priv);
113
+
if (ret)
114
+
return ret;
115
+
116
+
for (byte = 0; byte < count; byte++) {
117
+
otp_device_set_address(priv, (u16)(off + byte));
118
+
data = readl(rb + MMAP_OTP_OFFSET(OTP_FUNC_CMD_OFFSET));
119
+
writel(data | OTP_FUNC_RD_BIT,
120
+
rb + MMAP_OTP_OFFSET(OTP_FUNC_CMD_OFFSET));
121
+
data = readl(rb + MMAP_OTP_OFFSET(OTP_CMD_GO_OFFSET));
122
+
writel(data | OTP_CMD_GO_BIT,
123
+
rb + MMAP_OTP_OFFSET(OTP_CMD_GO_OFFSET));
124
+
125
+
ret = read_poll_timeout(readl, regval,
126
+
!(regval & OTP_STATUS_BUSY_BIT),
127
+
STATUS_READ_DELAY_US,
128
+
STATUS_READ_TIMEOUT_US, true,
129
+
rb + MMAP_OTP_OFFSET(OTP_STATUS_OFFSET));
130
+
131
+
data = readl(rb + MMAP_OTP_OFFSET(OTP_PASS_FAIL_OFFSET));
132
+
if (ret < 0 || data & OTP_FAIL_BIT) {
133
+
ret = -EIO;
134
+
goto error;
135
+
}
136
+
137
+
buf[byte] = readl(rb + MMAP_OTP_OFFSET(OTP_RD_DATA_OFFSET));
138
+
}
139
+
ret = byte;
140
+
error:
141
+
release_sys_lock(priv);
142
+
return ret;
143
+
}
144
+
145
+
static int pci1xxxx_otp_write(void *priv_t, unsigned int off,
146
+
void *value_t, size_t count)
147
+
{
148
+
struct pci1xxxx_otp_eeprom_device *priv = priv_t;
149
+
void __iomem *rb = priv->reg_base;
150
+
char *value = value_t;
151
+
u32 regval;
152
+
u32 byte;
153
+
int ret;
154
+
u8 data;
155
+
156
+
if (off >= priv->nvmem_config_otp.size)
157
+
return -EFAULT;
158
+
159
+
if ((off + count) > priv->nvmem_config_otp.size)
160
+
count = priv->nvmem_config_otp.size - off;
161
+
162
+
ret = set_sys_lock(priv);
163
+
if (ret)
164
+
return ret;
165
+
166
+
for (byte = 0; byte < count; byte++) {
167
+
otp_device_set_address(priv, (u16)(off + byte));
168
+
169
+
/*
170
+
* Set OTP_PGM_MODE_BYTE command bit in OTP_PRGM_MODE register
171
+
* to enable Byte programming
172
+
*/
173
+
data = readl(rb + MMAP_OTP_OFFSET(OTP_PRGM_MODE_OFFSET));
174
+
writel(data | OTP_PGM_MODE_BYTE_BIT,
175
+
rb + MMAP_OTP_OFFSET(OTP_PRGM_MODE_OFFSET));
176
+
writel(*(value + byte), rb + MMAP_OTP_OFFSET(OTP_PRGM_DATA_OFFSET));
177
+
data = readl(rb + MMAP_OTP_OFFSET(OTP_FUNC_CMD_OFFSET));
178
+
writel(data | OTP_FUNC_PGM_BIT,
179
+
rb + MMAP_OTP_OFFSET(OTP_FUNC_CMD_OFFSET));
180
+
data = readl(rb + MMAP_OTP_OFFSET(OTP_CMD_GO_OFFSET));
181
+
writel(data | OTP_CMD_GO_BIT,
182
+
rb + MMAP_OTP_OFFSET(OTP_CMD_GO_OFFSET));
183
+
184
+
ret = read_poll_timeout(readl, regval,
185
+
!(regval & OTP_STATUS_BUSY_BIT),
186
+
STATUS_READ_DELAY_US,
187
+
STATUS_READ_TIMEOUT_US, true,
188
+
rb + MMAP_OTP_OFFSET(OTP_STATUS_OFFSET));
189
+
190
+
data = readl(rb + MMAP_OTP_OFFSET(OTP_PASS_FAIL_OFFSET));
191
+
if (ret < 0 || data & OTP_FAIL_BIT) {
192
+
ret = -EIO;
193
+
goto error;
194
+
}
195
+
}
196
+
ret = byte;
197
+
error:
198
+
release_sys_lock(priv);
199
+
return ret;
200
+
}
201
+
202
+
static int pci1xxxx_otp_eeprom_probe(struct auxiliary_device *aux_dev,
203
+
const struct auxiliary_device_id *id)
204
+
{
205
+
struct auxiliary_device_wrapper *aux_dev_wrapper;
206
+
struct pci1xxxx_otp_eeprom_device *priv;
207
+
struct gp_aux_data_type *pdata;
208
+
int ret;
209
+
u8 data;
210
+
211
+
aux_dev_wrapper = container_of(aux_dev, struct auxiliary_device_wrapper,
212
+
aux_dev);
213
+
pdata = &aux_dev_wrapper->gp_aux_data;
214
+
if (!pdata)
215
+
return -EINVAL;
216
+
217
+
priv = devm_kzalloc(&aux_dev->dev, sizeof(*priv), GFP_KERNEL);
218
+
if (!priv)
219
+
return -ENOMEM;
220
+
221
+
priv->pdev = aux_dev;
222
+
223
+
if (!devm_request_mem_region(&aux_dev->dev, pdata->region_start +
224
+
PERI_PF3_SYSTEM_REG_ADDR_BASE,
225
+
PERI_PF3_SYSTEM_REG_LENGTH,
226
+
aux_dev->name))
227
+
return -ENOMEM;
228
+
229
+
priv->reg_base = devm_ioremap(&aux_dev->dev, pdata->region_start +
230
+
PERI_PF3_SYSTEM_REG_ADDR_BASE,
231
+
PERI_PF3_SYSTEM_REG_LENGTH);
232
+
if (!priv->reg_base)
233
+
return -ENOMEM;
234
+
235
+
ret = set_sys_lock(priv);
236
+
if (ret)
237
+
return ret;
238
+
239
+
/* Set OTP_PWR_DN to 0 to make OTP Operational */
240
+
data = readl(priv->reg_base + MMAP_OTP_OFFSET(OTP_PWR_DN_OFFSET));
241
+
writel(data & ~OTP_PWR_DN_BIT,
242
+
priv->reg_base + MMAP_OTP_OFFSET(OTP_PWR_DN_OFFSET));
243
+
244
+
dev_set_drvdata(&aux_dev->dev, priv);
245
+
246
+
release_sys_lock(priv);
247
+
248
+
priv->nvmem_config_otp.type = NVMEM_TYPE_OTP;
249
+
priv->nvmem_config_otp.name = OTP_NAME;
250
+
priv->nvmem_config_otp.dev = &aux_dev->dev;
251
+
priv->nvmem_config_otp.owner = THIS_MODULE;
252
+
priv->nvmem_config_otp.reg_read = pci1xxxx_otp_read;
253
+
priv->nvmem_config_otp.reg_write = pci1xxxx_otp_write;
254
+
priv->nvmem_config_otp.priv = priv;
255
+
priv->nvmem_config_otp.stride = 1;
256
+
priv->nvmem_config_otp.word_size = 1;
257
+
priv->nvmem_config_otp.size = OTP_SIZE_BYTES;
258
+
259
+
priv->nvmem_otp = devm_nvmem_register(&aux_dev->dev,
260
+
&priv->nvmem_config_otp);
261
+
if (!priv->nvmem_otp)
262
+
return -ENOMEM;
263
+
264
+
return ret;
265
+
}
266
+
267
+
static void pci1xxxx_otp_eeprom_remove(struct auxiliary_device *aux_dev)
268
+
{
269
+
struct pci1xxxx_otp_eeprom_device *priv;
270
+
void __iomem *sys_lock;
271
+
272
+
priv = dev_get_drvdata(&aux_dev->dev);
273
+
sys_lock = priv->reg_base + MMAP_CFG_OFFSET(CFG_SYS_LOCK_OFFSET);
274
+
writel(CFG_SYS_LOCK_PF3, sys_lock);
275
+
276
+
/* Shut down OTP */
277
+
writel(OTP_PWR_DN_BIT,
278
+
priv->reg_base + MMAP_OTP_OFFSET(OTP_PWR_DN_OFFSET));
279
+
280
+
writel(0, sys_lock);
281
+
}
282
+
283
+
static const struct auxiliary_device_id pci1xxxx_otp_eeprom_auxiliary_id_table[] = {
284
+
{.name = "mchp_pci1xxxx_gp.gp_otp_e2p"},
285
+
{},
286
+
};
287
+
MODULE_DEVICE_TABLE(auxiliary, pci1xxxx_otp_eeprom_auxiliary_id_table);
288
+
289
+
static struct auxiliary_driver pci1xxxx_otp_eeprom_driver = {
290
+
.driver = {
291
+
.name = AUX_DRIVER_NAME,
292
+
},
293
+
.probe = pci1xxxx_otp_eeprom_probe,
294
+
.remove = pci1xxxx_otp_eeprom_remove,
295
+
.id_table = pci1xxxx_otp_eeprom_auxiliary_id_table
296
+
};
297
+
module_auxiliary_driver(pci1xxxx_otp_eeprom_driver);
298
+
299
+
MODULE_LICENSE("GPL");
300
+
MODULE_AUTHOR("Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>");
301
+
MODULE_AUTHOR("Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>");
302
+
MODULE_AUTHOR("Vaibhaav Ram T.L <vaibhaavram.tl@microchip.com>");
303
+
MODULE_DESCRIPTION("Microchip Technology Inc. PCI1xxxx OTP EEPROM Programmer");