tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Arnd Bergmann:
"Here are a bunch of small bug fixes for various ARM platforms, nothing
really sticks out this week, most of either fixes bugs in code that
was just added in 4.4, or that has been broken for many years without
anyone noticing.

at91/sama5d2:
- fix sama5de hardware setup of sd/mmc interface
- proper selection of pinctrl drivers. PIO4 is necessary for sama5d2

berlin:
- fix incorrect clock input for SDIO

exynos:
- Fix potential NULL pointer dereference in Exynos PMU driver.

imx:
- Fix vf610 SAI clock configuration bug which is discovered by the
newly added master mode support in SAI audio driver.
- Fix buggy L2 cache latency values in vf610 device trees, which may
cause system hang when cpu runs at a higher frequency.

ixp4xx:
- fix prototypes for readl/writel functions

ls2080a:
- use little-endian register access for GPIO and SDHCI

omap:
- Fix clock source for ARM TWD and global timers on am437x
- Always select REGULATOR_FIXED_VOLTAGE for omap2+ instead of when
MACH_OMAP3_PANDORA is selected
- Fix SPI DMA handles for dm816x as only some were mapped
- Fix up mbox cells for dm816x to make mailbox usable

pxa:
- use PWM lookup table for all ezx machines

s3c24xx:
- Remove incorrect __init annotation from s3c24xx cpufreq driver
structures.

versatile:
- fix PCI IRQ mapping on Versatile PB"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ls2080a/dts: Add little endian property for GPIO IP block
dt-bindings: define little-endian property for QorIQ GPIO
ARM64: dts: ls2080a: fix eSDHC endianness
ARM: dts: vf610: use reset values for L2 cache latencies
ARM: pxa: use PWM lookup table for all machines
ARM: dts: berlin: add 2nd clock for BG2Q sdhci0 and sdhci1
ARM: dts: berlin: correct BG2Q's sdhci2 2nd clock
ARM: dts: am4372: fix clock source for arm twd and global timers
ARM: at91: fix pinctrl driver selection
ARM: at91/dt: add always-on to 1.8V regulator
ARM: dts: vf610: fix clock definition for SAI2
ARM: imx: clk-vf610: fix SAI clock tree
ARM: ixp4xx: fix read{b,w,l} return types
irqchip/versatile-fpga: Fix PCI IRQ mapping on Versatile PB
ARM: OMAP2+: enable REGULATOR_FIXED_VOLTAGE
ARM: dts: add dm816x missing spi DT dma handles
ARM: dts: add dm816x missing #mbox-cells
cpufreq: s3c24xx: Do not mark s3c2410_plls_add as __init
ARM: EXYNOS: Fix potential NULL pointer access in exynos_sys_powerdown_conf

Linus Torvalds 097b285d 79dbddaf

+76 -32
+4
Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt
··· 11 11 0 = active high 12 12 1 = active low 13 13 14 + Optional properties: 15 + - little-endian : GPIO registers are used as little endian. If not 16 + present registers are used as big endian by default. 17 + 14 18 Example: 15 19 16 20 gpio0: gpio@1100 {
+2 -2
arch/arm/boot/dts/am4372.dtsi
··· 74 74 reg = <0x48240200 0x100>; 75 75 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; 76 76 interrupt-parent = <&gic>; 77 - clocks = <&dpll_mpu_m2_ck>; 77 + clocks = <&mpu_periphclk>; 78 78 }; 79 79 80 80 local_timer: timer@48240600 { ··· 82 82 reg = <0x48240600 0x100>; 83 83 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; 84 84 interrupt-parent = <&gic>; 85 - clocks = <&dpll_mpu_m2_ck>; 85 + clocks = <&mpu_periphclk>; 86 86 }; 87 87 88 88 l2-cache-controller@48242000 {
+8
arch/arm/boot/dts/am43xx-clocks.dtsi
··· 259 259 ti,invert-autoidle-bit; 260 260 }; 261 261 262 + mpu_periphclk: mpu_periphclk { 263 + #clock-cells = <0>; 264 + compatible = "fixed-factor-clock"; 265 + clocks = <&dpll_mpu_m2_ck>; 266 + clock-mult = <1>; 267 + clock-div = <2>; 268 + }; 269 + 262 270 dpll_ddr_ck: dpll_ddr_ck { 263 271 #clock-cells = <0>; 264 272 compatible = "ti,am3-dpll-clock";
+1
arch/arm/boot/dts/at91-sama5d2_xplained.dts
··· 184 184 regulator-name = "VDD_SDHC_1V8"; 185 185 regulator-min-microvolt = <1800000>; 186 186 regulator-max-microvolt = <1800000>; 187 + regulator-always-on; 187 188 }; 188 189 }; 189 190 };
+5 -3
arch/arm/boot/dts/berlin2q.dtsi
··· 118 118 sdhci0: sdhci@ab0000 { 119 119 compatible = "mrvl,pxav3-mmc"; 120 120 reg = <0xab0000 0x200>; 121 - clocks = <&chip_clk CLKID_SDIO1XIN>; 121 + clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; 122 + clock-names = "io", "core"; 122 123 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 123 124 status = "disabled"; 124 125 }; ··· 127 126 sdhci1: sdhci@ab0800 { 128 127 compatible = "mrvl,pxav3-mmc"; 129 128 reg = <0xab0800 0x200>; 130 - clocks = <&chip_clk CLKID_SDIO1XIN>; 129 + clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; 130 + clock-names = "io", "core"; 131 131 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 132 132 status = "disabled"; 133 133 }; ··· 137 135 compatible = "mrvl,pxav3-mmc"; 138 136 reg = <0xab1000 0x200>; 139 137 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 140 - clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>; 138 + clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_SDIO>; 141 139 clock-names = "io", "core"; 142 140 status = "disabled"; 143 141 };
+6 -2
arch/arm/boot/dts/dm816x.dtsi
··· 218 218 reg = <0x480c8000 0x2000>; 219 219 interrupts = <77>; 220 220 ti,hwmods = "mailbox"; 221 + #mbox-cells = <1>; 221 222 ti,mbox-num-users = <4>; 222 223 ti,mbox-num-fifos = <12>; 223 224 mbox_dsp: mbox_dsp { ··· 280 279 ti,spi-num-cs = <4>; 281 280 ti,hwmods = "mcspi1"; 282 281 dmas = <&edma 16 &edma 17 283 - &edma 18 &edma 19>; 284 - dma-names = "tx0", "rx0", "tx1", "rx1"; 282 + &edma 18 &edma 19 283 + &edma 20 &edma 21 284 + &edma 22 &edma 23>; 285 + dma-names = "tx0", "rx0", "tx1", "rx1", 286 + "tx2", "rx2", "tx3", "rx3"; 285 287 }; 286 288 287 289 mmc1: mmc@48060000 {
-5
arch/arm/boot/dts/vf610-colibri.dtsi
··· 18 18 reg = <0x80000000 0x10000000>; 19 19 }; 20 20 }; 21 - 22 - &L2 { 23 - arm,data-latency = <2 1 2>; 24 - arm,tag-latency = <3 2 3>; 25 - };
+1 -1
arch/arm/boot/dts/vf610.dtsi
··· 19 19 reg = <0x40006000 0x1000>; 20 20 cache-unified; 21 21 cache-level = <2>; 22 - arm,data-latency = <1 1 1>; 22 + arm,data-latency = <3 3 3>; 23 23 arm,tag-latency = <2 2 2>; 24 24 }; 25 25 };
+4 -2
arch/arm/boot/dts/vfxxx.dtsi
··· 178 178 compatible = "fsl,vf610-sai"; 179 179 reg = <0x40031000 0x1000>; 180 180 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>; 181 - clocks = <&clks VF610_CLK_SAI2>; 182 - clock-names = "sai"; 181 + clocks = <&clks VF610_CLK_SAI2>, 182 + <&clks VF610_CLK_SAI2_DIV>, 183 + <&clks 0>, <&clks 0>; 184 + clock-names = "bus", "mclk1", "mclk2", "mclk3"; 183 185 dma-names = "tx", "rx"; 184 186 dmas = <&edma0 0 21>, 185 187 <&edma0 0 20>;
+5 -1
arch/arm/mach-at91/Kconfig
··· 4 4 select ARCH_REQUIRE_GPIOLIB 5 5 select COMMON_CLK_AT91 6 6 select PINCTRL 7 - select PINCTRL_AT91 8 7 select SOC_BUS 9 8 10 9 if ARCH_AT91 ··· 16 17 select HAVE_AT91_USB_CLK 17 18 select HAVE_AT91_H32MX 18 19 select HAVE_AT91_GENERATED_CLK 20 + select PINCTRL_AT91PIO4 19 21 help 20 22 Select this if ou are using one of Atmel's SAMA5D2 family SoC. 21 23 ··· 27 27 select HAVE_AT91_UTMI 28 28 select HAVE_AT91_SMD 29 29 select HAVE_AT91_USB_CLK 30 + select PINCTRL_AT91 30 31 help 31 32 Select this if you are using one of Atmel's SAMA5D3 family SoC. 32 33 This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36. ··· 41 40 select HAVE_AT91_SMD 42 41 select HAVE_AT91_USB_CLK 43 42 select HAVE_AT91_H32MX 43 + select PINCTRL_AT91 44 44 help 45 45 Select this if you are using one of Atmel's SAMA5D4 family SoC. 46 46 ··· 52 50 select CPU_ARM920T 53 51 select HAVE_AT91_USB_CLK 54 52 select MIGHT_HAVE_PCI 53 + select PINCTRL_AT91 55 54 select SOC_SAM_V4_V5 56 55 select SRAM if PM 57 56 help ··· 68 65 select HAVE_AT91_UTMI 69 66 select HAVE_FB_ATMEL 70 67 select MEMORY 68 + select PINCTRL_AT91 71 69 select SOC_SAM_V4_V5 72 70 select SRAM if PM 73 71 help
+6 -1
arch/arm/mach-at91/pm.c
··· 41 41 * implementation should be moved down into the pinctrl driver and get 42 42 * called as part of the generic suspend/resume path. 43 43 */ 44 + #ifdef CONFIG_PINCTRL_AT91 44 45 extern void at91_pinctrl_gpio_suspend(void); 45 46 extern void at91_pinctrl_gpio_resume(void); 47 + #endif 46 48 47 49 static struct { 48 50 unsigned long uhp_udp_mask; ··· 153 151 154 152 static int at91_pm_enter(suspend_state_t state) 155 153 { 154 + #ifdef CONFIG_PINCTRL_AT91 156 155 at91_pinctrl_gpio_suspend(); 157 - 156 + #endif 158 157 switch (state) { 159 158 /* 160 159 * Suspend-to-RAM is like STANDBY plus slow clock mode, so ··· 195 192 error: 196 193 target_state = PM_SUSPEND_ON; 197 194 195 + #ifdef CONFIG_PINCTRL_AT91 198 196 at91_pinctrl_gpio_resume(); 197 + #endif 199 198 return 0; 200 199 } 201 200
+5 -1
arch/arm/mach-exynos/pmu.c
··· 748 748 void exynos_sys_powerdown_conf(enum sys_powerdown mode) 749 749 { 750 750 unsigned int i; 751 + const struct exynos_pmu_data *pmu_data; 751 752 752 - const struct exynos_pmu_data *pmu_data = pmu_context->pmu_data; 753 + if (!pmu_context) 754 + return; 755 + 756 + pmu_data = pmu_context->pmu_data; 753 757 754 758 if (pmu_data->powerdown_conf) 755 759 pmu_data->powerdown_conf(mode);
+6 -6
arch/arm/mach-ixp4xx/include/mach/io.h
··· 143 143 writel(*vaddr++, bus_addr); 144 144 } 145 145 146 - static inline unsigned char __indirect_readb(const volatile void __iomem *p) 146 + static inline u8 __indirect_readb(const volatile void __iomem *p) 147 147 { 148 148 u32 addr = (u32)p; 149 149 u32 n, byte_enables, data; ··· 166 166 *vaddr++ = readb(bus_addr); 167 167 } 168 168 169 - static inline unsigned short __indirect_readw(const volatile void __iomem *p) 169 + static inline u16 __indirect_readw(const volatile void __iomem *p) 170 170 { 171 171 u32 addr = (u32)p; 172 172 u32 n, byte_enables, data; ··· 189 189 *vaddr++ = readw(bus_addr); 190 190 } 191 191 192 - static inline unsigned long __indirect_readl(const volatile void __iomem *p) 192 + static inline u32 __indirect_readl(const volatile void __iomem *p) 193 193 { 194 194 u32 addr = (__force u32)p; 195 195 u32 data; ··· 350 350 ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) 351 351 352 352 #define ioread8(p) ioread8(p) 353 - static inline unsigned int ioread8(const void __iomem *addr) 353 + static inline u8 ioread8(const void __iomem *addr) 354 354 { 355 355 unsigned long port = (unsigned long __force)addr; 356 356 if (__is_io_address(port)) ··· 378 378 } 379 379 380 380 #define ioread16(p) ioread16(p) 381 - static inline unsigned int ioread16(const void __iomem *addr) 381 + static inline u16 ioread16(const void __iomem *addr) 382 382 { 383 383 unsigned long port = (unsigned long __force)addr; 384 384 if (__is_io_address(port)) ··· 407 407 } 408 408 409 409 #define ioread32(p) ioread32(p) 410 - static inline unsigned int ioread32(const void __iomem *addr) 410 + static inline u32 ioread32(const void __iomem *addr) 411 411 { 412 412 unsigned long port = (unsigned long __force)addr; 413 413 if (__is_io_address(port))
+1 -1
arch/arm/mach-omap2/Kconfig
··· 121 121 select NEON if CPU_V7 122 122 select PM 123 123 select REGULATOR 124 + select REGULATOR_FIXED_VOLTAGE 124 125 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 125 126 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 126 127 select VFP ··· 202 201 depends on ARCH_OMAP3 203 202 default y 204 203 select OMAP_PACKAGE_CBB 205 - select REGULATOR_FIXED_VOLTAGE if REGULATOR 206 204 207 205 config MACH_NOKIA_N810 208 206 bool
+5
arch/arm/mach-pxa/ezx.c
··· 889 889 890 890 pxa_set_keypad_info(&e680_keypad_platform_data); 891 891 892 + pwm_add_table(ezx_pwm_lookup, ARRAY_SIZE(ezx_pwm_lookup)); 892 893 platform_add_devices(ARRAY_AND_SIZE(ezx_devices)); 893 894 platform_add_devices(ARRAY_AND_SIZE(e680_devices)); 894 895 } ··· 957 956 958 957 pxa_set_keypad_info(&a1200_keypad_platform_data); 959 958 959 + pwm_add_table(ezx_pwm_lookup, ARRAY_SIZE(ezx_pwm_lookup)); 960 960 platform_add_devices(ARRAY_AND_SIZE(ezx_devices)); 961 961 platform_add_devices(ARRAY_AND_SIZE(a1200_devices)); 962 962 } ··· 1150 1148 platform_device_register(&a910_camera); 1151 1149 } 1152 1150 1151 + pwm_add_table(ezx_pwm_lookup, ARRAY_SIZE(ezx_pwm_lookup)); 1153 1152 platform_add_devices(ARRAY_AND_SIZE(ezx_devices)); 1154 1153 platform_add_devices(ARRAY_AND_SIZE(a910_devices)); 1155 1154 } ··· 1218 1215 1219 1216 pxa_set_keypad_info(&e6_keypad_platform_data); 1220 1217 1218 + pwm_add_table(ezx_pwm_lookup, ARRAY_SIZE(ezx_pwm_lookup)); 1221 1219 platform_add_devices(ARRAY_AND_SIZE(ezx_devices)); 1222 1220 platform_add_devices(ARRAY_AND_SIZE(e6_devices)); 1223 1221 } ··· 1260 1256 1261 1257 pxa_set_keypad_info(&e2_keypad_platform_data); 1262 1258 1259 + pwm_add_table(ezx_pwm_lookup, ARRAY_SIZE(ezx_pwm_lookup)); 1263 1260 platform_add_devices(ARRAY_AND_SIZE(ezx_devices)); 1264 1261 platform_add_devices(ARRAY_AND_SIZE(e2_devices)); 1265 1262 }
+1 -1
arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
··· 20 20 #include <plat/cpu.h> 21 21 #include <plat/cpu-freq-core.h> 22 22 23 - static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = { 23 + static struct cpufreq_frequency_table s3c2440_plls_12[] = { 24 24 { .frequency = 75000000, .driver_data = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */ 25 25 { .frequency = 80000000, .driver_data = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */ 26 26 { .frequency = 90000000, .driver_data = PLLVAL(0x70, 2, 3), }, /* FVco 720.000000 */
+1 -1
arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
··· 20 20 #include <plat/cpu.h> 21 21 #include <plat/cpu-freq-core.h> 22 22 23 - static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = { 23 + static struct cpufreq_frequency_table s3c2440_plls_169344[] = { 24 24 { .frequency = 78019200, .driver_data = PLLVAL(121, 5, 3), }, /* FVco 624.153600 */ 25 25 { .frequency = 84067200, .driver_data = PLLVAL(131, 5, 3), }, /* FVco 672.537600 */ 26 26 { .frequency = 90115200, .driver_data = PLLVAL(141, 5, 3), }, /* FVco 720.921600 */
+5
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
··· 269 269 clock-frequency = <0>; /* Updated by bootloader */ 270 270 voltage-ranges = <1800 1800 3300 3300>; 271 271 sdhci,auto-cmd12; 272 + little-endian; 272 273 bus-width = <4>; 273 274 }; 274 275 ··· 278 277 reg = <0x0 0x2300000 0x0 0x10000>; 279 278 interrupts = <0 36 0x4>; /* Level high type */ 280 279 gpio-controller; 280 + little-endian; 281 281 #gpio-cells = <2>; 282 282 interrupt-controller; 283 283 #interrupt-cells = <2>; ··· 289 287 reg = <0x0 0x2310000 0x0 0x10000>; 290 288 interrupts = <0 36 0x4>; /* Level high type */ 291 289 gpio-controller; 290 + little-endian; 292 291 #gpio-cells = <2>; 293 292 interrupt-controller; 294 293 #interrupt-cells = <2>; ··· 300 297 reg = <0x0 0x2320000 0x0 0x10000>; 301 298 interrupts = <0 37 0x4>; /* Level high type */ 302 299 gpio-controller; 300 + little-endian; 303 301 #gpio-cells = <2>; 304 302 interrupt-controller; 305 303 #interrupt-cells = <2>; ··· 311 307 reg = <0x0 0x2330000 0x0 0x10000>; 312 308 interrupts = <0 37 0x4>; /* Level high type */ 313 309 gpio-controller; 310 + little-endian; 314 311 #gpio-cells = <2>; 315 312 interrupt-controller; 316 313 #interrupt-cells = <2>;
+4 -4
drivers/clk/imx/clk-vf610.c
··· 335 335 clk[VF610_CLK_SAI0_SEL] = imx_clk_mux("sai0_sel", CCM_CSCMR1, 0, 2, sai_sels, 4); 336 336 clk[VF610_CLK_SAI0_EN] = imx_clk_gate("sai0_en", "sai0_sel", CCM_CSCDR1, 16); 337 337 clk[VF610_CLK_SAI0_DIV] = imx_clk_divider("sai0_div", "sai0_en", CCM_CSCDR1, 0, 4); 338 - clk[VF610_CLK_SAI0] = imx_clk_gate2("sai0", "sai0_div", CCM_CCGR0, CCM_CCGRx_CGn(15)); 338 + clk[VF610_CLK_SAI0] = imx_clk_gate2("sai0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(15)); 339 339 340 340 clk[VF610_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", CCM_CSCMR1, 2, 2, sai_sels, 4); 341 341 clk[VF610_CLK_SAI1_EN] = imx_clk_gate("sai1_en", "sai1_sel", CCM_CSCDR1, 17); 342 342 clk[VF610_CLK_SAI1_DIV] = imx_clk_divider("sai1_div", "sai1_en", CCM_CSCDR1, 4, 4); 343 - clk[VF610_CLK_SAI1] = imx_clk_gate2("sai1", "sai1_div", CCM_CCGR1, CCM_CCGRx_CGn(0)); 343 + clk[VF610_CLK_SAI1] = imx_clk_gate2("sai1", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(0)); 344 344 345 345 clk[VF610_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", CCM_CSCMR1, 4, 2, sai_sels, 4); 346 346 clk[VF610_CLK_SAI2_EN] = imx_clk_gate("sai2_en", "sai2_sel", CCM_CSCDR1, 18); 347 347 clk[VF610_CLK_SAI2_DIV] = imx_clk_divider("sai2_div", "sai2_en", CCM_CSCDR1, 8, 4); 348 - clk[VF610_CLK_SAI2] = imx_clk_gate2("sai2", "sai2_div", CCM_CCGR1, CCM_CCGRx_CGn(1)); 348 + clk[VF610_CLK_SAI2] = imx_clk_gate2("sai2", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(1)); 349 349 350 350 clk[VF610_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", CCM_CSCMR1, 6, 2, sai_sels, 4); 351 351 clk[VF610_CLK_SAI3_EN] = imx_clk_gate("sai3_en", "sai3_sel", CCM_CSCDR1, 19); 352 352 clk[VF610_CLK_SAI3_DIV] = imx_clk_divider("sai3_div", "sai3_en", CCM_CSCDR1, 12, 4); 353 - clk[VF610_CLK_SAI3] = imx_clk_gate2("sai3", "sai3_div", CCM_CCGR1, CCM_CCGRx_CGn(2)); 353 + clk[VF610_CLK_SAI3] = imx_clk_gate2("sai3", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(2)); 354 354 355 355 clk[VF610_CLK_NFC_SEL] = imx_clk_mux("nfc_sel", CCM_CSCMR1, 12, 2, nfc_sels, 4); 356 356 clk[VF610_CLK_NFC_EN] = imx_clk_gate("nfc_en", "nfc_sel", CCM_CSCDR2, 9);
+1 -1
drivers/cpufreq/s3c24xx-cpufreq.c
··· 648 648 * 649 649 * Register the given set of PLLs with the system. 650 650 */ 651 - int __init s3c_plltab_register(struct cpufreq_frequency_table *plls, 651 + int s3c_plltab_register(struct cpufreq_frequency_table *plls, 652 652 unsigned int plls_no) 653 653 { 654 654 struct cpufreq_frequency_table *vals;
+5
drivers/irqchip/irq-versatile-fpga.c
··· 210 210 parent_irq = -1; 211 211 } 212 212 213 + #ifdef CONFIG_ARCH_VERSATILE 214 + fpga_irq_init(base, node->name, IRQ_SIC_START, parent_irq, valid_mask, 215 + node); 216 + #else 213 217 fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node); 218 + #endif 214 219 215 220 writel(clear_mask, base + IRQ_ENABLE_CLEAR); 216 221 writel(clear_mask, base + FIQ_ENABLE_CLEAR);