Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'icc-7.1-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
Georgi writes:
This pull request contains the interconnect changes for the 7.1-rc1
merge window. They are listed below:
- New driver for Mahua SoC
- New driver for Eliza SoC
- Enable QoS support for QCS8300 and QCS615 SoCs
- Add L3 cache scaling compatibles for SM8550 and Eliza SoCs
- Fix multiple issues in the msm8974 driver
- Fix kfree mismatch
- Misc cleanups
- Add maintainer entry for the interconnect KUnit tests
Signed-off-by: Georgi Djakov <djakov@kernel.org>
* tag 'icc-7.1-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc: (22 commits)
MAINTAINERS: Add interconnect kunit test entry
interconnect: debugfs: fix devm_kstrdup and kfree mismatch
interconnect: qcom: msm8974: expand DEFINE_QNODE macros
interconnect: qcom: msm8974: switch to the main icc-rpm driver
interconnect: qcom: let platforms declare their bugginess
interconnect: qcom: define OCMEM bus resource
interconnect: qcom: icc-rpm: allow overwriting get_bw callback
interconnect: qcom: drop unused is_on flag
dt-bindings: interconnect: qcom,msm8974: use qcom,rpm-common
dt-bindings: interconnect: qcom,msm8974: drop bus clocks
interconnect: qcom: qcs615: enable QoS configuration
dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoS
interconnect: qcom: Add Eliza interconnect provider driver
dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Eliza SoC
dt-bindings: interconnect: OSM L3: Add Eliza EPSS L3 compatible
interconnect: qcom: De-acronymize SoC names
dt-bindings: interconnect: qcom,glymur-rpmh: De-acronymize SoC name
dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatible
interconnect: qcom: qcs8300: enable QoS configuration
dt-bindings: interconnect: qcom,qcs8300-rpmh: add clocks property to enable QoS
...
+4002
-449
+142
Documentation/devicetree/bindings/interconnect/qcom,eliza-rpmh.yaml
+142
Documentation/devicetree/bindings/interconnect/qcom,eliza-rpmh.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interconnect/qcom,eliza-rpmh.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm RPMh Network-On-Chip Interconnect on Eliza SoC
8
+
9
+
maintainers:
10
+
- Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
11
+
12
+
description: |
13
+
RPMh interconnect providers support system bandwidth requirements through
14
+
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
15
+
able to communicate with the BCM through the Resource State Coordinator (RSC)
16
+
associated with each execution environment. Provider nodes must point to at
17
+
least one RPMh device child node pertaining to their RSC and each provider
18
+
can map to multiple RPMh resources.
19
+
20
+
See also: include/dt-bindings/interconnect/qcom,eliza-rpmh.h
21
+
22
+
properties:
23
+
compatible:
24
+
enum:
25
+
- qcom,eliza-aggre1-noc
26
+
- qcom,eliza-aggre2-noc
27
+
- qcom,eliza-clk-virt
28
+
- qcom,eliza-cnoc-cfg
29
+
- qcom,eliza-cnoc-main
30
+
- qcom,eliza-gem-noc
31
+
- qcom,eliza-lpass-ag-noc
32
+
- qcom,eliza-lpass-lpiaon-noc
33
+
- qcom,eliza-lpass-lpicx-noc
34
+
- qcom,eliza-mc-virt
35
+
- qcom,eliza-mmss-noc
36
+
- qcom,eliza-nsp-noc
37
+
- qcom,eliza-pcie-anoc
38
+
- qcom,eliza-system-noc
39
+
40
+
reg:
41
+
maxItems: 1
42
+
43
+
clocks:
44
+
minItems: 1
45
+
maxItems: 2
46
+
47
+
required:
48
+
- compatible
49
+
50
+
allOf:
51
+
- $ref: qcom,rpmh-common.yaml#
52
+
- if:
53
+
properties:
54
+
compatible:
55
+
contains:
56
+
enum:
57
+
- qcom,eliza-clk-virt
58
+
- qcom,eliza-mc-virt
59
+
then:
60
+
properties:
61
+
reg: false
62
+
else:
63
+
required:
64
+
- reg
65
+
66
+
- if:
67
+
properties:
68
+
compatible:
69
+
contains:
70
+
enum:
71
+
- qcom,eliza-aggre1-noc
72
+
then:
73
+
properties:
74
+
clocks:
75
+
items:
76
+
- description: aggre UFS PHY AXI clock
77
+
- description: aggre USB3 PRIM AXI clock
78
+
79
+
- if:
80
+
properties:
81
+
compatible:
82
+
contains:
83
+
enum:
84
+
- qcom,eliza-aggre2-noc
85
+
then:
86
+
properties:
87
+
clocks:
88
+
items:
89
+
- description: RPMH CC IPA clock
90
+
91
+
- if:
92
+
properties:
93
+
compatible:
94
+
contains:
95
+
enum:
96
+
- qcom,eliza-pcie-anoc
97
+
then:
98
+
properties:
99
+
clocks:
100
+
items:
101
+
- description: aggre-NOC PCIe AXI clock
102
+
- description: cfg-NOC PCIe a-NOC AHB clock
103
+
104
+
- if:
105
+
properties:
106
+
compatible:
107
+
contains:
108
+
enum:
109
+
- qcom,eliza-aggre1-noc
110
+
- qcom,eliza-aggre2-noc
111
+
- qcom,eliza-pcie-anoc
112
+
then:
113
+
required:
114
+
- clocks
115
+
else:
116
+
properties:
117
+
clocks: false
118
+
119
+
unevaluatedProperties: false
120
+
121
+
examples:
122
+
- |
123
+
gem_noc: interconnect@24100000 {
124
+
compatible = "qcom,eliza-gem-noc";
125
+
reg = <0x24100000 0x163080>;
126
+
#interconnect-cells = <2>;
127
+
qcom,bcm-voters = <&apps_bcm_voter>;
128
+
};
129
+
130
+
mc_virt: interconnect-2 {
131
+
compatible = "qcom,eliza-mc-virt";
132
+
#interconnect-cells = <2>;
133
+
qcom,bcm-voters = <&apps_bcm_voter>;
134
+
};
135
+
136
+
aggre1_noc: interconnect@16e0000 {
137
+
compatible = "qcom,eliza-aggre1-noc";
138
+
reg = <0x16e0000 0x16400>;
139
+
#interconnect-cells = <2>;
140
+
clocks = <&gcc_phy_axi_clk>, <&gcc_prim_axi_clk>;
141
+
qcom,bcm-voters = <&apps_bcm_voter>;
142
+
};
+111
-25
Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml
+111
-25
Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml
···
4
4
$id: http://devicetree.org/schemas/interconnect/qcom,glymur-rpmh.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: Qualcomm RPMh Network-On-Chip Interconnect on GLYMUR
7
+
title: Qualcomm RPMh Network-On-Chip Interconnect on Glymur and Mahua SoCs
8
8
9
9
maintainers:
10
10
- Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
···
21
21
22
22
properties:
23
23
compatible:
24
-
enum:
25
-
- qcom,glymur-aggre1-noc
26
-
- qcom,glymur-aggre2-noc
27
-
- qcom,glymur-aggre3-noc
28
-
- qcom,glymur-aggre4-noc
29
-
- qcom,glymur-clk-virt
30
-
- qcom,glymur-cnoc-cfg
31
-
- qcom,glymur-cnoc-main
32
-
- qcom,glymur-hscnoc
33
-
- qcom,glymur-lpass-ag-noc
34
-
- qcom,glymur-lpass-lpiaon-noc
35
-
- qcom,glymur-lpass-lpicx-noc
36
-
- qcom,glymur-mc-virt
37
-
- qcom,glymur-mmss-noc
38
-
- qcom,glymur-nsinoc
39
-
- qcom,glymur-nsp-noc
40
-
- qcom,glymur-oobm-ss-noc
41
-
- qcom,glymur-pcie-east-anoc
42
-
- qcom,glymur-pcie-east-slv-noc
43
-
- qcom,glymur-pcie-west-anoc
44
-
- qcom,glymur-pcie-west-slv-noc
45
-
- qcom,glymur-system-noc
24
+
oneOf:
25
+
- items:
26
+
- enum:
27
+
- qcom,mahua-aggre1-noc
28
+
- const: qcom,glymur-aggre1-noc
29
+
- items:
30
+
- enum:
31
+
- qcom,mahua-aggre2-noc
32
+
- const: qcom,glymur-aggre2-noc
33
+
- items:
34
+
- enum:
35
+
- qcom,mahua-aggre3-noc
36
+
- const: qcom,glymur-aggre3-noc
37
+
- items:
38
+
- enum:
39
+
- qcom,mahua-aggre4-noc
40
+
- const: qcom,glymur-aggre4-noc
41
+
- items:
42
+
- enum:
43
+
- qcom,mahua-clk-virt
44
+
- const: qcom,glymur-clk-virt
45
+
- items:
46
+
- enum:
47
+
- qcom,mahua-cnoc-main
48
+
- const: qcom,glymur-cnoc-main
49
+
- items:
50
+
- enum:
51
+
- qcom,mahua-lpass-ag-noc
52
+
- const: qcom,glymur-lpass-ag-noc
53
+
- items:
54
+
- enum:
55
+
- qcom,mahua-lpass-lpiaon-noc
56
+
- const: qcom,glymur-lpass-lpiaon-noc
57
+
- items:
58
+
- enum:
59
+
- qcom,mahua-lpass-lpicx-noc
60
+
- const: qcom,glymur-lpass-lpicx-noc
61
+
- items:
62
+
- enum:
63
+
- qcom,mahua-mmss-noc
64
+
- const: qcom,glymur-mmss-noc
65
+
- items:
66
+
- enum:
67
+
- qcom,mahua-nsinoc
68
+
- const: qcom,glymur-nsinoc
69
+
- items:
70
+
- enum:
71
+
- qcom,mahua-nsp-noc
72
+
- const: qcom,glymur-nsp-noc
73
+
- items:
74
+
- enum:
75
+
- qcom,mahua-oobm-ss-noc
76
+
- const: qcom,glymur-oobm-ss-noc
77
+
- items:
78
+
- enum:
79
+
- qcom,mahua-pcie-east-anoc
80
+
- const: qcom,glymur-pcie-east-anoc
81
+
- items:
82
+
- enum:
83
+
- qcom,mahua-pcie-east-slv-noc
84
+
- const: qcom,glymur-pcie-east-slv-noc
85
+
- items:
86
+
- enum:
87
+
- qcom,mahua-system-noc
88
+
- const: qcom,glymur-system-noc
89
+
- enum:
90
+
- qcom,glymur-aggre1-noc
91
+
- qcom,glymur-aggre2-noc
92
+
- qcom,glymur-aggre3-noc
93
+
- qcom,glymur-aggre4-noc
94
+
- qcom,glymur-clk-virt
95
+
- qcom,glymur-cnoc-cfg
96
+
- qcom,glymur-cnoc-main
97
+
- qcom,glymur-hscnoc
98
+
- qcom,glymur-lpass-ag-noc
99
+
- qcom,glymur-lpass-lpiaon-noc
100
+
- qcom,glymur-lpass-lpicx-noc
101
+
- qcom,glymur-mc-virt
102
+
- qcom,glymur-mmss-noc
103
+
- qcom,glymur-nsinoc
104
+
- qcom,glymur-nsp-noc
105
+
- qcom,glymur-oobm-ss-noc
106
+
- qcom,glymur-pcie-east-anoc
107
+
- qcom,glymur-pcie-east-slv-noc
108
+
- qcom,glymur-pcie-west-anoc
109
+
- qcom,glymur-pcie-west-slv-noc
110
+
- qcom,glymur-system-noc
111
+
- qcom,mahua-cnoc-cfg
112
+
- qcom,mahua-hscnoc
113
+
- qcom,mahua-mc-virt
114
+
- qcom,mahua-pcie-west-anoc
115
+
- qcom,mahua-pcie-west-slv-noc
46
116
47
117
reg:
48
118
maxItems: 1
···
133
63
enum:
134
64
- qcom,glymur-clk-virt
135
65
- qcom,glymur-mc-virt
66
+
- qcom,mahua-mc-virt
136
67
then:
137
68
properties:
138
69
reg: false
···
152
81
clocks:
153
82
items:
154
83
- description: aggre PCIE_3A WEST AXI clock
84
+
- description: aggre PCIE_3B WEST AXI clock
85
+
- description: aggre PCIE_4 WEST AXI clock
86
+
- description: aggre PCIE_6 WEST AXI clock
87
+
88
+
- if:
89
+
properties:
90
+
compatible:
91
+
contains:
92
+
enum:
93
+
- qcom,mahua-pcie-west-anoc
94
+
then:
95
+
properties:
96
+
clocks:
97
+
items:
155
98
- description: aggre PCIE_3B WEST AXI clock
156
99
- description: aggre PCIE_4 WEST AXI clock
157
100
- description: aggre PCIE_6 WEST AXI clock
···
216
131
compatible:
217
132
contains:
218
133
enum:
219
-
- qcom,glymur-pcie-west-anoc
220
-
- qcom,glymur-pcie-east-anoc
221
134
- qcom,glymur-aggre2-noc
222
135
- qcom,glymur-aggre4-noc
136
+
- qcom,glymur-pcie-east-anoc
137
+
- qcom,glymur-pcie-west-anoc
138
+
- qcom,mahua-pcie-west-anoc
223
139
then:
224
140
required:
225
141
- clocks
+16
-12
Documentation/devicetree/bindings/interconnect/qcom,msm8974.yaml
+16
-12
Documentation/devicetree/bindings/interconnect/qcom,msm8974.yaml
···
26
26
- qcom,msm8974-pnoc
27
27
- qcom,msm8974-snoc
28
28
29
-
'#interconnect-cells':
30
-
const: 1
31
-
32
29
clock-names:
33
30
items:
34
31
- const: bus
35
-
- const: bus_a
36
32
37
33
clocks:
38
34
items:
39
35
- description: Bus Clock
40
-
- description: Bus A Clock
41
36
42
37
required:
43
38
- compatible
44
39
- reg
45
-
- '#interconnect-cells'
46
-
- clock-names
47
-
- clocks
48
40
49
-
additionalProperties: false
41
+
unevaluatedProperties: false
42
+
43
+
allOf:
44
+
- $ref: qcom,rpm-common.yaml#
45
+
- if:
46
+
properties:
47
+
compatible:
48
+
const: qcom,msm8974-mmssnoc
49
+
then:
50
+
required:
51
+
- clocks
52
+
- clock-names
53
+
else:
54
+
properties:
55
+
clocks: false
56
+
clock-names: false
50
57
51
58
examples:
52
59
- |
···
63
56
reg = <0xfc380000 0x6a000>;
64
57
compatible = "qcom,msm8974-bimc";
65
58
#interconnect-cells = <1>;
66
-
clock-names = "bus", "bus_a";
67
-
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
68
-
<&rpmcc RPM_SMD_BIMC_A_CLK>;
69
59
};
+2
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+2
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
···
28
28
- const: qcom,osm-l3
29
29
- items:
30
30
- enum:
31
+
- qcom,eliza-epss-l3
31
32
- qcom,sa8775p-epss-l3
32
33
- qcom,sc7280-epss-l3
33
34
- qcom,sc8280xp-epss-l3
34
35
- qcom,sm6375-cpucp-l3
35
36
- qcom,sm8250-epss-l3
36
37
- qcom,sm8350-epss-l3
38
+
- qcom,sm8550-epss-l3
37
39
- qcom,sm8650-epss-l3
38
40
- const: qcom,epss-l3
39
41
- items:
+23
Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
+23
Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
···
34
34
reg:
35
35
maxItems: 1
36
36
37
+
clocks:
38
+
items:
39
+
- description: aggre UFS PHY AXI clock
40
+
- description: aggre USB2 SEC AXI clock
41
+
- description: aggre USB3 PRIM AXI clock
42
+
- description: RPMH CC IPA clock
43
+
37
44
required:
38
45
- compatible
39
46
···
59
52
else:
60
53
required:
61
54
- reg
55
+
56
+
- if:
57
+
properties:
58
+
compatible:
59
+
contains:
60
+
enum:
61
+
- qcom,qcs615-camnoc-virt
62
+
- qcom,qcs615-config-noc
63
+
- qcom,qcs615-dc-noc
64
+
- qcom,qcs615-gem-noc
65
+
- qcom,qcs615-mc-virt
66
+
- qcom,qcs615-mmss-noc
67
+
- qcom,qcs615-system-noc
68
+
then:
69
+
properties:
70
+
clocks: false
62
71
63
72
unevaluatedProperties: false
64
73
+63
Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.yaml
+63
Documentation/devicetree/bindings/interconnect/qcom,qcs8300-rpmh.yaml
···
35
35
reg:
36
36
maxItems: 1
37
37
38
+
clocks:
39
+
minItems: 1
40
+
maxItems: 4
41
+
38
42
required:
39
43
- compatible
40
44
···
58
54
required:
59
55
- reg
60
56
57
+
- if:
58
+
properties:
59
+
compatible:
60
+
contains:
61
+
enum:
62
+
- qcom,qcs8300-aggre1-noc
63
+
then:
64
+
properties:
65
+
clocks:
66
+
items:
67
+
- description: aggre UFS PHY AXI clock
68
+
- description: aggre QUP PRIM AXI clock
69
+
- description: aggre USB2 PRIM AXI clock
70
+
- description: aggre USB3 PRIM AXI clock
71
+
72
+
- if:
73
+
properties:
74
+
compatible:
75
+
contains:
76
+
enum:
77
+
- qcom,qcs8300-aggre2-noc
78
+
then:
79
+
properties:
80
+
clocks:
81
+
items:
82
+
- description: RPMH CC IPA clock
83
+
84
+
- if:
85
+
properties:
86
+
compatible:
87
+
contains:
88
+
enum:
89
+
- qcom,qcs8300-gem-noc
90
+
then:
91
+
properties:
92
+
clocks:
93
+
items:
94
+
- description: GCC DDRSS GPU AXI clock
95
+
96
+
- if:
97
+
properties:
98
+
compatible:
99
+
contains:
100
+
enum:
101
+
- qcom,qcs8300-clk-virt
102
+
- qcom,qcs8300-config-noc
103
+
- qcom,qcs8300-dc-noc
104
+
- qcom,qcs8300-gpdsp-anoc
105
+
- qcom,qcs8300-lpass-ag-noc
106
+
- qcom,qcs8300-mc-virt
107
+
- qcom,qcs8300-mmss-noc
108
+
- qcom,qcs8300-nspa-noc
109
+
- qcom,qcs8300-pcie-anoc
110
+
- qcom,qcs8300-system-noc
111
+
then:
112
+
properties:
113
+
clocks: false
114
+
61
115
unevaluatedProperties: false
62
116
63
117
examples:
···
125
63
reg = <0x9100000 0xf7080>;
126
64
#interconnect-cells = <2>;
127
65
qcom,bcm-voters = <&apps_bcm_voter>;
66
+
clocks = <&gcc_ddrss_gpu_axi_clk>;
128
67
};
129
68
130
69
clk_virt: interconnect-0 {
+6
MAINTAINERS
+6
MAINTAINERS
···
13352
13352
F: include/linux/interconnect-provider.h
13353
13353
F: include/linux/interconnect.h
13354
13354
13355
+
INTERCONNECT KUNIT TESTS
13356
+
M: Kuan-Wei Chiu <visitorckw@gmail.com>
13357
+
L: linux-pm@vger.kernel.org
13358
+
S: Maintained
13359
+
F: drivers/interconnect/icc-kunit.c
13360
+
13355
13361
INTERRUPT COUNTER DRIVER
13356
13362
M: Oleksij Rempel <o.rempel@pengutronix.de>
13357
13363
R: Pengutronix Kernel Team <kernel@pengutronix.de>
+6
-3
drivers/interconnect/debugfs-client.c
+6
-3
drivers/interconnect/debugfs-client.c
···
150
150
return ret;
151
151
}
152
152
153
-
src_node = devm_kstrdup(&pdev->dev, "", GFP_KERNEL);
154
-
dst_node = devm_kstrdup(&pdev->dev, "", GFP_KERNEL);
155
-
if (!src_node || !dst_node)
153
+
src_node = kstrdup("", GFP_KERNEL);
154
+
dst_node = kstrdup("", GFP_KERNEL);
155
+
if (!src_node || !dst_node) {
156
+
kfree(dst_node);
157
+
kfree(src_node);
156
158
return -ENOMEM;
159
+
}
157
160
158
161
client_dir = debugfs_create_dir("test_client", icc_dir);
159
162
+11
-2
drivers/interconnect/qcom/Kconfig
+11
-2
drivers/interconnect/qcom/Kconfig
···
8
8
config INTERCONNECT_QCOM_BCM_VOTER
9
9
tristate
10
10
11
+
config INTERCONNECT_QCOM_ELIZA
12
+
tristate "Qualcomm Eliza interconnect driver"
13
+
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
14
+
select INTERCONNECT_QCOM_RPMH
15
+
select INTERCONNECT_QCOM_BCM_VOTER
16
+
help
17
+
This is a driver for the Qualcomm Network-on-Chip on Eliza-based
18
+
platforms.
19
+
11
20
config INTERCONNECT_QCOM_GLYMUR
12
-
tristate "Qualcomm GLYMUR interconnect driver"
21
+
tristate "Qualcomm Glymur interconnect driver"
13
22
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
14
23
select INTERCONNECT_QCOM_RPMH
15
24
select INTERCONNECT_QCOM_BCM_VOTER
···
27
18
platforms.
28
19
29
20
config INTERCONNECT_QCOM_KAANAPALI
30
-
tristate "Qualcomm KAANAPALI interconnect driver"
21
+
tristate "Qualcomm Kaanapali interconnect driver"
31
22
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
32
23
select INTERCONNECT_QCOM_RPMH
33
24
select INTERCONNECT_QCOM_BCM_VOTER
+2
drivers/interconnect/qcom/Makefile
+2
drivers/interconnect/qcom/Makefile
···
4
4
5
5
interconnect_qcom-y := icc-common.o
6
6
icc-bcm-voter-objs := bcm-voter.o
7
+
qnoc-eliza-objs := eliza.o
7
8
qnoc-glymur-objs := glymur.o
8
9
qnoc-kaanapali-objs := kaanapali.o
9
10
qnoc-milos-objs := milos.o
···
49
48
icc-smd-rpm-objs := smd-rpm.o icc-rpm.o icc-rpm-clocks.o
50
49
51
50
obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
51
+
obj-$(CONFIG_INTERCONNECT_QCOM_ELIZA) += qnoc-eliza.o
52
52
obj-$(CONFIG_INTERCONNECT_QCOM_GLYMUR) += qnoc-glymur.o
53
53
obj-$(CONFIG_INTERCONNECT_QCOM_KAANAPALI) += qnoc-kaanapali.o
54
54
obj-$(CONFIG_INTERCONNECT_QCOM_MILOS) += qnoc-milos.o
+1585
drivers/interconnect/qcom/eliza.c
+1585
drivers/interconnect/qcom/eliza.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
5
+
6
+
#include <linux/device.h>
7
+
#include <linux/interconnect.h>
8
+
#include <linux/interconnect-provider.h>
9
+
#include <linux/module.h>
10
+
#include <linux/of_platform.h>
11
+
#include <dt-bindings/interconnect/qcom,eliza-rpmh.h>
12
+
13
+
#include "bcm-voter.h"
14
+
#include "icc-rpmh.h"
15
+
16
+
static struct qcom_icc_node qup1_core_slave = {
17
+
.name = "qup1_core_slave",
18
+
.channels = 1,
19
+
.buswidth = 4,
20
+
};
21
+
22
+
static struct qcom_icc_node qup2_core_slave = {
23
+
.name = "qup2_core_slave",
24
+
.channels = 1,
25
+
.buswidth = 4,
26
+
};
27
+
28
+
static struct qcom_icc_node qhs_ahb2phy0 = {
29
+
.name = "qhs_ahb2phy0",
30
+
.channels = 1,
31
+
.buswidth = 4,
32
+
};
33
+
34
+
static struct qcom_icc_node qhs_ahb2phy1 = {
35
+
.name = "qhs_ahb2phy1",
36
+
.channels = 1,
37
+
.buswidth = 4,
38
+
};
39
+
40
+
static struct qcom_icc_node qhs_camera_cfg = {
41
+
.name = "qhs_camera_cfg",
42
+
.channels = 1,
43
+
.buswidth = 4,
44
+
};
45
+
46
+
static struct qcom_icc_node qhs_clk_ctl = {
47
+
.name = "qhs_clk_ctl",
48
+
.channels = 1,
49
+
.buswidth = 4,
50
+
};
51
+
52
+
static struct qcom_icc_node qhs_crypto0_cfg = {
53
+
.name = "qhs_crypto0_cfg",
54
+
.channels = 1,
55
+
.buswidth = 4,
56
+
};
57
+
58
+
static struct qcom_icc_node qhs_display_cfg = {
59
+
.name = "qhs_display_cfg",
60
+
.channels = 1,
61
+
.buswidth = 4,
62
+
};
63
+
64
+
static struct qcom_icc_node qhs_gpuss_cfg = {
65
+
.name = "qhs_gpuss_cfg",
66
+
.channels = 1,
67
+
.buswidth = 8,
68
+
};
69
+
70
+
static struct qcom_icc_node qhs_i3c_ibi0_cfg = {
71
+
.name = "qhs_i3c_ibi0_cfg",
72
+
.channels = 1,
73
+
.buswidth = 4,
74
+
};
75
+
76
+
static struct qcom_icc_node qhs_i3c_ibi1_cfg = {
77
+
.name = "qhs_i3c_ibi1_cfg",
78
+
.channels = 1,
79
+
.buswidth = 4,
80
+
};
81
+
82
+
static struct qcom_icc_node qhs_imem_cfg = {
83
+
.name = "qhs_imem_cfg",
84
+
.channels = 1,
85
+
.buswidth = 4,
86
+
};
87
+
88
+
static struct qcom_icc_node qhs_mss_cfg = {
89
+
.name = "qhs_mss_cfg",
90
+
.channels = 1,
91
+
.buswidth = 4,
92
+
};
93
+
94
+
static struct qcom_icc_node qhs_pcie_0_cfg = {
95
+
.name = "qhs_pcie_0_cfg",
96
+
.channels = 1,
97
+
.buswidth = 4,
98
+
};
99
+
100
+
static struct qcom_icc_node qhs_prng = {
101
+
.name = "qhs_prng",
102
+
.channels = 1,
103
+
.buswidth = 4,
104
+
};
105
+
106
+
static struct qcom_icc_node qhs_qdss_cfg = {
107
+
.name = "qhs_qdss_cfg",
108
+
.channels = 1,
109
+
.buswidth = 4,
110
+
};
111
+
112
+
static struct qcom_icc_node qhs_qspi = {
113
+
.name = "qhs_qspi",
114
+
.channels = 1,
115
+
.buswidth = 4,
116
+
};
117
+
118
+
static struct qcom_icc_node qhs_qup1 = {
119
+
.name = "qhs_qup1",
120
+
.channels = 1,
121
+
.buswidth = 4,
122
+
};
123
+
124
+
static struct qcom_icc_node qhs_qup2 = {
125
+
.name = "qhs_qup2",
126
+
.channels = 1,
127
+
.buswidth = 4,
128
+
};
129
+
130
+
static struct qcom_icc_node qhs_sdc2 = {
131
+
.name = "qhs_sdc2",
132
+
.channels = 1,
133
+
.buswidth = 4,
134
+
};
135
+
136
+
static struct qcom_icc_node qhs_tcsr = {
137
+
.name = "qhs_tcsr",
138
+
.channels = 1,
139
+
.buswidth = 4,
140
+
};
141
+
142
+
static struct qcom_icc_node qhs_tlmm = {
143
+
.name = "qhs_tlmm",
144
+
.channels = 1,
145
+
.buswidth = 4,
146
+
};
147
+
148
+
static struct qcom_icc_node qhs_ufs_mem_cfg = {
149
+
.name = "qhs_ufs_mem_cfg",
150
+
.channels = 1,
151
+
.buswidth = 4,
152
+
};
153
+
154
+
static struct qcom_icc_node qhs_usb3_0 = {
155
+
.name = "qhs_usb3_0",
156
+
.channels = 1,
157
+
.buswidth = 4,
158
+
};
159
+
160
+
static struct qcom_icc_node qhs_venus_cfg = {
161
+
.name = "qhs_venus_cfg",
162
+
.channels = 1,
163
+
.buswidth = 4,
164
+
};
165
+
166
+
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
167
+
.name = "qhs_vsense_ctrl_cfg",
168
+
.channels = 1,
169
+
.buswidth = 4,
170
+
};
171
+
172
+
static struct qcom_icc_node xs_qdss_stm = {
173
+
.name = "xs_qdss_stm",
174
+
.channels = 1,
175
+
.buswidth = 4,
176
+
};
177
+
178
+
static struct qcom_icc_node xs_sys_tcu_cfg = {
179
+
.name = "xs_sys_tcu_cfg",
180
+
.channels = 1,
181
+
.buswidth = 8,
182
+
};
183
+
184
+
static struct qcom_icc_node qhs_aoss = {
185
+
.name = "qhs_aoss",
186
+
.channels = 1,
187
+
.buswidth = 4,
188
+
};
189
+
190
+
static struct qcom_icc_node qhs_ipa = {
191
+
.name = "qhs_ipa",
192
+
.channels = 1,
193
+
.buswidth = 4,
194
+
};
195
+
196
+
static struct qcom_icc_node qhs_ipc_router = {
197
+
.name = "qhs_ipc_router",
198
+
.channels = 1,
199
+
.buswidth = 4,
200
+
};
201
+
202
+
static struct qcom_icc_node qhs_soccp = {
203
+
.name = "qhs_soccp",
204
+
.channels = 1,
205
+
.buswidth = 4,
206
+
};
207
+
208
+
static struct qcom_icc_node qhs_tme_cfg = {
209
+
.name = "qhs_tme_cfg",
210
+
.channels = 1,
211
+
.buswidth = 4,
212
+
};
213
+
214
+
static struct qcom_icc_node qss_apss = {
215
+
.name = "qss_apss",
216
+
.channels = 1,
217
+
.buswidth = 4,
218
+
};
219
+
220
+
static struct qcom_icc_node qss_ddrss_cfg = {
221
+
.name = "qss_ddrss_cfg",
222
+
.channels = 1,
223
+
.buswidth = 4,
224
+
};
225
+
226
+
static struct qcom_icc_node qxs_boot_imem = {
227
+
.name = "qxs_boot_imem",
228
+
.channels = 1,
229
+
.buswidth = 16,
230
+
};
231
+
232
+
static struct qcom_icc_node qxs_imem = {
233
+
.name = "qxs_imem",
234
+
.channels = 1,
235
+
.buswidth = 8,
236
+
};
237
+
238
+
static struct qcom_icc_node qxs_modem_boot_imem = {
239
+
.name = "qxs_modem_boot_imem",
240
+
.channels = 1,
241
+
.buswidth = 8,
242
+
};
243
+
244
+
static struct qcom_icc_node srvc_cnoc_main = {
245
+
.name = "srvc_cnoc_main",
246
+
.channels = 1,
247
+
.buswidth = 4,
248
+
};
249
+
250
+
static struct qcom_icc_node xs_pcie_0 = {
251
+
.name = "xs_pcie_0",
252
+
.channels = 1,
253
+
.buswidth = 8,
254
+
};
255
+
256
+
static struct qcom_icc_node xs_pcie_1 = {
257
+
.name = "xs_pcie_1",
258
+
.channels = 1,
259
+
.buswidth = 8,
260
+
};
261
+
262
+
static struct qcom_icc_node ebi = {
263
+
.name = "ebi",
264
+
.channels = 4,
265
+
.buswidth = 4,
266
+
};
267
+
268
+
static struct qcom_icc_node srvc_mnoc_sf = {
269
+
.name = "srvc_mnoc_sf",
270
+
.channels = 1,
271
+
.buswidth = 4,
272
+
};
273
+
274
+
static struct qcom_icc_node srvc_mnoc_hf = {
275
+
.name = "srvc_mnoc_hf",
276
+
.channels = 1,
277
+
.buswidth = 4,
278
+
};
279
+
280
+
static struct qcom_icc_node srvc_pcie_aggre_noc = {
281
+
.name = "srvc_pcie_aggre_noc",
282
+
.channels = 1,
283
+
.buswidth = 4,
284
+
};
285
+
286
+
static struct qcom_icc_node qup1_core_master = {
287
+
.name = "qup1_core_master",
288
+
.channels = 1,
289
+
.buswidth = 4,
290
+
.num_links = 1,
291
+
.link_nodes = { &qup1_core_slave },
292
+
};
293
+
294
+
static struct qcom_icc_node qup2_core_master = {
295
+
.name = "qup2_core_master",
296
+
.channels = 1,
297
+
.buswidth = 4,
298
+
.num_links = 1,
299
+
.link_nodes = { &qup2_core_slave },
300
+
};
301
+
302
+
static struct qcom_icc_node qnm_gemnoc_pcie = {
303
+
.name = "qnm_gemnoc_pcie",
304
+
.channels = 1,
305
+
.buswidth = 16,
306
+
.num_links = 2,
307
+
.link_nodes = { &xs_pcie_0, &xs_pcie_1 },
308
+
};
309
+
310
+
static struct qcom_icc_node llcc_mc = {
311
+
.name = "llcc_mc",
312
+
.channels = 4,
313
+
.buswidth = 4,
314
+
.num_links = 1,
315
+
.link_nodes = { &ebi },
316
+
};
317
+
318
+
static struct qcom_icc_node qsm_sf_mnoc_cfg = {
319
+
.name = "qsm_sf_mnoc_cfg",
320
+
.channels = 1,
321
+
.buswidth = 4,
322
+
.num_links = 1,
323
+
.link_nodes = { &srvc_mnoc_sf },
324
+
};
325
+
326
+
static struct qcom_icc_node qsm_hf_mnoc_cfg = {
327
+
.name = "qsm_hf_mnoc_cfg",
328
+
.channels = 1,
329
+
.buswidth = 4,
330
+
.num_links = 1,
331
+
.link_nodes = { &srvc_mnoc_hf },
332
+
};
333
+
334
+
static struct qcom_icc_node qsm_pcie_anoc_cfg = {
335
+
.name = "qsm_pcie_anoc_cfg",
336
+
.channels = 1,
337
+
.buswidth = 4,
338
+
.num_links = 1,
339
+
.link_nodes = { &srvc_pcie_aggre_noc },
340
+
};
341
+
342
+
static struct qcom_icc_node qss_mnoc_hf_cfg = {
343
+
.name = "qss_mnoc_hf_cfg",
344
+
.channels = 1,
345
+
.buswidth = 4,
346
+
.num_links = 1,
347
+
.link_nodes = { &qsm_hf_mnoc_cfg },
348
+
};
349
+
350
+
static struct qcom_icc_node qss_mnoc_sf_cfg = {
351
+
.name = "qss_mnoc_sf_cfg",
352
+
.channels = 1,
353
+
.buswidth = 4,
354
+
.num_links = 1,
355
+
.link_nodes = { &qsm_sf_mnoc_cfg },
356
+
};
357
+
358
+
static struct qcom_icc_node qss_pcie_anoc_cfg = {
359
+
.name = "qss_pcie_anoc_cfg",
360
+
.channels = 1,
361
+
.buswidth = 4,
362
+
.num_links = 1,
363
+
.link_nodes = { &qsm_pcie_anoc_cfg },
364
+
};
365
+
366
+
static struct qcom_icc_node qns_llcc = {
367
+
.name = "qns_llcc",
368
+
.channels = 2,
369
+
.buswidth = 16,
370
+
.num_links = 1,
371
+
.link_nodes = { &llcc_mc },
372
+
};
373
+
374
+
static struct qcom_icc_node qns_pcie = {
375
+
.name = "qns_pcie",
376
+
.channels = 1,
377
+
.buswidth = 16,
378
+
.num_links = 1,
379
+
.link_nodes = { &qnm_gemnoc_pcie },
380
+
};
381
+
382
+
static struct qcom_icc_node qsm_cfg = {
383
+
.name = "qsm_cfg",
384
+
.channels = 1,
385
+
.buswidth = 4,
386
+
.num_links = 29,
387
+
.link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
388
+
&qhs_camera_cfg, &qhs_clk_ctl,
389
+
&qhs_crypto0_cfg, &qhs_display_cfg,
390
+
&qhs_gpuss_cfg, &qhs_i3c_ibi0_cfg,
391
+
&qhs_i3c_ibi1_cfg, &qhs_imem_cfg,
392
+
&qhs_mss_cfg, &qhs_pcie_0_cfg,
393
+
&qhs_prng, &qhs_qdss_cfg,
394
+
&qhs_qspi, &qhs_qup1,
395
+
&qhs_qup2, &qhs_sdc2,
396
+
&qhs_tcsr, &qhs_tlmm,
397
+
&qhs_ufs_mem_cfg, &qhs_usb3_0,
398
+
&qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
399
+
&qss_mnoc_hf_cfg, &qss_mnoc_sf_cfg,
400
+
&qss_pcie_anoc_cfg, &xs_qdss_stm,
401
+
&xs_sys_tcu_cfg },
402
+
};
403
+
404
+
static struct qcom_icc_node xm_gic = {
405
+
.name = "xm_gic",
406
+
.channels = 1,
407
+
.buswidth = 8,
408
+
.qosbox = &(const struct qcom_icc_qosbox) {
409
+
.num_ports = 1,
410
+
.port_offsets = { 0x15d000 },
411
+
.prio = 4,
412
+
.urg_fwd = 0,
413
+
.prio_fwd_disable = 1,
414
+
},
415
+
.num_links = 1,
416
+
.link_nodes = { &qns_llcc },
417
+
};
418
+
419
+
static struct qcom_icc_node qss_cfg = {
420
+
.name = "qss_cfg",
421
+
.channels = 1,
422
+
.buswidth = 4,
423
+
.num_links = 1,
424
+
.link_nodes = { &qsm_cfg },
425
+
};
426
+
427
+
static struct qcom_icc_node qnm_gemnoc_cnoc = {
428
+
.name = "qnm_gemnoc_cnoc",
429
+
.channels = 1,
430
+
.buswidth = 16,
431
+
.num_links = 12,
432
+
.link_nodes = { &qhs_aoss, &qhs_ipa,
433
+
&qhs_ipc_router, &qhs_soccp,
434
+
&qhs_tme_cfg, &qss_apss,
435
+
&qss_cfg, &qss_ddrss_cfg,
436
+
&qxs_boot_imem, &qxs_imem,
437
+
&qxs_modem_boot_imem, &srvc_cnoc_main },
438
+
};
439
+
440
+
static struct qcom_icc_node qns_gem_noc_cnoc = {
441
+
.name = "qns_gem_noc_cnoc",
442
+
.channels = 1,
443
+
.buswidth = 16,
444
+
.num_links = 1,
445
+
.link_nodes = { &qnm_gemnoc_cnoc },
446
+
};
447
+
448
+
static struct qcom_icc_qosbox alm_gpu_tcu_qos = {
449
+
.num_ports = 1,
450
+
.port_offsets = { 0x155000 },
451
+
.prio = 1,
452
+
.urg_fwd = 0,
453
+
.prio_fwd_disable = 1,
454
+
};
455
+
456
+
static struct qcom_icc_node alm_gpu_tcu = {
457
+
.name = "alm_gpu_tcu",
458
+
.channels = 1,
459
+
.buswidth = 8,
460
+
.qosbox = &alm_gpu_tcu_qos,
461
+
.num_links = 2,
462
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
463
+
};
464
+
465
+
static struct qcom_icc_qosbox alm_sys_tcu_qos = {
466
+
.num_ports = 1,
467
+
.port_offsets = { 0x157000 },
468
+
.prio = 6,
469
+
.urg_fwd = 0,
470
+
.prio_fwd_disable = 1,
471
+
};
472
+
473
+
static struct qcom_icc_node alm_sys_tcu = {
474
+
.name = "alm_sys_tcu",
475
+
.channels = 1,
476
+
.buswidth = 8,
477
+
.qosbox = &alm_sys_tcu_qos,
478
+
.num_links = 2,
479
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
480
+
};
481
+
482
+
static struct qcom_icc_node chm_apps = {
483
+
.name = "chm_apps",
484
+
.channels = 3,
485
+
.buswidth = 32,
486
+
.num_links = 3,
487
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
488
+
&qns_pcie },
489
+
};
490
+
491
+
static struct qcom_icc_qosbox qnm_gpu_qos = {
492
+
.num_ports = 2,
493
+
.port_offsets = { 0x31000, 0xb1000 },
494
+
.prio = 0,
495
+
.urg_fwd = 1,
496
+
.prio_fwd_disable = 1,
497
+
};
498
+
499
+
static struct qcom_icc_node qnm_gpu = {
500
+
.name = "qnm_gpu",
501
+
.channels = 2,
502
+
.buswidth = 32,
503
+
.qosbox = &qnm_gpu_qos,
504
+
.num_links = 2,
505
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
506
+
};
507
+
508
+
static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = {
509
+
.num_ports = 1,
510
+
.port_offsets = { 0x159000 },
511
+
.prio = 0,
512
+
.urg_fwd = 1,
513
+
.prio_fwd_disable = 0,
514
+
};
515
+
516
+
static struct qcom_icc_node qnm_lpass_gemnoc = {
517
+
.name = "qnm_lpass_gemnoc",
518
+
.channels = 1,
519
+
.buswidth = 16,
520
+
.qosbox = &qnm_lpass_gemnoc_qos,
521
+
.num_links = 3,
522
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
523
+
&qns_pcie },
524
+
};
525
+
526
+
static struct qcom_icc_node qnm_mdsp = {
527
+
.name = "qnm_mdsp",
528
+
.channels = 1,
529
+
.buswidth = 16,
530
+
.num_links = 3,
531
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
532
+
&qns_pcie },
533
+
};
534
+
535
+
static struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
536
+
.num_ports = 2,
537
+
.port_offsets = { 0x33000, 0xb3000 },
538
+
.prio = 0,
539
+
.urg_fwd = 1,
540
+
.prio_fwd_disable = 0,
541
+
};
542
+
543
+
static struct qcom_icc_node qnm_mnoc_hf = {
544
+
.name = "qnm_mnoc_hf",
545
+
.channels = 2,
546
+
.buswidth = 32,
547
+
.qosbox = &qnm_mnoc_hf_qos,
548
+
.num_links = 2,
549
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
550
+
};
551
+
552
+
static struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
553
+
.num_ports = 2,
554
+
.port_offsets = { 0x35000, 0xb5000 },
555
+
.prio = 0,
556
+
.urg_fwd = 0,
557
+
.prio_fwd_disable = 0,
558
+
};
559
+
560
+
static struct qcom_icc_node qnm_mnoc_sf = {
561
+
.name = "qnm_mnoc_sf",
562
+
.channels = 2,
563
+
.buswidth = 32,
564
+
.qosbox = &qnm_mnoc_sf_qos,
565
+
.num_links = 2,
566
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
567
+
};
568
+
569
+
static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
570
+
.num_ports = 2,
571
+
.port_offsets = { 0x37000, 0xb7000 },
572
+
.prio = 0,
573
+
.urg_fwd = 1,
574
+
.prio_fwd_disable = 1,
575
+
};
576
+
577
+
static struct qcom_icc_node qnm_nsp_gemnoc = {
578
+
.name = "qnm_nsp_gemnoc",
579
+
.channels = 2,
580
+
.buswidth = 32,
581
+
.qosbox = &qnm_nsp_gemnoc_qos,
582
+
.num_links = 3,
583
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
584
+
&qns_pcie },
585
+
};
586
+
587
+
static struct qcom_icc_qosbox qnm_pcie_qos = {
588
+
.num_ports = 1,
589
+
.port_offsets = { 0x15b000 },
590
+
.prio = 2,
591
+
.urg_fwd = 1,
592
+
.prio_fwd_disable = 0,
593
+
};
594
+
595
+
static struct qcom_icc_node qnm_pcie = {
596
+
.name = "qnm_pcie",
597
+
.channels = 1,
598
+
.buswidth = 16,
599
+
.qosbox = &qnm_pcie_qos,
600
+
.num_links = 2,
601
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
602
+
};
603
+
604
+
static struct qcom_icc_node qnm_snoc_sf = {
605
+
.name = "qnm_snoc_sf",
606
+
.channels = 1,
607
+
.buswidth = 16,
608
+
.qosbox = &(const struct qcom_icc_qosbox) {
609
+
.num_ports = 1,
610
+
.port_offsets = { 0x15f000 },
611
+
.prio = 0,
612
+
.urg_fwd = 1,
613
+
.prio_fwd_disable = 0,
614
+
},
615
+
.num_links = 3,
616
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
617
+
&qns_pcie },
618
+
};
619
+
620
+
static struct qcom_icc_node qxm_wlan_q6 = {
621
+
.name = "qxm_wlan_q6",
622
+
.channels = 1,
623
+
.buswidth = 8,
624
+
.num_links = 3,
625
+
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
626
+
&qns_pcie },
627
+
};
628
+
629
+
static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
630
+
.name = "qns_lpass_ag_noc_gemnoc",
631
+
.channels = 1,
632
+
.buswidth = 16,
633
+
.num_links = 1,
634
+
.link_nodes = { &qnm_lpass_gemnoc },
635
+
};
636
+
637
+
static struct qcom_icc_node qns_mem_noc_sf = {
638
+
.name = "qns_mem_noc_sf",
639
+
.channels = 2,
640
+
.buswidth = 32,
641
+
.num_links = 1,
642
+
.link_nodes = { &qnm_mnoc_sf },
643
+
};
644
+
645
+
static struct qcom_icc_node qns_mem_noc_hf = {
646
+
.name = "qns_mem_noc_hf",
647
+
.channels = 2,
648
+
.buswidth = 32,
649
+
.num_links = 1,
650
+
.link_nodes = { &qnm_mnoc_hf },
651
+
};
652
+
653
+
static struct qcom_icc_node qns_nsp_gemnoc = {
654
+
.name = "qns_nsp_gemnoc",
655
+
.channels = 2,
656
+
.buswidth = 32,
657
+
.num_links = 1,
658
+
.link_nodes = { &qnm_nsp_gemnoc },
659
+
};
660
+
661
+
static struct qcom_icc_node qns_pcie_mem_noc = {
662
+
.name = "qns_pcie_mem_noc",
663
+
.channels = 1,
664
+
.buswidth = 16,
665
+
.num_links = 1,
666
+
.link_nodes = { &qnm_pcie },
667
+
};
668
+
669
+
static struct qcom_icc_node qns_gemnoc_sf = {
670
+
.name = "qns_gemnoc_sf",
671
+
.channels = 1,
672
+
.buswidth = 16,
673
+
.num_links = 1,
674
+
.link_nodes = { &qnm_snoc_sf },
675
+
};
676
+
677
+
static struct qcom_icc_node qnm_lpiaon_noc = {
678
+
.name = "qnm_lpiaon_noc",
679
+
.channels = 1,
680
+
.buswidth = 16,
681
+
.num_links = 1,
682
+
.link_nodes = { &qns_lpass_ag_noc_gemnoc },
683
+
};
684
+
685
+
static struct qcom_icc_qosbox qnm_camnoc_nrt_icp_sf_qos = {
686
+
.num_ports = 1,
687
+
.port_offsets = { 0x25000 },
688
+
.prio = 4,
689
+
.urg_fwd = 0,
690
+
.prio_fwd_disable = 1,
691
+
};
692
+
693
+
static struct qcom_icc_node qnm_camnoc_nrt_icp_sf = {
694
+
.name = "qnm_camnoc_nrt_icp_sf",
695
+
.channels = 1,
696
+
.buswidth = 8,
697
+
.qosbox = &qnm_camnoc_nrt_icp_sf_qos,
698
+
.num_links = 1,
699
+
.link_nodes = { &qns_mem_noc_sf },
700
+
};
701
+
702
+
static struct qcom_icc_node qnm_camnoc_rt_cdm_sf = {
703
+
.name = "qnm_camnoc_rt_cdm_sf",
704
+
.channels = 1,
705
+
.buswidth = 8,
706
+
.qosbox = &(const struct qcom_icc_qosbox) {
707
+
.num_ports = 1,
708
+
.port_offsets = { 0x2c000 },
709
+
.prio = 2,
710
+
.urg_fwd = 0,
711
+
.prio_fwd_disable = 1,
712
+
},
713
+
.num_links = 1,
714
+
.link_nodes = { &qns_mem_noc_sf },
715
+
};
716
+
717
+
static struct qcom_icc_node qnm_camnoc_sf = {
718
+
.name = "qnm_camnoc_sf",
719
+
.channels = 2,
720
+
.buswidth = 32,
721
+
.qosbox = &(const struct qcom_icc_qosbox) {
722
+
.num_ports = 2,
723
+
.port_offsets = { 0x26000, 0x27000 },
724
+
.prio = 0,
725
+
.urg_fwd = 1,
726
+
.prio_fwd_disable = 0,
727
+
},
728
+
.num_links = 1,
729
+
.link_nodes = { &qns_mem_noc_sf },
730
+
};
731
+
732
+
static struct qcom_icc_node qnm_video_mvp = {
733
+
.name = "qnm_video_mvp",
734
+
.channels = 1,
735
+
.buswidth = 32,
736
+
.qosbox = &(const struct qcom_icc_qosbox) {
737
+
.num_ports = 1,
738
+
.port_offsets = { 0x28000 },
739
+
.prio = 0,
740
+
.urg_fwd = 1,
741
+
.prio_fwd_disable = 0,
742
+
},
743
+
.num_links = 1,
744
+
.link_nodes = { &qns_mem_noc_sf },
745
+
};
746
+
747
+
static struct qcom_icc_node qnm_video_v_cpu = {
748
+
.name = "qnm_video_v_cpu",
749
+
.channels = 1,
750
+
.buswidth = 8,
751
+
.qosbox = &(const struct qcom_icc_qosbox) {
752
+
.num_ports = 1,
753
+
.port_offsets = { 0x2b000 },
754
+
.prio = 4,
755
+
.urg_fwd = 0,
756
+
.prio_fwd_disable = 1,
757
+
},
758
+
.num_links = 1,
759
+
.link_nodes = { &qns_mem_noc_sf },
760
+
};
761
+
762
+
static struct qcom_icc_node qnm_camnoc_hf = {
763
+
.name = "qnm_camnoc_hf",
764
+
.channels = 2,
765
+
.buswidth = 32,
766
+
.qosbox = &(const struct qcom_icc_qosbox) {
767
+
.num_ports = 2,
768
+
.port_offsets = { 0x64000, 0x65000 },
769
+
.prio = 0,
770
+
.urg_fwd = 1,
771
+
.prio_fwd_disable = 0,
772
+
},
773
+
.num_links = 1,
774
+
.link_nodes = { &qns_mem_noc_hf },
775
+
};
776
+
777
+
static struct qcom_icc_node qnm_mdp = {
778
+
.name = "qnm_mdp",
779
+
.channels = 2,
780
+
.buswidth = 32,
781
+
.qosbox = &(const struct qcom_icc_qosbox) {
782
+
.num_ports = 2,
783
+
.port_offsets = { 0x66000, 0x67000 },
784
+
.prio = 0,
785
+
.urg_fwd = 1,
786
+
.prio_fwd_disable = 0,
787
+
},
788
+
.num_links = 1,
789
+
.link_nodes = { &qns_mem_noc_hf },
790
+
};
791
+
792
+
static struct qcom_icc_node qxm_nsp = {
793
+
.name = "qxm_nsp",
794
+
.channels = 2,
795
+
.buswidth = 32,
796
+
.num_links = 1,
797
+
.link_nodes = { &qns_nsp_gemnoc },
798
+
};
799
+
800
+
static struct qcom_icc_node xm_pcie3_0 = {
801
+
.name = "xm_pcie3_0",
802
+
.channels = 1,
803
+
.buswidth = 8,
804
+
.qosbox = &(const struct qcom_icc_qosbox) {
805
+
.num_ports = 1,
806
+
.port_offsets = { 0xb000 },
807
+
.prio = 3,
808
+
.urg_fwd = 0,
809
+
.prio_fwd_disable = 1,
810
+
},
811
+
.num_links = 1,
812
+
.link_nodes = { &qns_pcie_mem_noc },
813
+
};
814
+
815
+
static struct qcom_icc_node xm_pcie3_1 = {
816
+
.name = "xm_pcie3_1",
817
+
.channels = 1,
818
+
.buswidth = 8,
819
+
.qosbox = &(const struct qcom_icc_qosbox) {
820
+
.num_ports = 1,
821
+
.port_offsets = { 0xc000 },
822
+
.prio = 3,
823
+
.urg_fwd = 0,
824
+
.prio_fwd_disable = 1,
825
+
},
826
+
.num_links = 1,
827
+
.link_nodes = { &qns_pcie_mem_noc },
828
+
};
829
+
830
+
static struct qcom_icc_node qnm_aggre1_noc = {
831
+
.name = "qnm_aggre1_noc",
832
+
.channels = 1,
833
+
.buswidth = 16,
834
+
.num_links = 1,
835
+
.link_nodes = { &qns_gemnoc_sf },
836
+
};
837
+
838
+
static struct qcom_icc_node qnm_aggre2_noc = {
839
+
.name = "qnm_aggre2_noc",
840
+
.channels = 1,
841
+
.buswidth = 16,
842
+
.num_links = 1,
843
+
.link_nodes = { &qns_gemnoc_sf },
844
+
};
845
+
846
+
static struct qcom_icc_node qnm_cnoc_data = {
847
+
.name = "qnm_cnoc_data",
848
+
.channels = 1,
849
+
.buswidth = 8,
850
+
.qosbox = &(const struct qcom_icc_qosbox) {
851
+
.num_ports = 1,
852
+
.port_offsets = { 0x1d000 },
853
+
.prio = 2,
854
+
.urg_fwd = 0,
855
+
.prio_fwd_disable = 1,
856
+
},
857
+
.num_links = 1,
858
+
.link_nodes = { &qns_gemnoc_sf },
859
+
};
860
+
861
+
static struct qcom_icc_node qnm_nsinoc_snoc = {
862
+
.name = "qnm_nsinoc_snoc",
863
+
.channels = 1,
864
+
.buswidth = 8,
865
+
.qosbox = &(const struct qcom_icc_qosbox) {
866
+
.num_ports = 1,
867
+
.port_offsets = { 0x1c000 },
868
+
.prio = 2,
869
+
.urg_fwd = 0,
870
+
.prio_fwd_disable = 1,
871
+
},
872
+
.num_links = 1,
873
+
.link_nodes = { &qns_gemnoc_sf },
874
+
};
875
+
876
+
static struct qcom_icc_node qns_a1noc_snoc = {
877
+
.name = "qns_a1noc_snoc",
878
+
.channels = 1,
879
+
.buswidth = 16,
880
+
.num_links = 1,
881
+
.link_nodes = { &qnm_aggre1_noc },
882
+
};
883
+
884
+
static struct qcom_icc_node qns_a2noc_snoc = {
885
+
.name = "qns_a2noc_snoc",
886
+
.channels = 1,
887
+
.buswidth = 16,
888
+
.num_links = 1,
889
+
.link_nodes = { &qnm_aggre2_noc },
890
+
};
891
+
892
+
static struct qcom_icc_node qns_lpass_aggnoc = {
893
+
.name = "qns_lpass_aggnoc",
894
+
.channels = 1,
895
+
.buswidth = 16,
896
+
.num_links = 1,
897
+
.link_nodes = { &qnm_lpiaon_noc },
898
+
};
899
+
900
+
static struct qcom_icc_node qhm_qspi = {
901
+
.name = "qhm_qspi",
902
+
.channels = 1,
903
+
.buswidth = 4,
904
+
.qosbox = &(const struct qcom_icc_qosbox) {
905
+
.num_ports = 1,
906
+
.port_offsets = { 0xc000 },
907
+
.prio = 2,
908
+
.urg_fwd = 0,
909
+
.prio_fwd_disable = 1,
910
+
},
911
+
.num_links = 1,
912
+
.link_nodes = { &qns_a1noc_snoc },
913
+
};
914
+
915
+
static struct qcom_icc_node qhm_qup1 = {
916
+
.name = "qhm_qup1",
917
+
.channels = 1,
918
+
.buswidth = 4,
919
+
.qosbox = &(const struct qcom_icc_qosbox) {
920
+
.num_ports = 1,
921
+
.port_offsets = { 0xd000 },
922
+
.prio = 2,
923
+
.urg_fwd = 0,
924
+
.prio_fwd_disable = 1,
925
+
},
926
+
.num_links = 1,
927
+
.link_nodes = { &qns_a1noc_snoc },
928
+
};
929
+
930
+
static struct qcom_icc_node xm_ufs_mem = {
931
+
.name = "xm_ufs_mem",
932
+
.channels = 1,
933
+
.buswidth = 16,
934
+
.qosbox = &(const struct qcom_icc_qosbox) {
935
+
.num_ports = 1,
936
+
.port_offsets = { 0xf000 },
937
+
.prio = 2,
938
+
.urg_fwd = 0,
939
+
.prio_fwd_disable = 1,
940
+
},
941
+
.num_links = 1,
942
+
.link_nodes = { &qns_a1noc_snoc },
943
+
};
944
+
945
+
static struct qcom_icc_node xm_usb3_0 = {
946
+
.name = "xm_usb3_0",
947
+
.channels = 1,
948
+
.buswidth = 8,
949
+
.qosbox = &(const struct qcom_icc_qosbox) {
950
+
.num_ports = 1,
951
+
.port_offsets = { 0x10000 },
952
+
.prio = 2,
953
+
.urg_fwd = 0,
954
+
.prio_fwd_disable = 1,
955
+
},
956
+
.num_links = 1,
957
+
.link_nodes = { &qns_a1noc_snoc },
958
+
};
959
+
960
+
static struct qcom_icc_node qhm_qup2 = {
961
+
.name = "qhm_qup2",
962
+
.channels = 1,
963
+
.buswidth = 4,
964
+
.qosbox = &(const struct qcom_icc_qosbox) {
965
+
.num_ports = 1,
966
+
.port_offsets = { 0x14000 },
967
+
.prio = 2,
968
+
.urg_fwd = 0,
969
+
.prio_fwd_disable = 1,
970
+
},
971
+
.num_links = 1,
972
+
.link_nodes = { &qns_a2noc_snoc },
973
+
};
974
+
975
+
static struct qcom_icc_node qxm_crypto = {
976
+
.name = "qxm_crypto",
977
+
.channels = 1,
978
+
.buswidth = 8,
979
+
.qosbox = &(const struct qcom_icc_qosbox) {
980
+
.num_ports = 1,
981
+
.port_offsets = { 0x15000 },
982
+
.prio = 2,
983
+
.urg_fwd = 0,
984
+
.prio_fwd_disable = 1,
985
+
},
986
+
.num_links = 1,
987
+
.link_nodes = { &qns_a2noc_snoc },
988
+
};
989
+
990
+
static struct qcom_icc_node qxm_ipa = {
991
+
.name = "qxm_ipa",
992
+
.channels = 1,
993
+
.buswidth = 8,
994
+
.qosbox = &(const struct qcom_icc_qosbox) {
995
+
.num_ports = 1,
996
+
.port_offsets = { 0x16000 },
997
+
.prio = 2,
998
+
.urg_fwd = 0,
999
+
.prio_fwd_disable = 1,
1000
+
},
1001
+
.num_links = 1,
1002
+
.link_nodes = { &qns_a2noc_snoc },
1003
+
};
1004
+
1005
+
static struct qcom_icc_node qxm_soccp = {
1006
+
.name = "qxm_soccp",
1007
+
.channels = 1,
1008
+
.buswidth = 8,
1009
+
.qosbox = &(const struct qcom_icc_qosbox) {
1010
+
.num_ports = 1,
1011
+
.port_offsets = { 0x1a000 },
1012
+
.prio = 2,
1013
+
.urg_fwd = 0,
1014
+
.prio_fwd_disable = 1,
1015
+
},
1016
+
.num_links = 1,
1017
+
.link_nodes = { &qns_a2noc_snoc },
1018
+
};
1019
+
1020
+
static struct qcom_icc_node xm_qdss_etr_0 = {
1021
+
.name = "xm_qdss_etr_0",
1022
+
.channels = 1,
1023
+
.buswidth = 8,
1024
+
.qosbox = &(const struct qcom_icc_qosbox) {
1025
+
.num_ports = 1,
1026
+
.port_offsets = { 0x17000 },
1027
+
.prio = 2,
1028
+
.urg_fwd = 0,
1029
+
.prio_fwd_disable = 1,
1030
+
},
1031
+
.num_links = 1,
1032
+
.link_nodes = { &qns_a2noc_snoc },
1033
+
};
1034
+
1035
+
static struct qcom_icc_node xm_qdss_etr_1 = {
1036
+
.name = "xm_qdss_etr_1",
1037
+
.channels = 1,
1038
+
.buswidth = 8,
1039
+
.qosbox = &(const struct qcom_icc_qosbox) {
1040
+
.num_ports = 1,
1041
+
.port_offsets = { 0x18000 },
1042
+
.prio = 2,
1043
+
.urg_fwd = 0,
1044
+
.prio_fwd_disable = 1,
1045
+
},
1046
+
.num_links = 1,
1047
+
.link_nodes = { &qns_a2noc_snoc },
1048
+
};
1049
+
1050
+
static struct qcom_icc_node xm_sdc1 = {
1051
+
.name = "xm_sdc1",
1052
+
.channels = 1,
1053
+
.buswidth = 8,
1054
+
.qosbox = &(const struct qcom_icc_qosbox) {
1055
+
.num_ports = 1,
1056
+
.port_offsets = { 0x13000 },
1057
+
.prio = 2,
1058
+
.urg_fwd = 0,
1059
+
.prio_fwd_disable = 1,
1060
+
},
1061
+
.num_links = 1,
1062
+
.link_nodes = { &qns_a2noc_snoc },
1063
+
};
1064
+
1065
+
static struct qcom_icc_node xm_sdc2 = {
1066
+
.name = "xm_sdc2",
1067
+
.channels = 1,
1068
+
.buswidth = 8,
1069
+
.qosbox = &(const struct qcom_icc_qosbox) {
1070
+
.num_ports = 1,
1071
+
.port_offsets = { 0x19000 },
1072
+
.prio = 2,
1073
+
.urg_fwd = 0,
1074
+
.prio_fwd_disable = 1,
1075
+
},
1076
+
.num_links = 1,
1077
+
.link_nodes = { &qns_a2noc_snoc },
1078
+
};
1079
+
1080
+
static struct qcom_icc_node qnm_lpass_lpinoc = {
1081
+
.name = "qnm_lpass_lpinoc",
1082
+
.channels = 1,
1083
+
.buswidth = 16,
1084
+
.num_links = 1,
1085
+
.link_nodes = { &qns_lpass_aggnoc },
1086
+
};
1087
+
1088
+
static struct qcom_icc_node qns_lpi_aon_noc = {
1089
+
.name = "qns_lpi_aon_noc",
1090
+
.channels = 1,
1091
+
.buswidth = 16,
1092
+
.num_links = 1,
1093
+
.link_nodes = { &qnm_lpass_lpinoc },
1094
+
};
1095
+
1096
+
static struct qcom_icc_node qxm_lpinoc_dsp_axim = {
1097
+
.name = "qxm_lpinoc_dsp_axim",
1098
+
.channels = 1,
1099
+
.buswidth = 16,
1100
+
.num_links = 1,
1101
+
.link_nodes = { &qns_lpi_aon_noc },
1102
+
};
1103
+
1104
+
static struct qcom_icc_bcm bcm_ce0 = {
1105
+
.name = "CE0",
1106
+
.num_nodes = 1,
1107
+
.nodes = { &qxm_crypto },
1108
+
};
1109
+
1110
+
static struct qcom_icc_bcm bcm_cn0 = {
1111
+
.name = "CN0",
1112
+
.enable_mask = BIT(0),
1113
+
.keepalive = true,
1114
+
.num_nodes = 43,
1115
+
.nodes = { &qsm_cfg, &qhs_ahb2phy0,
1116
+
&qhs_ahb2phy1, &qhs_camera_cfg,
1117
+
&qhs_clk_ctl, &qhs_crypto0_cfg,
1118
+
&qhs_gpuss_cfg, &qhs_i3c_ibi0_cfg,
1119
+
&qhs_i3c_ibi1_cfg, &qhs_imem_cfg,
1120
+
&qhs_mss_cfg, &qhs_pcie_0_cfg,
1121
+
&qhs_prng, &qhs_qdss_cfg,
1122
+
&qhs_qspi, &qhs_sdc2,
1123
+
&qhs_tcsr, &qhs_tlmm,
1124
+
&qhs_ufs_mem_cfg, &qhs_usb3_0,
1125
+
&qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
1126
+
&qss_mnoc_hf_cfg, &qss_mnoc_sf_cfg,
1127
+
&qss_pcie_anoc_cfg, &xs_qdss_stm,
1128
+
&xs_sys_tcu_cfg, &qnm_gemnoc_cnoc,
1129
+
&qnm_gemnoc_pcie, &qhs_aoss,
1130
+
&qhs_ipa, &qhs_ipc_router,
1131
+
&qhs_soccp, &qhs_tme_cfg,
1132
+
&qss_apss, &qss_cfg,
1133
+
&qss_ddrss_cfg, &qxs_boot_imem,
1134
+
&qxs_imem, &qxs_modem_boot_imem,
1135
+
&srvc_cnoc_main, &xs_pcie_0,
1136
+
&xs_pcie_1 },
1137
+
};
1138
+
1139
+
static struct qcom_icc_bcm bcm_cn1 = {
1140
+
.name = "CN1",
1141
+
.num_nodes = 3,
1142
+
.nodes = { &qhs_display_cfg, &qhs_qup1,
1143
+
&qhs_qup2 },
1144
+
};
1145
+
1146
+
static struct qcom_icc_bcm bcm_co0 = {
1147
+
.name = "CO0",
1148
+
.enable_mask = BIT(0),
1149
+
.num_nodes = 2,
1150
+
.nodes = { &qxm_nsp, &qns_nsp_gemnoc },
1151
+
};
1152
+
1153
+
static struct qcom_icc_bcm bcm_lp0 = {
1154
+
.name = "LP0",
1155
+
.num_nodes = 2,
1156
+
.nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc },
1157
+
};
1158
+
1159
+
static struct qcom_icc_bcm bcm_mc0 = {
1160
+
.name = "MC0",
1161
+
.keepalive = true,
1162
+
.num_nodes = 1,
1163
+
.nodes = { &ebi },
1164
+
};
1165
+
1166
+
static struct qcom_icc_bcm bcm_mm0 = {
1167
+
.name = "MM0",
1168
+
.num_nodes = 1,
1169
+
.nodes = { &qns_mem_noc_hf },
1170
+
};
1171
+
1172
+
static struct qcom_icc_bcm bcm_mm1 = {
1173
+
.name = "MM1",
1174
+
.enable_mask = BIT(0),
1175
+
.num_nodes = 7,
1176
+
.nodes = { &qnm_camnoc_nrt_icp_sf, &qnm_camnoc_rt_cdm_sf,
1177
+
&qnm_camnoc_sf, &qnm_video_mvp,
1178
+
&qnm_video_v_cpu, &qnm_camnoc_hf,
1179
+
&qns_mem_noc_sf },
1180
+
};
1181
+
1182
+
static struct qcom_icc_bcm bcm_qup1 = {
1183
+
.name = "QUP1",
1184
+
.vote_scale = 1,
1185
+
.keepalive = true,
1186
+
.num_nodes = 1,
1187
+
.nodes = { &qup1_core_slave },
1188
+
};
1189
+
1190
+
static struct qcom_icc_bcm bcm_qup2 = {
1191
+
.name = "QUP2",
1192
+
.vote_scale = 1,
1193
+
.keepalive = true,
1194
+
.num_nodes = 1,
1195
+
.nodes = { &qup2_core_slave },
1196
+
};
1197
+
1198
+
static struct qcom_icc_bcm bcm_sh0 = {
1199
+
.name = "SH0",
1200
+
.keepalive = true,
1201
+
.num_nodes = 1,
1202
+
.nodes = { &qns_llcc },
1203
+
};
1204
+
1205
+
static struct qcom_icc_bcm bcm_sh1 = {
1206
+
.name = "SH1",
1207
+
.enable_mask = BIT(0),
1208
+
.num_nodes = 14,
1209
+
.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
1210
+
&chm_apps, &qnm_gpu,
1211
+
&qnm_mdsp, &qnm_mnoc_hf,
1212
+
&qnm_mnoc_sf, &qnm_nsp_gemnoc,
1213
+
&qnm_pcie, &qnm_snoc_sf,
1214
+
&qxm_wlan_q6, &xm_gic,
1215
+
&qns_gem_noc_cnoc, &qns_pcie },
1216
+
};
1217
+
1218
+
static struct qcom_icc_bcm bcm_sn0 = {
1219
+
.name = "SN0",
1220
+
.keepalive = true,
1221
+
.num_nodes = 1,
1222
+
.nodes = { &qns_gemnoc_sf },
1223
+
};
1224
+
1225
+
static struct qcom_icc_bcm bcm_sn2 = {
1226
+
.name = "SN2",
1227
+
.num_nodes = 1,
1228
+
.nodes = { &qnm_aggre1_noc },
1229
+
};
1230
+
1231
+
static struct qcom_icc_bcm bcm_sn3 = {
1232
+
.name = "SN3",
1233
+
.num_nodes = 1,
1234
+
.nodes = { &qnm_aggre2_noc },
1235
+
};
1236
+
1237
+
static struct qcom_icc_bcm bcm_sn4 = {
1238
+
.name = "SN4",
1239
+
.num_nodes = 1,
1240
+
.nodes = { &qns_pcie_mem_noc },
1241
+
};
1242
+
1243
+
static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1244
+
[MASTER_QSPI_0] = &qhm_qspi,
1245
+
[MASTER_QUP_1] = &qhm_qup1,
1246
+
[MASTER_UFS_MEM] = &xm_ufs_mem,
1247
+
[MASTER_USB3_0] = &xm_usb3_0,
1248
+
[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1249
+
};
1250
+
1251
+
static const struct qcom_icc_desc eliza_aggre1_noc = {
1252
+
.nodes = aggre1_noc_nodes,
1253
+
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1254
+
.qos_requires_clocks = true,
1255
+
};
1256
+
1257
+
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1258
+
&bcm_ce0,
1259
+
};
1260
+
1261
+
static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1262
+
[MASTER_QUP_2] = &qhm_qup2,
1263
+
[MASTER_CRYPTO] = &qxm_crypto,
1264
+
[MASTER_IPA] = &qxm_ipa,
1265
+
[MASTER_SOCCP_AGGR_NOC] = &qxm_soccp,
1266
+
[MASTER_QDSS_ETR] = &xm_qdss_etr_0,
1267
+
[MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1268
+
[MASTER_SDCC_1] = &xm_sdc1,
1269
+
[MASTER_SDCC_2] = &xm_sdc2,
1270
+
[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1271
+
};
1272
+
1273
+
static const struct qcom_icc_desc eliza_aggre2_noc = {
1274
+
.nodes = aggre2_noc_nodes,
1275
+
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1276
+
.bcms = aggre2_noc_bcms,
1277
+
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1278
+
.qos_requires_clocks = true,
1279
+
};
1280
+
1281
+
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1282
+
&bcm_qup1,
1283
+
&bcm_qup2,
1284
+
};
1285
+
1286
+
static struct qcom_icc_node * const clk_virt_nodes[] = {
1287
+
[MASTER_QUP_CORE_1] = &qup1_core_master,
1288
+
[MASTER_QUP_CORE_2] = &qup2_core_master,
1289
+
[SLAVE_QUP_CORE_1] = &qup1_core_slave,
1290
+
[SLAVE_QUP_CORE_2] = &qup2_core_slave,
1291
+
};
1292
+
1293
+
static const struct qcom_icc_desc eliza_clk_virt = {
1294
+
.nodes = clk_virt_nodes,
1295
+
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
1296
+
.bcms = clk_virt_bcms,
1297
+
.num_bcms = ARRAY_SIZE(clk_virt_bcms),
1298
+
};
1299
+
1300
+
static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = {
1301
+
&bcm_cn0,
1302
+
&bcm_cn1,
1303
+
};
1304
+
1305
+
static struct qcom_icc_node * const cnoc_cfg_nodes[] = {
1306
+
[MASTER_CNOC_CFG] = &qsm_cfg,
1307
+
[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1308
+
[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1309
+
[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1310
+
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
1311
+
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1312
+
[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1313
+
[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1314
+
[SLAVE_I3C_IBI0_CFG] = &qhs_i3c_ibi0_cfg,
1315
+
[SLAVE_I3C_IBI1_CFG] = &qhs_i3c_ibi1_cfg,
1316
+
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1317
+
[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1318
+
[SLAVE_PCIE_0_CFG] = &qhs_pcie_0_cfg,
1319
+
[SLAVE_PRNG] = &qhs_prng,
1320
+
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1321
+
[SLAVE_QSPI_0] = &qhs_qspi,
1322
+
[SLAVE_QUP_1] = &qhs_qup1,
1323
+
[SLAVE_QUP_2] = &qhs_qup2,
1324
+
[SLAVE_SDCC_2] = &qhs_sdc2,
1325
+
[SLAVE_TCSR] = &qhs_tcsr,
1326
+
[SLAVE_TLMM] = &qhs_tlmm,
1327
+
[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1328
+
[SLAVE_USB3_0] = &qhs_usb3_0,
1329
+
[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1330
+
[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1331
+
[SLAVE_CNOC_MNOC_HF_CFG] = &qss_mnoc_hf_cfg,
1332
+
[SLAVE_CNOC_MNOC_SF_CFG] = &qss_mnoc_sf_cfg,
1333
+
[SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg,
1334
+
[SLAVE_QDSS_STM] = &xs_qdss_stm,
1335
+
[SLAVE_TCU] = &xs_sys_tcu_cfg,
1336
+
};
1337
+
1338
+
static const struct qcom_icc_desc eliza_cnoc_cfg = {
1339
+
.nodes = cnoc_cfg_nodes,
1340
+
.num_nodes = ARRAY_SIZE(cnoc_cfg_nodes),
1341
+
.bcms = cnoc_cfg_bcms,
1342
+
.num_bcms = ARRAY_SIZE(cnoc_cfg_bcms),
1343
+
};
1344
+
1345
+
static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
1346
+
&bcm_cn0,
1347
+
};
1348
+
1349
+
static struct qcom_icc_node * const cnoc_main_nodes[] = {
1350
+
[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1351
+
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1352
+
[SLAVE_AOSS] = &qhs_aoss,
1353
+
[SLAVE_IPA_CFG] = &qhs_ipa,
1354
+
[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1355
+
[SLAVE_SOCCP] = &qhs_soccp,
1356
+
[SLAVE_TME_CFG] = &qhs_tme_cfg,
1357
+
[SLAVE_APPSS] = &qss_apss,
1358
+
[SLAVE_CNOC_CFG] = &qss_cfg,
1359
+
[SLAVE_DDRSS_CFG] = &qss_ddrss_cfg,
1360
+
[SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1361
+
[SLAVE_IMEM] = &qxs_imem,
1362
+
[SLAVE_BOOT_IMEM_2] = &qxs_modem_boot_imem,
1363
+
[SLAVE_SERVICE_CNOC] = &srvc_cnoc_main,
1364
+
[SLAVE_PCIE_0] = &xs_pcie_0,
1365
+
[SLAVE_PCIE_1] = &xs_pcie_1,
1366
+
};
1367
+
1368
+
static const struct qcom_icc_desc eliza_cnoc_main = {
1369
+
.nodes = cnoc_main_nodes,
1370
+
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
1371
+
.bcms = cnoc_main_bcms,
1372
+
.num_bcms = ARRAY_SIZE(cnoc_main_bcms),
1373
+
};
1374
+
1375
+
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1376
+
&bcm_sh0,
1377
+
&bcm_sh1,
1378
+
};
1379
+
1380
+
static struct qcom_icc_node * const gem_noc_nodes[] = {
1381
+
[MASTER_GPU_TCU] = &alm_gpu_tcu,
1382
+
[MASTER_SYS_TCU] = &alm_sys_tcu,
1383
+
[MASTER_APPSS_PROC] = &chm_apps,
1384
+
[MASTER_GFX3D] = &qnm_gpu,
1385
+
[MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc,
1386
+
[MASTER_MSS_PROC] = &qnm_mdsp,
1387
+
[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1388
+
[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1389
+
[MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
1390
+
[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1391
+
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1392
+
[MASTER_WLAN_Q6] = &qxm_wlan_q6,
1393
+
[MASTER_GIC] = &xm_gic,
1394
+
[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1395
+
[SLAVE_LLCC] = &qns_llcc,
1396
+
[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1397
+
};
1398
+
1399
+
static const struct qcom_icc_desc eliza_gem_noc = {
1400
+
.nodes = gem_noc_nodes,
1401
+
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
1402
+
.bcms = gem_noc_bcms,
1403
+
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
1404
+
};
1405
+
1406
+
static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1407
+
[MASTER_LPIAON_NOC] = &qnm_lpiaon_noc,
1408
+
[SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
1409
+
};
1410
+
1411
+
static const struct qcom_icc_desc eliza_lpass_ag_noc = {
1412
+
.nodes = lpass_ag_noc_nodes,
1413
+
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1414
+
};
1415
+
1416
+
static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {
1417
+
&bcm_lp0,
1418
+
};
1419
+
1420
+
static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
1421
+
[MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc,
1422
+
[SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc,
1423
+
};
1424
+
1425
+
static const struct qcom_icc_desc eliza_lpass_lpiaon_noc = {
1426
+
.nodes = lpass_lpiaon_noc_nodes,
1427
+
.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
1428
+
.bcms = lpass_lpiaon_noc_bcms,
1429
+
.num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),
1430
+
};
1431
+
1432
+
static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
1433
+
[MASTER_LPASS_PROC] = &qxm_lpinoc_dsp_axim,
1434
+
[SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc,
1435
+
};
1436
+
1437
+
static const struct qcom_icc_desc eliza_lpass_lpicx_noc = {
1438
+
.nodes = lpass_lpicx_noc_nodes,
1439
+
.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
1440
+
};
1441
+
1442
+
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1443
+
&bcm_mc0,
1444
+
};
1445
+
1446
+
static struct qcom_icc_node * const mc_virt_nodes[] = {
1447
+
[MASTER_LLCC] = &llcc_mc,
1448
+
[SLAVE_EBI1] = &ebi,
1449
+
};
1450
+
1451
+
static const struct qcom_icc_desc eliza_mc_virt = {
1452
+
.nodes = mc_virt_nodes,
1453
+
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
1454
+
.bcms = mc_virt_bcms,
1455
+
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
1456
+
};
1457
+
1458
+
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1459
+
&bcm_mm0,
1460
+
&bcm_mm1,
1461
+
};
1462
+
1463
+
static struct qcom_icc_node * const mmss_noc_nodes[] = {
1464
+
[MASTER_CAMNOC_NRT_ICP_SF] = &qnm_camnoc_nrt_icp_sf,
1465
+
[MASTER_CAMNOC_RT_CDM_SF] = &qnm_camnoc_rt_cdm_sf,
1466
+
[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1467
+
[MASTER_VIDEO_MVP] = &qnm_video_mvp,
1468
+
[MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
1469
+
[MASTER_CNOC_MNOC_SF_CFG] = &qsm_sf_mnoc_cfg,
1470
+
[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1471
+
[MASTER_MDP] = &qnm_mdp,
1472
+
[MASTER_CNOC_MNOC_HF_CFG] = &qsm_hf_mnoc_cfg,
1473
+
[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1474
+
[SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf,
1475
+
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1476
+
[SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf,
1477
+
};
1478
+
1479
+
static const struct qcom_icc_desc eliza_mmss_noc = {
1480
+
.nodes = mmss_noc_nodes,
1481
+
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1482
+
.bcms = mmss_noc_bcms,
1483
+
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1484
+
};
1485
+
1486
+
static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1487
+
&bcm_co0,
1488
+
};
1489
+
1490
+
static struct qcom_icc_node * const nsp_noc_nodes[] = {
1491
+
[MASTER_CDSP_PROC] = &qxm_nsp,
1492
+
[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1493
+
};
1494
+
1495
+
static const struct qcom_icc_desc eliza_nsp_noc = {
1496
+
.nodes = nsp_noc_nodes,
1497
+
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1498
+
.bcms = nsp_noc_bcms,
1499
+
.num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1500
+
};
1501
+
1502
+
static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
1503
+
&bcm_sn4,
1504
+
};
1505
+
1506
+
static struct qcom_icc_node * const pcie_anoc_nodes[] = {
1507
+
[MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg,
1508
+
[MASTER_PCIE_0] = &xm_pcie3_0,
1509
+
[MASTER_PCIE_1] = &xm_pcie3_1,
1510
+
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1511
+
[SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc,
1512
+
};
1513
+
1514
+
static const struct qcom_icc_desc eliza_pcie_anoc = {
1515
+
.nodes = pcie_anoc_nodes,
1516
+
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
1517
+
.bcms = pcie_anoc_bcms,
1518
+
.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
1519
+
.qos_requires_clocks = true,
1520
+
};
1521
+
1522
+
static struct qcom_icc_bcm * const system_noc_bcms[] = {
1523
+
&bcm_sn0,
1524
+
&bcm_sn2,
1525
+
&bcm_sn3,
1526
+
};
1527
+
1528
+
static struct qcom_icc_node * const system_noc_nodes[] = {
1529
+
[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1530
+
[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1531
+
[MASTER_CNOC_SNOC] = &qnm_cnoc_data,
1532
+
[MASTER_NSINOC_SNOC] = &qnm_nsinoc_snoc,
1533
+
[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1534
+
};
1535
+
1536
+
static const struct qcom_icc_desc eliza_system_noc = {
1537
+
.nodes = system_noc_nodes,
1538
+
.num_nodes = ARRAY_SIZE(system_noc_nodes),
1539
+
.bcms = system_noc_bcms,
1540
+
.num_bcms = ARRAY_SIZE(system_noc_bcms),
1541
+
};
1542
+
1543
+
static const struct of_device_id qnoc_of_match[] = {
1544
+
{ .compatible = "qcom,eliza-aggre1-noc", .data = &eliza_aggre1_noc },
1545
+
{ .compatible = "qcom,eliza-aggre2-noc", .data = &eliza_aggre2_noc },
1546
+
{ .compatible = "qcom,eliza-clk-virt", .data = &eliza_clk_virt },
1547
+
{ .compatible = "qcom,eliza-cnoc-cfg", .data = &eliza_cnoc_cfg },
1548
+
{ .compatible = "qcom,eliza-cnoc-main", .data = &eliza_cnoc_main },
1549
+
{ .compatible = "qcom,eliza-gem-noc", .data = &eliza_gem_noc },
1550
+
{ .compatible = "qcom,eliza-lpass-ag-noc", .data = &eliza_lpass_ag_noc },
1551
+
{ .compatible = "qcom,eliza-lpass-lpiaon-noc", .data = &eliza_lpass_lpiaon_noc },
1552
+
{ .compatible = "qcom,eliza-lpass-lpicx-noc", .data = &eliza_lpass_lpicx_noc },
1553
+
{ .compatible = "qcom,eliza-mc-virt", .data = &eliza_mc_virt },
1554
+
{ .compatible = "qcom,eliza-mmss-noc", .data = &eliza_mmss_noc },
1555
+
{ .compatible = "qcom,eliza-nsp-noc", .data = &eliza_nsp_noc },
1556
+
{ .compatible = "qcom,eliza-pcie-anoc", .data = &eliza_pcie_anoc },
1557
+
{ .compatible = "qcom,eliza-system-noc", .data = &eliza_system_noc },
1558
+
{ }
1559
+
};
1560
+
MODULE_DEVICE_TABLE(of, qnoc_of_match);
1561
+
1562
+
static struct platform_driver qnoc_driver = {
1563
+
.probe = qcom_icc_rpmh_probe,
1564
+
.remove = qcom_icc_rpmh_remove,
1565
+
.driver = {
1566
+
.name = "qnoc-eliza",
1567
+
.of_match_table = qnoc_of_match,
1568
+
.sync_state = icc_sync_state,
1569
+
},
1570
+
};
1571
+
1572
+
static int __init qnoc_driver_init(void)
1573
+
{
1574
+
return platform_driver_register(&qnoc_driver);
1575
+
}
1576
+
core_initcall(qnoc_driver_init);
1577
+
1578
+
static void __exit qnoc_driver_exit(void)
1579
+
{
1580
+
platform_driver_unregister(&qnoc_driver);
1581
+
}
1582
+
module_exit(qnoc_driver_exit);
1583
+
1584
+
MODULE_DESCRIPTION(" Qualcomm Eliza NoC driver");
1585
+
MODULE_LICENSE("GPL");
+34
-6
drivers/interconnect/qcom/glymur.c
+34
-6
drivers/interconnect/qcom/glymur.c
···
9
9
#include <linux/interconnect-provider.h>
10
10
#include <linux/module.h>
11
11
#include <linux/of_platform.h>
12
+
#include <linux/property.h>
12
13
#include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
13
14
14
15
#include "bcm-voter.h"
···
1986
1985
&bcm_cn1,
1987
1986
};
1988
1987
1989
-
static struct qcom_icc_node * const cnoc_cfg_nodes[] = {
1988
+
static struct qcom_icc_node *cnoc_cfg_nodes[] = {
1990
1989
[MASTER_CNOC_CFG] = &qsm_cfg,
1991
1990
[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1992
1991
[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
···
2094
2093
&bcm_sh1,
2095
2094
};
2096
2095
2097
-
static struct qcom_icc_node * const hscnoc_nodes[] = {
2096
+
static struct qcom_icc_node *hscnoc_nodes[] = {
2098
2097
[MASTER_GPU_TCU] = &alm_gpu_tcu,
2099
2098
[MASTER_PCIE_TCU] = &alm_pcie_qtc,
2100
2099
[MASTER_SYS_TCU] = &alm_sys_tcu,
···
2378
2377
&bcm_sn6,
2379
2378
};
2380
2379
2381
-
static struct qcom_icc_node * const pcie_west_anoc_nodes[] = {
2380
+
static struct qcom_icc_node *pcie_west_anoc_nodes[] = {
2382
2381
[MASTER_PCIE_WEST_ANOC_CFG] = &qsm_pcie_west_anoc_cfg,
2383
2382
[MASTER_PCIE_2] = &xm_pcie_2,
2384
2383
[MASTER_PCIE_3A] = &xm_pcie_3a,
···
2410
2409
&bcm_sn6,
2411
2410
};
2412
2411
2413
-
static struct qcom_icc_node * const pcie_west_slv_noc_nodes[] = {
2412
+
static struct qcom_icc_node *pcie_west_slv_noc_nodes[] = {
2414
2413
[MASTER_HSCNOC_PCIE_WEST] = &qnm_hscnoc_pcie_west,
2415
2414
[MASTER_CNOC_PCIE_WEST_SLAVE_CFG] = &qsm_cnoc_pcie_west_slave_cfg,
2416
2415
[SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG] = &qhs_hscnoc_pcie_west_ms_mpu_cfg,
···
2471
2470
.num_bcms = ARRAY_SIZE(system_noc_bcms),
2472
2471
};
2473
2472
2473
+
static int glymur_qnoc_probe(struct platform_device *pdev)
2474
+
{
2475
+
if (device_is_compatible(&pdev->dev, "qcom,mahua-mc-virt")) {
2476
+
llcc_mc.channels = 8;
2477
+
ebi.channels = 8;
2478
+
} else if (device_is_compatible(&pdev->dev, "qcom,mahua-hscnoc")) {
2479
+
qns_llcc.channels = 8;
2480
+
chm_apps.channels = 4;
2481
+
qnm_pcie_west.buswidth = 32;
2482
+
hscnoc_nodes[MASTER_WLAN_Q6] = NULL;
2483
+
} else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-anoc")) {
2484
+
qns_pcie_west_mem_noc.buswidth = 32;
2485
+
pcie_west_anoc_nodes[MASTER_PCIE_3A] = NULL;
2486
+
} else if (device_is_compatible(&pdev->dev, "qcom,mahua-cnoc-cfg")) {
2487
+
cnoc_cfg_nodes[SLAVE_PCIE_3A_CFG] = NULL;
2488
+
} else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-slv-noc")) {
2489
+
pcie_west_slv_noc_nodes[SLAVE_PCIE_3A] = NULL;
2490
+
}
2491
+
2492
+
return qcom_icc_rpmh_probe(pdev);
2493
+
}
2494
+
2474
2495
static const struct of_device_id qnoc_of_match[] = {
2475
2496
{ .compatible = "qcom,glymur-aggre1-noc", .data = &glymur_aggre1_noc},
2476
2497
{ .compatible = "qcom,glymur-aggre2-noc", .data = &glymur_aggre2_noc},
···
2500
2477
{ .compatible = "qcom,glymur-aggre4-noc", .data = &glymur_aggre4_noc},
2501
2478
{ .compatible = "qcom,glymur-clk-virt", .data = &glymur_clk_virt},
2502
2479
{ .compatible = "qcom,glymur-cnoc-cfg", .data = &glymur_cnoc_cfg},
2480
+
{ .compatible = "qcom,mahua-cnoc-cfg", .data = &glymur_cnoc_cfg},
2503
2481
{ .compatible = "qcom,glymur-cnoc-main", .data = &glymur_cnoc_main},
2504
2482
{ .compatible = "qcom,glymur-hscnoc", .data = &glymur_hscnoc},
2483
+
{ .compatible = "qcom,mahua-hscnoc", .data = &glymur_hscnoc},
2505
2484
{ .compatible = "qcom,glymur-lpass-ag-noc", .data = &glymur_lpass_ag_noc},
2506
2485
{ .compatible = "qcom,glymur-lpass-lpiaon-noc", .data = &glymur_lpass_lpiaon_noc},
2507
2486
{ .compatible = "qcom,glymur-lpass-lpicx-noc", .data = &glymur_lpass_lpicx_noc},
2508
2487
{ .compatible = "qcom,glymur-mc-virt", .data = &glymur_mc_virt},
2488
+
{ .compatible = "qcom,mahua-mc-virt", .data = &glymur_mc_virt},
2509
2489
{ .compatible = "qcom,glymur-mmss-noc", .data = &glymur_mmss_noc},
2510
2490
{ .compatible = "qcom,glymur-nsinoc", .data = &glymur_nsinoc},
2511
2491
{ .compatible = "qcom,glymur-nsp-noc", .data = &glymur_nsp_noc},
···
2516
2490
{ .compatible = "qcom,glymur-pcie-east-anoc", .data = &glymur_pcie_east_anoc},
2517
2491
{ .compatible = "qcom,glymur-pcie-east-slv-noc", .data = &glymur_pcie_east_slv_noc},
2518
2492
{ .compatible = "qcom,glymur-pcie-west-anoc", .data = &glymur_pcie_west_anoc},
2493
+
{ .compatible = "qcom,mahua-pcie-west-anoc", .data = &glymur_pcie_west_anoc},
2519
2494
{ .compatible = "qcom,glymur-pcie-west-slv-noc", .data = &glymur_pcie_west_slv_noc},
2495
+
{ .compatible = "qcom,mahua-pcie-west-slv-noc", .data = &glymur_pcie_west_slv_noc},
2520
2496
{ .compatible = "qcom,glymur-system-noc", .data = &glymur_system_noc},
2521
2497
{ }
2522
2498
};
2523
2499
MODULE_DEVICE_TABLE(of, qnoc_of_match);
2524
2500
2525
2501
static struct platform_driver qnoc_driver = {
2526
-
.probe = qcom_icc_rpmh_probe,
2502
+
.probe = glymur_qnoc_probe,
2527
2503
.remove = qcom_icc_rpmh_remove,
2528
2504
.driver = {
2529
2505
.name = "qnoc-glymur",
···
2546
2518
}
2547
2519
module_exit(qnoc_driver_exit);
2548
2520
2549
-
MODULE_DESCRIPTION("GLYMUR NoC driver");
2521
+
MODULE_DESCRIPTION("Glymur NoC driver");
2550
2522
MODULE_LICENSE("GPL");
+6
drivers/interconnect/qcom/icc-rpm-clocks.c
+6
drivers/interconnect/qcom/icc-rpm-clocks.c
···
31
31
};
32
32
EXPORT_SYMBOL_GPL(mem_1_clk);
33
33
34
+
const struct rpm_clk_resource gpu_mem_2_clk = {
35
+
.resource_type = QCOM_SMD_RPM_MEM_CLK,
36
+
.clock_id = 2,
37
+
};
38
+
EXPORT_SYMBOL_GPL(gpu_mem_2_clk);
39
+
34
40
const struct rpm_clk_resource bus_0_clk = {
35
41
.resource_type = QCOM_SMD_RPM_BUS_CLK,
36
42
.clock_id = 0,
+11
-7
drivers/interconnect/qcom/icc-rpm.c
+11
-7
drivers/interconnect/qcom/icc-rpm.c
···
204
204
}
205
205
}
206
206
207
-
static int qcom_icc_rpm_set(struct qcom_icc_node *qn, u64 *bw)
207
+
static int qcom_icc_rpm_set(struct qcom_icc_node *qn, u64 *bw, bool ignore_enxio)
208
208
{
209
209
int ret, rpm_ctx = 0;
210
210
u64 bw_bps;
···
222
222
bw_bps);
223
223
if (ret) {
224
224
pr_err("qcom_icc_rpm_smd_send mas %d error %d\n",
225
-
qn->mas_rpm_id, ret);
226
-
return ret;
225
+
qn->mas_rpm_id, ret);
226
+
if (ret != -ENXIO || !ignore_enxio)
227
+
return ret;
227
228
}
228
229
}
229
230
···
235
234
bw_bps);
236
235
if (ret) {
237
236
pr_err("qcom_icc_rpm_smd_send slv %d error %d\n",
238
-
qn->slv_rpm_id, ret);
239
-
return ret;
237
+
qn->slv_rpm_id, ret);
238
+
if (ret != -ENXIO || !ignore_enxio)
239
+
return ret;
240
240
}
241
241
}
242
242
}
···
363
361
active_rate = agg_clk_rate[QCOM_SMD_RPM_ACTIVE_STATE];
364
362
sleep_rate = agg_clk_rate[QCOM_SMD_RPM_SLEEP_STATE];
365
363
366
-
ret = qcom_icc_rpm_set(src_qn, src_qn->sum_avg);
364
+
ret = qcom_icc_rpm_set(src_qn, src_qn->sum_avg, qp->ignore_enxio);
367
365
if (ret)
368
366
return ret;
369
367
370
368
if (dst_qn) {
371
-
ret = qcom_icc_rpm_set(dst_qn, dst_qn->sum_avg);
369
+
ret = qcom_icc_rpm_set(dst_qn, dst_qn->sum_avg, qp->ignore_enxio);
372
370
if (ret)
373
371
return ret;
374
372
}
···
511
509
for (i = 0; i < cd_num; i++)
512
510
qp->intf_clks[i].id = cds[i];
513
511
512
+
qp->ignore_enxio = desc->ignore_enxio;
514
513
qp->keep_alive = desc->keep_alive;
515
514
qp->type = desc->type;
516
515
qp->qos_offset = desc->qos_offset;
···
556
553
provider->aggregate = qcom_icc_bw_aggregate;
557
554
provider->xlate_extended = qcom_icc_xlate_extended;
558
555
provider->data = data;
556
+
provider->get_bw = desc->get_bw;
559
557
560
558
icc_provider_init(provider);
561
559
+5
-2
drivers/interconnect/qcom/icc-rpm.h
+5
-2
drivers/interconnect/qcom/icc-rpm.h
···
51
51
* @bus_clk: a pointer to a HLOS-owned bus clock
52
52
* @intf_clks: a clk_bulk_data array of interface clocks
53
53
* @keep_alive: whether to always keep a minimum vote on the bus clocks
54
-
* @is_on: whether the bus is powered on
54
+
* @ignore_enxio: whether to ignore ENXIO errors (for MSM8974)
55
55
*/
56
56
struct qcom_icc_provider {
57
57
struct icc_provider provider;
···
66
66
struct clk *bus_clk;
67
67
struct clk_bulk_data *intf_clks;
68
68
bool keep_alive;
69
-
bool is_on;
69
+
bool ignore_enxio;
70
70
};
71
71
72
72
/**
···
137
137
unsigned int qos_offset;
138
138
u16 ab_coeff;
139
139
u16 ib_coeff;
140
+
int (*get_bw)(struct icc_node *node, u32 *avg, u32 *peak);
141
+
bool ignore_enxio;
140
142
};
141
143
142
144
/* Valid for all bus types */
···
154
152
extern const struct rpm_clk_resource bus_0_clk;
155
153
extern const struct rpm_clk_resource bus_1_clk;
156
154
extern const struct rpm_clk_resource bus_2_clk;
155
+
extern const struct rpm_clk_resource gpu_mem_2_clk;
157
156
extern const struct rpm_clk_resource mem_1_clk;
158
157
extern const struct rpm_clk_resource mmaxi_0_clk;
159
158
extern const struct rpm_clk_resource mmaxi_1_clk;
+1221
-392
drivers/interconnect/qcom/msm8974.c
+1221
-392
drivers/interconnect/qcom/msm8974.c
···
173
173
MSM8974_SNOC_SLV_QDSS_STM,
174
174
};
175
175
176
-
#define to_msm8974_icc_provider(_provider) \
177
-
container_of(_provider, struct msm8974_icc_provider, provider)
176
+
static int msm8974_get_bw(struct icc_node *node, u32 *avg, u32 *peak)
177
+
{
178
+
*avg = 0;
179
+
*peak = 0;
178
180
179
-
static const struct clk_bulk_data msm8974_icc_bus_clocks[] = {
180
-
{ .id = "bus" },
181
-
{ .id = "bus_a" },
181
+
return 0;
182
182
};
183
183
184
-
/**
185
-
* struct msm8974_icc_provider - Qualcomm specific interconnect provider
186
-
* @provider: generic interconnect provider
187
-
* @bus_clks: the clk_bulk_data table of bus clocks
188
-
* @num_clks: the total number of clk_bulk_data entries
189
-
*/
190
-
struct msm8974_icc_provider {
191
-
struct icc_provider provider;
192
-
struct clk_bulk_data *bus_clks;
193
-
int num_clks;
184
+
static struct qcom_icc_node mas_ampss_m0 = {
185
+
.name = "mas_ampss_m0",
186
+
.id = MSM8974_BIMC_MAS_AMPSS_M0,
187
+
.buswidth = 8,
188
+
.mas_rpm_id = 0,
189
+
.slv_rpm_id = -1,
194
190
};
195
191
196
-
#define MSM8974_ICC_MAX_LINKS 3
197
-
198
-
/**
199
-
* struct msm8974_icc_node - Qualcomm specific interconnect nodes
200
-
* @name: the node name used in debugfs
201
-
* @id: a unique node identifier
202
-
* @links: an array of nodes where we can go next while traversing
203
-
* @num_links: the total number of @links
204
-
* @buswidth: width of the interconnect between a node and the bus (bytes)
205
-
* @mas_rpm_id: RPM ID for devices that are bus masters
206
-
* @slv_rpm_id: RPM ID for devices that are bus slaves
207
-
* @rate: current bus clock rate in Hz
208
-
*/
209
-
struct msm8974_icc_node {
210
-
unsigned char *name;
211
-
u16 id;
212
-
u16 links[MSM8974_ICC_MAX_LINKS];
213
-
u16 num_links;
214
-
u16 buswidth;
215
-
int mas_rpm_id;
216
-
int slv_rpm_id;
217
-
u64 rate;
192
+
static struct qcom_icc_node mas_ampss_m1 = {
193
+
.name = "mas_ampss_m1",
194
+
.id = MSM8974_BIMC_MAS_AMPSS_M1,
195
+
.buswidth = 8,
196
+
.mas_rpm_id = 0,
197
+
.slv_rpm_id = -1,
218
198
};
219
199
220
-
struct msm8974_icc_desc {
221
-
struct msm8974_icc_node * const *nodes;
222
-
size_t num_nodes;
200
+
static struct qcom_icc_node mas_mss_proc = {
201
+
.name = "mas_mss_proc",
202
+
.id = MSM8974_BIMC_MAS_MSS_PROC,
203
+
.buswidth = 8,
204
+
.mas_rpm_id = 1,
205
+
.slv_rpm_id = -1,
223
206
};
224
207
225
-
#define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \
226
-
...) \
227
-
static struct msm8974_icc_node _name = { \
228
-
.name = #_name, \
229
-
.id = _id, \
230
-
.buswidth = _buswidth, \
231
-
.mas_rpm_id = _mas_rpm_id, \
232
-
.slv_rpm_id = _slv_rpm_id, \
233
-
.num_links = COUNT_ARGS(__VA_ARGS__), \
234
-
.links = { __VA_ARGS__ }, \
235
-
}
208
+
static const u16 bimc_to_mnoc_links[] = {
209
+
MSM8974_BIMC_SLV_EBI_CH0
210
+
};
236
211
237
-
DEFINE_QNODE(mas_ampss_m0, MSM8974_BIMC_MAS_AMPSS_M0, 8, 0, -1);
238
-
DEFINE_QNODE(mas_ampss_m1, MSM8974_BIMC_MAS_AMPSS_M1, 8, 0, -1);
239
-
DEFINE_QNODE(mas_mss_proc, MSM8974_BIMC_MAS_MSS_PROC, 8, 1, -1);
240
-
DEFINE_QNODE(bimc_to_mnoc, MSM8974_BIMC_TO_MNOC, 8, 2, -1, MSM8974_BIMC_SLV_EBI_CH0);
241
-
DEFINE_QNODE(bimc_to_snoc, MSM8974_BIMC_TO_SNOC, 8, 3, 2, MSM8974_SNOC_TO_BIMC, MSM8974_BIMC_SLV_EBI_CH0, MSM8974_BIMC_MAS_AMPSS_M0);
242
-
DEFINE_QNODE(slv_ebi_ch0, MSM8974_BIMC_SLV_EBI_CH0, 8, -1, 0);
243
-
DEFINE_QNODE(slv_ampss_l2, MSM8974_BIMC_SLV_AMPSS_L2, 8, -1, 1);
212
+
static struct qcom_icc_node bimc_to_mnoc = {
213
+
.name = "bimc_to_mnoc",
214
+
.id = MSM8974_BIMC_TO_MNOC,
215
+
.buswidth = 8,
216
+
.mas_rpm_id = 2,
217
+
.slv_rpm_id = -1,
218
+
.num_links = ARRAY_SIZE(bimc_to_mnoc_links),
219
+
.links = bimc_to_mnoc_links,
220
+
};
244
221
245
-
static struct msm8974_icc_node * const msm8974_bimc_nodes[] = {
222
+
static const u16 bimc_to_snoc_links[] = {
223
+
MSM8974_SNOC_TO_BIMC,
224
+
MSM8974_BIMC_SLV_EBI_CH0,
225
+
MSM8974_BIMC_MAS_AMPSS_M0
226
+
};
227
+
228
+
static struct qcom_icc_node bimc_to_snoc = {
229
+
.name = "bimc_to_snoc",
230
+
.id = MSM8974_BIMC_TO_SNOC,
231
+
.buswidth = 8,
232
+
.mas_rpm_id = 3,
233
+
.slv_rpm_id = 2,
234
+
.num_links = ARRAY_SIZE(bimc_to_snoc_links),
235
+
.links = bimc_to_snoc_links,
236
+
};
237
+
238
+
static struct qcom_icc_node slv_ebi_ch0 = {
239
+
.name = "slv_ebi_ch0",
240
+
.id = MSM8974_BIMC_SLV_EBI_CH0,
241
+
.buswidth = 8,
242
+
.mas_rpm_id = -1,
243
+
.slv_rpm_id = 0,
244
+
};
245
+
246
+
static struct qcom_icc_node slv_ampss_l2 = {
247
+
.name = "slv_ampss_l2",
248
+
.id = MSM8974_BIMC_SLV_AMPSS_L2,
249
+
.buswidth = 8,
250
+
.mas_rpm_id = -1,
251
+
.slv_rpm_id = 1,
252
+
};
253
+
254
+
static struct qcom_icc_node * const msm8974_bimc_nodes[] = {
246
255
[BIMC_MAS_AMPSS_M0] = &mas_ampss_m0,
247
256
[BIMC_MAS_AMPSS_M1] = &mas_ampss_m1,
248
257
[BIMC_MAS_MSS_PROC] = &mas_mss_proc,
···
261
252
[BIMC_SLV_AMPSS_L2] = &slv_ampss_l2,
262
253
};
263
254
264
-
static const struct msm8974_icc_desc msm8974_bimc = {
255
+
static const struct qcom_icc_desc msm8974_bimc = {
265
256
.nodes = msm8974_bimc_nodes,
266
257
.num_nodes = ARRAY_SIZE(msm8974_bimc_nodes),
258
+
.bus_clk_desc = &bimc_clk,
259
+
.get_bw = msm8974_get_bw,
260
+
.ignore_enxio = true,
267
261
};
268
262
269
-
DEFINE_QNODE(mas_rpm_inst, MSM8974_CNOC_MAS_RPM_INST, 8, 45, -1);
270
-
DEFINE_QNODE(mas_rpm_data, MSM8974_CNOC_MAS_RPM_DATA, 8, 46, -1);
271
-
DEFINE_QNODE(mas_rpm_sys, MSM8974_CNOC_MAS_RPM_SYS, 8, 47, -1);
272
-
DEFINE_QNODE(mas_dehr, MSM8974_CNOC_MAS_DEHR, 8, 48, -1);
273
-
DEFINE_QNODE(mas_qdss_dap, MSM8974_CNOC_MAS_QDSS_DAP, 8, 49, -1);
274
-
DEFINE_QNODE(mas_spdm, MSM8974_CNOC_MAS_SPDM, 8, 50, -1);
275
-
DEFINE_QNODE(mas_tic, MSM8974_CNOC_MAS_TIC, 8, 51, -1);
276
-
DEFINE_QNODE(slv_clk_ctl, MSM8974_CNOC_SLV_CLK_CTL, 8, -1, 47);
277
-
DEFINE_QNODE(slv_cnoc_mss, MSM8974_CNOC_SLV_CNOC_MSS, 8, -1, 48);
278
-
DEFINE_QNODE(slv_security, MSM8974_CNOC_SLV_SECURITY, 8, -1, 49);
279
-
DEFINE_QNODE(slv_tcsr, MSM8974_CNOC_SLV_TCSR, 8, -1, 50);
280
-
DEFINE_QNODE(slv_tlmm, MSM8974_CNOC_SLV_TLMM, 8, -1, 51);
281
-
DEFINE_QNODE(slv_crypto_0_cfg, MSM8974_CNOC_SLV_CRYPTO_0_CFG, 8, -1, 52);
282
-
DEFINE_QNODE(slv_crypto_1_cfg, MSM8974_CNOC_SLV_CRYPTO_1_CFG, 8, -1, 53);
283
-
DEFINE_QNODE(slv_imem_cfg, MSM8974_CNOC_SLV_IMEM_CFG, 8, -1, 54);
284
-
DEFINE_QNODE(slv_message_ram, MSM8974_CNOC_SLV_MESSAGE_RAM, 8, -1, 55);
285
-
DEFINE_QNODE(slv_bimc_cfg, MSM8974_CNOC_SLV_BIMC_CFG, 8, -1, 56);
286
-
DEFINE_QNODE(slv_boot_rom, MSM8974_CNOC_SLV_BOOT_ROM, 8, -1, 57);
287
-
DEFINE_QNODE(slv_pmic_arb, MSM8974_CNOC_SLV_PMIC_ARB, 8, -1, 59);
288
-
DEFINE_QNODE(slv_spdm_wrapper, MSM8974_CNOC_SLV_SPDM_WRAPPER, 8, -1, 60);
289
-
DEFINE_QNODE(slv_dehr_cfg, MSM8974_CNOC_SLV_DEHR_CFG, 8, -1, 61);
290
-
DEFINE_QNODE(slv_mpm, MSM8974_CNOC_SLV_MPM, 8, -1, 62);
291
-
DEFINE_QNODE(slv_qdss_cfg, MSM8974_CNOC_SLV_QDSS_CFG, 8, -1, 63);
292
-
DEFINE_QNODE(slv_rbcpr_cfg, MSM8974_CNOC_SLV_RBCPR_CFG, 8, -1, 64);
293
-
DEFINE_QNODE(slv_rbcpr_qdss_apu_cfg, MSM8974_CNOC_SLV_RBCPR_QDSS_APU_CFG, 8, -1, 65);
294
-
DEFINE_QNODE(cnoc_to_snoc, MSM8974_CNOC_TO_SNOC, 8, 52, 75);
295
-
DEFINE_QNODE(slv_cnoc_onoc_cfg, MSM8974_CNOC_SLV_CNOC_ONOC_CFG, 8, -1, 68);
296
-
DEFINE_QNODE(slv_cnoc_mnoc_mmss_cfg, MSM8974_CNOC_SLV_CNOC_MNOC_MMSS_CFG, 8, -1, 58);
297
-
DEFINE_QNODE(slv_cnoc_mnoc_cfg, MSM8974_CNOC_SLV_CNOC_MNOC_CFG, 8, -1, 66);
298
-
DEFINE_QNODE(slv_pnoc_cfg, MSM8974_CNOC_SLV_PNOC_CFG, 8, -1, 69);
299
-
DEFINE_QNODE(slv_snoc_mpu_cfg, MSM8974_CNOC_SLV_SNOC_MPU_CFG, 8, -1, 67);
300
-
DEFINE_QNODE(slv_snoc_cfg, MSM8974_CNOC_SLV_SNOC_CFG, 8, -1, 70);
301
-
DEFINE_QNODE(slv_ebi1_dll_cfg, MSM8974_CNOC_SLV_EBI1_DLL_CFG, 8, -1, 71);
302
-
DEFINE_QNODE(slv_phy_apu_cfg, MSM8974_CNOC_SLV_PHY_APU_CFG, 8, -1, 72);
303
-
DEFINE_QNODE(slv_ebi1_phy_cfg, MSM8974_CNOC_SLV_EBI1_PHY_CFG, 8, -1, 73);
304
-
DEFINE_QNODE(slv_rpm, MSM8974_CNOC_SLV_RPM, 8, -1, 74);
305
-
DEFINE_QNODE(slv_service_cnoc, MSM8974_CNOC_SLV_SERVICE_CNOC, 8, -1, 76);
263
+
static struct qcom_icc_node mas_rpm_inst = {
264
+
.name = "mas_rpm_inst",
265
+
.id = MSM8974_CNOC_MAS_RPM_INST,
266
+
.buswidth = 8,
267
+
.mas_rpm_id = 45,
268
+
.slv_rpm_id = -1,
269
+
};
306
270
307
-
static struct msm8974_icc_node * const msm8974_cnoc_nodes[] = {
271
+
static struct qcom_icc_node mas_rpm_data = {
272
+
.name = "mas_rpm_data",
273
+
.id = MSM8974_CNOC_MAS_RPM_DATA,
274
+
.buswidth = 8,
275
+
.mas_rpm_id = 46,
276
+
.slv_rpm_id = -1,
277
+
};
278
+
279
+
static struct qcom_icc_node mas_rpm_sys = {
280
+
.name = "mas_rpm_sys",
281
+
.id = MSM8974_CNOC_MAS_RPM_SYS,
282
+
.buswidth = 8,
283
+
.mas_rpm_id = 47,
284
+
.slv_rpm_id = -1,
285
+
};
286
+
287
+
static struct qcom_icc_node mas_dehr = {
288
+
.name = "mas_dehr",
289
+
.id = MSM8974_CNOC_MAS_DEHR,
290
+
.buswidth = 8,
291
+
.mas_rpm_id = 48,
292
+
.slv_rpm_id = -1,
293
+
};
294
+
295
+
static struct qcom_icc_node mas_qdss_dap = {
296
+
.name = "mas_qdss_dap",
297
+
.id = MSM8974_CNOC_MAS_QDSS_DAP,
298
+
.buswidth = 8,
299
+
.mas_rpm_id = 49,
300
+
.slv_rpm_id = -1,
301
+
};
302
+
303
+
static struct qcom_icc_node mas_spdm = {
304
+
.name = "mas_spdm",
305
+
.id = MSM8974_CNOC_MAS_SPDM,
306
+
.buswidth = 8,
307
+
.mas_rpm_id = 50,
308
+
.slv_rpm_id = -1,
309
+
};
310
+
311
+
static struct qcom_icc_node mas_tic = {
312
+
.name = "mas_tic",
313
+
.id = MSM8974_CNOC_MAS_TIC,
314
+
.buswidth = 8,
315
+
.mas_rpm_id = 51,
316
+
.slv_rpm_id = -1,
317
+
};
318
+
319
+
static struct qcom_icc_node slv_clk_ctl = {
320
+
.name = "slv_clk_ctl",
321
+
.id = MSM8974_CNOC_SLV_CLK_CTL,
322
+
.buswidth = 8,
323
+
.mas_rpm_id = -1,
324
+
.slv_rpm_id = 47,
325
+
};
326
+
327
+
static struct qcom_icc_node slv_cnoc_mss = {
328
+
.name = "slv_cnoc_mss",
329
+
.id = MSM8974_CNOC_SLV_CNOC_MSS,
330
+
.buswidth = 8,
331
+
.mas_rpm_id = -1,
332
+
.slv_rpm_id = 48,
333
+
};
334
+
335
+
static struct qcom_icc_node slv_security = {
336
+
.name = "slv_security",
337
+
.id = MSM8974_CNOC_SLV_SECURITY,
338
+
.buswidth = 8,
339
+
.mas_rpm_id = -1,
340
+
.slv_rpm_id = 49,
341
+
};
342
+
343
+
static struct qcom_icc_node slv_tcsr = {
344
+
.name = "slv_tcsr",
345
+
.id = MSM8974_CNOC_SLV_TCSR,
346
+
.buswidth = 8,
347
+
.mas_rpm_id = -1,
348
+
.slv_rpm_id = 50,
349
+
};
350
+
351
+
static struct qcom_icc_node slv_tlmm = {
352
+
.name = "slv_tlmm",
353
+
.id = MSM8974_CNOC_SLV_TLMM,
354
+
.buswidth = 8,
355
+
.mas_rpm_id = -1,
356
+
.slv_rpm_id = 51,
357
+
};
358
+
359
+
static struct qcom_icc_node slv_crypto_0_cfg = {
360
+
.name = "slv_crypto_0_cfg",
361
+
.id = MSM8974_CNOC_SLV_CRYPTO_0_CFG,
362
+
.buswidth = 8,
363
+
.mas_rpm_id = -1,
364
+
.slv_rpm_id = 52,
365
+
};
366
+
367
+
static struct qcom_icc_node slv_crypto_1_cfg = {
368
+
.name = "slv_crypto_1_cfg",
369
+
.id = MSM8974_CNOC_SLV_CRYPTO_1_CFG,
370
+
.buswidth = 8,
371
+
.mas_rpm_id = -1,
372
+
.slv_rpm_id = 53,
373
+
};
374
+
375
+
static struct qcom_icc_node slv_imem_cfg = {
376
+
.name = "slv_imem_cfg",
377
+
.id = MSM8974_CNOC_SLV_IMEM_CFG,
378
+
.buswidth = 8,
379
+
.mas_rpm_id = -1,
380
+
.slv_rpm_id = 54,
381
+
};
382
+
383
+
static struct qcom_icc_node slv_message_ram = {
384
+
.name = "slv_message_ram",
385
+
.id = MSM8974_CNOC_SLV_MESSAGE_RAM,
386
+
.buswidth = 8,
387
+
.mas_rpm_id = -1,
388
+
.slv_rpm_id = 55,
389
+
};
390
+
391
+
static struct qcom_icc_node slv_bimc_cfg = {
392
+
.name = "slv_bimc_cfg",
393
+
.id = MSM8974_CNOC_SLV_BIMC_CFG,
394
+
.buswidth = 8,
395
+
.mas_rpm_id = -1,
396
+
.slv_rpm_id = 56,
397
+
};
398
+
399
+
static struct qcom_icc_node slv_boot_rom = {
400
+
.name = "slv_boot_rom",
401
+
.id = MSM8974_CNOC_SLV_BOOT_ROM,
402
+
.buswidth = 8,
403
+
.mas_rpm_id = -1,
404
+
.slv_rpm_id = 57,
405
+
};
406
+
407
+
static struct qcom_icc_node slv_pmic_arb = {
408
+
.name = "slv_pmic_arb",
409
+
.id = MSM8974_CNOC_SLV_PMIC_ARB,
410
+
.buswidth = 8,
411
+
.mas_rpm_id = -1,
412
+
.slv_rpm_id = 59,
413
+
};
414
+
415
+
static struct qcom_icc_node slv_spdm_wrapper = {
416
+
.name = "slv_spdm_wrapper",
417
+
.id = MSM8974_CNOC_SLV_SPDM_WRAPPER,
418
+
.buswidth = 8,
419
+
.mas_rpm_id = -1,
420
+
.slv_rpm_id = 60,
421
+
};
422
+
423
+
static struct qcom_icc_node slv_dehr_cfg = {
424
+
.name = "slv_dehr_cfg",
425
+
.id = MSM8974_CNOC_SLV_DEHR_CFG,
426
+
.buswidth = 8,
427
+
.mas_rpm_id = -1,
428
+
.slv_rpm_id = 61,
429
+
};
430
+
431
+
static struct qcom_icc_node slv_mpm = {
432
+
.name = "slv_mpm",
433
+
.id = MSM8974_CNOC_SLV_MPM,
434
+
.buswidth = 8,
435
+
.mas_rpm_id = -1,
436
+
.slv_rpm_id = 62,
437
+
};
438
+
439
+
static struct qcom_icc_node slv_qdss_cfg = {
440
+
.name = "slv_qdss_cfg",
441
+
.id = MSM8974_CNOC_SLV_QDSS_CFG,
442
+
.buswidth = 8,
443
+
.mas_rpm_id = -1,
444
+
.slv_rpm_id = 63,
445
+
};
446
+
447
+
static struct qcom_icc_node slv_rbcpr_cfg = {
448
+
.name = "slv_rbcpr_cfg",
449
+
.id = MSM8974_CNOC_SLV_RBCPR_CFG,
450
+
.buswidth = 8,
451
+
.mas_rpm_id = -1,
452
+
.slv_rpm_id = 64,
453
+
};
454
+
455
+
static struct qcom_icc_node slv_rbcpr_qdss_apu_cfg = {
456
+
.name = "slv_rbcpr_qdss_apu_cfg",
457
+
.id = MSM8974_CNOC_SLV_RBCPR_QDSS_APU_CFG,
458
+
.buswidth = 8,
459
+
.mas_rpm_id = -1,
460
+
.slv_rpm_id = 65,
461
+
};
462
+
463
+
static struct qcom_icc_node cnoc_to_snoc = {
464
+
.name = "cnoc_to_snoc",
465
+
.id = MSM8974_CNOC_TO_SNOC,
466
+
.buswidth = 8,
467
+
.mas_rpm_id = 52,
468
+
.slv_rpm_id = 75,
469
+
};
470
+
471
+
static struct qcom_icc_node slv_cnoc_onoc_cfg = {
472
+
.name = "slv_cnoc_onoc_cfg",
473
+
.id = MSM8974_CNOC_SLV_CNOC_ONOC_CFG,
474
+
.buswidth = 8,
475
+
.mas_rpm_id = -1,
476
+
.slv_rpm_id = 68,
477
+
};
478
+
479
+
static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = {
480
+
.name = "slv_cnoc_mnoc_mmss_cfg",
481
+
.id = MSM8974_CNOC_SLV_CNOC_MNOC_MMSS_CFG,
482
+
.buswidth = 8,
483
+
.mas_rpm_id = -1,
484
+
.slv_rpm_id = 58,
485
+
};
486
+
487
+
static struct qcom_icc_node slv_cnoc_mnoc_cfg = {
488
+
.name = "slv_cnoc_mnoc_cfg",
489
+
.id = MSM8974_CNOC_SLV_CNOC_MNOC_CFG,
490
+
.buswidth = 8,
491
+
.mas_rpm_id = -1,
492
+
.slv_rpm_id = 66,
493
+
};
494
+
495
+
static struct qcom_icc_node slv_pnoc_cfg = {
496
+
.name = "slv_pnoc_cfg",
497
+
.id = MSM8974_CNOC_SLV_PNOC_CFG,
498
+
.buswidth = 8,
499
+
.mas_rpm_id = -1,
500
+
.slv_rpm_id = 69,
501
+
};
502
+
503
+
static struct qcom_icc_node slv_snoc_mpu_cfg = {
504
+
.name = "slv_snoc_mpu_cfg",
505
+
.id = MSM8974_CNOC_SLV_SNOC_MPU_CFG,
506
+
.buswidth = 8,
507
+
.mas_rpm_id = -1,
508
+
.slv_rpm_id = 67,
509
+
};
510
+
511
+
static struct qcom_icc_node slv_snoc_cfg = {
512
+
.name = "slv_snoc_cfg",
513
+
.id = MSM8974_CNOC_SLV_SNOC_CFG,
514
+
.buswidth = 8,
515
+
.mas_rpm_id = -1,
516
+
.slv_rpm_id = 70,
517
+
};
518
+
519
+
static struct qcom_icc_node slv_ebi1_dll_cfg = {
520
+
.name = "slv_ebi1_dll_cfg",
521
+
.id = MSM8974_CNOC_SLV_EBI1_DLL_CFG,
522
+
.buswidth = 8,
523
+
.mas_rpm_id = -1,
524
+
.slv_rpm_id = 71,
525
+
};
526
+
527
+
static struct qcom_icc_node slv_phy_apu_cfg = {
528
+
.name = "slv_phy_apu_cfg",
529
+
.id = MSM8974_CNOC_SLV_PHY_APU_CFG,
530
+
.buswidth = 8,
531
+
.mas_rpm_id = -1,
532
+
.slv_rpm_id = 72,
533
+
};
534
+
535
+
static struct qcom_icc_node slv_ebi1_phy_cfg = {
536
+
.name = "slv_ebi1_phy_cfg",
537
+
.id = MSM8974_CNOC_SLV_EBI1_PHY_CFG,
538
+
.buswidth = 8,
539
+
.mas_rpm_id = -1,
540
+
.slv_rpm_id = 73,
541
+
};
542
+
543
+
static struct qcom_icc_node slv_rpm = {
544
+
.name = "slv_rpm",
545
+
.id = MSM8974_CNOC_SLV_RPM,
546
+
.buswidth = 8,
547
+
.mas_rpm_id = -1,
548
+
.slv_rpm_id = 74,
549
+
};
550
+
551
+
static struct qcom_icc_node slv_service_cnoc = {
552
+
.name = "slv_service_cnoc",
553
+
.id = MSM8974_CNOC_SLV_SERVICE_CNOC,
554
+
.buswidth = 8,
555
+
.mas_rpm_id = -1,
556
+
.slv_rpm_id = 76,
557
+
};
558
+
559
+
static struct qcom_icc_node * const msm8974_cnoc_nodes[] = {
308
560
[CNOC_MAS_RPM_INST] = &mas_rpm_inst,
309
561
[CNOC_MAS_RPM_DATA] = &mas_rpm_data,
310
562
[CNOC_MAS_RPM_SYS] = &mas_rpm_sys,
···
605
335
[CNOC_SLV_SERVICE_CNOC] = &slv_service_cnoc,
606
336
};
607
337
608
-
static const struct msm8974_icc_desc msm8974_cnoc = {
338
+
static const struct qcom_icc_desc msm8974_cnoc = {
609
339
.nodes = msm8974_cnoc_nodes,
610
340
.num_nodes = ARRAY_SIZE(msm8974_cnoc_nodes),
341
+
.bus_clk_desc = &bus_2_clk,
342
+
.get_bw = msm8974_get_bw,
343
+
.ignore_enxio = true,
611
344
};
612
345
613
-
DEFINE_QNODE(mas_graphics_3d, MSM8974_MNOC_MAS_GRAPHICS_3D, 16, 6, -1, MSM8974_MNOC_TO_BIMC);
614
-
DEFINE_QNODE(mas_jpeg, MSM8974_MNOC_MAS_JPEG, 16, 7, -1, MSM8974_MNOC_TO_BIMC);
615
-
DEFINE_QNODE(mas_mdp_port0, MSM8974_MNOC_MAS_MDP_PORT0, 16, 8, -1, MSM8974_MNOC_TO_BIMC);
616
-
DEFINE_QNODE(mas_video_p0, MSM8974_MNOC_MAS_VIDEO_P0, 16, 9, -1);
617
-
DEFINE_QNODE(mas_video_p1, MSM8974_MNOC_MAS_VIDEO_P1, 16, 10, -1);
618
-
DEFINE_QNODE(mas_vfe, MSM8974_MNOC_MAS_VFE, 16, 11, -1, MSM8974_MNOC_TO_BIMC);
619
-
DEFINE_QNODE(mnoc_to_cnoc, MSM8974_MNOC_TO_CNOC, 16, 4, -1);
620
-
DEFINE_QNODE(mnoc_to_bimc, MSM8974_MNOC_TO_BIMC, 16, -1, 16, MSM8974_BIMC_TO_MNOC);
621
-
DEFINE_QNODE(slv_camera_cfg, MSM8974_MNOC_SLV_CAMERA_CFG, 16, -1, 3);
622
-
DEFINE_QNODE(slv_display_cfg, MSM8974_MNOC_SLV_DISPLAY_CFG, 16, -1, 4);
623
-
DEFINE_QNODE(slv_ocmem_cfg, MSM8974_MNOC_SLV_OCMEM_CFG, 16, -1, 5);
624
-
DEFINE_QNODE(slv_cpr_cfg, MSM8974_MNOC_SLV_CPR_CFG, 16, -1, 6);
625
-
DEFINE_QNODE(slv_cpr_xpu_cfg, MSM8974_MNOC_SLV_CPR_XPU_CFG, 16, -1, 7);
626
-
DEFINE_QNODE(slv_misc_cfg, MSM8974_MNOC_SLV_MISC_CFG, 16, -1, 8);
627
-
DEFINE_QNODE(slv_misc_xpu_cfg, MSM8974_MNOC_SLV_MISC_XPU_CFG, 16, -1, 9);
628
-
DEFINE_QNODE(slv_venus_cfg, MSM8974_MNOC_SLV_VENUS_CFG, 16, -1, 10);
629
-
DEFINE_QNODE(slv_graphics_3d_cfg, MSM8974_MNOC_SLV_GRAPHICS_3D_CFG, 16, -1, 11);
630
-
DEFINE_QNODE(slv_mmss_clk_cfg, MSM8974_MNOC_SLV_MMSS_CLK_CFG, 16, -1, 12);
631
-
DEFINE_QNODE(slv_mmss_clk_xpu_cfg, MSM8974_MNOC_SLV_MMSS_CLK_XPU_CFG, 16, -1, 13);
632
-
DEFINE_QNODE(slv_mnoc_mpu_cfg, MSM8974_MNOC_SLV_MNOC_MPU_CFG, 16, -1, 14);
633
-
DEFINE_QNODE(slv_onoc_mpu_cfg, MSM8974_MNOC_SLV_ONOC_MPU_CFG, 16, -1, 15);
634
-
DEFINE_QNODE(slv_service_mnoc, MSM8974_MNOC_SLV_SERVICE_MNOC, 16, -1, 17);
346
+
static const u16 mas_graphics_3d_links[] = {
347
+
MSM8974_MNOC_TO_BIMC
348
+
};
635
349
636
-
static struct msm8974_icc_node * const msm8974_mnoc_nodes[] = {
350
+
static struct qcom_icc_node mas_graphics_3d = {
351
+
.name = "mas_graphics_3d",
352
+
.id = MSM8974_MNOC_MAS_GRAPHICS_3D,
353
+
.buswidth = 16,
354
+
.mas_rpm_id = 6,
355
+
.slv_rpm_id = -1,
356
+
.num_links = ARRAY_SIZE(mas_graphics_3d_links),
357
+
.links = mas_graphics_3d_links,
358
+
};
359
+
360
+
static const u16 mas_jpeg_links[] = {
361
+
MSM8974_MNOC_TO_BIMC
362
+
};
363
+
364
+
static struct qcom_icc_node mas_jpeg = {
365
+
.name = "mas_jpeg",
366
+
.id = MSM8974_MNOC_MAS_JPEG,
367
+
.buswidth = 16,
368
+
.mas_rpm_id = 7,
369
+
.slv_rpm_id = -1,
370
+
.num_links = ARRAY_SIZE(mas_jpeg_links),
371
+
.links = mas_jpeg_links,
372
+
};
373
+
374
+
static const u16 mas_mdp_port0_links[] = {
375
+
MSM8974_MNOC_TO_BIMC
376
+
};
377
+
378
+
static struct qcom_icc_node mas_mdp_port0 = {
379
+
.name = "mas_mdp_port0",
380
+
.id = MSM8974_MNOC_MAS_MDP_PORT0,
381
+
.buswidth = 16,
382
+
.mas_rpm_id = 8,
383
+
.slv_rpm_id = -1,
384
+
.num_links = ARRAY_SIZE(mas_mdp_port0_links),
385
+
.links = mas_mdp_port0_links,
386
+
};
387
+
388
+
static struct qcom_icc_node mas_video_p0 = {
389
+
.name = "mas_video_p0",
390
+
.id = MSM8974_MNOC_MAS_VIDEO_P0,
391
+
.buswidth = 16,
392
+
.mas_rpm_id = 9,
393
+
.slv_rpm_id = -1,
394
+
};
395
+
396
+
static struct qcom_icc_node mas_video_p1 = {
397
+
.name = "mas_video_p1",
398
+
.id = MSM8974_MNOC_MAS_VIDEO_P1,
399
+
.buswidth = 16,
400
+
.mas_rpm_id = 10,
401
+
.slv_rpm_id = -1,
402
+
};
403
+
404
+
static const u16 mas_vfe_links[] = {
405
+
MSM8974_MNOC_TO_BIMC
406
+
};
407
+
408
+
static struct qcom_icc_node mas_vfe = {
409
+
.name = "mas_vfe",
410
+
.id = MSM8974_MNOC_MAS_VFE,
411
+
.buswidth = 16,
412
+
.mas_rpm_id = 11,
413
+
.slv_rpm_id = -1,
414
+
.num_links = ARRAY_SIZE(mas_vfe_links),
415
+
.links = mas_vfe_links,
416
+
};
417
+
418
+
static struct qcom_icc_node mnoc_to_cnoc = {
419
+
.name = "mnoc_to_cnoc",
420
+
.id = MSM8974_MNOC_TO_CNOC,
421
+
.buswidth = 16,
422
+
.mas_rpm_id = 4,
423
+
.slv_rpm_id = -1,
424
+
};
425
+
426
+
static const u16 mnoc_to_bimc_links[] = {
427
+
MSM8974_BIMC_TO_MNOC
428
+
};
429
+
430
+
static struct qcom_icc_node mnoc_to_bimc = {
431
+
.name = "mnoc_to_bimc",
432
+
.id = MSM8974_MNOC_TO_BIMC,
433
+
.buswidth = 16,
434
+
.mas_rpm_id = -1,
435
+
.slv_rpm_id = 16,
436
+
.num_links = ARRAY_SIZE(mnoc_to_bimc_links),
437
+
.links = mnoc_to_bimc_links,
438
+
};
439
+
440
+
static struct qcom_icc_node slv_camera_cfg = {
441
+
.name = "slv_camera_cfg",
442
+
.id = MSM8974_MNOC_SLV_CAMERA_CFG,
443
+
.buswidth = 16,
444
+
.mas_rpm_id = -1,
445
+
.slv_rpm_id = 3,
446
+
};
447
+
448
+
static struct qcom_icc_node slv_display_cfg = {
449
+
.name = "slv_display_cfg",
450
+
.id = MSM8974_MNOC_SLV_DISPLAY_CFG,
451
+
.buswidth = 16,
452
+
.mas_rpm_id = -1,
453
+
.slv_rpm_id = 4,
454
+
};
455
+
456
+
static struct qcom_icc_node slv_ocmem_cfg = {
457
+
.name = "slv_ocmem_cfg",
458
+
.id = MSM8974_MNOC_SLV_OCMEM_CFG,
459
+
.buswidth = 16,
460
+
.mas_rpm_id = -1,
461
+
.slv_rpm_id = 5,
462
+
};
463
+
464
+
static struct qcom_icc_node slv_cpr_cfg = {
465
+
.name = "slv_cpr_cfg",
466
+
.id = MSM8974_MNOC_SLV_CPR_CFG,
467
+
.buswidth = 16,
468
+
.mas_rpm_id = -1,
469
+
.slv_rpm_id = 6,
470
+
};
471
+
472
+
static struct qcom_icc_node slv_cpr_xpu_cfg = {
473
+
.name = "slv_cpr_xpu_cfg",
474
+
.id = MSM8974_MNOC_SLV_CPR_XPU_CFG,
475
+
.buswidth = 16,
476
+
.mas_rpm_id = -1,
477
+
.slv_rpm_id = 7,
478
+
};
479
+
480
+
static struct qcom_icc_node slv_misc_cfg = {
481
+
.name = "slv_misc_cfg",
482
+
.id = MSM8974_MNOC_SLV_MISC_CFG,
483
+
.buswidth = 16,
484
+
.mas_rpm_id = -1,
485
+
.slv_rpm_id = 8,
486
+
};
487
+
488
+
static struct qcom_icc_node slv_misc_xpu_cfg = {
489
+
.name = "slv_misc_xpu_cfg",
490
+
.id = MSM8974_MNOC_SLV_MISC_XPU_CFG,
491
+
.buswidth = 16,
492
+
.mas_rpm_id = -1,
493
+
.slv_rpm_id = 9,
494
+
};
495
+
496
+
static struct qcom_icc_node slv_venus_cfg = {
497
+
.name = "slv_venus_cfg",
498
+
.id = MSM8974_MNOC_SLV_VENUS_CFG,
499
+
.buswidth = 16,
500
+
.mas_rpm_id = -1,
501
+
.slv_rpm_id = 10,
502
+
};
503
+
504
+
static struct qcom_icc_node slv_graphics_3d_cfg = {
505
+
.name = "slv_graphics_3d_cfg",
506
+
.id = MSM8974_MNOC_SLV_GRAPHICS_3D_CFG,
507
+
.buswidth = 16,
508
+
.mas_rpm_id = -1,
509
+
.slv_rpm_id = 11,
510
+
};
511
+
512
+
static struct qcom_icc_node slv_mmss_clk_cfg = {
513
+
.name = "slv_mmss_clk_cfg",
514
+
.id = MSM8974_MNOC_SLV_MMSS_CLK_CFG,
515
+
.buswidth = 16,
516
+
.mas_rpm_id = -1,
517
+
.slv_rpm_id = 12,
518
+
};
519
+
520
+
static struct qcom_icc_node slv_mmss_clk_xpu_cfg = {
521
+
.name = "slv_mmss_clk_xpu_cfg",
522
+
.id = MSM8974_MNOC_SLV_MMSS_CLK_XPU_CFG,
523
+
.buswidth = 16,
524
+
.mas_rpm_id = -1,
525
+
.slv_rpm_id = 13,
526
+
};
527
+
528
+
static struct qcom_icc_node slv_mnoc_mpu_cfg = {
529
+
.name = "slv_mnoc_mpu_cfg",
530
+
.id = MSM8974_MNOC_SLV_MNOC_MPU_CFG,
531
+
.buswidth = 16,
532
+
.mas_rpm_id = -1,
533
+
.slv_rpm_id = 14,
534
+
};
535
+
536
+
static struct qcom_icc_node slv_onoc_mpu_cfg = {
537
+
.name = "slv_onoc_mpu_cfg",
538
+
.id = MSM8974_MNOC_SLV_ONOC_MPU_CFG,
539
+
.buswidth = 16,
540
+
.mas_rpm_id = -1,
541
+
.slv_rpm_id = 15,
542
+
};
543
+
544
+
static struct qcom_icc_node slv_service_mnoc = {
545
+
.name = "slv_service_mnoc",
546
+
.id = MSM8974_MNOC_SLV_SERVICE_MNOC,
547
+
.buswidth = 16,
548
+
.mas_rpm_id = -1,
549
+
.slv_rpm_id = 17,
550
+
};
551
+
552
+
static struct qcom_icc_node * const msm8974_mnoc_nodes[] = {
637
553
[MNOC_MAS_GRAPHICS_3D] = &mas_graphics_3d,
638
554
[MNOC_MAS_JPEG] = &mas_jpeg,
639
555
[MNOC_MAS_MDP_PORT0] = &mas_mdp_port0,
···
844
388
[MNOC_SLV_SERVICE_MNOC] = &slv_service_mnoc,
845
389
};
846
390
847
-
static const struct msm8974_icc_desc msm8974_mnoc = {
391
+
static const struct qcom_icc_desc msm8974_mnoc = {
848
392
.nodes = msm8974_mnoc_nodes,
849
393
.num_nodes = ARRAY_SIZE(msm8974_mnoc_nodes),
394
+
.get_bw = msm8974_get_bw,
395
+
.ignore_enxio = true,
850
396
};
851
397
852
-
DEFINE_QNODE(ocmem_noc_to_ocmem_vnoc, MSM8974_OCMEM_NOC_TO_OCMEM_VNOC, 16, 54, 78, MSM8974_OCMEM_SLV_OCMEM);
853
-
DEFINE_QNODE(mas_jpeg_ocmem, MSM8974_OCMEM_MAS_JPEG_OCMEM, 16, 13, -1);
854
-
DEFINE_QNODE(mas_mdp_ocmem, MSM8974_OCMEM_MAS_MDP_OCMEM, 16, 14, -1);
855
-
DEFINE_QNODE(mas_video_p0_ocmem, MSM8974_OCMEM_MAS_VIDEO_P0_OCMEM, 16, 15, -1);
856
-
DEFINE_QNODE(mas_video_p1_ocmem, MSM8974_OCMEM_MAS_VIDEO_P1_OCMEM, 16, 16, -1);
857
-
DEFINE_QNODE(mas_vfe_ocmem, MSM8974_OCMEM_MAS_VFE_OCMEM, 16, 17, -1);
858
-
DEFINE_QNODE(mas_cnoc_onoc_cfg, MSM8974_OCMEM_MAS_CNOC_ONOC_CFG, 16, 12, -1);
859
-
DEFINE_QNODE(slv_service_onoc, MSM8974_OCMEM_SLV_SERVICE_ONOC, 16, -1, 19);
860
-
DEFINE_QNODE(slv_ocmem, MSM8974_OCMEM_SLV_OCMEM, 16, -1, 18);
398
+
static const u16 ocmem_noc_to_ocmem_vnoc_links[] = {
399
+
MSM8974_OCMEM_SLV_OCMEM
400
+
};
401
+
402
+
static struct qcom_icc_node ocmem_noc_to_ocmem_vnoc = {
403
+
.name = "ocmem_noc_to_ocmem_vnoc",
404
+
.id = MSM8974_OCMEM_NOC_TO_OCMEM_VNOC,
405
+
.buswidth = 16,
406
+
.mas_rpm_id = 54,
407
+
.slv_rpm_id = 78,
408
+
.num_links = ARRAY_SIZE(ocmem_noc_to_ocmem_vnoc_links),
409
+
.links = ocmem_noc_to_ocmem_vnoc_links,
410
+
};
411
+
412
+
static struct qcom_icc_node mas_jpeg_ocmem = {
413
+
.name = "mas_jpeg_ocmem",
414
+
.id = MSM8974_OCMEM_MAS_JPEG_OCMEM,
415
+
.buswidth = 16,
416
+
.mas_rpm_id = 13,
417
+
.slv_rpm_id = -1,
418
+
};
419
+
420
+
static struct qcom_icc_node mas_mdp_ocmem = {
421
+
.name = "mas_mdp_ocmem",
422
+
.id = MSM8974_OCMEM_MAS_MDP_OCMEM,
423
+
.buswidth = 16,
424
+
.mas_rpm_id = 14,
425
+
.slv_rpm_id = -1,
426
+
};
427
+
428
+
static struct qcom_icc_node mas_video_p0_ocmem = {
429
+
.name = "mas_video_p0_ocmem",
430
+
.id = MSM8974_OCMEM_MAS_VIDEO_P0_OCMEM,
431
+
.buswidth = 16,
432
+
.mas_rpm_id = 15,
433
+
.slv_rpm_id = -1,
434
+
};
435
+
436
+
static struct qcom_icc_node mas_video_p1_ocmem = {
437
+
.name = "mas_video_p1_ocmem",
438
+
.id = MSM8974_OCMEM_MAS_VIDEO_P1_OCMEM,
439
+
.buswidth = 16,
440
+
.mas_rpm_id = 16,
441
+
.slv_rpm_id = -1,
442
+
};
443
+
444
+
static struct qcom_icc_node mas_vfe_ocmem = {
445
+
.name = "mas_vfe_ocmem",
446
+
.id = MSM8974_OCMEM_MAS_VFE_OCMEM,
447
+
.buswidth = 16,
448
+
.mas_rpm_id = 17,
449
+
.slv_rpm_id = -1,
450
+
};
451
+
452
+
static struct qcom_icc_node mas_cnoc_onoc_cfg = {
453
+
.name = "mas_cnoc_onoc_cfg",
454
+
.id = MSM8974_OCMEM_MAS_CNOC_ONOC_CFG,
455
+
.buswidth = 16,
456
+
.mas_rpm_id = 12,
457
+
.slv_rpm_id = -1,
458
+
};
459
+
460
+
static struct qcom_icc_node slv_service_onoc = {
461
+
.name = "slv_service_onoc",
462
+
.id = MSM8974_OCMEM_SLV_SERVICE_ONOC,
463
+
.buswidth = 16,
464
+
.mas_rpm_id = -1,
465
+
.slv_rpm_id = 19,
466
+
};
467
+
468
+
static struct qcom_icc_node slv_ocmem = {
469
+
.name = "slv_ocmem",
470
+
.id = MSM8974_OCMEM_SLV_OCMEM,
471
+
.buswidth = 16,
472
+
.mas_rpm_id = -1,
473
+
.slv_rpm_id = 18,
474
+
};
861
475
862
476
/* Virtual NoC is needed for connection to OCMEM */
863
-
DEFINE_QNODE(ocmem_vnoc_to_onoc, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC, 16, 56, 79, MSM8974_OCMEM_NOC_TO_OCMEM_VNOC);
864
-
DEFINE_QNODE(ocmem_vnoc_to_snoc, MSM8974_OCMEM_VNOC_TO_SNOC, 8, 57, 80);
865
-
DEFINE_QNODE(mas_v_ocmem_gfx3d, MSM8974_OCMEM_VNOC_MAS_GFX3D, 8, 55, -1, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC);
477
+
static const u16 ocmem_vnoc_to_onoc_links[] = {
478
+
MSM8974_OCMEM_NOC_TO_OCMEM_VNOC
479
+
};
866
480
867
-
static struct msm8974_icc_node * const msm8974_onoc_nodes[] = {
481
+
static struct qcom_icc_node ocmem_vnoc_to_onoc = {
482
+
.name = "ocmem_vnoc_to_onoc",
483
+
.id = MSM8974_OCMEM_VNOC_TO_OCMEM_NOC,
484
+
.buswidth = 16,
485
+
.mas_rpm_id = 56,
486
+
.slv_rpm_id = 79,
487
+
.num_links = ARRAY_SIZE(ocmem_vnoc_to_onoc_links),
488
+
.links = ocmem_vnoc_to_onoc_links,
489
+
};
490
+
491
+
static struct qcom_icc_node ocmem_vnoc_to_snoc = {
492
+
.name = "ocmem_vnoc_to_snoc",
493
+
.id = MSM8974_OCMEM_VNOC_TO_SNOC,
494
+
.buswidth = 8,
495
+
.mas_rpm_id = 57,
496
+
.slv_rpm_id = 80,
497
+
};
498
+
499
+
static const u16 mas_v_ocmem_gfx3d_links[] = {
500
+
MSM8974_OCMEM_VNOC_TO_OCMEM_NOC
501
+
};
502
+
503
+
static struct qcom_icc_node mas_v_ocmem_gfx3d = {
504
+
.name = "mas_v_ocmem_gfx3d",
505
+
.id = MSM8974_OCMEM_VNOC_MAS_GFX3D,
506
+
.buswidth = 8,
507
+
.mas_rpm_id = 55,
508
+
.slv_rpm_id = -1,
509
+
.num_links = ARRAY_SIZE(mas_v_ocmem_gfx3d_links),
510
+
.links = mas_v_ocmem_gfx3d_links,
511
+
};
512
+
513
+
514
+
static struct qcom_icc_node * const msm8974_onoc_nodes[] = {
868
515
[OCMEM_NOC_TO_OCMEM_VNOC] = &ocmem_noc_to_ocmem_vnoc,
869
516
[OCMEM_MAS_JPEG_OCMEM] = &mas_jpeg_ocmem,
870
517
[OCMEM_MAS_MDP_OCMEM] = &mas_mdp_ocmem,
···
982
423
[OCMEM_SLV_OCMEM] = &slv_ocmem,
983
424
};
984
425
985
-
static const struct msm8974_icc_desc msm8974_onoc = {
426
+
static const struct qcom_icc_desc msm8974_onoc = {
986
427
.nodes = msm8974_onoc_nodes,
987
428
.num_nodes = ARRAY_SIZE(msm8974_onoc_nodes),
429
+
.bus_clk_desc = &gpu_mem_2_clk,
430
+
.get_bw = msm8974_get_bw,
431
+
.ignore_enxio = true,
988
432
};
989
433
990
-
DEFINE_QNODE(mas_pnoc_cfg, MSM8974_PNOC_MAS_PNOC_CFG, 8, 43, -1);
991
-
DEFINE_QNODE(mas_sdcc_1, MSM8974_PNOC_MAS_SDCC_1, 8, 33, -1, MSM8974_PNOC_TO_SNOC);
992
-
DEFINE_QNODE(mas_sdcc_3, MSM8974_PNOC_MAS_SDCC_3, 8, 34, -1, MSM8974_PNOC_TO_SNOC);
993
-
DEFINE_QNODE(mas_sdcc_4, MSM8974_PNOC_MAS_SDCC_4, 8, 36, -1, MSM8974_PNOC_TO_SNOC);
994
-
DEFINE_QNODE(mas_sdcc_2, MSM8974_PNOC_MAS_SDCC_2, 8, 35, -1, MSM8974_PNOC_TO_SNOC);
995
-
DEFINE_QNODE(mas_tsif, MSM8974_PNOC_MAS_TSIF, 8, 37, -1, MSM8974_PNOC_TO_SNOC);
996
-
DEFINE_QNODE(mas_bam_dma, MSM8974_PNOC_MAS_BAM_DMA, 8, 38, -1);
997
-
DEFINE_QNODE(mas_blsp_2, MSM8974_PNOC_MAS_BLSP_2, 8, 39, -1, MSM8974_PNOC_TO_SNOC);
998
-
DEFINE_QNODE(mas_usb_hsic, MSM8974_PNOC_MAS_USB_HSIC, 8, 40, -1, MSM8974_PNOC_TO_SNOC);
999
-
DEFINE_QNODE(mas_blsp_1, MSM8974_PNOC_MAS_BLSP_1, 8, 41, -1, MSM8974_PNOC_TO_SNOC);
1000
-
DEFINE_QNODE(mas_usb_hs, MSM8974_PNOC_MAS_USB_HS, 8, 42, -1, MSM8974_PNOC_TO_SNOC);
1001
-
DEFINE_QNODE(pnoc_to_snoc, MSM8974_PNOC_TO_SNOC, 8, 44, 45, MSM8974_SNOC_TO_PNOC, MSM8974_PNOC_SLV_PRNG);
1002
-
DEFINE_QNODE(slv_sdcc_1, MSM8974_PNOC_SLV_SDCC_1, 8, -1, 31);
1003
-
DEFINE_QNODE(slv_sdcc_3, MSM8974_PNOC_SLV_SDCC_3, 8, -1, 32);
1004
-
DEFINE_QNODE(slv_sdcc_2, MSM8974_PNOC_SLV_SDCC_2, 8, -1, 33);
1005
-
DEFINE_QNODE(slv_sdcc_4, MSM8974_PNOC_SLV_SDCC_4, 8, -1, 34);
1006
-
DEFINE_QNODE(slv_tsif, MSM8974_PNOC_SLV_TSIF, 8, -1, 35);
1007
-
DEFINE_QNODE(slv_bam_dma, MSM8974_PNOC_SLV_BAM_DMA, 8, -1, 36);
1008
-
DEFINE_QNODE(slv_blsp_2, MSM8974_PNOC_SLV_BLSP_2, 8, -1, 37);
1009
-
DEFINE_QNODE(slv_usb_hsic, MSM8974_PNOC_SLV_USB_HSIC, 8, -1, 38);
1010
-
DEFINE_QNODE(slv_blsp_1, MSM8974_PNOC_SLV_BLSP_1, 8, -1, 39);
1011
-
DEFINE_QNODE(slv_usb_hs, MSM8974_PNOC_SLV_USB_HS, 8, -1, 40);
1012
-
DEFINE_QNODE(slv_pdm, MSM8974_PNOC_SLV_PDM, 8, -1, 41);
1013
-
DEFINE_QNODE(slv_periph_apu_cfg, MSM8974_PNOC_SLV_PERIPH_APU_CFG, 8, -1, 42);
1014
-
DEFINE_QNODE(slv_pnoc_mpu_cfg, MSM8974_PNOC_SLV_PNOC_MPU_CFG, 8, -1, 43);
1015
-
DEFINE_QNODE(slv_prng, MSM8974_PNOC_SLV_PRNG, 8, -1, 44, MSM8974_PNOC_TO_SNOC);
1016
-
DEFINE_QNODE(slv_service_pnoc, MSM8974_PNOC_SLV_SERVICE_PNOC, 8, -1, 46);
434
+
static struct qcom_icc_node mas_pnoc_cfg = {
435
+
.name = "mas_pnoc_cfg",
436
+
.id = MSM8974_PNOC_MAS_PNOC_CFG,
437
+
.buswidth = 8,
438
+
.mas_rpm_id = 43,
439
+
.slv_rpm_id = -1,
440
+
};
1017
441
1018
-
static struct msm8974_icc_node * const msm8974_pnoc_nodes[] = {
442
+
static const u16 mas_sdcc_1_links[] = {
443
+
MSM8974_PNOC_TO_SNOC
444
+
};
445
+
446
+
static struct qcom_icc_node mas_sdcc_1 = {
447
+
.name = "mas_sdcc_1",
448
+
.id = MSM8974_PNOC_MAS_SDCC_1,
449
+
.buswidth = 8,
450
+
.mas_rpm_id = 33,
451
+
.slv_rpm_id = -1,
452
+
.num_links = ARRAY_SIZE(mas_sdcc_1_links),
453
+
.links = mas_sdcc_1_links,
454
+
};
455
+
456
+
static const u16 mas_sdcc_3_links[] = {
457
+
MSM8974_PNOC_TO_SNOC
458
+
};
459
+
460
+
static struct qcom_icc_node mas_sdcc_3 = {
461
+
.name = "mas_sdcc_3",
462
+
.id = MSM8974_PNOC_MAS_SDCC_3,
463
+
.buswidth = 8,
464
+
.mas_rpm_id = 34,
465
+
.slv_rpm_id = -1,
466
+
.num_links = ARRAY_SIZE(mas_sdcc_3_links),
467
+
.links = mas_sdcc_3_links,
468
+
};
469
+
470
+
static const u16 mas_sdcc_4_links[] = {
471
+
MSM8974_PNOC_TO_SNOC
472
+
};
473
+
474
+
static struct qcom_icc_node mas_sdcc_4 = {
475
+
.name = "mas_sdcc_4",
476
+
.id = MSM8974_PNOC_MAS_SDCC_4,
477
+
.buswidth = 8,
478
+
.mas_rpm_id = 36,
479
+
.slv_rpm_id = -1,
480
+
.num_links = ARRAY_SIZE(mas_sdcc_4_links),
481
+
.links = mas_sdcc_4_links,
482
+
};
483
+
484
+
static const u16 mas_sdcc_2_links[] = {
485
+
MSM8974_PNOC_TO_SNOC
486
+
};
487
+
488
+
static struct qcom_icc_node mas_sdcc_2 = {
489
+
.name = "mas_sdcc_2",
490
+
.id = MSM8974_PNOC_MAS_SDCC_2,
491
+
.buswidth = 8,
492
+
.mas_rpm_id = 35,
493
+
.slv_rpm_id = -1,
494
+
.num_links = ARRAY_SIZE(mas_sdcc_2_links),
495
+
.links = mas_sdcc_2_links,
496
+
};
497
+
498
+
static const u16 mas_tsif_links[] = {
499
+
MSM8974_PNOC_TO_SNOC
500
+
};
501
+
502
+
static struct qcom_icc_node mas_tsif = {
503
+
.name = "mas_tsif",
504
+
.id = MSM8974_PNOC_MAS_TSIF,
505
+
.buswidth = 8,
506
+
.mas_rpm_id = 37,
507
+
.slv_rpm_id = -1,
508
+
.num_links = ARRAY_SIZE(mas_tsif_links),
509
+
.links = mas_tsif_links,
510
+
};
511
+
512
+
static struct qcom_icc_node mas_bam_dma = {
513
+
.name = "mas_bam_dma",
514
+
.id = MSM8974_PNOC_MAS_BAM_DMA,
515
+
.buswidth = 8,
516
+
.mas_rpm_id = 38,
517
+
.slv_rpm_id = -1,
518
+
};
519
+
520
+
static const u16 mas_blsp_2_links[] = {
521
+
MSM8974_PNOC_TO_SNOC
522
+
};
523
+
524
+
static struct qcom_icc_node mas_blsp_2 = {
525
+
.name = "mas_blsp_2",
526
+
.id = MSM8974_PNOC_MAS_BLSP_2,
527
+
.buswidth = 8,
528
+
.mas_rpm_id = 39,
529
+
.slv_rpm_id = -1,
530
+
.num_links = ARRAY_SIZE(mas_blsp_2_links),
531
+
.links = mas_blsp_2_links,
532
+
};
533
+
534
+
static const u16 mas_usb_hsic_links[] = {
535
+
MSM8974_PNOC_TO_SNOC
536
+
};
537
+
538
+
static struct qcom_icc_node mas_usb_hsic = {
539
+
.name = "mas_usb_hsic",
540
+
.id = MSM8974_PNOC_MAS_USB_HSIC,
541
+
.buswidth = 8,
542
+
.mas_rpm_id = 40,
543
+
.slv_rpm_id = -1,
544
+
.num_links = ARRAY_SIZE(mas_usb_hsic_links),
545
+
.links = mas_usb_hsic_links,
546
+
};
547
+
548
+
static const u16 mas_blsp_1_links[] = {
549
+
MSM8974_PNOC_TO_SNOC
550
+
};
551
+
552
+
static struct qcom_icc_node mas_blsp_1 = {
553
+
.name = "mas_blsp_1",
554
+
.id = MSM8974_PNOC_MAS_BLSP_1,
555
+
.buswidth = 8,
556
+
.mas_rpm_id = 41,
557
+
.slv_rpm_id = -1,
558
+
.num_links = ARRAY_SIZE(mas_blsp_1_links),
559
+
.links = mas_blsp_1_links,
560
+
};
561
+
562
+
static const u16 mas_usb_hs_links[] = {
563
+
MSM8974_PNOC_TO_SNOC
564
+
};
565
+
566
+
static struct qcom_icc_node mas_usb_hs = {
567
+
.name = "mas_usb_hs",
568
+
.id = MSM8974_PNOC_MAS_USB_HS,
569
+
.buswidth = 8,
570
+
.mas_rpm_id = 42,
571
+
.slv_rpm_id = -1,
572
+
.num_links = ARRAY_SIZE(mas_usb_hs_links),
573
+
.links = mas_usb_hs_links,
574
+
};
575
+
576
+
static const u16 pnoc_to_snoc_links[] = {
577
+
MSM8974_SNOC_TO_PNOC,
578
+
MSM8974_PNOC_SLV_PRNG
579
+
};
580
+
581
+
static struct qcom_icc_node pnoc_to_snoc = {
582
+
.name = "pnoc_to_snoc",
583
+
.id = MSM8974_PNOC_TO_SNOC,
584
+
.buswidth = 8,
585
+
.mas_rpm_id = 44,
586
+
.slv_rpm_id = 45,
587
+
.num_links = ARRAY_SIZE(pnoc_to_snoc_links),
588
+
.links = pnoc_to_snoc_links,
589
+
};
590
+
591
+
static struct qcom_icc_node slv_sdcc_1 = {
592
+
.name = "slv_sdcc_1",
593
+
.id = MSM8974_PNOC_SLV_SDCC_1,
594
+
.buswidth = 8,
595
+
.mas_rpm_id = -1,
596
+
.slv_rpm_id = 31,
597
+
};
598
+
599
+
static struct qcom_icc_node slv_sdcc_3 = {
600
+
.name = "slv_sdcc_3",
601
+
.id = MSM8974_PNOC_SLV_SDCC_3,
602
+
.buswidth = 8,
603
+
.mas_rpm_id = -1,
604
+
.slv_rpm_id = 32,
605
+
};
606
+
607
+
static struct qcom_icc_node slv_sdcc_2 = {
608
+
.name = "slv_sdcc_2",
609
+
.id = MSM8974_PNOC_SLV_SDCC_2,
610
+
.buswidth = 8,
611
+
.mas_rpm_id = -1,
612
+
.slv_rpm_id = 33,
613
+
};
614
+
615
+
static struct qcom_icc_node slv_sdcc_4 = {
616
+
.name = "slv_sdcc_4",
617
+
.id = MSM8974_PNOC_SLV_SDCC_4,
618
+
.buswidth = 8,
619
+
.mas_rpm_id = -1,
620
+
.slv_rpm_id = 34,
621
+
};
622
+
623
+
static struct qcom_icc_node slv_tsif = {
624
+
.name = "slv_tsif",
625
+
.id = MSM8974_PNOC_SLV_TSIF,
626
+
.buswidth = 8,
627
+
.mas_rpm_id = -1,
628
+
.slv_rpm_id = 35,
629
+
};
630
+
631
+
static struct qcom_icc_node slv_bam_dma = {
632
+
.name = "slv_bam_dma",
633
+
.id = MSM8974_PNOC_SLV_BAM_DMA,
634
+
.buswidth = 8,
635
+
.mas_rpm_id = -1,
636
+
.slv_rpm_id = 36,
637
+
};
638
+
639
+
static struct qcom_icc_node slv_blsp_2 = {
640
+
.name = "slv_blsp_2",
641
+
.id = MSM8974_PNOC_SLV_BLSP_2,
642
+
.buswidth = 8,
643
+
.mas_rpm_id = -1,
644
+
.slv_rpm_id = 37,
645
+
};
646
+
647
+
static struct qcom_icc_node slv_usb_hsic = {
648
+
.name = "slv_usb_hsic",
649
+
.id = MSM8974_PNOC_SLV_USB_HSIC,
650
+
.buswidth = 8,
651
+
.mas_rpm_id = -1,
652
+
.slv_rpm_id = 38,
653
+
};
654
+
655
+
static struct qcom_icc_node slv_blsp_1 = {
656
+
.name = "slv_blsp_1",
657
+
.id = MSM8974_PNOC_SLV_BLSP_1,
658
+
.buswidth = 8,
659
+
.mas_rpm_id = -1,
660
+
.slv_rpm_id = 39,
661
+
};
662
+
663
+
static struct qcom_icc_node slv_usb_hs = {
664
+
.name = "slv_usb_hs",
665
+
.id = MSM8974_PNOC_SLV_USB_HS,
666
+
.buswidth = 8,
667
+
.mas_rpm_id = -1,
668
+
.slv_rpm_id = 40,
669
+
};
670
+
671
+
static struct qcom_icc_node slv_pdm = {
672
+
.name = "slv_pdm",
673
+
.id = MSM8974_PNOC_SLV_PDM,
674
+
.buswidth = 8,
675
+
.mas_rpm_id = -1,
676
+
.slv_rpm_id = 41,
677
+
};
678
+
679
+
static struct qcom_icc_node slv_periph_apu_cfg = {
680
+
.name = "slv_periph_apu_cfg",
681
+
.id = MSM8974_PNOC_SLV_PERIPH_APU_CFG,
682
+
.buswidth = 8,
683
+
.mas_rpm_id = -1,
684
+
.slv_rpm_id = 42,
685
+
};
686
+
687
+
static struct qcom_icc_node slv_pnoc_mpu_cfg = {
688
+
.name = "slv_pnoc_mpu_cfg",
689
+
.id = MSM8974_PNOC_SLV_PNOC_MPU_CFG,
690
+
.buswidth = 8,
691
+
.mas_rpm_id = -1,
692
+
.slv_rpm_id = 43,
693
+
};
694
+
695
+
static const u16 slv_prng_links[] = {
696
+
MSM8974_PNOC_TO_SNOC
697
+
};
698
+
699
+
static struct qcom_icc_node slv_prng = {
700
+
.name = "slv_prng",
701
+
.id = MSM8974_PNOC_SLV_PRNG,
702
+
.buswidth = 8,
703
+
.mas_rpm_id = -1,
704
+
.slv_rpm_id = 44,
705
+
.num_links = ARRAY_SIZE(slv_prng_links),
706
+
.links = slv_prng_links,
707
+
};
708
+
709
+
static struct qcom_icc_node slv_service_pnoc = {
710
+
.name = "slv_service_pnoc",
711
+
.id = MSM8974_PNOC_SLV_SERVICE_PNOC,
712
+
.buswidth = 8,
713
+
.mas_rpm_id = -1,
714
+
.slv_rpm_id = 46,
715
+
};
716
+
717
+
static struct qcom_icc_node * const msm8974_pnoc_nodes[] = {
1019
718
[PNOC_MAS_PNOC_CFG] = &mas_pnoc_cfg,
1020
719
[PNOC_MAS_SDCC_1] = &mas_sdcc_1,
1021
720
[PNOC_MAS_SDCC_3] = &mas_sdcc_3,
···
1303
486
[PNOC_SLV_SERVICE_PNOC] = &slv_service_pnoc,
1304
487
};
1305
488
1306
-
static const struct msm8974_icc_desc msm8974_pnoc = {
489
+
static const struct qcom_icc_desc msm8974_pnoc = {
1307
490
.nodes = msm8974_pnoc_nodes,
1308
491
.num_nodes = ARRAY_SIZE(msm8974_pnoc_nodes),
492
+
.bus_clk_desc = &bus_0_clk,
493
+
.get_bw = msm8974_get_bw,
494
+
.keep_alive = true,
495
+
.ignore_enxio = true,
1309
496
};
1310
497
1311
-
DEFINE_QNODE(mas_lpass_ahb, MSM8974_SNOC_MAS_LPASS_AHB, 8, 18, -1);
1312
-
DEFINE_QNODE(mas_qdss_bam, MSM8974_SNOC_MAS_QDSS_BAM, 8, 19, -1);
1313
-
DEFINE_QNODE(mas_snoc_cfg, MSM8974_SNOC_MAS_SNOC_CFG, 8, 20, -1);
1314
-
DEFINE_QNODE(snoc_to_bimc, MSM8974_SNOC_TO_BIMC, 8, 21, 24, MSM8974_BIMC_TO_SNOC);
1315
-
DEFINE_QNODE(snoc_to_cnoc, MSM8974_SNOC_TO_CNOC, 8, 22, 25);
1316
-
DEFINE_QNODE(snoc_to_pnoc, MSM8974_SNOC_TO_PNOC, 8, 29, 28, MSM8974_PNOC_TO_SNOC);
1317
-
DEFINE_QNODE(snoc_to_ocmem_vnoc, MSM8974_SNOC_TO_OCMEM_VNOC, 8, 53, 77, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC);
1318
-
DEFINE_QNODE(mas_crypto_core0, MSM8974_SNOC_MAS_CRYPTO_CORE0, 8, 23, -1, MSM8974_SNOC_TO_BIMC);
1319
-
DEFINE_QNODE(mas_crypto_core1, MSM8974_SNOC_MAS_CRYPTO_CORE1, 8, 24, -1);
1320
-
DEFINE_QNODE(mas_lpass_proc, MSM8974_SNOC_MAS_LPASS_PROC, 8, 25, -1, MSM8974_SNOC_TO_OCMEM_VNOC);
1321
-
DEFINE_QNODE(mas_mss, MSM8974_SNOC_MAS_MSS, 8, 26, -1);
1322
-
DEFINE_QNODE(mas_mss_nav, MSM8974_SNOC_MAS_MSS_NAV, 8, 27, -1);
1323
-
DEFINE_QNODE(mas_ocmem_dma, MSM8974_SNOC_MAS_OCMEM_DMA, 8, 28, -1);
1324
-
DEFINE_QNODE(mas_wcss, MSM8974_SNOC_MAS_WCSS, 8, 30, -1);
1325
-
DEFINE_QNODE(mas_qdss_etr, MSM8974_SNOC_MAS_QDSS_ETR, 8, 31, -1);
1326
-
DEFINE_QNODE(mas_usb3, MSM8974_SNOC_MAS_USB3, 8, 32, -1, MSM8974_SNOC_TO_BIMC);
1327
-
DEFINE_QNODE(slv_ampss, MSM8974_SNOC_SLV_AMPSS, 8, -1, 20);
1328
-
DEFINE_QNODE(slv_lpass, MSM8974_SNOC_SLV_LPASS, 8, -1, 21);
1329
-
DEFINE_QNODE(slv_usb3, MSM8974_SNOC_SLV_USB3, 8, -1, 22);
1330
-
DEFINE_QNODE(slv_wcss, MSM8974_SNOC_SLV_WCSS, 8, -1, 23);
1331
-
DEFINE_QNODE(slv_ocimem, MSM8974_SNOC_SLV_OCIMEM, 8, -1, 26);
1332
-
DEFINE_QNODE(slv_snoc_ocmem, MSM8974_SNOC_SLV_SNOC_OCMEM, 8, -1, 27);
1333
-
DEFINE_QNODE(slv_service_snoc, MSM8974_SNOC_SLV_SERVICE_SNOC, 8, -1, 29);
1334
-
DEFINE_QNODE(slv_qdss_stm, MSM8974_SNOC_SLV_QDSS_STM, 8, -1, 30);
498
+
static struct qcom_icc_node mas_lpass_ahb = {
499
+
.name = "mas_lpass_ahb",
500
+
.id = MSM8974_SNOC_MAS_LPASS_AHB,
501
+
.buswidth = 8,
502
+
.mas_rpm_id = 18,
503
+
.slv_rpm_id = -1,
504
+
};
1335
505
1336
-
static struct msm8974_icc_node * const msm8974_snoc_nodes[] = {
506
+
static struct qcom_icc_node mas_qdss_bam = {
507
+
.name = "mas_qdss_bam",
508
+
.id = MSM8974_SNOC_MAS_QDSS_BAM,
509
+
.buswidth = 8,
510
+
.mas_rpm_id = 19,
511
+
.slv_rpm_id = -1,
512
+
};
513
+
514
+
static struct qcom_icc_node mas_snoc_cfg = {
515
+
.name = "mas_snoc_cfg",
516
+
.id = MSM8974_SNOC_MAS_SNOC_CFG,
517
+
.buswidth = 8,
518
+
.mas_rpm_id = 20,
519
+
.slv_rpm_id = -1,
520
+
};
521
+
522
+
static const u16 snoc_to_bimc_links[] = {
523
+
MSM8974_BIMC_TO_SNOC
524
+
};
525
+
526
+
static struct qcom_icc_node snoc_to_bimc = {
527
+
.name = "snoc_to_bimc",
528
+
.id = MSM8974_SNOC_TO_BIMC,
529
+
.buswidth = 8,
530
+
.mas_rpm_id = 21,
531
+
.slv_rpm_id = 24,
532
+
.num_links = ARRAY_SIZE(snoc_to_bimc_links),
533
+
.links = snoc_to_bimc_links,
534
+
};
535
+
536
+
static struct qcom_icc_node snoc_to_cnoc = {
537
+
.name = "snoc_to_cnoc",
538
+
.id = MSM8974_SNOC_TO_CNOC,
539
+
.buswidth = 8,
540
+
.mas_rpm_id = 22,
541
+
.slv_rpm_id = 25,
542
+
};
543
+
544
+
static const u16 snoc_to_pnoc_links[] = {
545
+
MSM8974_PNOC_TO_SNOC
546
+
};
547
+
548
+
static struct qcom_icc_node snoc_to_pnoc = {
549
+
.name = "snoc_to_pnoc",
550
+
.id = MSM8974_SNOC_TO_PNOC,
551
+
.buswidth = 8,
552
+
.mas_rpm_id = 29,
553
+
.slv_rpm_id = 28,
554
+
.num_links = ARRAY_SIZE(snoc_to_pnoc_links),
555
+
.links = snoc_to_pnoc_links,
556
+
};
557
+
558
+
static const u16 snoc_to_ocmem_vnoc_links[] = {
559
+
MSM8974_OCMEM_VNOC_TO_OCMEM_NOC
560
+
};
561
+
562
+
static struct qcom_icc_node snoc_to_ocmem_vnoc = {
563
+
.name = "snoc_to_ocmem_vnoc",
564
+
.id = MSM8974_SNOC_TO_OCMEM_VNOC,
565
+
.buswidth = 8,
566
+
.mas_rpm_id = 53,
567
+
.slv_rpm_id = 77,
568
+
.num_links = ARRAY_SIZE(snoc_to_ocmem_vnoc_links),
569
+
.links = snoc_to_ocmem_vnoc_links,
570
+
};
571
+
572
+
static const u16 mas_crypto_core0_links[] = {
573
+
MSM8974_SNOC_TO_BIMC
574
+
};
575
+
576
+
static struct qcom_icc_node mas_crypto_core0 = {
577
+
.name = "mas_crypto_core0",
578
+
.id = MSM8974_SNOC_MAS_CRYPTO_CORE0,
579
+
.buswidth = 8,
580
+
.mas_rpm_id = 23,
581
+
.slv_rpm_id = -1,
582
+
.num_links = ARRAY_SIZE(mas_crypto_core0_links),
583
+
.links = mas_crypto_core0_links,
584
+
};
585
+
586
+
static struct qcom_icc_node mas_crypto_core1 = {
587
+
.name = "mas_crypto_core1",
588
+
.id = MSM8974_SNOC_MAS_CRYPTO_CORE1,
589
+
.buswidth = 8,
590
+
.mas_rpm_id = 24,
591
+
.slv_rpm_id = -1,
592
+
};
593
+
594
+
static const u16 mas_lpass_proc_links[] = {
595
+
MSM8974_SNOC_TO_OCMEM_VNOC
596
+
};
597
+
598
+
static struct qcom_icc_node mas_lpass_proc = {
599
+
.name = "mas_lpass_proc",
600
+
.id = MSM8974_SNOC_MAS_LPASS_PROC,
601
+
.buswidth = 8,
602
+
.mas_rpm_id = 25,
603
+
.slv_rpm_id = -1,
604
+
.num_links = ARRAY_SIZE(mas_lpass_proc_links),
605
+
.links = mas_lpass_proc_links,
606
+
};
607
+
608
+
static struct qcom_icc_node mas_mss = {
609
+
.name = "mas_mss",
610
+
.id = MSM8974_SNOC_MAS_MSS,
611
+
.buswidth = 8,
612
+
.mas_rpm_id = 26,
613
+
.slv_rpm_id = -1,
614
+
};
615
+
616
+
static struct qcom_icc_node mas_mss_nav = {
617
+
.name = "mas_mss_nav",
618
+
.id = MSM8974_SNOC_MAS_MSS_NAV,
619
+
.buswidth = 8,
620
+
.mas_rpm_id = 27,
621
+
.slv_rpm_id = -1,
622
+
};
623
+
624
+
static struct qcom_icc_node mas_ocmem_dma = {
625
+
.name = "mas_ocmem_dma",
626
+
.id = MSM8974_SNOC_MAS_OCMEM_DMA,
627
+
.buswidth = 8,
628
+
.mas_rpm_id = 28,
629
+
.slv_rpm_id = -1,
630
+
};
631
+
632
+
static struct qcom_icc_node mas_wcss = {
633
+
.name = "mas_wcss",
634
+
.id = MSM8974_SNOC_MAS_WCSS,
635
+
.buswidth = 8,
636
+
.mas_rpm_id = 30,
637
+
.slv_rpm_id = -1,
638
+
};
639
+
640
+
static struct qcom_icc_node mas_qdss_etr = {
641
+
.name = "mas_qdss_etr",
642
+
.id = MSM8974_SNOC_MAS_QDSS_ETR,
643
+
.buswidth = 8,
644
+
.mas_rpm_id = 31,
645
+
.slv_rpm_id = -1,
646
+
};
647
+
648
+
static const u16 mas_usb3_links[] = {
649
+
MSM8974_SNOC_TO_BIMC
650
+
};
651
+
652
+
static struct qcom_icc_node mas_usb3 = {
653
+
.name = "mas_usb3",
654
+
.id = MSM8974_SNOC_MAS_USB3,
655
+
.buswidth = 8,
656
+
.mas_rpm_id = 32,
657
+
.slv_rpm_id = -1,
658
+
.num_links = ARRAY_SIZE(mas_usb3_links),
659
+
.links = mas_usb3_links,
660
+
};
661
+
662
+
static struct qcom_icc_node slv_ampss = {
663
+
.name = "slv_ampss",
664
+
.id = MSM8974_SNOC_SLV_AMPSS,
665
+
.buswidth = 8,
666
+
.mas_rpm_id = -1,
667
+
.slv_rpm_id = 20,
668
+
};
669
+
670
+
static struct qcom_icc_node slv_lpass = {
671
+
.name = "slv_lpass",
672
+
.id = MSM8974_SNOC_SLV_LPASS,
673
+
.buswidth = 8,
674
+
.mas_rpm_id = -1,
675
+
.slv_rpm_id = 21,
676
+
};
677
+
678
+
static struct qcom_icc_node slv_usb3 = {
679
+
.name = "slv_usb3",
680
+
.id = MSM8974_SNOC_SLV_USB3,
681
+
.buswidth = 8,
682
+
.mas_rpm_id = -1,
683
+
.slv_rpm_id = 22,
684
+
};
685
+
686
+
static struct qcom_icc_node slv_wcss = {
687
+
.name = "slv_wcss",
688
+
.id = MSM8974_SNOC_SLV_WCSS,
689
+
.buswidth = 8,
690
+
.mas_rpm_id = -1,
691
+
.slv_rpm_id = 23,
692
+
};
693
+
694
+
static struct qcom_icc_node slv_ocimem = {
695
+
.name = "slv_ocimem",
696
+
.id = MSM8974_SNOC_SLV_OCIMEM,
697
+
.buswidth = 8,
698
+
.mas_rpm_id = -1,
699
+
.slv_rpm_id = 26,
700
+
};
701
+
702
+
static struct qcom_icc_node slv_snoc_ocmem = {
703
+
.name = "slv_snoc_ocmem",
704
+
.id = MSM8974_SNOC_SLV_SNOC_OCMEM,
705
+
.buswidth = 8,
706
+
.mas_rpm_id = -1,
707
+
.slv_rpm_id = 27,
708
+
};
709
+
710
+
static struct qcom_icc_node slv_service_snoc = {
711
+
.name = "slv_service_snoc",
712
+
.id = MSM8974_SNOC_SLV_SERVICE_SNOC,
713
+
.buswidth = 8,
714
+
.mas_rpm_id = -1,
715
+
.slv_rpm_id = 29,
716
+
};
717
+
718
+
static struct qcom_icc_node slv_qdss_stm = {
719
+
.name = "slv_qdss_stm",
720
+
.id = MSM8974_SNOC_SLV_QDSS_STM,
721
+
.buswidth = 8,
722
+
.mas_rpm_id = -1,
723
+
.slv_rpm_id = 30,
724
+
};
725
+
726
+
static struct qcom_icc_node * const msm8974_snoc_nodes[] = {
1337
727
[SNOC_MAS_LPASS_AHB] = &mas_lpass_ahb,
1338
728
[SNOC_MAS_QDSS_BAM] = &mas_qdss_bam,
1339
729
[SNOC_MAS_SNOC_CFG] = &mas_snoc_cfg,
···
1567
543
[SNOC_SLV_QDSS_STM] = &slv_qdss_stm,
1568
544
};
1569
545
1570
-
static const struct msm8974_icc_desc msm8974_snoc = {
546
+
static const struct qcom_icc_desc msm8974_snoc = {
1571
547
.nodes = msm8974_snoc_nodes,
1572
548
.num_nodes = ARRAY_SIZE(msm8974_snoc_nodes),
549
+
.bus_clk_desc = &bus_1_clk,
550
+
.get_bw = msm8974_get_bw,
551
+
.ignore_enxio = true,
1573
552
};
1574
-
1575
-
static void msm8974_icc_rpm_smd_send(struct device *dev, int rsc_type,
1576
-
char *name, int id, u64 val)
1577
-
{
1578
-
int ret;
1579
-
1580
-
if (id == -1)
1581
-
return;
1582
-
1583
-
/*
1584
-
* Setting the bandwidth requests for some nodes fails and this same
1585
-
* behavior occurs on the downstream MSM 3.4 kernel sources based on
1586
-
* errors like this in that kernel:
1587
-
*
1588
-
* msm_rpm_get_error_from_ack(): RPM NACK Unsupported resource
1589
-
* AXI: msm_bus_rpm_req(): RPM: Ack failed
1590
-
* AXI: msm_bus_rpm_commit_arb(): RPM: Req fail: mas:32, bw:240000000
1591
-
*
1592
-
* Since there's no publicly available documentation for this hardware,
1593
-
* and the bandwidth for some nodes in the path can be set properly,
1594
-
* let's not return an error.
1595
-
*/
1596
-
ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, rsc_type, id,
1597
-
val);
1598
-
if (ret)
1599
-
dev_dbg(dev, "Cannot set bandwidth for node %s (%d): %d\n",
1600
-
name, id, ret);
1601
-
}
1602
-
1603
-
static int msm8974_icc_set(struct icc_node *src, struct icc_node *dst)
1604
-
{
1605
-
struct msm8974_icc_node *src_qn, *dst_qn;
1606
-
struct msm8974_icc_provider *qp;
1607
-
u64 sum_bw, max_peak_bw, rate;
1608
-
u32 agg_avg = 0, agg_peak = 0;
1609
-
struct icc_provider *provider;
1610
-
struct icc_node *n;
1611
-
int ret, i;
1612
-
1613
-
src_qn = src->data;
1614
-
dst_qn = dst->data;
1615
-
provider = src->provider;
1616
-
qp = to_msm8974_icc_provider(provider);
1617
-
1618
-
list_for_each_entry(n, &provider->nodes, node_list)
1619
-
provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
1620
-
&agg_avg, &agg_peak);
1621
-
1622
-
sum_bw = icc_units_to_bps(agg_avg);
1623
-
max_peak_bw = icc_units_to_bps(agg_peak);
1624
-
1625
-
/* Set bandwidth on source node */
1626
-
msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_MASTER_REQ,
1627
-
src_qn->name, src_qn->mas_rpm_id, sum_bw);
1628
-
1629
-
msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_SLAVE_REQ,
1630
-
src_qn->name, src_qn->slv_rpm_id, sum_bw);
1631
-
1632
-
/* Set bandwidth on destination node */
1633
-
msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_MASTER_REQ,
1634
-
dst_qn->name, dst_qn->mas_rpm_id, sum_bw);
1635
-
1636
-
msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_SLAVE_REQ,
1637
-
dst_qn->name, dst_qn->slv_rpm_id, sum_bw);
1638
-
1639
-
rate = max(sum_bw, max_peak_bw);
1640
-
1641
-
do_div(rate, src_qn->buswidth);
1642
-
1643
-
rate = min_t(u32, rate, INT_MAX);
1644
-
1645
-
if (src_qn->rate == rate)
1646
-
return 0;
1647
-
1648
-
for (i = 0; i < qp->num_clks; i++) {
1649
-
ret = clk_set_rate(qp->bus_clks[i].clk, rate);
1650
-
if (ret) {
1651
-
dev_err(provider->dev, "%s clk_set_rate error: %d\n",
1652
-
qp->bus_clks[i].id, ret);
1653
-
ret = 0;
1654
-
}
1655
-
}
1656
-
1657
-
src_qn->rate = rate;
1658
-
1659
-
return 0;
1660
-
}
1661
-
1662
-
static int msm8974_get_bw(struct icc_node *node, u32 *avg, u32 *peak)
1663
-
{
1664
-
*avg = 0;
1665
-
*peak = 0;
1666
-
1667
-
return 0;
1668
-
}
1669
-
1670
-
static int msm8974_icc_probe(struct platform_device *pdev)
1671
-
{
1672
-
const struct msm8974_icc_desc *desc;
1673
-
struct msm8974_icc_node * const *qnodes;
1674
-
struct msm8974_icc_provider *qp;
1675
-
struct device *dev = &pdev->dev;
1676
-
struct icc_onecell_data *data;
1677
-
struct icc_provider *provider;
1678
-
struct icc_node *node;
1679
-
size_t num_nodes, i;
1680
-
int ret;
1681
-
1682
-
/* wait for the RPM proxy */
1683
-
if (!qcom_icc_rpm_smd_available())
1684
-
return -EPROBE_DEFER;
1685
-
1686
-
desc = of_device_get_match_data(dev);
1687
-
if (!desc)
1688
-
return -EINVAL;
1689
-
1690
-
qnodes = desc->nodes;
1691
-
num_nodes = desc->num_nodes;
1692
-
1693
-
qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL);
1694
-
if (!qp)
1695
-
return -ENOMEM;
1696
-
1697
-
data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes),
1698
-
GFP_KERNEL);
1699
-
if (!data)
1700
-
return -ENOMEM;
1701
-
data->num_nodes = num_nodes;
1702
-
1703
-
qp->bus_clks = devm_kmemdup(dev, msm8974_icc_bus_clocks,
1704
-
sizeof(msm8974_icc_bus_clocks), GFP_KERNEL);
1705
-
if (!qp->bus_clks)
1706
-
return -ENOMEM;
1707
-
1708
-
qp->num_clks = ARRAY_SIZE(msm8974_icc_bus_clocks);
1709
-
ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks);
1710
-
if (ret)
1711
-
return ret;
1712
-
1713
-
ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks);
1714
-
if (ret)
1715
-
return ret;
1716
-
1717
-
provider = &qp->provider;
1718
-
provider->dev = dev;
1719
-
provider->set = msm8974_icc_set;
1720
-
provider->aggregate = icc_std_aggregate;
1721
-
provider->xlate = of_icc_xlate_onecell;
1722
-
provider->data = data;
1723
-
provider->get_bw = msm8974_get_bw;
1724
-
1725
-
icc_provider_init(provider);
1726
-
1727
-
for (i = 0; i < num_nodes; i++) {
1728
-
size_t j;
1729
-
1730
-
node = icc_node_create(qnodes[i]->id);
1731
-
if (IS_ERR(node)) {
1732
-
ret = PTR_ERR(node);
1733
-
goto err_remove_nodes;
1734
-
}
1735
-
1736
-
node->name = qnodes[i]->name;
1737
-
node->data = qnodes[i];
1738
-
icc_node_add(node, provider);
1739
-
1740
-
dev_dbg(dev, "registered node %s\n", node->name);
1741
-
1742
-
/* populate links */
1743
-
for (j = 0; j < qnodes[i]->num_links; j++)
1744
-
icc_link_create(node, qnodes[i]->links[j]);
1745
-
1746
-
data->nodes[i] = node;
1747
-
}
1748
-
1749
-
ret = icc_provider_register(provider);
1750
-
if (ret)
1751
-
goto err_remove_nodes;
1752
-
1753
-
platform_set_drvdata(pdev, qp);
1754
-
1755
-
return 0;
1756
-
1757
-
err_remove_nodes:
1758
-
icc_nodes_remove(provider);
1759
-
clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
1760
-
1761
-
return ret;
1762
-
}
1763
-
1764
-
static void msm8974_icc_remove(struct platform_device *pdev)
1765
-
{
1766
-
struct msm8974_icc_provider *qp = platform_get_drvdata(pdev);
1767
-
1768
-
icc_provider_deregister(&qp->provider);
1769
-
icc_nodes_remove(&qp->provider);
1770
-
clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
1771
-
}
1772
553
1773
554
static const struct of_device_id msm8974_noc_of_match[] = {
1774
555
{ .compatible = "qcom,msm8974-bimc", .data = &msm8974_bimc},
···
1587
758
MODULE_DEVICE_TABLE(of, msm8974_noc_of_match);
1588
759
1589
760
static struct platform_driver msm8974_noc_driver = {
1590
-
.probe = msm8974_icc_probe,
1591
-
.remove = msm8974_icc_remove,
761
+
.probe = qnoc_probe,
762
+
.remove = qnoc_remove,
1592
763
.driver = {
1593
764
.name = "qnoc-msm8974",
1594
765
.of_match_table = msm8974_noc_of_match,
+247
drivers/interconnect/qcom/qcs615.c
+247
drivers/interconnect/qcom/qcs615.c
···
142
142
.name = "qhm_qdss_bam",
143
143
.channels = 1,
144
144
.buswidth = 4,
145
+
.qosbox = &(const struct qcom_icc_qosbox) {
146
+
.num_ports = 1,
147
+
.port_offsets = { 0xc000 },
148
+
.prio = 2,
149
+
.urg_fwd = 0,
150
+
},
145
151
.num_links = 1,
146
152
.link_nodes = { &qns_a1noc_snoc },
147
153
};
···
156
150
.name = "qhm_qspi",
157
151
.channels = 1,
158
152
.buswidth = 4,
153
+
.qosbox = &(const struct qcom_icc_qosbox) {
154
+
.num_ports = 1,
155
+
.port_offsets = { 0x17000 },
156
+
.prio = 2,
157
+
.urg_fwd = 0,
158
+
},
159
159
.num_links = 1,
160
160
.link_nodes = { &qns_a1noc_snoc },
161
161
};
···
170
158
.name = "qhm_qup0",
171
159
.channels = 1,
172
160
.buswidth = 4,
161
+
.qosbox = &(const struct qcom_icc_qosbox) {
162
+
.num_ports = 1,
163
+
.port_offsets = { 0x10000 },
164
+
.prio = 2,
165
+
.urg_fwd = 0,
166
+
},
173
167
.num_links = 1,
174
168
.link_nodes = { &qns_a1noc_snoc },
175
169
};
···
184
166
.name = "qhm_qup1",
185
167
.channels = 1,
186
168
.buswidth = 4,
169
+
.qosbox = &(const struct qcom_icc_qosbox) {
170
+
.num_ports = 1,
171
+
.port_offsets = { 0x12000 },
172
+
.prio = 2,
173
+
.urg_fwd = 0,
174
+
},
187
175
.num_links = 1,
188
176
.link_nodes = { &qns_a1noc_snoc },
189
177
};
···
198
174
.name = "qnm_cnoc",
199
175
.channels = 1,
200
176
.buswidth = 8,
177
+
.qosbox = &(const struct qcom_icc_qosbox) {
178
+
.num_ports = 1,
179
+
.port_offsets = { 0x4000 },
180
+
.prio = 2,
181
+
.urg_fwd = 1,
182
+
},
201
183
.num_links = 1,
202
184
.link_nodes = { &qns_a1noc_snoc },
203
185
};
···
212
182
.name = "qxm_crypto",
213
183
.channels = 1,
214
184
.buswidth = 8,
185
+
.qosbox = &(const struct qcom_icc_qosbox) {
186
+
.num_ports = 1,
187
+
.port_offsets = { 0x5000 },
188
+
.prio = 2,
189
+
.urg_fwd = 1,
190
+
},
215
191
.num_links = 1,
216
192
.link_nodes = { &qns_a1noc_snoc },
217
193
};
···
226
190
.name = "qxm_ipa",
227
191
.channels = 1,
228
192
.buswidth = 8,
193
+
.qosbox = &(const struct qcom_icc_qosbox) {
194
+
.num_ports = 1,
195
+
.port_offsets = { 0x6000 },
196
+
.prio = 2,
197
+
.urg_fwd = 1,
198
+
},
229
199
.num_links = 1,
230
200
.link_nodes = { &qns_lpass_snoc },
231
201
};
···
240
198
.name = "xm_emac_avb",
241
199
.channels = 1,
242
200
.buswidth = 8,
201
+
.qosbox = &(const struct qcom_icc_qosbox) {
202
+
.num_ports = 1,
203
+
.port_offsets = { 0xa000 },
204
+
.prio = 2,
205
+
.urg_fwd = 0,
206
+
},
243
207
.num_links = 1,
244
208
.link_nodes = { &qns_a1noc_snoc },
245
209
};
···
254
206
.name = "xm_pcie",
255
207
.channels = 1,
256
208
.buswidth = 8,
209
+
.qosbox = &(const struct qcom_icc_qosbox) {
210
+
.num_ports = 1,
211
+
.port_offsets = { 0x13000 },
212
+
.prio = 0,
213
+
.urg_fwd = 0,
214
+
},
257
215
.num_links = 1,
258
216
.link_nodes = { &qns_pcie_snoc },
259
217
};
···
268
214
.name = "xm_qdss_etr",
269
215
.channels = 1,
270
216
.buswidth = 8,
217
+
.qosbox = &(const struct qcom_icc_qosbox) {
218
+
.num_ports = 1,
219
+
.port_offsets = { 0xb000 },
220
+
.prio = 2,
221
+
.urg_fwd = 0,
222
+
},
271
223
.num_links = 1,
272
224
.link_nodes = { &qns_a1noc_snoc },
273
225
};
···
282
222
.name = "xm_sdc1",
283
223
.channels = 1,
284
224
.buswidth = 8,
225
+
.qosbox = &(const struct qcom_icc_qosbox) {
226
+
.num_ports = 1,
227
+
.port_offsets = { 0xe000 },
228
+
.prio = 2,
229
+
.urg_fwd = 0,
230
+
},
285
231
.num_links = 1,
286
232
.link_nodes = { &qns_a1noc_snoc },
287
233
};
···
296
230
.name = "xm_sdc2",
297
231
.channels = 1,
298
232
.buswidth = 8,
233
+
.qosbox = &(const struct qcom_icc_qosbox) {
234
+
.num_ports = 1,
235
+
.port_offsets = { 0x16000 },
236
+
.prio = 2,
237
+
.urg_fwd = 0,
238
+
},
299
239
.num_links = 1,
300
240
.link_nodes = { &qns_a1noc_snoc },
301
241
};
···
310
238
.name = "xm_ufs_mem",
311
239
.channels = 1,
312
240
.buswidth = 8,
241
+
.qosbox = &(const struct qcom_icc_qosbox) {
242
+
.num_ports = 1,
243
+
.port_offsets = { 0x11000 },
244
+
.prio = 2,
245
+
.urg_fwd = 0,
246
+
},
313
247
.num_links = 1,
314
248
.link_nodes = { &qns_a1noc_snoc },
315
249
};
···
324
246
.name = "xm_usb2",
325
247
.channels = 1,
326
248
.buswidth = 8,
249
+
.qosbox = &(const struct qcom_icc_qosbox) {
250
+
.num_ports = 1,
251
+
.port_offsets = { 0x15000 },
252
+
.prio = 2,
253
+
.urg_fwd = 0,
254
+
},
327
255
.num_links = 1,
328
256
.link_nodes = { &qns_a1noc_snoc },
329
257
};
···
338
254
.name = "xm_usb3_0",
339
255
.channels = 1,
340
256
.buswidth = 8,
257
+
.qosbox = &(const struct qcom_icc_qosbox) {
258
+
.num_ports = 1,
259
+
.port_offsets = { 0xd000 },
260
+
.prio = 2,
261
+
.urg_fwd = 0,
262
+
},
341
263
.num_links = 1,
342
264
.link_nodes = { &qns_a1noc_snoc },
343
265
};
···
446
356
.name = "acm_apps",
447
357
.channels = 1,
448
358
.buswidth = 16,
359
+
.qosbox = &(const struct qcom_icc_qosbox) {
360
+
.num_ports = 2,
361
+
.port_offsets = { 0x2e000, 0x2e100 },
362
+
.prio = 0,
363
+
.urg_fwd = 1,
364
+
},
449
365
.num_links = 3,
450
366
.link_nodes = { &qns_gem_noc_snoc, &qns_llcc,
451
367
&qns_sys_pcie },
···
461
365
.name = "acm_gpu_tcu",
462
366
.channels = 1,
463
367
.buswidth = 8,
368
+
.qosbox = &(const struct qcom_icc_qosbox) {
369
+
.num_ports = 1,
370
+
.port_offsets = { 0x36000 },
371
+
.prio = 6,
372
+
.urg_fwd = 0,
373
+
},
464
374
.num_links = 2,
465
375
.link_nodes = { &qns_gem_noc_snoc, &qns_llcc },
466
376
};
···
475
373
.name = "acm_sys_tcu",
476
374
.channels = 1,
477
375
.buswidth = 8,
376
+
.qosbox = &(const struct qcom_icc_qosbox) {
377
+
.num_ports = 1,
378
+
.port_offsets = { 0x37000 },
379
+
.prio = 6,
380
+
.urg_fwd = 0,
381
+
},
478
382
.num_links = 2,
479
383
.link_nodes = { &qns_gem_noc_snoc, &qns_llcc },
480
384
};
···
497
389
.name = "qnm_gpu",
498
390
.channels = 2,
499
391
.buswidth = 32,
392
+
.qosbox = &(const struct qcom_icc_qosbox) {
393
+
.num_ports = 2,
394
+
.port_offsets = { 0x34000, 0x34080 },
395
+
.prio = 0,
396
+
.urg_fwd = 1,
397
+
},
500
398
.num_links = 2,
501
399
.link_nodes = { &qns_gem_noc_snoc, &qns_llcc },
502
400
};
···
511
397
.name = "qnm_mnoc_hf",
512
398
.channels = 1,
513
399
.buswidth = 32,
400
+
.qosbox = &(const struct qcom_icc_qosbox) {
401
+
.num_ports = 1,
402
+
.port_offsets = { 0x2f000 },
403
+
.prio = 0,
404
+
.urg_fwd = 1,
405
+
},
514
406
.num_links = 1,
515
407
.link_nodes = { &qns_llcc },
516
408
};
···
525
405
.name = "qnm_mnoc_sf",
526
406
.channels = 1,
527
407
.buswidth = 32,
408
+
.qosbox = &(const struct qcom_icc_qosbox) {
409
+
.num_ports = 1,
410
+
.port_offsets = { 0x35000 },
411
+
.prio = 0,
412
+
.urg_fwd = 1,
413
+
},
528
414
.num_links = 2,
529
415
.link_nodes = { &qns_gem_noc_snoc, &qns_llcc },
530
416
};
···
539
413
.name = "qnm_snoc_gc",
540
414
.channels = 1,
541
415
.buswidth = 8,
416
+
.qosbox = &(const struct qcom_icc_qosbox) {
417
+
.num_ports = 1,
418
+
.port_offsets = { 0x31000 },
419
+
.prio = 0,
420
+
.urg_fwd = 1,
421
+
},
542
422
.num_links = 1,
543
423
.link_nodes = { &qns_llcc },
544
424
};
···
553
421
.name = "qnm_snoc_sf",
554
422
.channels = 1,
555
423
.buswidth = 16,
424
+
.qosbox = &(const struct qcom_icc_qosbox) {
425
+
.num_ports = 1,
426
+
.port_offsets = { 0x30000 },
427
+
.prio = 0,
428
+
.urg_fwd = 1,
429
+
},
556
430
.num_links = 1,
557
431
.link_nodes = { &qns_llcc },
558
432
};
···
583
445
.name = "qxm_camnoc_hf0",
584
446
.channels = 1,
585
447
.buswidth = 32,
448
+
.qosbox = &(const struct qcom_icc_qosbox) {
449
+
.num_ports = 1,
450
+
.port_offsets = { 0xa000 },
451
+
.prio = 0,
452
+
.urg_fwd = 1,
453
+
},
586
454
.num_links = 1,
587
455
.link_nodes = { &qns_mem_noc_hf },
588
456
};
···
597
453
.name = "qxm_camnoc_hf1",
598
454
.channels = 1,
599
455
.buswidth = 32,
456
+
.qosbox = &(const struct qcom_icc_qosbox) {
457
+
.num_ports = 1,
458
+
.port_offsets = { 0xb000 },
459
+
.prio = 0,
460
+
.urg_fwd = 1,
461
+
},
600
462
.num_links = 1,
601
463
.link_nodes = { &qns_mem_noc_hf },
602
464
};
···
611
461
.name = "qxm_camnoc_sf",
612
462
.channels = 1,
613
463
.buswidth = 32,
464
+
.qosbox = &(const struct qcom_icc_qosbox) {
465
+
.num_ports = 1,
466
+
.port_offsets = { 0x9000 },
467
+
.prio = 0,
468
+
.urg_fwd = 1,
469
+
},
614
470
.num_links = 1,
615
471
.link_nodes = { &qns2_mem_noc },
616
472
};
···
625
469
.name = "qxm_mdp0",
626
470
.channels = 1,
627
471
.buswidth = 32,
472
+
.qosbox = &(const struct qcom_icc_qosbox) {
473
+
.num_ports = 1,
474
+
.port_offsets = { 0xc000 },
475
+
.prio = 0,
476
+
.urg_fwd = 1,
477
+
},
628
478
.num_links = 1,
629
479
.link_nodes = { &qns_mem_noc_hf },
630
480
};
···
639
477
.name = "qxm_rot",
640
478
.channels = 1,
641
479
.buswidth = 32,
480
+
.qosbox = &(const struct qcom_icc_qosbox) {
481
+
.num_ports = 1,
482
+
.port_offsets = { 0xe000 },
483
+
.prio = 0,
484
+
.urg_fwd = 1,
485
+
},
642
486
.num_links = 1,
643
487
.link_nodes = { &qns2_mem_noc },
644
488
};
···
653
485
.name = "qxm_venus0",
654
486
.channels = 1,
655
487
.buswidth = 32,
488
+
.qosbox = &(const struct qcom_icc_qosbox) {
489
+
.num_ports = 1,
490
+
.port_offsets = { 0xf000 },
491
+
.prio = 0,
492
+
.urg_fwd = 1,
493
+
},
656
494
.num_links = 1,
657
495
.link_nodes = { &qns2_mem_noc },
658
496
};
···
667
493
.name = "qxm_venus_arm9",
668
494
.channels = 1,
669
495
.buswidth = 8,
496
+
.qosbox = &(const struct qcom_icc_qosbox) {
497
+
.num_ports = 1,
498
+
.port_offsets = { 0x11000 },
499
+
.prio = 0,
500
+
.urg_fwd = 1,
501
+
},
670
502
.num_links = 1,
671
503
.link_nodes = { &qns2_mem_noc },
672
504
};
···
739
559
.name = "qxm_pimem",
740
560
.channels = 1,
741
561
.buswidth = 8,
562
+
.qosbox = &(const struct qcom_icc_qosbox) {
563
+
.num_ports = 1,
564
+
.port_offsets = { 0xc000 },
565
+
.prio = 2,
566
+
.urg_fwd = 1,
567
+
},
742
568
.num_links = 2,
743
569
.link_nodes = { &qns_memnoc_gc, &qxs_imem },
744
570
};
···
753
567
.name = "xm_gic",
754
568
.channels = 1,
755
569
.buswidth = 8,
570
+
.qosbox = &(const struct qcom_icc_qosbox) {
571
+
.num_ports = 1,
572
+
.port_offsets = { 0xd000 },
573
+
.prio = 2,
574
+
.urg_fwd = 1,
575
+
},
756
576
.num_links = 2,
757
577
.link_nodes = { &qns_memnoc_gc, &qxs_imem },
758
578
};
···
1405
1213
[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1406
1214
};
1407
1215
1216
+
static const struct regmap_config qcs615_aggre1_noc_regmap_config = {
1217
+
.reg_bits = 32,
1218
+
.reg_stride = 4,
1219
+
.val_bits = 32,
1220
+
.max_register = 0x3f200,
1221
+
.fast_io = true,
1222
+
};
1223
+
1408
1224
static const struct qcom_icc_desc qcs615_aggre1_noc = {
1225
+
.config = &qcs615_aggre1_noc_regmap_config,
1409
1226
.nodes = aggre1_noc_nodes,
1410
1227
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1411
1228
.bcms = aggre1_noc_bcms,
1412
1229
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1230
+
.qos_requires_clocks = true,
1413
1231
};
1414
1232
1415
1233
static struct qcom_icc_bcm * const camnoc_virt_bcms[] = {
···
1491
1289
[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1492
1290
};
1493
1291
1292
+
static const struct regmap_config qcs615_config_noc_regmap_config = {
1293
+
.reg_bits = 32,
1294
+
.reg_stride = 4,
1295
+
.val_bits = 32,
1296
+
.max_register = 0x5080,
1297
+
.fast_io = true,
1298
+
};
1299
+
1494
1300
static const struct qcom_icc_desc qcs615_config_noc = {
1301
+
.config = &qcs615_config_noc_regmap_config,
1495
1302
.nodes = config_noc_nodes,
1496
1303
.num_nodes = ARRAY_SIZE(config_noc_nodes),
1497
1304
.bcms = config_noc_bcms,
···
1513
1302
[SLAVE_LLCC_CFG] = &qhs_llcc,
1514
1303
};
1515
1304
1305
+
static const struct regmap_config qcs615_dc_noc_regmap_config = {
1306
+
.reg_bits = 32,
1307
+
.reg_stride = 4,
1308
+
.val_bits = 32,
1309
+
.max_register = 0x3200,
1310
+
.fast_io = true,
1311
+
};
1312
+
1516
1313
static const struct qcom_icc_desc qcs615_dc_noc = {
1314
+
.config = &qcs615_dc_noc_regmap_config,
1517
1315
.nodes = dc_noc_nodes,
1518
1316
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
1519
1317
};
···
1551
1331
[SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
1552
1332
};
1553
1333
1334
+
static const struct regmap_config qcs615_gem_noc_regmap_config = {
1335
+
.reg_bits = 32,
1336
+
.reg_stride = 4,
1337
+
.val_bits = 32,
1338
+
.max_register = 0x3e200,
1339
+
.fast_io = true,
1340
+
};
1341
+
1554
1342
static const struct qcom_icc_desc qcs615_gem_noc = {
1343
+
.config = &qcs615_gem_noc_regmap_config,
1555
1344
.nodes = gem_noc_nodes,
1556
1345
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
1557
1346
.bcms = gem_noc_bcms,
···
1605
1376
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1606
1377
};
1607
1378
1379
+
static const struct regmap_config qcs615_mmss_noc_regmap_config = {
1380
+
.reg_bits = 32,
1381
+
.reg_stride = 4,
1382
+
.val_bits = 32,
1383
+
.max_register = 0x1c100,
1384
+
.fast_io = true,
1385
+
};
1386
+
1608
1387
static const struct qcom_icc_desc qcs615_mmss_noc = {
1388
+
.config = &qcs615_mmss_noc_regmap_config,
1609
1389
.nodes = mmss_noc_nodes,
1610
1390
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1611
1391
.bcms = mmss_noc_bcms,
···
1656
1418
[SLAVE_TCU] = &xs_sys_tcu_cfg,
1657
1419
};
1658
1420
1421
+
static const struct regmap_config qcs615_system_noc_regmap_config = {
1422
+
.reg_bits = 32,
1423
+
.reg_stride = 4,
1424
+
.val_bits = 32,
1425
+
.max_register = 0x1f300,
1426
+
.fast_io = true,
1427
+
};
1428
+
1659
1429
static const struct qcom_icc_desc qcs615_system_noc = {
1430
+
.config = &qcs615_system_noc_regmap_config,
1660
1431
.nodes = system_noc_nodes,
1661
1432
.num_nodes = ARRAY_SIZE(system_noc_nodes),
1662
1433
.bcms = system_noc_bcms,
+375
drivers/interconnect/qcom/qcs8300.c
+375
drivers/interconnect/qcom/qcs8300.c
···
186
186
.name = "qxm_qup3",
187
187
.channels = 1,
188
188
.buswidth = 8,
189
+
.qosbox = &(const struct qcom_icc_qosbox) {
190
+
.num_ports = 1,
191
+
.port_offsets = { 0x11000 },
192
+
.prio_fwd_disable = 1,
193
+
.prio = 2,
194
+
.urg_fwd = 0,
195
+
},
189
196
.num_links = 1,
190
197
.link_nodes = { &qns_a1noc_snoc },
191
198
};
···
201
194
.name = "xm_emac_0",
202
195
.channels = 1,
203
196
.buswidth = 8,
197
+
.qosbox = &(const struct qcom_icc_qosbox) {
198
+
.num_ports = 1,
199
+
.port_offsets = { 0x12000 },
200
+
.prio_fwd_disable = 1,
201
+
.prio = 2,
202
+
.urg_fwd = 0,
203
+
},
204
204
.num_links = 1,
205
205
.link_nodes = { &qns_a1noc_snoc },
206
206
};
···
216
202
.name = "xm_sdc1",
217
203
.channels = 1,
218
204
.buswidth = 8,
205
+
.qosbox = &(const struct qcom_icc_qosbox) {
206
+
.num_ports = 1,
207
+
.port_offsets = { 0x14000 },
208
+
.prio_fwd_disable = 1,
209
+
.prio = 2,
210
+
.urg_fwd = 0,
211
+
},
219
212
.num_links = 1,
220
213
.link_nodes = { &qns_a1noc_snoc },
221
214
};
···
231
210
.name = "xm_ufs_mem",
232
211
.channels = 1,
233
212
.buswidth = 8,
213
+
.qosbox = &(const struct qcom_icc_qosbox) {
214
+
.num_ports = 1,
215
+
.port_offsets = { 0x15000 },
216
+
.prio_fwd_disable = 1,
217
+
.prio = 2,
218
+
.urg_fwd = 0,
219
+
},
234
220
.num_links = 1,
235
221
.link_nodes = { &qns_a1noc_snoc },
236
222
};
···
246
218
.name = "xm_usb2_2",
247
219
.channels = 1,
248
220
.buswidth = 8,
221
+
.qosbox = &(const struct qcom_icc_qosbox) {
222
+
.num_ports = 1,
223
+
.port_offsets = { 0x16000 },
224
+
.prio_fwd_disable = 1,
225
+
.prio = 2,
226
+
.urg_fwd = 0,
227
+
},
249
228
.num_links = 1,
250
229
.link_nodes = { &qns_a1noc_snoc },
251
230
};
···
261
226
.name = "xm_usb3_0",
262
227
.channels = 1,
263
228
.buswidth = 8,
229
+
.qosbox = &(const struct qcom_icc_qosbox) {
230
+
.num_ports = 1,
231
+
.port_offsets = { 0x17000 },
232
+
.prio_fwd_disable = 1,
233
+
.prio = 2,
234
+
.urg_fwd = 0,
235
+
},
264
236
.num_links = 1,
265
237
.link_nodes = { &qns_a1noc_snoc },
266
238
};
···
276
234
.name = "qhm_qdss_bam",
277
235
.channels = 1,
278
236
.buswidth = 4,
237
+
.qosbox = &(const struct qcom_icc_qosbox) {
238
+
.num_ports = 1,
239
+
.port_offsets = { 0x14000 },
240
+
.prio_fwd_disable = 1,
241
+
.prio = 2,
242
+
.urg_fwd = 0,
243
+
},
279
244
.num_links = 1,
280
245
.link_nodes = { &qns_a2noc_snoc },
281
246
};
···
291
242
.name = "qhm_qup0",
292
243
.channels = 1,
293
244
.buswidth = 4,
245
+
.qosbox = &(const struct qcom_icc_qosbox) {
246
+
.num_ports = 1,
247
+
.port_offsets = { 0x17000 },
248
+
.prio_fwd_disable = 1,
249
+
.prio = 2,
250
+
.urg_fwd = 0,
251
+
},
294
252
.num_links = 1,
295
253
.link_nodes = { &qns_a2noc_snoc },
296
254
};
···
306
250
.name = "qhm_qup1",
307
251
.channels = 1,
308
252
.buswidth = 4,
253
+
.qosbox = &(const struct qcom_icc_qosbox) {
254
+
.num_ports = 1,
255
+
.port_offsets = { 0x12000 },
256
+
.prio_fwd_disable = 1,
257
+
.prio = 2,
258
+
.urg_fwd = 0,
259
+
},
309
260
.num_links = 1,
310
261
.link_nodes = { &qns_a2noc_snoc },
311
262
};
···
321
258
.name = "qnm_cnoc_datapath",
322
259
.channels = 1,
323
260
.buswidth = 8,
261
+
.qosbox = &(const struct qcom_icc_qosbox) {
262
+
.num_ports = 1,
263
+
.port_offsets = { 0x16000 },
264
+
.prio_fwd_disable = 1,
265
+
.prio = 2,
266
+
.urg_fwd = 0,
267
+
},
324
268
.num_links = 1,
325
269
.link_nodes = { &qns_a2noc_snoc },
326
270
};
···
336
266
.name = "qxm_crypto_0",
337
267
.channels = 1,
338
268
.buswidth = 8,
269
+
.qosbox = &(const struct qcom_icc_qosbox) {
270
+
.num_ports = 1,
271
+
.port_offsets = { 0x18000 },
272
+
.prio_fwd_disable = 1,
273
+
.prio = 2,
274
+
.urg_fwd = 0,
275
+
},
339
276
.num_links = 1,
340
277
.link_nodes = { &qns_a2noc_snoc },
341
278
};
···
351
274
.name = "qxm_crypto_1",
352
275
.channels = 1,
353
276
.buswidth = 8,
277
+
.qosbox = &(const struct qcom_icc_qosbox) {
278
+
.num_ports = 1,
279
+
.port_offsets = { 0x1a000 },
280
+
.prio_fwd_disable = 1,
281
+
.prio = 2,
282
+
.urg_fwd = 0,
283
+
},
354
284
.num_links = 1,
355
285
.link_nodes = { &qns_a2noc_snoc },
356
286
};
···
366
282
.name = "qxm_ipa",
367
283
.channels = 1,
368
284
.buswidth = 8,
285
+
.qosbox = &(const struct qcom_icc_qosbox) {
286
+
.num_ports = 1,
287
+
.port_offsets = { 0x11000 },
288
+
.prio_fwd_disable = 1,
289
+
.prio = 2,
290
+
.urg_fwd = 0,
291
+
},
369
292
.num_links = 1,
370
293
.link_nodes = { &qns_a2noc_snoc },
371
294
};
···
381
290
.name = "xm_qdss_etr_0",
382
291
.channels = 1,
383
292
.buswidth = 8,
293
+
.qosbox = &(const struct qcom_icc_qosbox) {
294
+
.num_ports = 1,
295
+
.port_offsets = { 0x13000 },
296
+
.prio_fwd_disable = 1,
297
+
.prio = 2,
298
+
.urg_fwd = 0,
299
+
},
384
300
.num_links = 1,
385
301
.link_nodes = { &qns_a2noc_snoc },
386
302
};
···
396
298
.name = "xm_qdss_etr_1",
397
299
.channels = 1,
398
300
.buswidth = 8,
301
+
.qosbox = &(const struct qcom_icc_qosbox) {
302
+
.num_ports = 1,
303
+
.port_offsets = { 0x19000 },
304
+
.prio_fwd_disable = 1,
305
+
.prio = 2,
306
+
.urg_fwd = 0,
307
+
},
399
308
.num_links = 1,
400
309
.link_nodes = { &qns_a2noc_snoc },
401
310
};
···
495
390
.name = "alm_gpu_tcu",
496
391
.channels = 1,
497
392
.buswidth = 8,
393
+
.qosbox = &(const struct qcom_icc_qosbox) {
394
+
.num_ports = 1,
395
+
.port_offsets = { 0xaf000 },
396
+
.prio_fwd_disable = 1,
397
+
.prio = 1,
398
+
.urg_fwd = 0,
399
+
},
498
400
.num_links = 2,
499
401
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
500
402
};
···
510
398
.name = "alm_pcie_tcu",
511
399
.channels = 1,
512
400
.buswidth = 8,
401
+
.qosbox = &(const struct qcom_icc_qosbox) {
402
+
.num_ports = 1,
403
+
.port_offsets = { 0xb0000 },
404
+
.prio_fwd_disable = 1,
405
+
.prio = 3,
406
+
.urg_fwd = 0,
407
+
},
513
408
.num_links = 2,
514
409
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
515
410
};
···
525
406
.name = "alm_sys_tcu",
526
407
.channels = 1,
527
408
.buswidth = 8,
409
+
.qosbox = &(const struct qcom_icc_qosbox) {
410
+
.num_ports = 1,
411
+
.port_offsets = { 0xb1000 },
412
+
.prio_fwd_disable = 1,
413
+
.prio = 6,
414
+
.urg_fwd = 0,
415
+
},
528
416
.num_links = 2,
529
417
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
530
418
};
···
549
423
.name = "qnm_cmpnoc0",
550
424
.channels = 2,
551
425
.buswidth = 32,
426
+
.qosbox = &(const struct qcom_icc_qosbox) {
427
+
.num_ports = 2,
428
+
.port_offsets = { 0xf6000, 0xf7000 },
429
+
.prio_fwd_disable = 1,
430
+
.prio = 0,
431
+
.urg_fwd = 0,
432
+
},
552
433
.num_links = 2,
553
434
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
554
435
};
···
581
448
.name = "qnm_gpu",
582
449
.channels = 2,
583
450
.buswidth = 32,
451
+
.qosbox = &(const struct qcom_icc_qosbox) {
452
+
.num_ports = 2,
453
+
.port_offsets = { 0xf0000, 0xf1000 },
454
+
.prio_fwd_disable = 1,
455
+
.prio = 0,
456
+
.urg_fwd = 0,
457
+
},
584
458
.num_links = 2,
585
459
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
586
460
};
···
596
456
.name = "qnm_mnoc_hf",
597
457
.channels = 2,
598
458
.buswidth = 32,
459
+
.qosbox = &(const struct qcom_icc_qosbox) {
460
+
.num_ports = 2,
461
+
.port_offsets = { 0xf2000, 0xf3000 },
462
+
.prio_fwd_disable = 0,
463
+
.prio = 0,
464
+
.urg_fwd = 1,
465
+
},
599
466
.num_links = 2,
600
467
.link_nodes = { &qns_llcc, &qns_pcie },
601
468
};
···
611
464
.name = "qnm_mnoc_sf",
612
465
.channels = 2,
613
466
.buswidth = 32,
467
+
.qosbox = &(const struct qcom_icc_qosbox) {
468
+
.num_ports = 2,
469
+
.port_offsets = { 0xf4000, 0xf5000 },
470
+
.prio_fwd_disable = 0,
471
+
.prio = 0,
472
+
.urg_fwd = 1,
473
+
},
614
474
.num_links = 3,
615
475
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
616
476
&qns_pcie },
···
627
473
.name = "qnm_pcie",
628
474
.channels = 1,
629
475
.buswidth = 32,
476
+
.qosbox = &(const struct qcom_icc_qosbox) {
477
+
.num_ports = 1,
478
+
.port_offsets = { 0xb3000 },
479
+
.prio_fwd_disable = 1,
480
+
.prio = 2,
481
+
.urg_fwd = 0,
482
+
},
630
483
.num_links = 2,
631
484
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
632
485
};
···
642
481
.name = "qnm_snoc_gc",
643
482
.channels = 1,
644
483
.buswidth = 8,
484
+
.qosbox = &(const struct qcom_icc_qosbox) {
485
+
.num_ports = 1,
486
+
.port_offsets = { 0xb4000 },
487
+
.prio_fwd_disable = 0,
488
+
.prio = 0,
489
+
.urg_fwd = 1,
490
+
},
645
491
.num_links = 1,
646
492
.link_nodes = { &qns_llcc },
647
493
};
···
657
489
.name = "qnm_snoc_sf",
658
490
.channels = 1,
659
491
.buswidth = 16,
492
+
.qosbox = &(const struct qcom_icc_qosbox) {
493
+
.num_ports = 1,
494
+
.port_offsets = { 0xb5000 },
495
+
.prio_fwd_disable = 0,
496
+
.prio = 0,
497
+
.urg_fwd = 1,
498
+
},
660
499
.num_links = 3,
661
500
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
662
501
&qns_pcie },
···
716
541
.name = "qnm_camnoc_hf",
717
542
.channels = 1,
718
543
.buswidth = 32,
544
+
.qosbox = &(const struct qcom_icc_qosbox) {
545
+
.num_ports = 1,
546
+
.port_offsets = { 0xa000 },
547
+
.prio_fwd_disable = 0,
548
+
.prio = 0,
549
+
.urg_fwd = 1,
550
+
},
719
551
.num_links = 1,
720
552
.link_nodes = { &qns_mem_noc_hf },
721
553
};
···
731
549
.name = "qnm_camnoc_icp",
732
550
.channels = 1,
733
551
.buswidth = 8,
552
+
.qosbox = &(const struct qcom_icc_qosbox) {
553
+
.num_ports = 1,
554
+
.port_offsets = { 0x2a000 },
555
+
.prio_fwd_disable = 0,
556
+
.prio = 0,
557
+
.urg_fwd = 1,
558
+
},
734
559
.num_links = 1,
735
560
.link_nodes = { &qns_mem_noc_sf },
736
561
};
···
746
557
.name = "qnm_camnoc_sf",
747
558
.channels = 1,
748
559
.buswidth = 32,
560
+
.qosbox = &(const struct qcom_icc_qosbox) {
561
+
.num_ports = 1,
562
+
.port_offsets = { 0x2a080 },
563
+
.prio_fwd_disable = 0,
564
+
.prio = 0,
565
+
.urg_fwd = 1,
566
+
},
749
567
.num_links = 1,
750
568
.link_nodes = { &qns_mem_noc_sf },
751
569
};
···
761
565
.name = "qnm_mdp0_0",
762
566
.channels = 1,
763
567
.buswidth = 32,
568
+
.qosbox = &(const struct qcom_icc_qosbox) {
569
+
.num_ports = 1,
570
+
.port_offsets = { 0xa080 },
571
+
.prio_fwd_disable = 0,
572
+
.prio = 0,
573
+
.urg_fwd = 1,
574
+
},
764
575
.num_links = 1,
765
576
.link_nodes = { &qns_mem_noc_hf },
766
577
};
···
776
573
.name = "qnm_mdp0_1",
777
574
.channels = 1,
778
575
.buswidth = 32,
576
+
.qosbox = &(const struct qcom_icc_qosbox) {
577
+
.num_ports = 1,
578
+
.port_offsets = { 0xa180 },
579
+
.prio_fwd_disable = 0,
580
+
.prio = 0,
581
+
.urg_fwd = 1,
582
+
},
779
583
.num_links = 1,
780
584
.link_nodes = { &qns_mem_noc_hf },
781
585
};
···
807
597
.name = "qnm_video0",
808
598
.channels = 1,
809
599
.buswidth = 32,
600
+
.qosbox = &(const struct qcom_icc_qosbox) {
601
+
.num_ports = 1,
602
+
.port_offsets = { 0x2a100 },
603
+
.prio_fwd_disable = 0,
604
+
.prio = 0,
605
+
.urg_fwd = 1,
606
+
},
810
607
.num_links = 1,
811
608
.link_nodes = { &qns_mem_noc_sf },
812
609
};
···
822
605
.name = "qnm_video_cvp",
823
606
.channels = 1,
824
607
.buswidth = 32,
608
+
.qosbox = &(const struct qcom_icc_qosbox) {
609
+
.num_ports = 1,
610
+
.port_offsets = { 0x2a200 },
611
+
.prio_fwd_disable = 0,
612
+
.prio = 0,
613
+
.urg_fwd = 1,
614
+
},
825
615
.num_links = 1,
826
616
.link_nodes = { &qns_mem_noc_sf },
827
617
};
···
837
613
.name = "qnm_video_v_cpu",
838
614
.channels = 1,
839
615
.buswidth = 8,
616
+
.qosbox = &(const struct qcom_icc_qosbox) {
617
+
.num_ports = 1,
618
+
.port_offsets = { 0x2a280 },
619
+
.prio_fwd_disable = 0,
620
+
.prio = 0,
621
+
.urg_fwd = 1,
622
+
},
840
623
.num_links = 1,
841
624
.link_nodes = { &qns_mem_noc_sf },
842
625
};
···
868
637
.name = "xm_pcie3_0",
869
638
.channels = 1,
870
639
.buswidth = 16,
640
+
.qosbox = &(const struct qcom_icc_qosbox) {
641
+
.num_ports = 1,
642
+
.port_offsets = { 0xb000 },
643
+
.prio_fwd_disable = 1,
644
+
.prio = 2,
645
+
.urg_fwd = 0,
646
+
},
871
647
.num_links = 1,
872
648
.link_nodes = { &qns_pcie_mem_noc },
873
649
};
···
883
645
.name = "xm_pcie3_1",
884
646
.channels = 1,
885
647
.buswidth = 32,
648
+
.qosbox = &(const struct qcom_icc_qosbox) {
649
+
.num_ports = 1,
650
+
.port_offsets = { 0xc000 },
651
+
.prio_fwd_disable = 1,
652
+
.prio = 2,
653
+
.urg_fwd = 0,
654
+
},
886
655
.num_links = 1,
887
656
.link_nodes = { &qns_pcie_mem_noc },
888
657
};
···
898
653
.name = "qhm_gic",
899
654
.channels = 1,
900
655
.buswidth = 4,
656
+
.qosbox = &(const struct qcom_icc_qosbox) {
657
+
.num_ports = 1,
658
+
.port_offsets = { 0x14000 },
659
+
.prio_fwd_disable = 1,
660
+
.prio = 2,
661
+
.urg_fwd = 0,
662
+
},
901
663
.num_links = 1,
902
664
.link_nodes = { &qns_gemnoc_sf },
903
665
};
···
929
677
.name = "qnm_lpass_noc",
930
678
.channels = 1,
931
679
.buswidth = 16,
680
+
.qosbox = &(const struct qcom_icc_qosbox) {
681
+
.num_ports = 1,
682
+
.port_offsets = { 0x12000 },
683
+
.prio_fwd_disable = 0,
684
+
.prio = 0,
685
+
.urg_fwd = 1,
686
+
},
932
687
.num_links = 1,
933
688
.link_nodes = { &qns_gemnoc_sf },
934
689
};
···
952
693
.name = "qxm_pimem",
953
694
.channels = 1,
954
695
.buswidth = 8,
696
+
.qosbox = &(const struct qcom_icc_qosbox) {
697
+
.num_ports = 1,
698
+
.port_offsets = { 0x13000 },
699
+
.prio_fwd_disable = 1,
700
+
.prio = 2,
701
+
.urg_fwd = 0,
702
+
},
955
703
.num_links = 1,
956
704
.link_nodes = { &qns_gemnoc_gc },
957
705
};
···
967
701
.name = "xm_gic",
968
702
.channels = 1,
969
703
.buswidth = 8,
704
+
.qosbox = &(const struct qcom_icc_qosbox) {
705
+
.num_ports = 1,
706
+
.port_offsets = { 0x15000 },
707
+
.prio_fwd_disable = 1,
708
+
.prio = 2,
709
+
.urg_fwd = 0,
710
+
},
970
711
.num_links = 1,
971
712
.link_nodes = { &qns_gemnoc_gc },
972
713
};
···
1872
1599
[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1873
1600
};
1874
1601
1602
+
static const struct regmap_config qcs8300_aggre1_noc_regmap_config = {
1603
+
.reg_bits = 32,
1604
+
.reg_stride = 4,
1605
+
.val_bits = 32,
1606
+
.max_register = 0x17080,
1607
+
.fast_io = true,
1608
+
};
1609
+
1875
1610
static const struct qcom_icc_desc qcs8300_aggre1_noc = {
1611
+
.config = &qcs8300_aggre1_noc_regmap_config,
1876
1612
.nodes = aggre1_noc_nodes,
1877
1613
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1878
1614
.bcms = aggre1_noc_bcms,
1879
1615
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1616
+
.qos_requires_clocks = true,
1880
1617
};
1881
1618
1882
1619
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
···
1907
1624
[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1908
1625
};
1909
1626
1627
+
static const struct regmap_config qcs8300_aggre2_noc_regmap_config = {
1628
+
.reg_bits = 32,
1629
+
.reg_stride = 4,
1630
+
.val_bits = 32,
1631
+
.max_register = 0x1a080,
1632
+
.fast_io = true,
1633
+
};
1634
+
1910
1635
static const struct qcom_icc_desc qcs8300_aggre2_noc = {
1636
+
.config = &qcs8300_aggre2_noc_regmap_config,
1911
1637
.nodes = aggre2_noc_nodes,
1912
1638
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1913
1639
.bcms = aggre2_noc_bcms,
1914
1640
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1641
+
.qos_requires_clocks = true,
1915
1642
};
1916
1643
1917
1644
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
···
2033
1740
[SLAVE_TCU] = &xs_sys_tcu_cfg,
2034
1741
};
2035
1742
1743
+
static const struct regmap_config qcs8300_config_noc_regmap_config = {
1744
+
.reg_bits = 32,
1745
+
.reg_stride = 4,
1746
+
.val_bits = 32,
1747
+
.max_register = 0x13080,
1748
+
.fast_io = true,
1749
+
};
1750
+
2036
1751
static const struct qcom_icc_desc qcs8300_config_noc = {
1752
+
.config = &qcs8300_config_noc_regmap_config,
2037
1753
.nodes = config_noc_nodes,
2038
1754
.num_nodes = ARRAY_SIZE(config_noc_nodes),
2039
1755
.bcms = config_noc_bcms,
···
2055
1753
[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
2056
1754
};
2057
1755
1756
+
static const struct regmap_config qcs8300_dc_noc_regmap_config = {
1757
+
.reg_bits = 32,
1758
+
.reg_stride = 4,
1759
+
.val_bits = 32,
1760
+
.max_register = 0x5080,
1761
+
.fast_io = true,
1762
+
};
1763
+
2058
1764
static const struct qcom_icc_desc qcs8300_dc_noc = {
1765
+
.config = &qcs8300_dc_noc_regmap_config,
2059
1766
.nodes = dc_noc_nodes,
2060
1767
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
2061
1768
};
···
2097
1786
[SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2,
2098
1787
};
2099
1788
1789
+
static const struct regmap_config qcs8300_gem_noc_regmap_config = {
1790
+
.reg_bits = 32,
1791
+
.reg_stride = 4,
1792
+
.val_bits = 32,
1793
+
.max_register = 0xf7080,
1794
+
.fast_io = true,
1795
+
};
1796
+
2100
1797
static const struct qcom_icc_desc qcs8300_gem_noc = {
1798
+
.config = &qcs8300_gem_noc_regmap_config,
2101
1799
.nodes = gem_noc_nodes,
2102
1800
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
2103
1801
.bcms = gem_noc_bcms,
2104
1802
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
1803
+
.qos_requires_clocks = true,
2105
1804
};
2106
1805
2107
1806
static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] = {
···
2124
1803
[SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc,
2125
1804
};
2126
1805
1806
+
static const struct regmap_config qcs8300_gpdsp_anoc_regmap_config = {
1807
+
.reg_bits = 32,
1808
+
.reg_stride = 4,
1809
+
.val_bits = 32,
1810
+
.max_register = 0xd080,
1811
+
.fast_io = true,
1812
+
};
1813
+
2127
1814
static const struct qcom_icc_desc qcs8300_gpdsp_anoc = {
1815
+
.config = &qcs8300_gpdsp_anoc_regmap_config,
2128
1816
.nodes = gpdsp_anoc_nodes,
2129
1817
.num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes),
2130
1818
.bcms = gpdsp_anoc_bcms,
···
2156
1826
[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
2157
1827
};
2158
1828
1829
+
static const struct regmap_config qcs8300_lpass_ag_noc_regmap_config = {
1830
+
.reg_bits = 32,
1831
+
.reg_stride = 4,
1832
+
.val_bits = 32,
1833
+
.max_register = 0x17200,
1834
+
.fast_io = true,
1835
+
};
1836
+
2159
1837
static const struct qcom_icc_desc qcs8300_lpass_ag_noc = {
1838
+
.config = &qcs8300_lpass_ag_noc_regmap_config,
2160
1839
.nodes = lpass_ag_noc_nodes,
2161
1840
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
2162
1841
.bcms = lpass_ag_noc_bcms,
···
2211
1872
[SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf,
2212
1873
};
2213
1874
1875
+
static const struct regmap_config qcs8300_mmss_noc_regmap_config = {
1876
+
.reg_bits = 32,
1877
+
.reg_stride = 4,
1878
+
.val_bits = 32,
1879
+
.max_register = 0x40000,
1880
+
.fast_io = true,
1881
+
};
1882
+
2214
1883
static const struct qcom_icc_desc qcs8300_mmss_noc = {
1884
+
.config = &qcs8300_mmss_noc_regmap_config,
2215
1885
.nodes = mmss_noc_nodes,
2216
1886
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
2217
1887
.bcms = mmss_noc_bcms,
···
2240
1892
[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
2241
1893
};
2242
1894
1895
+
static const struct regmap_config qcs8300_nspa_noc_regmap_config = {
1896
+
.reg_bits = 32,
1897
+
.reg_stride = 4,
1898
+
.val_bits = 32,
1899
+
.max_register = 0x16080,
1900
+
.fast_io = true,
1901
+
};
1902
+
2243
1903
static const struct qcom_icc_desc qcs8300_nspa_noc = {
1904
+
.config = &qcs8300_nspa_noc_regmap_config,
2244
1905
.nodes = nspa_noc_nodes,
2245
1906
.num_nodes = ARRAY_SIZE(nspa_noc_nodes),
2246
1907
.bcms = nspa_noc_bcms,
···
2266
1909
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
2267
1910
};
2268
1911
1912
+
static const struct regmap_config qcs8300_pcie_anoc_regmap_config = {
1913
+
.reg_bits = 32,
1914
+
.reg_stride = 4,
1915
+
.val_bits = 32,
1916
+
.max_register = 0xc080,
1917
+
.fast_io = true,
1918
+
};
1919
+
2269
1920
static const struct qcom_icc_desc qcs8300_pcie_anoc = {
1921
+
.config = &qcs8300_pcie_anoc_regmap_config,
2270
1922
.nodes = pcie_anoc_nodes,
2271
1923
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
2272
1924
.bcms = pcie_anoc_bcms,
···
2303
1937
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
2304
1938
};
2305
1939
1940
+
static const struct regmap_config qcs8300_system_noc_regmap_config = {
1941
+
.reg_bits = 32,
1942
+
.reg_stride = 4,
1943
+
.val_bits = 32,
1944
+
.max_register = 0x15080,
1945
+
.fast_io = true,
1946
+
};
1947
+
2306
1948
static const struct qcom_icc_desc qcs8300_system_noc = {
1949
+
.config = &qcs8300_system_noc_regmap_config,
2307
1950
.nodes = system_noc_nodes,
2308
1951
.num_nodes = ARRAY_SIZE(system_noc_nodes),
2309
1952
.bcms = system_noc_bcms,
+136
include/dt-bindings/interconnect/qcom,eliza-rpmh.h
+136
include/dt-bindings/interconnect/qcom,eliza-rpmh.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
5
+
6
+
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_ELIZA_H
7
+
#define __DT_BINDINGS_INTERCONNECT_QCOM_ELIZA_H
8
+
9
+
#define MASTER_QSPI_0 0
10
+
#define MASTER_QUP_1 1
11
+
#define MASTER_UFS_MEM 2
12
+
#define MASTER_USB3_0 3
13
+
#define SLAVE_A1NOC_SNOC 4
14
+
15
+
#define MASTER_QUP_2 0
16
+
#define MASTER_CRYPTO 1
17
+
#define MASTER_IPA 2
18
+
#define MASTER_SOCCP_AGGR_NOC 3
19
+
#define MASTER_QDSS_ETR 4
20
+
#define MASTER_QDSS_ETR_1 5
21
+
#define MASTER_SDCC_1 6
22
+
#define MASTER_SDCC_2 7
23
+
#define SLAVE_A2NOC_SNOC 8
24
+
25
+
#define MASTER_QUP_CORE_1 0
26
+
#define MASTER_QUP_CORE_2 1
27
+
#define SLAVE_QUP_CORE_1 2
28
+
#define SLAVE_QUP_CORE_2 3
29
+
30
+
#define MASTER_CNOC_CFG 0
31
+
#define SLAVE_AHB2PHY_SOUTH 1
32
+
#define SLAVE_AHB2PHY_NORTH 2
33
+
#define SLAVE_CAMERA_CFG 3
34
+
#define SLAVE_CLK_CTL 4
35
+
#define SLAVE_CRYPTO_0_CFG 5
36
+
#define SLAVE_DISPLAY_CFG 6
37
+
#define SLAVE_GFX3D_CFG 7
38
+
#define SLAVE_I3C_IBI0_CFG 8
39
+
#define SLAVE_I3C_IBI1_CFG 9
40
+
#define SLAVE_IMEM_CFG 10
41
+
#define SLAVE_CNOC_MSS 11
42
+
#define SLAVE_PCIE_0_CFG 12
43
+
#define SLAVE_PRNG 13
44
+
#define SLAVE_QDSS_CFG 14
45
+
#define SLAVE_QSPI_0 15
46
+
#define SLAVE_QUP_1 16
47
+
#define SLAVE_QUP_2 17
48
+
#define SLAVE_SDCC_2 18
49
+
#define SLAVE_TCSR 19
50
+
#define SLAVE_TLMM 20
51
+
#define SLAVE_UFS_MEM_CFG 21
52
+
#define SLAVE_USB3_0 22
53
+
#define SLAVE_VENUS_CFG 23
54
+
#define SLAVE_VSENSE_CTRL_CFG 24
55
+
#define SLAVE_CNOC_MNOC_HF_CFG 25
56
+
#define SLAVE_CNOC_MNOC_SF_CFG 26
57
+
#define SLAVE_PCIE_ANOC_CFG 27
58
+
#define SLAVE_QDSS_STM 28
59
+
#define SLAVE_TCU 29
60
+
61
+
#define MASTER_GEM_NOC_CNOC 0
62
+
#define MASTER_GEM_NOC_PCIE_SNOC 1
63
+
#define SLAVE_AOSS 2
64
+
#define SLAVE_IPA_CFG 3
65
+
#define SLAVE_IPC_ROUTER_CFG 4
66
+
#define SLAVE_SOCCP 5
67
+
#define SLAVE_TME_CFG 6
68
+
#define SLAVE_APPSS 7
69
+
#define SLAVE_CNOC_CFG 8
70
+
#define SLAVE_DDRSS_CFG 9
71
+
#define SLAVE_BOOT_IMEM 10
72
+
#define SLAVE_IMEM 11
73
+
#define SLAVE_BOOT_IMEM_2 12
74
+
#define SLAVE_SERVICE_CNOC 13
75
+
#define SLAVE_PCIE_0 14
76
+
#define SLAVE_PCIE_1 15
77
+
78
+
#define MASTER_GPU_TCU 0
79
+
#define MASTER_SYS_TCU 1
80
+
#define MASTER_APPSS_PROC 2
81
+
#define MASTER_GFX3D 3
82
+
#define MASTER_LPASS_GEM_NOC 4
83
+
#define MASTER_MSS_PROC 5
84
+
#define MASTER_MNOC_HF_MEM_NOC 6
85
+
#define MASTER_MNOC_SF_MEM_NOC 7
86
+
#define MASTER_COMPUTE_NOC 8
87
+
#define MASTER_ANOC_PCIE_GEM_NOC 9
88
+
#define MASTER_SNOC_SF_MEM_NOC 10
89
+
#define MASTER_WLAN_Q6 11
90
+
#define MASTER_GIC 12
91
+
#define SLAVE_GEM_NOC_CNOC 13
92
+
#define SLAVE_LLCC 14
93
+
#define SLAVE_MEM_NOC_PCIE_SNOC 15
94
+
95
+
#define MASTER_LPIAON_NOC 0
96
+
#define SLAVE_LPASS_GEM_NOC 1
97
+
98
+
#define MASTER_LPASS_LPINOC 0
99
+
#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1
100
+
101
+
#define MASTER_LPASS_PROC 0
102
+
#define SLAVE_LPICX_NOC_LPIAON_NOC 1
103
+
104
+
#define MASTER_LLCC 0
105
+
#define SLAVE_EBI1 1
106
+
107
+
#define MASTER_CAMNOC_NRT_ICP_SF 0
108
+
#define MASTER_CAMNOC_RT_CDM_SF 1
109
+
#define MASTER_CAMNOC_SF 2
110
+
#define MASTER_VIDEO_MVP 3
111
+
#define MASTER_VIDEO_V_PROC 4
112
+
#define MASTER_CNOC_MNOC_SF_CFG 5
113
+
#define MASTER_CAMNOC_HF 6
114
+
#define MASTER_MDP 7
115
+
#define MASTER_CNOC_MNOC_HF_CFG 8
116
+
#define SLAVE_MNOC_SF_MEM_NOC 9
117
+
#define SLAVE_SERVICE_MNOC_SF 10
118
+
#define SLAVE_MNOC_HF_MEM_NOC 11
119
+
#define SLAVE_SERVICE_MNOC_HF 12
120
+
121
+
#define MASTER_CDSP_PROC 0
122
+
#define SLAVE_CDSP_MEM_NOC 1
123
+
124
+
#define MASTER_PCIE_ANOC_CFG 0
125
+
#define MASTER_PCIE_0 1
126
+
#define MASTER_PCIE_1 2
127
+
#define SLAVE_ANOC_PCIE_GEM_NOC 3
128
+
#define SLAVE_SERVICE_PCIE_ANOC 4
129
+
130
+
#define MASTER_A1NOC_SNOC 0
131
+
#define MASTER_A2NOC_SNOC 1
132
+
#define MASTER_CNOC_SNOC 2
133
+
#define MASTER_NSINOC_SNOC 3
134
+
#define SLAVE_SNOC_GEM_NOC_SF 4
135
+
136
+
#endif