+1

drivers/staging/fbtft/fbtft-core.c

reviewed

··· 1276 1276 } 1277 1277 EXPORT_SYMBOL(fbtft_remove_common); 1278 1278 1279 1279 + MODULE_DESCRIPTION("Core FB support for small TFT LCD display modules"); 1279 1280 MODULE_LICENSE("GPL");

+1

drivers/staging/greybus/audio_manager.c

reviewed

··· 182 182 module_init(manager_init); 183 183 module_exit(manager_exit); 184 184 185 185 + MODULE_DESCRIPTION("Greybus audio operations manager"); 185 186 MODULE_LICENSE("GPL"); 186 187 MODULE_AUTHOR("Svetlin Ankov <ankov_svetlin@projectara.com>");

-6

drivers/staging/greybus/audio_topology.c

reviewed

··· 10 10 11 11 #define GBAUDIO_INVALID_ID 0xFF 12 12 13 13 - /* mixer control */ 14 14 - struct gb_mixer_control { 15 15 - int min, max; 16 16 - unsigned int reg, rreg, shift, rshift, invert; 17 17 - }; 18 18 - 19 13 struct gbaudio_ctl_pvt { 20 14 unsigned int ctl_id; 21 15 unsigned int data_cport;

+1

drivers/staging/greybus/bootrom.c

reviewed

··· 522 522 523 523 module_greybus_driver(gb_bootrom_driver); 524 524 525 525 + MODULE_DESCRIPTION("BOOTROM Greybus driver"); 525 526 MODULE_LICENSE("GPL v2");

+1

drivers/staging/greybus/camera.c

reviewed

··· 1374 1374 1375 1375 module_greybus_driver(gb_camera_driver); 1376 1376 1377 1377 + MODULE_DESCRIPTION("Greybus Camera protocol driver."); 1377 1378 MODULE_LICENSE("GPL v2");

+1

drivers/staging/greybus/gbphy.c

reviewed

··· 354 354 } 355 355 module_exit(gbphy_exit); 356 356 357 357 + MODULE_DESCRIPTION("Greybus Bridged-Phy Bus driver"); 357 358 MODULE_LICENSE("GPL v2");

+1

drivers/staging/greybus/gpio.c

reviewed

··· 631 631 }; 632 632 633 633 module_gbphy_driver(gpio_driver); 634 634 + MODULE_DESCRIPTION("GPIO Greybus driver"); 634 635 MODULE_LICENSE("GPL v2");

+1

drivers/staging/greybus/hid.c

reviewed

··· 516 516 }; 517 517 module_greybus_driver(gb_hid_driver); 518 518 519 519 + MODULE_DESCRIPTION("HID class driver for the Greybus"); 519 520 MODULE_LICENSE("GPL v2");

+1

drivers/staging/greybus/i2c.c

reviewed

··· 318 318 }; 319 319 320 320 module_gbphy_driver(i2c_driver); 321 321 + MODULE_DESCRIPTION("I2C bridge driver for the Greybus 'generic' I2C module"); 321 322 MODULE_LICENSE("GPL v2");

+1

drivers/staging/greybus/light.c

reviewed

··· 1339 1339 }; 1340 1340 module_greybus_driver(gb_lights_driver); 1341 1341 1342 1342 + MODULE_DESCRIPTION("Greybus Lights protocol driver"); 1342 1343 MODULE_LICENSE("GPL v2");

+1

drivers/staging/greybus/log.c

reviewed

··· 129 129 }; 130 130 module_greybus_driver(gb_log_driver); 131 131 132 132 + MODULE_DESCRIPTION("Greybus driver for the log protocol"); 132 133 MODULE_LICENSE("GPL v2");

+1

drivers/staging/greybus/loopback.c

reviewed

··· 1175 1175 } 1176 1176 module_exit(loopback_exit); 1177 1177 1178 1178 + MODULE_DESCRIPTION("Loopback bridge driver for the Greybus loopback module"); 1178 1179 MODULE_LICENSE("GPL v2");

+1

drivers/staging/greybus/power_supply.c

reviewed

··· 1136 1136 }; 1137 1137 module_greybus_driver(gb_power_supply_driver); 1138 1138 1139 1139 + MODULE_DESCRIPTION("Power Supply driver for a Greybus module"); 1139 1140 MODULE_LICENSE("GPL v2");

+1

drivers/staging/greybus/pwm.c

reviewed

··· 327 327 }; 328 328 329 329 module_gbphy_driver(pwm_driver); 330 330 + MODULE_DESCRIPTION("PWM Greybus driver"); 330 331 MODULE_LICENSE("GPL v2");

+1

drivers/staging/greybus/raw.c

reviewed

··· 377 377 } 378 378 module_exit(raw_exit); 379 379 380 380 + MODULE_DESCRIPTION("Greybus driver for the Raw protocol"); 380 381 MODULE_LICENSE("GPL v2");

+1

drivers/staging/greybus/sdio.c

reviewed

··· 880 880 }; 881 881 882 882 module_gbphy_driver(sdio_driver); 883 883 + MODULE_DESCRIPTION("SD/MMC Greybus driver"); 883 884 MODULE_LICENSE("GPL v2");

+1

drivers/staging/greybus/spi.c

reviewed

··· 75 75 }; 76 76 77 77 module_gbphy_driver(spi_driver); 78 78 + MODULE_DESCRIPTION("Greybus SPI bridge PHY driver"); 78 79 MODULE_LICENSE("GPL v2");

+1

drivers/staging/greybus/spilib.c

reviewed

··· 567 567 } 568 568 EXPORT_SYMBOL_GPL(gb_spilib_master_exit); 569 569 570 570 + MODULE_DESCRIPTION("Greybus SPI library"); 570 571 MODULE_LICENSE("GPL v2");

+1

drivers/staging/greybus/uart.c

reviewed

··· 1024 1024 } 1025 1025 1026 1026 module_exit(gb_uart_driver_exit); 1027 1027 + MODULE_DESCRIPTION("UART driver for the Greybus 'generic' UART module"); 1027 1028 MODULE_LICENSE("GPL v2");

+1

drivers/staging/greybus/usb.c

reviewed

··· 242 242 }; 243 243 244 244 module_gbphy_driver(usb_driver); 245 245 + MODULE_DESCRIPTION("USB host driver for the Greybus 'generic' USB module"); 245 246 MODULE_LICENSE("GPL v2");

+1

drivers/staging/greybus/vibrator.c

reviewed

··· 245 245 } 246 246 module_exit(gb_vibrator_exit); 247 247 248 248 + MODULE_DESCRIPTION("Greybus Vibrator protocol driver"); 248 249 MODULE_LICENSE("GPL v2");

+26 -19

drivers/staging/nvec/nvec.c

reviewed

··· 300 300 { 301 301 mutex_lock(&nvec->sync_write_mutex); 302 302 303 303 - if (msg != NULL) 303 303 + if (msg) 304 304 *msg = NULL; 305 305 306 306 nvec->sync_write_pending = (data[1] << 8) + data[0]; ··· 322 322 323 323 dev_dbg(nvec->dev, "nvec_sync_write: pong!\n"); 324 324 325 325 - if (msg != NULL) 325 325 + if (msg) 326 326 *msg = nvec->last_sync_msg; 327 327 else 328 328 nvec_msg_free(nvec, nvec->last_sync_msg); ··· 571 571 } 572 572 573 573 /** 574 574 + * tegra_i2c_writel - safely write to an I2C client controller register 575 575 + * @val: value to be written 576 576 + * @reg: register to write to 577 577 + * 578 578 + * A write to an I2C controller register needs to be read back to make sure 579 579 + * that the value has arrived. 580 580 + */ 581 581 + static void tegra_i2c_writel(u32 val, void *reg) 582 582 + { 583 583 + writel_relaxed(val, reg); 584 584 + 585 585 + /* read back register to make sure that register writes completed */ 586 586 + readl_relaxed(reg); 587 587 + } 588 588 + 589 589 + /** 574 590 * nvec_interrupt - Interrupt handler 575 591 * @irq: The IRQ 576 592 * @dev: The nvec device ··· 620 604 if ((status & RNW) == 0) { 621 605 received = readl(nvec->base + I2C_SL_RCVD); 622 606 if (status & RCVD) 623 623 - writel(0, nvec->base + I2C_SL_RCVD); 607 607 + tegra_i2c_writel(0, nvec->base + I2C_SL_RCVD); 624 608 } 625 609 626 610 if (status == (I2C_SL_IRQ | RCVD)) ··· 712 696 713 697 /* Send data if requested, but not on end of transmission */ 714 698 if ((status & (RNW | END_TRANS)) == RNW) 715 715 - writel(to_send, nvec->base + I2C_SL_RCVD); 699 699 + tegra_i2c_writel(to_send, nvec->base + I2C_SL_RCVD); 716 700 717 701 /* If we have send the first byte */ 718 702 if (status == (I2C_SL_IRQ | RNW | RCVD)) ··· 729 713 status & RCVD ? " RCVD" : "", 730 714 status & RNW ? " RNW" : ""); 731 715 732 732 - /* 733 733 - * TODO: replace the udelay with a read back after each writel above 734 734 - * in order to work around a hardware issue, see i2c-tegra.c 735 735 - * 736 736 - * Unfortunately, this change causes an initialisation issue with the 737 737 - * touchpad, which needs to be fixed first. 738 738 - */ 739 739 - udelay(100); 740 740 - 741 716 return IRQ_HANDLED; 742 717 } 743 718 ··· 744 737 745 738 val = I2C_CNFG_NEW_MASTER_SFM | I2C_CNFG_PACKET_MODE_EN | 746 739 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); 747 747 - writel(val, nvec->base + I2C_CNFG); 740 740 + tegra_i2c_writel(val, nvec->base + I2C_CNFG); 748 741 749 742 clk_set_rate(nvec->i2c_clk, 8 * 80000); 750 743 751 751 - writel(I2C_SL_NEWSL, nvec->base + I2C_SL_CNFG); 752 752 - writel(0x1E, nvec->base + I2C_SL_DELAY_COUNT); 744 744 + tegra_i2c_writel(I2C_SL_NEWSL, nvec->base + I2C_SL_CNFG); 745 745 + tegra_i2c_writel(0x1E, nvec->base + I2C_SL_DELAY_COUNT); 753 746 754 754 - writel(nvec->i2c_addr >> 1, nvec->base + I2C_SL_ADDR1); 755 755 - writel(0, nvec->base + I2C_SL_ADDR2); 747 747 + tegra_i2c_writel(nvec->i2c_addr >> 1, nvec->base + I2C_SL_ADDR1); 748 748 + tegra_i2c_writel(0, nvec->base + I2C_SL_ADDR2); 756 749 757 750 enable_irq(nvec->irq); 758 751 } ··· 761 754 static void nvec_disable_i2c_slave(struct nvec_chip *nvec) 762 755 { 763 756 disable_irq(nvec->irq); 764 764 - writel(I2C_SL_NEWSL | I2C_SL_NACK, nvec->base + I2C_SL_CNFG); 757 757 + tegra_i2c_writel(I2C_SL_NEWSL | I2C_SL_NACK, nvec->base + I2C_SL_CNFG); 765 758 clk_disable_unprepare(nvec->i2c_clk); 766 759 } 767 760 #endif

-9

drivers/staging/rtl8192e/rtl8192e/r8190P_def.h

reviewed

··· 88 88 VERSION_8190_BE 89 89 }; 90 90 91 91 - #define IC_VersionCut_C 0x2 92 91 #define IC_VersionCut_D 0x3 93 93 - #define IC_VersionCut_E 0x4 94 92 95 93 enum rf_optype { 96 94 RF_OP_By_SW_3wire = 0, ··· 134 136 u32 Retry_Limit:4; 135 137 u32 Reserved2:1; 136 138 u32 PacketID:13; 137 137 - }; 138 138 - 139 139 - struct phy_ofdm_rx_status_rxsc_sgien_exintfflag { 140 140 - u8 reserved:4; 141 141 - u8 rxsc:2; 142 142 - u8 sgi_en:1; 143 143 - u8 ex_intf_flag:1; 144 139 }; 145 140 146 141 struct phy_sts_ofdm_819xpci {

+10 -11

drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c

reviewed

··· 859 859 { 860 860 u8 tmp_Short; 861 861 862 862 - tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) : 863 863 - ((tcb_desc->bUseShortPreamble) ? 1 : 0); 862 862 + tmp_Short = (TxHT == 1) ? ((tcb_desc->use_short_gi) ? 1 : 0) : 863 863 + ((tcb_desc->use_short_preamble) ? 1 : 0); 864 864 if (TxHT == 1 && TxRate != DESC90_RATEMCS15) 865 865 tmp_Short = 0; 866 866 ··· 892 892 pTxFwInfo->RxAMD = 0; 893 893 } 894 894 895 895 - pTxFwInfo->RtsEnable = (cb_desc->bRTSEnable) ? 1 : 0; 896 896 - pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0; 897 897 - pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0; 895 895 + pTxFwInfo->RtsEnable = (cb_desc->rts_enable) ? 1 : 0; 896 896 + pTxFwInfo->CtsEnable = (cb_desc->cts_enable) ? 1 : 0; 897 897 + pTxFwInfo->RtsSTBC = (cb_desc->rtsstbc) ? 1 : 0; 898 898 pTxFwInfo->RtsHT = (cb_desc->rts_rate & 0x80) ? 1 : 0; 899 899 pTxFwInfo->RtsRate = _rtl92e_rate_mgn_to_hw(cb_desc->rts_rate); 900 900 pTxFwInfo->RtsBandwidth = 0; 901 901 pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC; 902 902 pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ? 903 903 (cb_desc->rts_use_short_preamble ? 1 : 0) : 904 904 - (cb_desc->bRTSUseShortGI ? 1 : 0); 904 904 + (cb_desc->rts_use_short_gi ? 1 : 0); 905 905 if (priv->current_chnl_bw == HT_CHANNEL_WIDTH_20_40) { 906 906 - if (cb_desc->bPacketBW) { 906 906 + if (cb_desc->packet_bw) { 907 907 pTxFwInfo->TxBandwidth = 1; 908 908 pTxFwInfo->TxSubCarrier = 0; 909 909 } else { ··· 934 934 935 935 pdesc->NoEnc = 1; 936 936 pdesc->SecType = 0x0; 937 937 - if (cb_desc->bHwSec) { 937 937 + if (cb_desc->hw_sec) { 938 938 static u8 tmp; 939 939 940 940 if (!tmp) ··· 1640 1640 if (stats->Length < 24) 1641 1641 stats->bHwError |= 1; 1642 1642 1643 1643 - if (stats->bHwError) { 1643 1643 + if (stats->bHwError) 1644 1644 return false; 1645 1645 - } 1646 1645 1647 1646 stats->RxDrvInfoSize = pdesc->RxDrvInfoSize; 1648 1647 stats->RxBufShift = (pdesc->Shift) & 0x03; 1649 1649 - stats->Decrypted = !pdesc->SWDec; 1648 1648 + stats->decrypted = !pdesc->SWDec; 1650 1649 1651 1650 pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift); 1652 1651

+1

drivers/staging/rtl8192e/rtl8192e/rtl_cam.h

reviewed

··· 11 11 #define _RTL_CAM_H 12 12 13 13 #include <linux/types.h> 14 14 + 14 15 struct net_device; 15 16 16 17 void rtl92e_cam_reset(struct net_device *dev);

+3 -3

drivers/staging/rtl8192e/rtl8192e/rtl_core.c

reviewed

··· 951 951 return; 952 952 953 953 if (priv->rtllib->link_state >= MAC80211_LINKED) { 954 954 - if (priv->rtllib->CntAfterLink < 2) 955 955 - priv->rtllib->CntAfterLink++; 954 954 + if (priv->rtllib->cnt_after_link < 2) 955 955 + priv->rtllib->cnt_after_link++; 956 956 } else { 957 957 - priv->rtllib->CntAfterLink = 0; 957 957 + priv->rtllib->cnt_after_link = 0; 958 958 } 959 959 960 960 rtl92e_dm_watchdog(dev);

+85 -91

drivers/staging/rtl8192e/rtl8192e/rtl_dm.c

reviewed

··· 377 377 378 378 priv->rtllib->bandwidth_auto_switch.threshold_20Mhzto40Mhz = BW_AUTO_SWITCH_LOW_HIGH; 379 379 priv->rtllib->bandwidth_auto_switch.threshold_40Mhzto20Mhz = BW_AUTO_SWITCH_HIGH_LOW; 380 380 - priv->rtllib->bandwidth_auto_switch.bforced_tx20Mhz = false; 380 380 + priv->rtllib->bandwidth_auto_switch.forced_tx_20MHz = false; 381 381 priv->rtllib->bandwidth_auto_switch.bautoswitch_enable = false; 382 382 } 383 383 ··· 388 388 if (priv->current_chnl_bw == HT_CHANNEL_WIDTH_20 || 389 389 !priv->rtllib->bandwidth_auto_switch.bautoswitch_enable) 390 390 return; 391 391 - if (!priv->rtllib->bandwidth_auto_switch.bforced_tx20Mhz) { 391 391 + if (!priv->rtllib->bandwidth_auto_switch.forced_tx_20MHz) { 392 392 if (priv->undecorated_smoothed_pwdb <= 393 393 priv->rtllib->bandwidth_auto_switch.threshold_40Mhzto20Mhz) 394 394 - priv->rtllib->bandwidth_auto_switch.bforced_tx20Mhz = true; 394 394 + priv->rtllib->bandwidth_auto_switch.forced_tx_20MHz = true; 395 395 } else { 396 396 if (priv->undecorated_smoothed_pwdb >= 397 397 priv->rtllib->bandwidth_auto_switch.threshold_20Mhzto40Mhz) 398 398 - priv->rtllib->bandwidth_auto_switch.bforced_tx20Mhz = false; 398 398 + priv->rtllib->bandwidth_auto_switch.forced_tx_20MHz = false; 399 399 } 400 400 } 401 401 ··· 1335 1335 for (i = 0; i < RF90_PATH_MAX; i++) { 1336 1336 dm_rx_path_sel_table.rf_rssi[i] = priv->stats.rx_rssi_percentage[i]; 1337 1337 1338 1338 - if (priv->brfpath_rxenable[i]) { 1339 1339 - rf_num++; 1340 1340 - cur_rf_rssi = dm_rx_path_sel_table.rf_rssi[i]; 1338 1338 + if (!priv->brfpath_rxenable[i]) 1339 1339 + continue; 1341 1340 1342 1342 - if (rf_num == 1) { 1343 1343 - max_rssi_index = min_rssi_index = sec_rssi_index = i; 1344 1344 - tmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi; 1345 1345 - } else if (rf_num == 2) { 1346 1346 - if (cur_rf_rssi >= tmp_max_rssi) { 1347 1347 - tmp_max_rssi = cur_rf_rssi; 1348 1348 - max_rssi_index = i; 1349 1349 - } else { 1350 1350 - tmp_sec_rssi = tmp_min_rssi = cur_rf_rssi; 1351 1351 - sec_rssi_index = min_rssi_index = i; 1352 1352 - } 1341 1341 + rf_num++; 1342 1342 + cur_rf_rssi = dm_rx_path_sel_table.rf_rssi[i]; 1343 1343 + 1344 1344 + if (rf_num == 1) { 1345 1345 + max_rssi_index = min_rssi_index = sec_rssi_index = i; 1346 1346 + tmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi; 1347 1347 + } else if (rf_num == 2) { 1348 1348 + if (cur_rf_rssi >= tmp_max_rssi) { 1349 1349 + tmp_max_rssi = cur_rf_rssi; 1350 1350 + max_rssi_index = i; 1353 1351 } else { 1354 1354 - if (cur_rf_rssi > tmp_max_rssi) { 1355 1355 - tmp_sec_rssi = tmp_max_rssi; 1356 1356 - sec_rssi_index = max_rssi_index; 1357 1357 - tmp_max_rssi = cur_rf_rssi; 1358 1358 - max_rssi_index = i; 1359 1359 - } else if (cur_rf_rssi == tmp_max_rssi) { 1352 1352 + tmp_sec_rssi = tmp_min_rssi = cur_rf_rssi; 1353 1353 + sec_rssi_index = min_rssi_index = i; 1354 1354 + } 1355 1355 + } else { 1356 1356 + if (cur_rf_rssi > tmp_max_rssi) { 1357 1357 + tmp_sec_rssi = tmp_max_rssi; 1358 1358 + sec_rssi_index = max_rssi_index; 1359 1359 + tmp_max_rssi = cur_rf_rssi; 1360 1360 + max_rssi_index = i; 1361 1361 + } else if (cur_rf_rssi == tmp_max_rssi) { 1362 1362 + tmp_sec_rssi = cur_rf_rssi; 1363 1363 + sec_rssi_index = i; 1364 1364 + } else if ((cur_rf_rssi < tmp_max_rssi) && 1365 1365 + (cur_rf_rssi > tmp_sec_rssi)) { 1366 1366 + tmp_sec_rssi = cur_rf_rssi; 1367 1367 + sec_rssi_index = i; 1368 1368 + } else if (cur_rf_rssi == tmp_sec_rssi) { 1369 1369 + if (tmp_sec_rssi == tmp_min_rssi) { 1360 1370 tmp_sec_rssi = cur_rf_rssi; 1361 1371 sec_rssi_index = i; 1362 1362 - } else if ((cur_rf_rssi < tmp_max_rssi) && 1363 1363 - (cur_rf_rssi > tmp_sec_rssi)) { 1364 1364 - tmp_sec_rssi = cur_rf_rssi; 1365 1365 - sec_rssi_index = i; 1366 1366 - } else if (cur_rf_rssi == tmp_sec_rssi) { 1367 1367 - if (tmp_sec_rssi == tmp_min_rssi) { 1368 1368 - tmp_sec_rssi = cur_rf_rssi; 1369 1369 - sec_rssi_index = i; 1370 1370 - } 1371 1371 - } else if ((cur_rf_rssi < tmp_sec_rssi) && 1372 1372 - (cur_rf_rssi > tmp_min_rssi)) { 1373 1373 - ; 1374 1374 - } else if (cur_rf_rssi == tmp_min_rssi) { 1375 1375 - if (tmp_sec_rssi == tmp_min_rssi) { 1376 1376 - tmp_min_rssi = cur_rf_rssi; 1377 1377 - min_rssi_index = i; 1378 1378 - } 1379 1379 - } else if (cur_rf_rssi < tmp_min_rssi) { 1372 1372 + } 1373 1373 + } else if ((cur_rf_rssi < tmp_sec_rssi) && 1374 1374 + (cur_rf_rssi > tmp_min_rssi)) { 1375 1375 + ; 1376 1376 + } else if (cur_rf_rssi == tmp_min_rssi) { 1377 1377 + if (tmp_sec_rssi == tmp_min_rssi) { 1380 1378 tmp_min_rssi = cur_rf_rssi; 1381 1379 min_rssi_index = i; 1382 1380 } 1381 1381 + } else if (cur_rf_rssi < tmp_min_rssi) { 1382 1382 + tmp_min_rssi = cur_rf_rssi; 1383 1383 + min_rssi_index = i; 1383 1384 } 1384 1385 } 1385 1386 } ··· 1388 1387 rf_num = 0; 1389 1388 if (dm_rx_path_sel_table.cck_method == CCK_Rx_Version_2) { 1390 1389 for (i = 0; i < RF90_PATH_MAX; i++) { 1391 1391 - if (priv->brfpath_rxenable[i]) { 1392 1392 - rf_num++; 1393 1393 - cur_cck_pwdb = 1394 1394 - dm_rx_path_sel_table.cck_pwdb_sta[i]; 1390 1390 + if (!priv->brfpath_rxenable[i]) 1391 1391 + continue; 1395 1392 1396 1396 - if (rf_num == 1) { 1397 1397 - cck_rx_ver2_max_index = i; 1398 1398 - cck_rx_ver2_sec_index = i; 1393 1393 + rf_num++; 1394 1394 + cur_cck_pwdb = dm_rx_path_sel_table.cck_pwdb_sta[i]; 1395 1395 + 1396 1396 + if (rf_num == 1) { 1397 1397 + cck_rx_ver2_max_index = i; 1398 1398 + cck_rx_ver2_sec_index = i; 1399 1399 + tmp_cck_max_pwdb = cur_cck_pwdb; 1400 1400 + tmp_cck_min_pwdb = cur_cck_pwdb; 1401 1401 + tmp_cck_sec_pwdb = cur_cck_pwdb; 1402 1402 + } else if (rf_num == 2) { 1403 1403 + if (cur_cck_pwdb >= tmp_cck_max_pwdb) { 1399 1404 tmp_cck_max_pwdb = cur_cck_pwdb; 1400 1400 - tmp_cck_min_pwdb = cur_cck_pwdb; 1401 1401 - tmp_cck_sec_pwdb = cur_cck_pwdb; 1402 1402 - } else if (rf_num == 2) { 1403 1403 - if (cur_cck_pwdb >= tmp_cck_max_pwdb) { 1404 1404 - tmp_cck_max_pwdb = cur_cck_pwdb; 1405 1405 - cck_rx_ver2_max_index = i; 1406 1406 - } else { 1407 1407 - tmp_cck_sec_pwdb = cur_cck_pwdb; 1408 1408 - tmp_cck_min_pwdb = cur_cck_pwdb; 1409 1409 - cck_rx_ver2_sec_index = i; 1410 1410 - } 1405 1405 + cck_rx_ver2_max_index = i; 1411 1406 } else { 1412 1412 - if (cur_cck_pwdb > tmp_cck_max_pwdb) { 1413 1413 - tmp_cck_sec_pwdb = 1414 1414 - tmp_cck_max_pwdb; 1415 1415 - cck_rx_ver2_sec_index = 1416 1416 - cck_rx_ver2_max_index; 1417 1417 - tmp_cck_max_pwdb = cur_cck_pwdb; 1418 1418 - cck_rx_ver2_max_index = i; 1419 1419 - } else if (cur_cck_pwdb == 1420 1420 - tmp_cck_max_pwdb) { 1407 1407 + tmp_cck_sec_pwdb = cur_cck_pwdb; 1408 1408 + tmp_cck_min_pwdb = cur_cck_pwdb; 1409 1409 + cck_rx_ver2_sec_index = i; 1410 1410 + } 1411 1411 + } else { 1412 1412 + if (cur_cck_pwdb > tmp_cck_max_pwdb) { 1413 1413 + tmp_cck_sec_pwdb = tmp_cck_max_pwdb; 1414 1414 + cck_rx_ver2_sec_index = cck_rx_ver2_max_index; 1415 1415 + tmp_cck_max_pwdb = cur_cck_pwdb; 1416 1416 + cck_rx_ver2_max_index = i; 1417 1417 + } else if (cur_cck_pwdb == tmp_cck_max_pwdb) { 1418 1418 + tmp_cck_sec_pwdb = cur_cck_pwdb; 1419 1419 + cck_rx_ver2_sec_index = i; 1420 1420 + } else if (PWDB_IN_RANGE) { 1421 1421 + tmp_cck_sec_pwdb = cur_cck_pwdb; 1422 1422 + cck_rx_ver2_sec_index = i; 1423 1423 + } else if (cur_cck_pwdb == tmp_cck_sec_pwdb) { 1424 1424 + if (tmp_cck_sec_pwdb == tmp_cck_min_pwdb) { 1421 1425 tmp_cck_sec_pwdb = cur_cck_pwdb; 1422 1426 cck_rx_ver2_sec_index = i; 1423 1423 - } else if (PWDB_IN_RANGE) { 1424 1424 - tmp_cck_sec_pwdb = cur_cck_pwdb; 1425 1425 - cck_rx_ver2_sec_index = i; 1426 1426 - } else if (cur_cck_pwdb == 1427 1427 - tmp_cck_sec_pwdb) { 1428 1428 - if (tmp_cck_sec_pwdb == 1429 1429 - tmp_cck_min_pwdb) { 1430 1430 - tmp_cck_sec_pwdb = 1431 1431 - cur_cck_pwdb; 1432 1432 - cck_rx_ver2_sec_index = 1433 1433 - i; 1434 1434 - } 1435 1435 - } else if ((cur_cck_pwdb < tmp_cck_sec_pwdb) && 1436 1436 - (cur_cck_pwdb > tmp_cck_min_pwdb)) { 1437 1437 - ; 1438 1438 - } else if (cur_cck_pwdb == tmp_cck_min_pwdb) { 1439 1439 - if (tmp_cck_sec_pwdb == tmp_cck_min_pwdb) 1440 1440 - tmp_cck_min_pwdb = cur_cck_pwdb; 1441 1441 - } else if (cur_cck_pwdb < tmp_cck_min_pwdb) { 1442 1442 - tmp_cck_min_pwdb = cur_cck_pwdb; 1443 1427 } 1428 1428 + } else if ((cur_cck_pwdb < tmp_cck_sec_pwdb) && 1429 1429 + (cur_cck_pwdb > tmp_cck_min_pwdb)) { 1430 1430 + ; 1431 1431 + } else if (cur_cck_pwdb == tmp_cck_min_pwdb) { 1432 1432 + if (tmp_cck_sec_pwdb == tmp_cck_min_pwdb) 1433 1433 + tmp_cck_min_pwdb = cur_cck_pwdb; 1434 1434 + } else if (cur_cck_pwdb < tmp_cck_min_pwdb) { 1435 1435 + tmp_cck_min_pwdb = cur_cck_pwdb; 1444 1436 } 1445 1437 } 1446 1438 } ··· 1752 1758 1753 1759 if (priv->rtllib->link_state == MAC80211_LINKED) { 1754 1760 if (priv->undecorated_smoothed_pwdb <= 1755 1755 - RegC38_TH) { 1761 1761 + REG_C38_TH) { 1756 1762 if (reg_c38_State != 1757 1763 RegC38_NonFsync_Other_AP) { 1758 1764 rtl92e_writeb(dev, ··· 1763 1769 RegC38_NonFsync_Other_AP; 1764 1770 } 1765 1771 } else if (priv->undecorated_smoothed_pwdb >= 1766 1766 - (RegC38_TH + 5)) { 1772 1772 + (REG_C38_TH + 5)) { 1767 1773 if (reg_c38_State) { 1768 1774 rtl92e_writeb(dev, 1769 1775 rOFDM0_RxDetector3,

+1 -5

drivers/staging/rtl8192e/rtl8192e/rtl_dm.h

reviewed

··· 33 33 #define RATE_ADAPTIVE_TH_LOW_40M 10 34 34 #define VERY_LOW_RSSI 15 35 35 36 36 - #define WA_IOT_TH_VAL 25 37 37 - 38 36 #define E_FOR_TX_POWER_TRACK 300 39 37 #define TX_POWER_NEAR_FIELD_THRESH_HIGH 68 40 38 #define TX_POWER_NEAR_FIELD_THRESH_LOW 62 ··· 42 44 #define CURRENT_TX_RATE_REG 0x1e0 43 45 #define INITIAL_TX_RATE_REG 0x1e1 44 46 #define TX_RETRY_COUNT_REG 0x1ac 45 45 - #define RegC38_TH 20 47 47 + #define REG_C38_TH 20 46 48 47 49 /*--------------------------Define Parameters-------------------------------*/ 48 50 ··· 133 135 extern const u32 dm_tx_bb_gain[TX_BB_GAIN_TABLE_LEN]; 134 136 extern const u8 dm_cck_tx_bb_gain[CCK_TX_BB_GAIN_TABLE_LEN][8]; 135 137 extern const u8 dm_cck_tx_bb_gain_ch14[CCK_TX_BB_GAIN_TABLE_LEN][8]; 136 136 - /* Maps table index to iq amplify gain (dB, 12 to -24dB) */ 137 137 - #define dm_tx_bb_gain_idx_to_amplify(idx) (-idx + 12) 138 138 139 139 /*------------------------Export global variable----------------------------*/ 140 140

+1

drivers/staging/rtl8192e/rtl8192e/rtl_pci.h

reviewed

··· 14 14 #include <linux/pci.h> 15 15 16 16 struct net_device; 17 17 + 17 18 bool rtl92e_check_adapter(struct pci_dev *pdev, struct net_device *dev); 18 19 19 20 #endif

+1 -1

drivers/staging/rtl8192e/rtl8192e/rtl_wx.c

reviewed

··· 241 241 (ieee->link_state <= RTLLIB_ASSOCIATING_AUTHENTICATED)) 242 242 return 0; 243 243 if ((priv->rtllib->link_state == MAC80211_LINKED) && 244 244 - (priv->rtllib->CntAfterLink < 2)) 244 244 + (priv->rtllib->cnt_after_link < 2)) 245 245 return 0; 246 246 } 247 247

+2 -2

drivers/staging/rtl8192e/rtl819x_HTProc.c

reviewed

··· 496 496 ieee->HTHighestOperaRate = ht_get_highest_mcs_rate(ieee, 497 497 ieee->dot11ht_oper_rate_set, 498 498 pMcsFilter); 499 499 - ieee->HTCurrentOperaRate = ieee->HTHighestOperaRate; 499 499 + ieee->ht_curr_op_rate = ieee->HTHighestOperaRate; 500 500 501 501 ht_info->current_op_mode = pPeerHTInfo->opt_mode; 502 502 } ··· 625 625 u8 ht_c_check(struct rtllib_device *ieee, u8 *pFrame) 626 626 { 627 627 if (ieee->ht_info->current_ht_support) { 628 628 - if ((IsQoSDataFrame(pFrame) && frame_order(pFrame)) == 1) { 628 628 + if ((is_qos_data_frame(pFrame) && frame_order(pFrame)) == 1) { 629 629 netdev_dbg(ieee->dev, "HT CONTROL FILED EXIST!!\n"); 630 630 return true; 631 631 }

+5 -5

drivers/staging/rtl8192e/rtl819x_TSProc.c

reviewed

··· 18 18 19 19 unsigned long flags = 0; 20 20 u8 index = 0; 21 21 - bool bPktInBuf = false; 21 21 + bool pkt_in_buf = false; 22 22 23 23 spin_lock_irqsave(&(ieee->reorder_spinlock), flags); 24 24 if (ts->rx_timeout_indicate_seq != 0xffff) { ··· 50 50 list_add_tail(&pReorderEntry->list, 51 51 &ieee->RxReorder_Unused_List); 52 52 } else { 53 53 - bPktInBuf = true; 53 53 + pkt_in_buf = true; 54 54 break; 55 55 } 56 56 } ··· 68 68 return; 69 69 } 70 70 rtllib_indicate_packets(ieee, ieee->stats_IndicateArray, index); 71 71 - bPktInBuf = false; 71 71 + pkt_in_buf = false; 72 72 } 73 73 74 74 - if (bPktInBuf && (ts->rx_timeout_indicate_seq == 0xffff)) { 74 74 + if (pkt_in_buf && (ts->rx_timeout_indicate_seq == 0xffff)) { 75 75 ts->rx_timeout_indicate_seq = ts->rx_indicate_seq; 76 76 mod_timer(&ts->rx_pkt_pending_timer, jiffies + 77 77 msecs_to_jiffies(ieee->ht_info->rx_reorder_pending_time) ··· 431 431 } 432 432 } 433 433 434 434 - void TsStartAddBaProcess(struct rtllib_device *ieee, struct tx_ts_record *pTxTS) 434 434 + void rtllib_ts_start_add_ba_process(struct rtllib_device *ieee, struct tx_ts_record *pTxTS) 435 435 { 436 436 if (pTxTS->add_ba_req_in_progress == false) { 437 437 pTxTS->add_ba_req_in_progress = true;

+32 -32

drivers/staging/rtl8192e/rtllib.h

reviewed

··· 105 105 u8 bCmdOrInit:1; 106 106 u8 tx_dis_rate_fallback:1; 107 107 u8 tx_use_drv_assinged_rate:1; 108 108 - u8 bHwSec:1; 108 108 + u8 hw_sec:1; 109 109 110 110 u8 nStuckCount; 111 111 112 112 /* Tx Firmware Related flags (10-11)*/ 113 113 - u8 bCTSEnable:1; 114 114 - u8 bRTSEnable:1; 115 115 - u8 bUseShortGI:1; 116 116 - u8 bUseShortPreamble:1; 113 113 + u8 cts_enable:1; 114 114 + u8 rts_enable:1; 115 115 + u8 use_short_gi:1; 116 116 + u8 use_short_preamble:1; 117 117 u8 tx_enable_fw_calc_dur:1; 118 118 u8 ampdu_enable:1; 119 119 - u8 bRTSSTBC:1; 119 119 + u8 rtsstbc:1; 120 120 u8 RTSSC:1; 121 121 122 122 - u8 bRTSBW:1; 123 123 - u8 bPacketBW:1; 122 122 + u8 rts_bw:1; 123 123 + u8 packet_bw:1; 124 124 u8 rts_use_short_preamble:1; 125 125 - u8 bRTSUseShortGI:1; 125 125 + u8 rts_use_short_gi:1; 126 126 u8 multicast:1; 127 127 - u8 bBroadcast:1; 127 127 + u8 broadcast:1; 128 128 u8 drv_agg_enable:1; 129 129 u8 reserved2:1; 130 130 ··· 338 338 #define RTLLIB_QCTL_TID 0x000F 339 339 340 340 #define FC_QOS_BIT BIT(7) 341 341 - #define IsDataFrame(pdu) (((pdu[0] & 0x0C) == 0x08) ? true : false) 342 342 - #define IsLegacyDataFrame(pdu) (IsDataFrame(pdu) && (!(pdu[0]&FC_QOS_BIT))) 343 343 - #define IsQoSDataFrame(pframe) \ 341 341 + #define is_data_frame(pdu) (((pdu[0] & 0x0C) == 0x08) ? true : false) 342 342 + #define is_legacy_data_frame(pdu) (is_data_frame(pdu) && (!(pdu[0]&FC_QOS_BIT))) 343 343 + #define is_qos_data_frame(pframe) \ 344 344 ((*(u16 *)pframe&(IEEE80211_STYPE_QOS_DATA|RTLLIB_FTYPE_DATA)) == \ 345 345 (IEEE80211_STYPE_QOS_DATA|RTLLIB_FTYPE_DATA)) 346 346 #define frame_order(pframe) (*(u16 *)pframe&IEEE80211_FCTL_ORDER) ··· 481 481 u16 bHwError:1; 482 482 u16 bCRC:1; 483 483 u16 bICV:1; 484 484 - u16 Decrypted:1; 484 484 + u16 decrypted:1; 485 485 u32 time_stamp_low; 486 486 u32 time_stamp_high; 487 487 ··· 489 489 u8 RxBufShift; 490 490 bool bIsAMPDU; 491 491 bool bFirstMPDU; 492 492 - bool bContainHTC; 492 492 + bool contain_htc; 493 493 u32 RxPWDBAll; 494 494 u8 RxMIMOSignalStrength[4]; 495 495 s8 RxMIMOSignalQuality[2]; ··· 728 728 #define QOS_VERSION_1 1 729 729 730 730 struct rtllib_qos_information_element { 731 731 - u8 elementID; 731 731 + u8 element_id; 732 732 u8 length; 733 733 u8 qui[QOS_OUI_LEN]; 734 734 u8 qui_type; ··· 799 799 eap_types[type]; 800 800 } 801 801 802 802 - static inline u8 Frame_QoSTID(u8 *buf) 802 802 + static inline u8 frame_qos_tid(u8 *buf) 803 803 { 804 804 struct ieee80211_hdr_3addr *hdr; 805 805 u16 fc; ··· 910 910 u8 hidden_ssid_len; 911 911 struct rtllib_qos_data qos_data; 912 912 913 913 - bool bWithAironetIE; 913 913 + bool with_aironet_ie; 914 914 bool ckip_supported; 915 915 bool ccx_rm_enable; 916 916 - u8 CcxRmState[2]; 917 917 - bool bMBssidValid; 918 918 - u8 MBssidMask; 919 919 - u8 MBssid[ETH_ALEN]; 920 920 - bool bWithCcxVerNum; 916 916 + u8 ccx_rm_state[2]; 917 917 + bool mb_ssid_valid; 918 918 + u8 mb_ssid_mask; 919 919 + u8 mb_ssid[ETH_ALEN]; 920 920 + bool with_ccx_ver_num; 921 921 u8 bss_ccx_ver_number; 922 922 /* These are network statistics */ 923 923 struct rtllib_rx_stats stats; ··· 949 949 u8 wmm_info; 950 950 struct rtllib_wmm_ac_param wmm_param[4]; 951 951 u8 turbo_enable; 952 952 - u16 CountryIeLen; 953 953 - u8 CountryIeBuf[MAX_IE_LEN]; 952 952 + u16 country_ie_len; 953 953 + u8 country_ie_buf[MAX_IE_LEN]; 954 954 struct bss_ht bssht; 955 955 bool broadcom_cap_exist; 956 956 bool realtek_cap_exit; ··· 1018 1018 struct bandwidth_autoswitch { 1019 1019 long threshold_20Mhzto40Mhz; 1020 1020 long threshold_40Mhzto20Mhz; 1021 1021 - bool bforced_tx20Mhz; 1021 1021 + bool forced_tx_20MHz; 1022 1022 bool bautoswitch_enable; 1023 1023 }; 1024 1024 ··· 1168 1168 bool disable_mgnt_queue; 1169 1169 1170 1170 unsigned long status; 1171 1171 - u8 CntAfterLink; 1171 1171 + u8 cnt_after_link; 1172 1172 1173 1173 enum rt_op_mode op_mode; 1174 1174 ··· 1198 1198 u8 reg_dot11tx_ht_oper_rate_set[16]; 1199 1199 u8 dot11ht_oper_rate_set[16]; 1200 1200 u8 reg_ht_supp_rate_set[16]; 1201 1201 - u8 HTCurrentOperaRate; 1201 1201 + u8 ht_curr_op_rate; 1202 1202 u8 HTHighestOperaRate; 1203 1203 u8 tx_dis_rate_fallback; 1204 1204 u8 tx_use_drv_assinged_rate; ··· 1407 1407 struct work_struct wx_sync_scan_wq; 1408 1408 1409 1409 union { 1410 1410 - struct rtllib_rxb *RfdArray[REORDER_WIN_SIZE]; 1410 1410 + struct rtllib_rxb *rfd_array[REORDER_WIN_SIZE]; 1411 1411 struct rtllib_rxb *stats_IndicateArray[REORDER_WIN_SIZE]; 1412 1412 - struct rtllib_rxb *prxbIndicateArray[REORDER_WIN_SIZE]; 1412 1412 + struct rtllib_rxb *prxb_indicate_array[REORDER_WIN_SIZE]; 1413 1413 struct { 1414 1414 struct sw_chnl_cmd PreCommonCmd[MAX_PRECMD_CNT]; 1415 1415 struct sw_chnl_cmd PostCommonCmd[MAX_POSTCMD_CNT]; ··· 1770 1770 bool rtllib_get_ts(struct rtllib_device *ieee, struct ts_common_info **ppTS, u8 *addr, 1771 1771 u8 TID, enum tr_select tx_rx_select, bool bAddNewTs); 1772 1772 void rtllib_ts_init(struct rtllib_device *ieee); 1773 1773 - void TsStartAddBaProcess(struct rtllib_device *ieee, 1773 1773 + void rtllib_ts_start_add_ba_process(struct rtllib_device *ieee, 1774 1774 struct tx_ts_record *pTxTS); 1775 1775 void remove_peer_ts(struct rtllib_device *ieee, u8 *addr); 1776 1776 void remove_all_ts(struct rtllib_device *ieee); ··· 1803 1803 struct rtllib_rx_stats *stats); 1804 1804 1805 1805 void rtllib_indicate_packets(struct rtllib_device *ieee, 1806 1806 - struct rtllib_rxb **prxbIndicateArray, u8 index); 1806 1806 + struct rtllib_rxb **prxb_indicate_array, u8 index); 1807 1807 #define RT_ASOC_RETRY_LIMIT 5 1808 1808 u8 mgnt_query_tx_rate_exclude_cck_rates(struct rtllib_device *ieee); 1809 1809

+3 -2

drivers/staging/rtl8192e/rtllib_crypt_ccmp.c

reviewed

··· 182 182 *pos++ = key->tx_pn[0]; 183 183 184 184 hdr = (struct ieee80211_hdr *)skb->data; 185 185 - if (!tcb_desc->bHwSec) { 185 185 + if (!tcb_desc->hw_sec) { 186 186 struct aead_request *req; 187 187 struct scatterlist sg[2]; 188 188 u8 *aad = key->tx_aad; ··· 265 265 key->dot11rsna_stats_ccmp_replays++; 266 266 return -4; 267 267 } 268 268 - if (!tcb_desc->bHwSec) { 268 268 + if (!tcb_desc->hw_sec) { 269 269 size_t data_len = skb->len - hdr_len - CCMP_HDR_LEN; 270 270 struct aead_request *req; 271 271 struct scatterlist sg[2]; ··· 407 407 module_init(rtllib_crypto_ccmp_init); 408 408 module_exit(rtllib_crypto_ccmp_exit); 409 409 410 410 + MODULE_DESCRIPTION("Support module for rtllib CCMP crypto"); 410 411 MODULE_LICENSE("GPL");

+6 -5

drivers/staging/rtl8192e/rtllib_crypt_tkip.c

reviewed

··· 268 268 269 269 hdr = (struct ieee80211_hdr *)skb->data; 270 270 271 271 - if (!tcb_desc->bHwSec) { 271 271 + if (!tcb_desc->hw_sec) { 272 272 if (!tkey->tx_phase1_done) { 273 273 tkip_mixing_phase1(tkey->tx_ttak, tkey->key, hdr->addr2, 274 274 tkey->tx_iv32); ··· 285 285 memmove(pos, pos + 8, hdr_len); 286 286 pos += hdr_len; 287 287 288 288 - if (tcb_desc->bHwSec) { 288 288 + if (tcb_desc->hw_sec) { 289 289 *pos++ = Hi8(tkey->tx_iv16); 290 290 *pos++ = (Hi8(tkey->tx_iv16) | 0x20) & 0x7F; 291 291 *pos++ = Lo8(tkey->tx_iv16); ··· 301 301 *pos++ = (tkey->tx_iv32 >> 16) & 0xff; 302 302 *pos++ = (tkey->tx_iv32 >> 24) & 0xff; 303 303 304 304 - if (!tcb_desc->bHwSec) { 304 304 + if (!tcb_desc->hw_sec) { 305 305 icv = skb_put(skb, 4); 306 306 crc = ~crc32_le(~0, pos, len); 307 307 icv[0] = crc; ··· 319 319 tkey->tx_iv32++; 320 320 } 321 321 322 322 - if (!tcb_desc->bHwSec) 322 322 + if (!tcb_desc->hw_sec) 323 323 return ret; 324 324 return 0; 325 325 } ··· 371 371 iv32 = pos[4] | (pos[5] << 8) | (pos[6] << 16) | (pos[7] << 24); 372 372 pos += 8; 373 373 374 374 - if (!tcb_desc->bHwSec || (skb->cb[0] == 1)) { 374 374 + if (!tcb_desc->hw_sec || (skb->cb[0] == 1)) { 375 375 if ((iv32 < tkey->rx_iv32 || 376 376 (iv32 == tkey->rx_iv32 && iv16 <= tkey->rx_iv16)) && 377 377 tkey->initialized) { ··· 708 708 module_init(rtllib_crypto_tkip_init); 709 709 module_exit(rtllib_crypto_tkip_exit); 710 710 711 711 + MODULE_DESCRIPTION("Support module for rtllib TKIP crypto"); 711 712 MODULE_LICENSE("GPL");

+3 -2

drivers/staging/rtl8192e/rtllib_crypt_wep.c

reviewed

··· 102 102 /* Copy rest of the WEP key (the secret part) */ 103 103 memcpy(key + 3, wep->key, wep->key_len); 104 104 105 105 - if (!tcb_desc->bHwSec) { 105 105 + if (!tcb_desc->hw_sec) { 106 106 /* Append little-endian CRC32 and encrypt it to produce ICV */ 107 107 crc = ~crc32_le(~0, pos, len); 108 108 icv = skb_put(skb, 4); ··· 155 155 /* Apply RC4 to data and compute CRC32 over decrypted data */ 156 156 plen = skb->len - hdr_len - 8; 157 157 158 158 - if (!tcb_desc->bHwSec) { 158 158 + if (!tcb_desc->hw_sec) { 159 159 arc4_setkey(&wep->rx_ctx_arc4, key, klen); 160 160 arc4_crypt(&wep->rx_ctx_arc4, pos, pos, plen + 4); 161 161 ··· 238 238 module_init(rtllib_crypto_wep_init); 239 239 module_exit(rtllib_crypto_wep_exit); 240 240 241 241 + MODULE_DESCRIPTION("Support module for rtllib WEP crypto"); 241 242 MODULE_LICENSE("GPL");

+1

drivers/staging/rtl8192e/rtllib_module.c

reviewed

··· 175 175 module_init(rtllib_init); 176 176 module_exit(rtllib_exit); 177 177 178 178 + MODULE_DESCRIPTION("Support module for rtllib wireless devices"); 178 179 MODULE_LICENSE("GPL");

+112 -116

drivers/staging/rtl8192e/rtllib_rx.c

reviewed

··· 55 55 /* Called only as a tasklet (software IRQ) */ 56 56 static struct rtllib_frag_entry * 57 57 rtllib_frag_cache_find(struct rtllib_device *ieee, unsigned int seq, 58 58 - unsigned int frag, u8 tid, u8 *src, u8 *dst) 58 58 + unsigned int frag, u8 tid, u8 *src, u8 *dst) 59 59 { 60 60 struct rtllib_frag_entry *entry; 61 61 int i; ··· 84 84 /* Called only as a tasklet (software IRQ) */ 85 85 static struct sk_buff * 86 86 rtllib_frag_cache_get(struct rtllib_device *ieee, 87 87 - struct ieee80211_hdr *hdr) 87 87 + struct ieee80211_hdr *hdr) 88 88 { 89 89 struct sk_buff *skb = NULL; 90 90 u16 fc = le16_to_cpu(hdr->frame_control); ··· 143 143 * should have already been received 144 144 */ 145 145 entry = rtllib_frag_cache_find(ieee, seq, frag, tid, hdr->addr2, 146 146 - hdr->addr1); 146 146 + hdr->addr1); 147 147 if (entry) { 148 148 entry->last_frag = frag; 149 149 skb = entry->skb; ··· 155 155 156 156 /* Called only as a tasklet (software IRQ) */ 157 157 static int rtllib_frag_cache_invalidate(struct rtllib_device *ieee, 158 158 - struct ieee80211_hdr *hdr) 158 158 + struct ieee80211_hdr *hdr) 159 159 { 160 160 u16 fc = le16_to_cpu(hdr->frame_control); 161 161 u16 sc = le16_to_cpu(hdr->seq_ctrl); ··· 181 181 } 182 182 183 183 entry = rtllib_frag_cache_find(ieee, seq, -1, tid, hdr->addr2, 184 184 - hdr->addr1); 184 184 + hdr->addr1); 185 185 186 186 if (!entry) { 187 187 netdev_dbg(ieee->dev, ··· 202 202 */ 203 203 static inline int 204 204 rtllib_rx_frame_mgmt(struct rtllib_device *ieee, struct sk_buff *skb, 205 205 - struct rtllib_rx_stats *rx_stats, u16 type, 206 206 - u16 stype) 205 205 + struct rtllib_rx_stats *rx_stats, u16 type, u16 stype) 207 206 { 208 207 /* On the struct stats definition there is written that 209 208 * this is not mandatory.... but seems that the probe ··· 227 228 228 229 /* Called by rtllib_rx_frame_decrypt */ 229 230 static int rtllib_is_eapol_frame(struct rtllib_device *ieee, 230 230 - struct sk_buff *skb, size_t hdrlen) 231 231 + struct sk_buff *skb, size_t hdrlen) 231 232 { 232 233 struct net_device *dev = ieee->dev; 233 234 u16 fc, ethertype; ··· 281 282 struct cb_desc *tcb_desc = (struct cb_desc *) 282 283 (skb->cb + MAX_DEV_ADDR_SIZE); 283 284 284 284 - tcb_desc->bHwSec = 1; 285 285 + tcb_desc->hw_sec = 1; 285 286 286 287 if (ieee->need_sw_enc) 287 287 - tcb_desc->bHwSec = 0; 288 288 + tcb_desc->hw_sec = 0; 288 289 } 289 290 290 291 hdr = (struct ieee80211_hdr *)skb->data; ··· 320 321 struct cb_desc *tcb_desc = (struct cb_desc *) 321 322 (skb->cb + MAX_DEV_ADDR_SIZE); 322 323 323 323 - tcb_desc->bHwSec = 1; 324 324 + tcb_desc->hw_sec = 1; 324 325 325 326 if (ieee->need_sw_enc) 326 326 - tcb_desc->bHwSec = 0; 327 327 + tcb_desc->hw_sec = 0; 327 328 } 328 329 329 330 hdr = (struct ieee80211_hdr *)skb->data; ··· 345 346 /* this function is stolen from ipw2200 driver*/ 346 347 #define IEEE_PACKET_RETRY_TIME (5 * HZ) 347 348 static int is_duplicate_packet(struct rtllib_device *ieee, 348 348 - struct ieee80211_hdr *header) 349 349 + struct ieee80211_hdr *header) 349 350 { 350 351 u16 fc = le16_to_cpu(header->frame_control); 351 352 u16 sc = le16_to_cpu(header->seq_ctrl); ··· 402 403 return 1; 403 404 } 404 405 405 405 - static bool AddReorderEntry(struct rx_ts_record *ts, 406 406 - struct rx_reorder_entry *pReorderEntry) 406 406 + static bool add_reorder_entry(struct rx_ts_record *ts, 407 407 + struct rx_reorder_entry *pReorderEntry) 407 408 { 408 408 - struct list_head *pList = &ts->rx_pending_pkt_list; 409 409 + struct list_head *list = &ts->rx_pending_pkt_list; 409 410 410 410 - while (pList->next != &ts->rx_pending_pkt_list) { 411 411 + while (list->next != &ts->rx_pending_pkt_list) { 411 412 if (SN_LESS(pReorderEntry->SeqNum, ((struct rx_reorder_entry *) 412 412 - list_entry(pList->next, struct rx_reorder_entry, 413 413 + list_entry(list->next, struct rx_reorder_entry, 413 414 list))->SeqNum)) 414 414 - pList = pList->next; 415 415 + list = list->next; 415 416 else if (SN_EQUAL(pReorderEntry->SeqNum, 416 416 - ((struct rx_reorder_entry *)list_entry(pList->next, 417 417 + ((struct rx_reorder_entry *)list_entry(list->next, 417 418 struct rx_reorder_entry, list))->SeqNum)) 418 419 return false; 419 420 else 420 421 break; 421 422 } 422 422 - pReorderEntry->list.next = pList->next; 423 423 + pReorderEntry->list.next = list->next; 423 424 pReorderEntry->list.next->prev = &pReorderEntry->list; 424 424 - pReorderEntry->list.prev = pList; 425 425 - pList->next = &pReorderEntry->list; 425 425 + pReorderEntry->list.prev = list; 426 426 + list->next = &pReorderEntry->list; 426 427 427 428 return true; 428 429 } 429 430 430 431 void rtllib_indicate_packets(struct rtllib_device *ieee, 431 431 - struct rtllib_rxb **prxbIndicateArray, u8 index) 432 432 + struct rtllib_rxb **prxb_indicate_array, u8 index) 432 433 { 433 434 struct net_device_stats *stats = &ieee->stats; 434 435 u8 i = 0, j = 0; 435 436 u16 ethertype; 436 437 437 438 for (j = 0; j < index; j++) { 438 438 - struct rtllib_rxb *prxb = prxbIndicateArray[j]; 439 439 + struct rtllib_rxb *prxb = prxb_indicate_array[j]; 439 440 440 441 for (i = 0; i < prxb->nr_subframes; i++) { 441 442 struct sk_buff *sub_skb = prxb->subframes[i]; ··· 490 491 struct rx_ts_record *ts) 491 492 { 492 493 struct rx_reorder_entry *pRxReorderEntry; 493 493 - u8 RfdCnt = 0; 494 494 + u8 rfd_cnt = 0; 494 495 495 496 del_timer_sync(&ts->rx_pkt_pending_timer); 496 497 while (!list_empty(&ts->rx_pending_pkt_list)) { 497 497 - if (RfdCnt >= REORDER_WIN_SIZE) { 498 498 + if (rfd_cnt >= REORDER_WIN_SIZE) { 498 499 netdev_info(ieee->dev, 499 499 - "-------------->%s() error! RfdCnt >= REORDER_WIN_SIZE\n", 500 500 + "-------------->%s() error! rfd_cnt >= REORDER_WIN_SIZE\n", 500 501 __func__); 501 502 break; 502 503 } ··· 508 509 pRxReorderEntry->SeqNum); 509 510 list_del_init(&pRxReorderEntry->list); 510 511 511 511 - ieee->RfdArray[RfdCnt] = pRxReorderEntry->prxb; 512 512 + ieee->rfd_array[rfd_cnt] = pRxReorderEntry->prxb; 512 513 513 513 - RfdCnt = RfdCnt + 1; 514 514 + rfd_cnt = rfd_cnt + 1; 514 515 list_add_tail(&pRxReorderEntry->list, 515 516 &ieee->RxReorder_Unused_List); 516 517 } 517 517 - rtllib_indicate_packets(ieee, ieee->RfdArray, RfdCnt); 518 518 + rtllib_indicate_packets(ieee, ieee->rfd_array, rfd_cnt); 518 519 519 520 ts->rx_indicate_seq = 0xffff; 520 521 } 521 522 522 522 - static void RxReorderIndicatePacket(struct rtllib_device *ieee, 523 523 - struct rtllib_rxb *prxb, 524 524 - struct rx_ts_record *ts, u16 SeqNum) 523 523 + static void rx_reorder_indicate_packet(struct rtllib_device *ieee, 524 524 + struct rtllib_rxb *prxb, 525 525 + struct rx_ts_record *ts, u16 SeqNum) 525 526 { 526 527 struct rt_hi_throughput *ht_info = ieee->ht_info; 527 528 struct rx_reorder_entry *pReorderEntry = NULL; 528 528 - u8 WinSize = ht_info->rx_reorder_win_size; 529 529 - u16 WinEnd = 0; 529 529 + u8 win_size = ht_info->rx_reorder_win_size; 530 530 + u16 win_end = 0; 530 531 u8 index = 0; 531 531 - bool bMatchWinStart = false, bPktInBuf = false; 532 532 + bool match_win_start = false, pkt_in_buf = false; 532 533 unsigned long flags; 533 534 534 535 netdev_dbg(ieee->dev, 535 535 - "%s(): Seq is %d, ts->rx_indicate_seq is %d, WinSize is %d\n", 536 536 - __func__, SeqNum, ts->rx_indicate_seq, WinSize); 536 536 + "%s(): Seq is %d, ts->rx_indicate_seq is %d, win_size is %d\n", 537 537 + __func__, SeqNum, ts->rx_indicate_seq, win_size); 537 538 538 539 spin_lock_irqsave(&(ieee->reorder_spinlock), flags); 539 540 540 540 - WinEnd = (ts->rx_indicate_seq + WinSize - 1) % 4096; 541 541 + win_end = (ts->rx_indicate_seq + win_size - 1) % 4096; 541 542 /* Rx Reorder initialize condition.*/ 542 543 if (ts->rx_indicate_seq == 0xffff) 543 544 ts->rx_indicate_seq = SeqNum; ··· 562 563 563 564 /* Sliding window manipulation. Conditions includes: 564 565 * 1. Incoming SeqNum is equal to WinStart =>Window shift 1 565 565 - * 2. Incoming SeqNum is larger than the WinEnd => Window shift N 566 566 + * 2. Incoming SeqNum is larger than the win_end => Window shift N 566 567 */ 567 568 if (SN_EQUAL(SeqNum, ts->rx_indicate_seq)) { 568 569 ts->rx_indicate_seq = (ts->rx_indicate_seq + 1) % 4096; 569 569 - bMatchWinStart = true; 570 570 - } else if (SN_LESS(WinEnd, SeqNum)) { 571 571 - if (SeqNum >= (WinSize - 1)) 572 572 - ts->rx_indicate_seq = SeqNum + 1 - WinSize; 570 570 + match_win_start = true; 571 571 + } else if (SN_LESS(win_end, SeqNum)) { 572 572 + if (SeqNum >= (win_size - 1)) 573 573 + ts->rx_indicate_seq = SeqNum + 1 - win_size; 573 574 else 574 575 ts->rx_indicate_seq = 4095 - 575 575 - (WinSize - (SeqNum + 1)) + 1; 576 576 + (win_size - (SeqNum + 1)) + 1; 576 577 netdev_dbg(ieee->dev, 577 578 "Window Shift! IndicateSeq: %d, NewSeq: %d\n", 578 579 ts->rx_indicate_seq, SeqNum); ··· 588 589 * 2. All packets with SeqNum larger than or equal to 589 590 * WinStart => Buffer it. 590 591 */ 591 591 - if (bMatchWinStart) { 592 592 + if (match_win_start) { 592 593 /* Current packet is going to be indicated.*/ 593 594 netdev_dbg(ieee->dev, 594 595 "Packets indication! IndicateSeq: %d, NewSeq: %d\n", 595 596 ts->rx_indicate_seq, SeqNum); 596 596 - ieee->prxbIndicateArray[0] = prxb; 597 597 + ieee->prxb_indicate_array[0] = prxb; 597 598 index = 1; 598 599 } else { 599 600 /* Current packet is going to be inserted into pending list.*/ ··· 609 610 pReorderEntry->SeqNum = SeqNum; 610 611 pReorderEntry->prxb = prxb; 611 612 612 612 - if (!AddReorderEntry(ts, pReorderEntry)) { 613 613 + if (!add_reorder_entry(ts, pReorderEntry)) { 613 614 int i; 614 615 615 616 netdev_dbg(ieee->dev, ··· 664 665 netdev_err(ieee->dev, 665 666 "%s(): Buffer overflow!\n", 666 667 __func__); 667 667 - bPktInBuf = true; 668 668 + pkt_in_buf = true; 668 669 break; 669 670 } 670 671 ··· 674 675 ts->rx_indicate_seq = (ts->rx_indicate_seq + 1) % 675 676 4096; 676 677 677 677 - ieee->prxbIndicateArray[index] = pReorderEntry->prxb; 678 678 + ieee->prxb_indicate_array[index] = pReorderEntry->prxb; 678 679 netdev_dbg(ieee->dev, "%s(): Indicate SeqNum %d!\n", 679 680 __func__, pReorderEntry->SeqNum); 680 681 index++; ··· 682 683 list_add_tail(&pReorderEntry->list, 683 684 &ieee->RxReorder_Unused_List); 684 685 } else { 685 685 - bPktInBuf = true; 686 686 + pkt_in_buf = true; 686 687 break; 687 688 } 688 689 } ··· 705 706 flags); 706 707 return; 707 708 } 708 708 - rtllib_indicate_packets(ieee, ieee->prxbIndicateArray, index); 709 709 - bPktInBuf = false; 709 709 + rtllib_indicate_packets(ieee, ieee->prxb_indicate_array, index); 710 710 + pkt_in_buf = false; 710 711 } 711 712 712 712 - if (bPktInBuf && ts->rx_timeout_indicate_seq == 0xffff) { 713 713 + if (pkt_in_buf && ts->rx_timeout_indicate_seq == 0xffff) { 713 714 netdev_dbg(ieee->dev, "%s(): SET rx timeout timer\n", __func__); 714 715 ts->rx_timeout_indicate_seq = ts->rx_indicate_seq; 715 716 spin_unlock_irqrestore(&ieee->reorder_spinlock, flags); ··· 727 728 struct ieee80211_hdr_3addr *hdr = (struct ieee80211_hdr_3addr *)skb->data; 728 729 u16 fc = le16_to_cpu(hdr->frame_control); 729 730 730 730 - u16 LLCOffset = sizeof(struct ieee80211_hdr_3addr); 731 731 - u16 ChkLength; 731 731 + u16 llc_offset = sizeof(struct ieee80211_hdr_3addr); 732 732 bool is_aggregate_frame = false; 733 733 u16 nSubframe_Length; 734 734 - u8 nPadding_Length = 0; 734 734 + u8 pad_len = 0; 735 735 u16 SeqNum = 0; 736 736 struct sk_buff *sub_skb; 737 737 /* just for debug purpose */ ··· 740 742 is_aggregate_frame = true; 741 743 742 744 if (RTLLIB_QOS_HAS_SEQ(fc)) 743 743 - LLCOffset += 2; 744 744 - if (rx_stats->bContainHTC) 745 745 - LLCOffset += sHTCLng; 745 745 + llc_offset += 2; 746 746 + if (rx_stats->contain_htc) 747 747 + llc_offset += sHTCLng; 746 748 747 747 - ChkLength = LLCOffset; 748 748 - 749 749 - if (skb->len <= ChkLength) 749 749 + if (skb->len <= llc_offset) 750 750 return 0; 751 751 752 752 - skb_pull(skb, LLCOffset); 752 752 + skb_pull(skb, llc_offset); 753 753 ieee->is_aggregate_frame = is_aggregate_frame; 754 754 if (!is_aggregate_frame) { 755 755 rxb->nr_subframes = 1; ··· 829 833 skb_pull(skb, nSubframe_Length); 830 834 831 835 if (skb->len != 0) { 832 832 - nPadding_Length = 4 - ((nSubframe_Length + 836 836 + pad_len = 4 - ((nSubframe_Length + 833 837 ETHERNET_HEADER_SIZE) % 4); 834 834 - if (nPadding_Length == 4) 835 835 - nPadding_Length = 0; 838 838 + if (pad_len == 4) 839 839 + pad_len = 0; 836 840 837 837 - if (skb->len < nPadding_Length) 841 841 + if (skb->len < pad_len) 838 842 return 0; 839 843 840 840 - skb_pull(skb, nPadding_Length); 844 844 + skb_pull(skb, pad_len); 841 845 } 842 846 } 843 847 ··· 858 862 netdev_info(ieee->dev, "%s: find HTCControl!\n", 859 863 __func__); 860 864 hdrlen += 4; 861 861 - rx_stats->bContainHTC = true; 865 865 + rx_stats->contain_htc = true; 862 866 } 863 867 864 868 return hdrlen; ··· 877 881 878 882 if (!ieee->ht_info->cur_rx_reorder_enable || 879 883 !ieee->current_network.qos_data.active || 880 880 - !IsDataFrame(skb->data) || 881 881 - IsLegacyDataFrame(skb->data)) { 884 884 + !is_data_frame(skb->data) || 885 885 + is_legacy_data_frame(skb->data)) { 882 886 if (!ieee80211_is_beacon(hdr->frame_control)) { 883 887 if (is_duplicate_packet(ieee, hdr)) 884 888 return -1; ··· 887 891 struct rx_ts_record *ts = NULL; 888 892 889 893 if (rtllib_get_ts(ieee, (struct ts_common_info **)&ts, hdr->addr2, 890 890 - (u8)Frame_QoSTID((u8 *)(skb->data)), RX_DIR, true)) { 894 894 + (u8)frame_qos_tid((u8 *)(skb->data)), RX_DIR, true)) { 891 895 if ((fc & (1 << 11)) && (frag == ts->rx_last_frag_num) && 892 896 (WLAN_GET_SEQ_SEQ(sc) == ts->rx_last_seq_num)) 893 897 return -1; ··· 1021 1025 sc = le16_to_cpu(hdr->seq_ctrl); 1022 1026 frag = WLAN_GET_SEQ_FRAG(sc); 1023 1027 1024 1024 - if ((!rx_stats->Decrypted)) 1028 1028 + if ((!rx_stats->decrypted)) 1025 1029 ieee->need_sw_enc = 1; 1026 1030 else 1027 1031 ieee->need_sw_enc = 0; ··· 1219 1223 kfree(rxb); 1220 1224 } 1221 1225 1222 1222 - static int rtllib_rx_InfraAdhoc(struct rtllib_device *ieee, struct sk_buff *skb, 1226 1226 + static int rtllib_rx_infra_adhoc(struct rtllib_device *ieee, struct sk_buff *skb, 1223 1227 struct rtllib_rx_stats *rx_stats) 1224 1228 { 1225 1229 struct net_device *dev = ieee->dev; ··· 1318 1322 1319 1323 /* Get TS for Rx Reorder */ 1320 1324 hdr = (struct ieee80211_hdr *)skb->data; 1321 1321 - if (ieee->current_network.qos_data.active && IsQoSDataFrame(skb->data) 1325 1325 + if (ieee->current_network.qos_data.active && is_qos_data_frame(skb->data) 1322 1326 && !is_multicast_ether_addr(hdr->addr1)) { 1323 1323 - TID = Frame_QoSTID(skb->data); 1327 1327 + TID = frame_qos_tid(skb->data); 1324 1328 SeqNum = WLAN_GET_SEQ_SEQ(sc); 1325 1329 rtllib_get_ts(ieee, (struct ts_common_info **)&ts, hdr->addr2, TID, 1326 1330 RX_DIR, true); ··· 1362 1366 if (!ieee->ht_info->cur_rx_reorder_enable || !ts) 1363 1367 rtllib_rx_indicate_pkt_legacy(ieee, rx_stats, rxb, dst, src); 1364 1368 else 1365 1365 - RxReorderIndicatePacket(ieee, rxb, ts, SeqNum); 1369 1369 + rx_reorder_indicate_packet(ieee, rxb, ts, SeqNum); 1366 1370 1367 1371 dev_kfree_skb(skb); 1368 1372 ··· 1379 1383 return 0; 1380 1384 } 1381 1385 1382 1382 - static int rtllib_rx_Monitor(struct rtllib_device *ieee, struct sk_buff *skb, 1386 1386 + static int rtllib_rx_monitor(struct rtllib_device *ieee, struct sk_buff *skb, 1383 1387 struct rtllib_rx_stats *rx_stats) 1384 1388 { 1385 1389 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; ··· 1427 1431 1428 1432 switch (ieee->iw_mode) { 1429 1433 case IW_MODE_INFRA: 1430 1430 - ret = rtllib_rx_InfraAdhoc(ieee, skb, rx_stats); 1434 1434 + ret = rtllib_rx_infra_adhoc(ieee, skb, rx_stats); 1431 1435 break; 1432 1436 case IW_MODE_MONITOR: 1433 1433 - ret = rtllib_rx_Monitor(ieee, skb, rx_stats); 1437 1437 + ret = rtllib_rx_monitor(ieee, skb, rx_stats); 1434 1438 break; 1435 1439 default: 1436 1440 netdev_info(ieee->dev, "%s: ERR iw mode!!!\n", __func__); ··· 1452 1456 static int rtllib_verify_qos_info(struct rtllib_qos_information_element 1453 1457 *info_element, int sub_type) 1454 1458 { 1455 1455 - if (info_element->elementID != QOS_ELEMENT_ID) 1459 1459 + if (info_element->element_id != QOS_ELEMENT_ID) 1456 1460 return -1; 1457 1461 if (info_element->qui_subtype != sub_type) 1458 1462 return -1; ··· 1809 1813 info_element->data[2] == 0x96 && 1810 1814 info_element->data[3] == 0x01) { 1811 1815 if (info_element->len == 6) { 1812 1812 - memcpy(network->CcxRmState, &info_element->data[4], 2); 1813 1813 - if (network->CcxRmState[0] != 0) 1816 1816 + memcpy(network->ccx_rm_state, &info_element->data[4], 2); 1817 1817 + if (network->ccx_rm_state[0] != 0) 1814 1818 network->ccx_rm_enable = true; 1815 1819 else 1816 1820 network->ccx_rm_enable = false; 1817 1817 - network->MBssidMask = network->CcxRmState[1] & 0x07; 1818 1818 - if (network->MBssidMask != 0) { 1819 1819 - network->bMBssidValid = true; 1820 1820 - network->MBssidMask = 0xff << 1821 1821 - (network->MBssidMask); 1822 1822 - ether_addr_copy(network->MBssid, 1821 1821 + network->mb_ssid_mask = network->ccx_rm_state[1] & 0x07; 1822 1822 + if (network->mb_ssid_mask != 0) { 1823 1823 + network->mb_ssid_valid = true; 1824 1824 + network->mb_ssid_mask = 0xff << 1825 1825 + (network->mb_ssid_mask); 1826 1826 + ether_addr_copy(network->mb_ssid, 1823 1827 network->bssid); 1824 1824 - network->MBssid[5] &= network->MBssidMask; 1828 1828 + network->mb_ssid[5] &= network->mb_ssid_mask; 1825 1829 } else { 1826 1826 - network->bMBssidValid = false; 1830 1830 + network->mb_ssid_valid = false; 1827 1831 } 1828 1832 } else { 1829 1833 network->ccx_rm_enable = false; ··· 1835 1839 info_element->data[2] == 0x96 && 1836 1840 info_element->data[3] == 0x03) { 1837 1841 if (info_element->len == 5) { 1838 1838 - network->bWithCcxVerNum = true; 1842 1842 + network->with_ccx_ver_num = true; 1839 1843 network->bss_ccx_ver_number = info_element->data[4]; 1840 1844 } else { 1841 1841 - network->bWithCcxVerNum = false; 1845 1845 + network->with_ccx_ver_num = false; 1842 1846 network->bss_ccx_ver_number = 0; 1843 1847 } 1844 1848 } ··· 1910 1914 switch (info_element->id) { 1911 1915 case MFIE_TYPE_SSID: 1912 1916 if (rtllib_is_empty_essid(info_element->data, 1913 1913 - info_element->len)) { 1917 1917 + info_element->len)) { 1914 1918 network->flags |= NETWORK_EMPTY_ESSID; 1915 1919 break; 1916 1920 } ··· 2086 2090 netdev_dbg(ieee->dev, "MFIE_TYPE_AIRONET: %d bytes\n", 2087 2091 info_element->len); 2088 2092 if (info_element->len > IE_CISCO_FLAG_POSITION) { 2089 2089 - network->bWithAironetIE = true; 2093 2093 + network->with_aironet_ie = true; 2090 2094 2091 2095 if ((info_element->data[IE_CISCO_FLAG_POSITION] 2092 2096 & SUPPORT_CKIP_MIC) || ··· 2096 2100 else 2097 2101 network->ckip_supported = false; 2098 2102 } else { 2099 2099 - network->bWithAironetIE = false; 2103 2103 + network->with_aironet_ie = false; 2100 2104 network->ckip_supported = false; 2101 2105 } 2102 2106 break; ··· 2179 2183 network->turbo_enable = 0; 2180 2184 network->SignalStrength = stats->SignalStrength; 2181 2185 network->RSSI = stats->SignalStrength; 2182 2182 - network->CountryIeLen = 0; 2183 2183 - memset(network->CountryIeBuf, 0, MAX_IE_LEN); 2186 2186 + network->country_ie_len = 0; 2187 2187 + memset(network->country_ie_buf, 0, MAX_IE_LEN); 2184 2188 ht_initialize_bss_desc(&network->bssht); 2185 2189 network->flags |= NETWORK_HAS_CCK; 2186 2190 ··· 2189 2193 network->wzc_ie_len = 0; 2190 2194 2191 2195 if (rtllib_parse_info_param(ieee, 2192 2192 - beacon->info_element, 2193 2193 - (stats->len - sizeof(*beacon)), 2194 2194 - network, 2195 2195 - stats)) 2196 2196 + beacon->info_element, 2197 2197 + (stats->len - sizeof(*beacon)), 2198 2198 + network, 2199 2199 + stats)) 2196 2200 return 1; 2197 2201 2198 2202 network->mode = 0; ··· 2338 2342 dst->RSSI = src->RSSI; 2339 2343 dst->turbo_enable = src->turbo_enable; 2340 2344 2341 2341 - dst->CountryIeLen = src->CountryIeLen; 2342 2342 - memcpy(dst->CountryIeBuf, src->CountryIeBuf, src->CountryIeLen); 2345 2345 + dst->country_ie_len = src->country_ie_len; 2346 2346 + memcpy(dst->country_ie_buf, src->country_ie_buf, src->country_ie_len); 2343 2347 2344 2344 - dst->bWithAironetIE = src->bWithAironetIE; 2348 2348 + dst->with_aironet_ie = src->with_aironet_ie; 2345 2349 dst->ckip_supported = src->ckip_supported; 2346 2346 - memcpy(dst->CcxRmState, src->CcxRmState, 2); 2350 2350 + memcpy(dst->ccx_rm_state, src->ccx_rm_state, 2); 2347 2351 dst->ccx_rm_enable = src->ccx_rm_enable; 2348 2348 - dst->MBssidMask = src->MBssidMask; 2349 2349 - dst->bMBssidValid = src->bMBssidValid; 2350 2350 - memcpy(dst->MBssid, src->MBssid, 6); 2351 2351 - dst->bWithCcxVerNum = src->bWithCcxVerNum; 2352 2352 + dst->mb_ssid_mask = src->mb_ssid_mask; 2353 2353 + dst->mb_ssid_valid = src->mb_ssid_valid; 2354 2354 + memcpy(dst->mb_ssid, src->mb_ssid, 6); 2355 2355 + dst->with_ccx_ver_num = src->with_ccx_ver_num; 2352 2356 dst->bss_ccx_ver_number = src->bss_ccx_ver_number; 2353 2357 } 2354 2358 2355 2355 - static int IsPassiveChannel(struct rtllib_device *rtllib, u8 channel) 2359 2359 + static int is_passive_channel(struct rtllib_device *rtllib, u8 channel) 2356 2360 { 2357 2361 if (channel > MAX_CHANNEL_NUMBER) { 2358 2362 netdev_info(rtllib->dev, "%s(): Invalid Channel\n", __func__); ··· 2428 2432 goto free_network; 2429 2433 2430 2434 if (ieee80211_is_probe_resp(frame_ctl)) { 2431 2431 - if (IsPassiveChannel(ieee, network->channel)) { 2435 2435 + if (is_passive_channel(ieee, network->channel)) { 2432 2436 netdev_info(ieee->dev, 2433 2437 "GetScanInfo(): For Global Domain, filter probe response at channel(%d).\n", 2434 2438 network->channel); ··· 2558 2562 schedule_work(&ieee->ps_task); 2559 2563 } else if (ieee80211_is_probe_resp(header->frame_control)) { 2560 2564 netdev_dbg(ieee->dev, "received PROBE RESPONSE\n"); 2561 2561 - rtllib_process_probe_response(ieee, 2562 2562 - (struct rtllib_probe_response *)header, stats); 2565 2565 + rtllib_process_probe_response(ieee, (struct rtllib_probe_response *)header, 2566 2566 + stats); 2563 2567 } 2564 2568 }

+4 -4

drivers/staging/rtl8192e/rtllib_softmac.c

reviewed

··· 421 421 * So we switch to MAC80211_LINKED_SCANNING to remember 422 422 * that we are still logically linked (not interested in 423 423 * new network events, despite for updating the net list, 424 424 - * but we are temporarly 'unlinked' as the driver shall 424 424 + * but we are temporarily 'unlinked' as the driver shall 425 425 * not filter RX frames and the channel is changing. 426 426 * So the only situation in which are interested is to check 427 427 * if the state become LINKED because of the #1 situation ··· 934 934 935 935 ieee->associate_seq++; 936 936 937 937 - /* don't scan, and avoid to have the RX path possibily 937 937 + /* don't scan, and avoid to have the RX path possibly 938 938 * try again to associate. Even do not react to AUTH or 939 939 * ASSOC response. Just wait for the retry wq to be scheduled. 940 940 * Here we will check if there are good nets to associate ··· 1359 1359 return 0; 1360 1360 timeout = ieee->current_network.beacon_interval; 1361 1361 ieee->current_network.dtim_data = RTLLIB_DTIM_INVALID; 1362 1362 - /* there's no need to nofity AP that I find you buffered 1362 1362 + /* there's no need to notify AP that I find you buffered 1363 1363 * with broadcast packet 1364 1364 */ 1365 1365 if (dtim & (RTLLIB_DTIM_UCAST & ieee->ps)) ··· 1806 1806 1807 1807 spin_lock_irqsave(&ieee->lock, flags); 1808 1808 1809 1809 - /* called with 2nd parm 0, no tx mgmt lock required */ 1809 1809 + /* called with 2nd param 0, no tx mgmt lock required */ 1810 1810 rtllib_sta_wakeup(ieee, 0); 1811 1811 1812 1812 /* update the tx status */

+65 -70

drivers/staging/rtl8192e/rtllib_tx.c

reviewed

··· 228 228 return NULL; 229 229 } 230 230 231 231 - static int rtllib_classify(struct sk_buff *skb, u8 bIsAmsdu) 231 231 + static int rtllib_classify(struct sk_buff *skb) 232 232 { 233 233 struct ethhdr *eth; 234 234 struct iphdr *ip; ··· 275 275 276 276 if (!ht_info->current_ht_support || !ht_info->enable_ht) 277 277 return; 278 278 - if (!IsQoSDataFrame(skb->data)) 278 278 + if (!is_qos_data_frame(skb->data)) 279 279 return; 280 280 if (is_multicast_ether_addr(hdr->addr1)) 281 281 return; 282 282 283 283 - if (tcb_desc->bdhcp || ieee->CntAfterLink < 2) 283 283 + if (tcb_desc->bdhcp || ieee->cnt_after_link < 2) 284 284 return; 285 285 286 286 if (ht_info->iot_action & HT_IOT_ACT_TX_NO_AGGREGATION) ··· 290 290 return; 291 291 if (ht_info->current_ampdu_enable) { 292 292 if (!rtllib_get_ts(ieee, (struct ts_common_info **)(&ts), hdr->addr1, 293 293 - skb->priority, TX_DIR, true)) { 293 293 + skb->priority, TX_DIR, true)) { 294 294 netdev_info(ieee->dev, "%s: can't get TS\n", __func__); 295 295 return; 296 296 } ··· 301 301 } else if (tcb_desc->bdhcp == 1) { 302 302 ; 303 303 } else if (!ts->disable_add_ba) { 304 304 - TsStartAddBaProcess(ieee, ts); 304 304 + rtllib_ts_start_add_ba_process(ieee, ts); 305 305 } 306 306 return; 307 307 } else if (!ts->using_ba) { ··· 319 319 } 320 320 } 321 321 322 322 - static void rtllib_query_ShortPreambleMode(struct rtllib_device *ieee, 323 323 - struct cb_desc *tcb_desc) 322 322 + static void rtllib_query_short_preamble_mode(struct rtllib_device *ieee, 323 323 + struct cb_desc *tcb_desc) 324 324 { 325 325 - tcb_desc->bUseShortPreamble = false; 325 325 + tcb_desc->use_short_preamble = false; 326 326 if (tcb_desc->data_rate == 2) 327 327 return; 328 328 else if (ieee->current_network.capability & 329 329 WLAN_CAPABILITY_SHORT_PREAMBLE) 330 330 - tcb_desc->bUseShortPreamble = true; 330 330 + tcb_desc->use_short_preamble = true; 331 331 } 332 332 333 333 - static void rtllib_query_HTCapShortGI(struct rtllib_device *ieee, 334 334 - struct cb_desc *tcb_desc) 333 333 + static void rtllib_query_ht_cap_short_gi(struct rtllib_device *ieee, 334 334 + struct cb_desc *tcb_desc) 335 335 { 336 336 struct rt_hi_throughput *ht_info = ieee->ht_info; 337 337 338 338 - tcb_desc->bUseShortGI = false; 338 338 + tcb_desc->use_short_gi = false; 339 339 340 340 if (!ht_info->current_ht_support || !ht_info->enable_ht) 341 341 return; 342 342 343 343 if (ht_info->cur_bw_40mhz && ht_info->cur_short_gi_40mhz) 344 344 - tcb_desc->bUseShortGI = true; 344 344 + tcb_desc->use_short_gi = true; 345 345 else if (!ht_info->cur_bw_40mhz && ht_info->cur_short_gi_20mhz) 346 346 - tcb_desc->bUseShortGI = true; 346 346 + tcb_desc->use_short_gi = true; 347 347 } 348 348 349 349 - static void rtllib_query_BandwidthMode(struct rtllib_device *ieee, 350 350 - struct cb_desc *tcb_desc) 349 349 + static void rtllib_query_bandwidth_mode(struct rtllib_device *ieee, 350 350 + struct cb_desc *tcb_desc) 351 351 { 352 352 struct rt_hi_throughput *ht_info = ieee->ht_info; 353 353 354 354 - tcb_desc->bPacketBW = false; 354 354 + tcb_desc->packet_bw = false; 355 355 356 356 if (!ht_info->current_ht_support || !ht_info->enable_ht) 357 357 return; 358 358 359 359 - if (tcb_desc->multicast || tcb_desc->bBroadcast) 359 359 + if (tcb_desc->multicast || tcb_desc->broadcast) 360 360 return; 361 361 362 362 if ((tcb_desc->data_rate & 0x80) == 0) 363 363 return; 364 364 if (ht_info->cur_bw_40mhz && ht_info->cur_tx_bw40mhz && 365 365 - !ieee->bandwidth_auto_switch.bforced_tx20Mhz) 366 366 - tcb_desc->bPacketBW = true; 365 365 + !ieee->bandwidth_auto_switch.forced_tx_20MHz) 366 366 + tcb_desc->packet_bw = true; 367 367 } 368 368 369 369 static void rtllib_query_protectionmode(struct rtllib_device *ieee, ··· 372 372 { 373 373 struct rt_hi_throughput *ht_info; 374 374 375 375 - tcb_desc->bRTSSTBC = false; 376 376 - tcb_desc->bRTSUseShortGI = false; 377 377 - tcb_desc->bCTSEnable = false; 375 375 + tcb_desc->rtsstbc = false; 376 376 + tcb_desc->rts_use_short_gi = false; 377 377 + tcb_desc->cts_enable = false; 378 378 tcb_desc->RTSSC = 0; 379 379 - tcb_desc->bRTSBW = false; 379 379 + tcb_desc->rts_bw = false; 380 380 381 381 - if (tcb_desc->bBroadcast || tcb_desc->multicast) 381 381 + if (tcb_desc->broadcast || tcb_desc->multicast) 382 382 return; 383 383 384 384 if (is_broadcast_ether_addr(skb->data + 16)) ··· 386 386 387 387 if (ieee->mode < WIRELESS_MODE_N_24G) { 388 388 if (skb->len > ieee->rts) { 389 389 - tcb_desc->bRTSEnable = true; 389 389 + tcb_desc->rts_enable = true; 390 390 tcb_desc->rts_rate = MGN_24M; 391 391 } else if (ieee->current_network.buseprotection) { 392 392 - tcb_desc->bRTSEnable = true; 393 393 - tcb_desc->bCTSEnable = true; 392 392 + tcb_desc->rts_enable = true; 393 393 + tcb_desc->cts_enable = true; 394 394 tcb_desc->rts_rate = MGN_24M; 395 395 } 396 396 return; ··· 400 400 401 401 while (true) { 402 402 if (ht_info->iot_action & HT_IOT_ACT_FORCED_CTS2SELF) { 403 403 - tcb_desc->bCTSEnable = true; 403 403 + tcb_desc->cts_enable = true; 404 404 tcb_desc->rts_rate = MGN_24M; 405 405 - tcb_desc->bRTSEnable = true; 405 405 + tcb_desc->rts_enable = true; 406 406 break; 407 407 } else if (ht_info->iot_action & (HT_IOT_ACT_FORCED_RTS | 408 408 HT_IOT_ACT_PURE_N_MODE)) { 409 409 - tcb_desc->bRTSEnable = true; 409 409 + tcb_desc->rts_enable = true; 410 410 tcb_desc->rts_rate = MGN_24M; 411 411 break; 412 412 } 413 413 if (ieee->current_network.buseprotection) { 414 414 - tcb_desc->bRTSEnable = true; 415 415 - tcb_desc->bCTSEnable = true; 414 414 + tcb_desc->rts_enable = true; 415 415 + tcb_desc->cts_enable = true; 416 416 tcb_desc->rts_rate = MGN_24M; 417 417 break; 418 418 } 419 419 if (ht_info->current_ht_support && ht_info->enable_ht) { 420 420 - u8 HTOpMode = ht_info->current_op_mode; 420 420 + u8 ht_op_mode = ht_info->current_op_mode; 421 421 422 422 - if ((ht_info->cur_bw_40mhz && (HTOpMode == 2 || 423 423 - HTOpMode == 3)) || 424 424 - (!ht_info->cur_bw_40mhz && HTOpMode == 3)) { 422 422 + if ((ht_info->cur_bw_40mhz && (ht_op_mode == 2 || 423 423 + ht_op_mode == 3)) || 424 424 + (!ht_info->cur_bw_40mhz && ht_op_mode == 3)) { 425 425 tcb_desc->rts_rate = MGN_24M; 426 426 - tcb_desc->bRTSEnable = true; 426 426 + tcb_desc->rts_enable = true; 427 427 break; 428 428 } 429 429 } 430 430 if (skb->len > ieee->rts) { 431 431 tcb_desc->rts_rate = MGN_24M; 432 432 - tcb_desc->bRTSEnable = true; 432 432 + tcb_desc->rts_enable = true; 433 433 break; 434 434 } 435 435 if (tcb_desc->ampdu_enable) { 436 436 tcb_desc->rts_rate = MGN_24M; 437 437 - tcb_desc->bRTSEnable = false; 437 437 + tcb_desc->rts_enable = false; 438 438 break; 439 439 } 440 440 goto NO_PROTECTION; 441 441 } 442 442 if (ieee->current_network.capability & WLAN_CAPABILITY_SHORT_PREAMBLE) 443 443 - tcb_desc->bUseShortPreamble = true; 443 443 + tcb_desc->use_short_preamble = true; 444 444 return; 445 445 NO_PROTECTION: 446 446 - tcb_desc->bRTSEnable = false; 447 447 - tcb_desc->bCTSEnable = false; 446 446 + tcb_desc->rts_enable = false; 447 447 + tcb_desc->cts_enable = false; 448 448 tcb_desc->rts_rate = 0; 449 449 tcb_desc->RTSSC = 0; 450 450 - tcb_desc->bRTSBW = false; 450 450 + tcb_desc->rts_bw = false; 451 451 } 452 452 453 453 static void rtllib_txrate_selectmode(struct rtllib_device *ieee, ··· 472 472 473 473 if (is_multicast_ether_addr(dst)) 474 474 return 0; 475 475 - if (IsQoSDataFrame(skb->data)) { 475 475 + if (is_qos_data_frame(skb->data)) { 476 476 struct tx_ts_record *ts = NULL; 477 477 478 478 if (!rtllib_get_ts(ieee, (struct ts_common_info **)(&ts), dst, 479 479 - skb->priority, TX_DIR, true)) 479 479 + skb->priority, TX_DIR, true)) 480 480 return 0; 481 481 seqnum = ts->tx_cur_seq; 482 482 ts->tx_cur_seq = (ts->tx_cur_seq + 1) % 4096; ··· 510 510 if (ieee->mode & IEEE_MODE_MASK) 511 511 return ieee->rate; 512 512 513 513 - if (ieee->HTCurrentOperaRate) 514 514 - return ieee->HTCurrentOperaRate; 513 513 + if (ieee->ht_curr_op_rate) 514 514 + return ieee->ht_curr_op_rate; 515 515 else 516 516 return ieee->rate & 0x7F; 517 517 } ··· 538 538 u8 src[ETH_ALEN]; 539 539 struct lib80211_crypt_data *crypt = NULL; 540 540 struct cb_desc *tcb_desc; 541 541 - u8 bIsMulticast = false; 542 542 - u8 IsAmsdu = false; 541 541 + u8 is_multicast = false; 543 542 bool bdhcp = false; 544 543 545 544 spin_lock_irqsave(&ieee->lock, flags); ··· 547 548 * creating it... 548 549 */ 549 550 if (!(ieee->softmac_features & IEEE_SOFTMAC_TX_QUEUE) || 550 550 - ((!ieee->softmac_data_hard_start_xmit && 551 551 - (ieee->softmac_features & IEEE_SOFTMAC_TX_QUEUE)))) { 551 551 + ((!ieee->softmac_data_hard_start_xmit && 552 552 + (ieee->softmac_features & IEEE_SOFTMAC_TX_QUEUE)))) { 552 553 netdev_warn(ieee->dev, "No xmit handler.\n"); 553 554 goto success; 554 555 } ··· 606 607 } 607 608 } 608 609 609 609 - skb->priority = rtllib_classify(skb, IsAmsdu); 610 610 + skb->priority = rtllib_classify(skb); 610 611 crypt = ieee->crypt_info.crypt[ieee->crypt_info.tx_keyidx]; 611 612 encrypt = !(ether_type == ETH_P_PAE && ieee->ieee802_1x) && crypt && crypt->ops; 612 613 if (!encrypt && ieee->ieee802_1x && ··· 647 648 ether_addr_copy(header.addr1, 648 649 ieee->current_network.bssid); 649 650 ether_addr_copy(header.addr2, src); 650 650 - if (IsAmsdu) 651 651 - ether_addr_copy(header.addr3, 652 652 - ieee->current_network.bssid); 653 653 - else 654 654 - ether_addr_copy(header.addr3, dest); 651 651 + ether_addr_copy(header.addr3, dest); 655 652 } 656 653 657 657 - bIsMulticast = is_multicast_ether_addr(header.addr1); 654 654 + is_multicast = is_multicast_ether_addr(header.addr1); 658 655 659 656 header.frame_control = cpu_to_le16(fc); 660 657 661 658 /* Determine fragmentation size based on destination (multicast 662 659 * and broadcast are not fragmented) 663 660 */ 664 664 - if (bIsMulticast) { 661 661 + if (is_multicast) { 665 662 frag_size = MAX_FRAG_THRESHOLD; 666 663 qos_ctl |= QOS_CTL_NOTCONTAIN_ACK; 667 664 } else { ··· 746 751 747 752 if (encrypt) { 748 753 if (ieee->hwsec_active) 749 749 - tcb_desc->bHwSec = 1; 754 754 + tcb_desc->hw_sec = 1; 750 755 else 751 751 - tcb_desc->bHwSec = 0; 756 756 + tcb_desc->hw_sec = 0; 752 757 skb_reserve(skb_frag, 753 758 crypt->ops->extra_mpdu_prefix_len + 754 759 crypt->ops->extra_msdu_prefix_len); 755 760 } else { 756 756 - tcb_desc->bHwSec = 0; 761 761 + tcb_desc->hw_sec = 0; 757 762 } 758 763 frag_hdr = skb_put_data(skb_frag, &header, hdr_len); 759 764 ··· 769 774 /* The last fragment has the remaining length */ 770 775 bytes = bytes_last_frag; 771 776 } 772 772 - if ((qos_activated) && (!bIsMulticast)) { 777 777 + if ((qos_activated) && (!is_multicast)) { 773 778 frag_hdr->seq_ctrl = 774 779 cpu_to_le16(rtllib_query_seqnum(ieee, skb_frag, 775 780 header.addr1)); ··· 804 809 skb_put(skb_frag, 4); 805 810 } 806 811 807 807 - if ((qos_activated) && (!bIsMulticast)) { 812 812 + if ((qos_activated) && (!is_multicast)) { 808 813 if (ieee->seq_ctrl[UP2AC(skb->priority) + 1] == 0xFFF) 809 814 ieee->seq_ctrl[UP2AC(skb->priority) + 1] = 0; 810 815 else ··· 840 845 if (is_multicast_ether_addr(header.addr1)) 841 846 tcb_desc->multicast = 1; 842 847 if (is_broadcast_ether_addr(header.addr1)) 843 843 - tcb_desc->bBroadcast = 1; 848 848 + tcb_desc->broadcast = 1; 844 849 rtllib_txrate_selectmode(ieee, tcb_desc); 845 845 - if (tcb_desc->multicast || tcb_desc->bBroadcast) 850 850 + if (tcb_desc->multicast || tcb_desc->broadcast) 846 851 tcb_desc->data_rate = ieee->basic_rate; 847 852 else 848 853 tcb_desc->data_rate = rtllib_current_rate(ieee); ··· 863 868 tcb_desc->bdhcp = 1; 864 869 } 865 870 866 866 - rtllib_query_ShortPreambleMode(ieee, tcb_desc); 871 871 + rtllib_query_short_preamble_mode(ieee, tcb_desc); 867 872 rtllib_tx_query_agg_cap(ieee, txb->fragments[0], 868 873 tcb_desc); 869 869 - rtllib_query_HTCapShortGI(ieee, tcb_desc); 870 870 - rtllib_query_BandwidthMode(ieee, tcb_desc); 874 874 + rtllib_query_ht_cap_short_gi(ieee, tcb_desc); 875 875 + rtllib_query_bandwidth_mode(ieee, tcb_desc); 871 876 rtllib_query_protectionmode(ieee, tcb_desc, 872 877 txb->fragments[0]); 873 878 }

+1 -1

drivers/staging/rtl8712/rtl8712_xmit.c

reviewed

··· 247 247 { 248 248 struct tx_desc *ptx_desc = (struct tx_desc *)pxmitbuf->pbuf; 249 249 250 250 - /* Fill up TxCmd Descriptor according as USB FW Tx Aaggregation info.*/ 250 250 + /* Fill up TxCmd Descriptor according as USB FW Tx Aggregation info.*/ 251 251 /* dw0 */ 252 252 ptx_desc->txdw0 = cpu_to_le32(CMD_HDR_SZ & 0xffff); 253 253 ptx_desc->txdw0 |=

+1 -1

drivers/staging/rtl8712/rtl871x_event.h

reviewed

··· 37 37 }; 38 38 39 39 /* 40 40 - * Used to report the link result of joinning the given bss 40 40 + * Used to report the link result of joining the given bss 41 41 * join_res: 42 42 * -1: authentication fail 43 43 * -2: association fail

+1 -1

drivers/staging/rtl8712/rtl871x_io.h

reviewed

··· 62 62 #define IO_WR_BURST(x) (IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | \ 63 63 ((x) & _IOSZ_MASK_)) 64 64 #define IO_RD_BURST(x) (_IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_)) 65 65 - /*below is for the intf_option bit defition...*/ 65 65 + /*below is for the intf_option bit definition...*/ 66 66 #define _INTF_ASYNC_ BIT(0) /*support async io*/ 67 67 struct intf_priv; 68 68 struct intf_hdl;

+1 -1

drivers/staging/rtl8712/rtl871x_mlme.c

reviewed

··· 944 944 945 945 /* When the Netgear 3500 AP is with WPA2PSK-AES mode, it will send 946 946 * the ADDBA req frame with start seq control = 0 to wifi client after 947 947 - * the WPA handshake and the seqence number of following data packet 947 947 + * the WPA handshake and the sequence number of following data packet 948 948 * will be 0. In this case, the Rx reorder sequence is not longer than 0 949 949 * and the WiFi client will drop the data with seq number 0. 950 950 * So, the 8712 firmware has to inform driver with receiving the

+5 -8

drivers/staging/rtl8712/rtl871x_xmit.c

reviewed

··· 117 117 /*init xmit_buf*/ 118 118 _init_queue(&pxmitpriv->free_xmitbuf_queue); 119 119 _init_queue(&pxmitpriv->pending_xmitbuf_queue); 120 120 - pxmitpriv->pallocated_xmitbuf = 121 121 - kmalloc(NR_XMITBUFF * sizeof(struct xmit_buf) + 4, GFP_ATOMIC); 122 122 - if (!pxmitpriv->pallocated_xmitbuf) 120 120 + pxmitpriv->pxmitbuf = kmalloc(NR_XMITBUFF * sizeof(struct xmit_buf), GFP_ATOMIC); 121 121 + if (!pxmitpriv->pxmitbuf) 123 122 goto clean_up_frame_buf; 124 124 - pxmitpriv->pxmitbuf = pxmitpriv->pallocated_xmitbuf + 4 - 125 125 - ((addr_t)(pxmitpriv->pallocated_xmitbuf) & 3); 126 123 pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf; 127 124 for (i = 0; i < NR_XMITBUFF; i++) { 128 125 INIT_LIST_HEAD(&pxmitbuf->list); ··· 162 165 for (k = 0; k < 8; k++) /* delete xmit urb's */ 163 166 usb_free_urb(pxmitbuf->pxmit_urb[k]); 164 167 } 165 165 - kfree(pxmitpriv->pallocated_xmitbuf); 166 166 - pxmitpriv->pallocated_xmitbuf = NULL; 168 168 + kfree(pxmitpriv->pxmitbuf); 169 169 + pxmitpriv->pxmitbuf = NULL; 167 170 clean_up_frame_buf: 168 171 kfree(pxmitpriv->pallocated_frame_buf); 169 172 pxmitpriv->pallocated_frame_buf = NULL; ··· 190 193 pxmitbuf++; 191 194 } 192 195 kfree(pxmitpriv->pallocated_frame_buf); 193 193 - kfree(pxmitpriv->pallocated_xmitbuf); 196 196 + kfree(pxmitpriv->pxmitbuf); 194 197 free_hwxmits(padapter); 195 198 } 196 199

-1

drivers/staging/rtl8712/rtl871x_xmit.h

reviewed

··· 244 244 int cmdseq; 245 245 struct __queue free_xmitbuf_queue; 246 246 struct __queue pending_xmitbuf_queue; 247 247 - u8 *pallocated_xmitbuf; 248 247 u8 *pxmitbuf; 249 248 uint free_xmitbuf_cnt; 250 249 };

-7

drivers/staging/rtl8712/usb_ops_linux.c

reviewed

··· 26 26 #define RTL871X_VENQT_READ 0xc0 27 27 #define RTL871X_VENQT_WRITE 0x40 28 28 29 29 - struct zero_bulkout_context { 30 30 - void *pbuf; 31 31 - void *purb; 32 32 - void *pirp; 33 33 - void *padapter; 34 34 - }; 35 35 - 36 29 uint r8712_usb_init_intf_priv(struct intf_priv *pintfpriv) 37 30 { 38 31 pintfpriv->piorw_urb = usb_alloc_urb(0, GFP_ATOMIC);

-373

drivers/staging/rtl8723bs/hal/Hal8723BReg.h

reviewed

··· 21 21 22 22 /* */ 23 23 /* */ 24 24 - /* */ 25 25 - 26 26 - /* */ 27 27 - /* */ 28 28 - /* 0x0000h ~ 0x00FFh System Configuration */ 29 29 - /* */ 30 30 - /* */ 31 31 - #define REG_SYS_ISO_CTRL_8723B 0x0000 /* 2 Byte */ 32 32 - #define REG_SYS_FUNC_EN_8723B 0x0002 /* 2 Byte */ 33 33 - #define REG_APS_FSMCO_8723B 0x0004 /* 4 Byte */ 34 34 - #define REG_SYS_CLKR_8723B 0x0008 /* 2 Byte */ 35 35 - #define REG_9346CR_8723B 0x000A /* 2 Byte */ 36 36 - #define REG_EE_VPD_8723B 0x000C /* 2 Byte */ 37 37 - #define REG_AFE_MISC_8723B 0x0010 /* 1 Byte */ 38 38 - #define REG_SPS0_CTRL_8723B 0x0011 /* 7 Byte */ 39 39 - #define REG_SPS_OCP_CFG_8723B 0x0018 /* 4 Byte */ 40 40 - #define REG_RSV_CTRL_8723B 0x001C /* 3 Byte */ 41 41 - #define REG_RF_CTRL_8723B 0x001F /* 1 Byte */ 42 42 - #define REG_LPLDO_CTRL_8723B 0x0023 /* 1 Byte */ 43 43 - #define REG_AFE_XTAL_CTRL_8723B 0x0024 /* 4 Byte */ 44 44 - #define REG_AFE_PLL_CTRL_8723B 0x0028 /* 4 Byte */ 45 45 - #define REG_MAC_PLL_CTRL_EXT_8723B 0x002c /* 4 Byte */ 46 46 - #define REG_EFUSE_CTRL_8723B 0x0030 47 47 - #define REG_EFUSE_TEST_8723B 0x0034 48 48 - #define REG_PWR_DATA_8723B 0x0038 49 49 - #define REG_CAL_TIMER_8723B 0x003C 50 50 - #define REG_ACLK_MON_8723B 0x003E 51 51 - #define REG_GPIO_MUXCFG_8723B 0x0040 52 52 - #define REG_GPIO_IO_SEL_8723B 0x0042 53 53 - #define REG_MAC_PINMUX_CFG_8723B 0x0043 54 54 - #define REG_GPIO_PIN_CTRL_8723B 0x0044 55 55 - #define REG_GPIO_INTM_8723B 0x0048 56 56 - #define REG_LEDCFG0_8723B 0x004C 57 57 - #define REG_LEDCFG1_8723B 0x004D 58 58 - #define REG_LEDCFG2_8723B 0x004E 59 59 - #define REG_LEDCFG3_8723B 0x004F 60 60 - #define REG_FSIMR_8723B 0x0050 61 61 - #define REG_FSISR_8723B 0x0054 62 62 - #define REG_HSIMR_8723B 0x0058 63 63 - #define REG_HSISR_8723B 0x005c 64 64 - #define REG_GPIO_EXT_CTRL 0x0060 65 65 - #define REG_MULTI_FUNC_CTRL_8723B 0x0068 66 66 - #define REG_GPIO_STATUS_8723B 0x006C 67 67 - #define REG_SDIO_CTRL_8723B 0x0070 68 68 - #define REG_OPT_CTRL_8723B 0x0074 69 69 - #define REG_AFE_XTAL_CTRL_EXT_8723B 0x0078 70 70 - #define REG_MCUFWDL_8723B 0x0080 71 71 - #define REG_BT_PATCH_STATUS_8723B 0x0088 72 72 - #define REG_HIMR0_8723B 0x00B0 73 73 - #define REG_HISR0_8723B 0x00B4 74 74 - #define REG_HIMR1_8723B 0x00B8 75 75 - #define REG_HISR1_8723B 0x00BC 76 76 - #define REG_PMC_DBG_CTRL2_8723B 0x00CC 77 77 - #define REG_EFUSE_BURN_GNT_8723B 0x00CF 78 78 - #define REG_HPON_FSM_8723B 0x00EC 79 79 - #define REG_SYS_CFG_8723B 0x00F0 80 80 - #define REG_SYS_CFG1_8723B 0x00FC 81 81 - #define REG_ROM_VERSION 0x00FD 82 82 - 83 83 - /* */ 84 84 - /* */ 85 24 /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ 86 25 /* */ 87 26 /* */ 88 88 - #define REG_CR_8723B 0x0100 89 89 - #define REG_PBP_8723B 0x0104 90 90 - #define REG_PKT_BUFF_ACCESS_CTRL_8723B 0x0106 91 91 - #define REG_TRXDMA_CTRL_8723B 0x010C 92 92 - #define REG_TRXFF_BNDY_8723B 0x0114 93 93 - #define REG_TRXFF_STATUS_8723B 0x0118 94 94 - #define REG_RXFF_PTR_8723B 0x011C 95 95 - #define REG_CPWM_8723B 0x012F 96 96 - #define REG_FWIMR_8723B 0x0130 97 97 - #define REG_FWISR_8723B 0x0134 98 98 - #define REG_FTIMR_8723B 0x0138 99 99 - #define REG_PKTBUF_DBG_CTRL_8723B 0x0140 100 100 - #define REG_RXPKTBUF_CTRL_8723B 0x0142 101 101 - #define REG_PKTBUF_DBG_DATA_L_8723B 0x0144 102 102 - #define REG_PKTBUF_DBG_DATA_H_8723B 0x0148 103 103 - 104 104 - #define REG_TC0_CTRL_8723B 0x0150 105 105 - #define REG_TC1_CTRL_8723B 0x0154 106 106 - #define REG_TC2_CTRL_8723B 0x0158 107 107 - #define REG_TC3_CTRL_8723B 0x015C 108 108 - #define REG_TC4_CTRL_8723B 0x0160 109 109 - #define REG_TCUNIT_BASE_8723B 0x0164 110 110 - #define REG_RSVD3_8723B 0x0168 111 111 - #define REG_C2HEVT_MSG_NORMAL_8723B 0x01A0 112 27 #define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 113 113 - #define REG_C2HEVT_CMD_CONTENT_88XX 0x01A2 114 28 #define REG_C2HEVT_CMD_LEN_88XX 0x01AE 115 115 - #define REG_C2HEVT_CLEAR_8723B 0x01AF 116 116 - #define REG_MCUTST_1_8723B 0x01C0 117 117 - #define REG_MCUTST_WOWLAN_8723B 0x01C7 118 118 - #define REG_FMETHR_8723B 0x01C8 119 119 - #define REG_HMETFR_8723B 0x01CC 120 120 - #define REG_HMEBOX_0_8723B 0x01D0 121 121 - #define REG_HMEBOX_1_8723B 0x01D4 122 122 - #define REG_HMEBOX_2_8723B 0x01D8 123 123 - #define REG_HMEBOX_3_8723B 0x01DC 124 124 - #define REG_LLT_INIT_8723B 0x01E0 125 125 - #define REG_HMEBOX_EXT0_8723B 0x01F0 126 126 - #define REG_HMEBOX_EXT1_8723B 0x01F4 127 127 - #define REG_HMEBOX_EXT2_8723B 0x01F8 128 128 - #define REG_HMEBOX_EXT3_8723B 0x01FC 129 29 130 30 /* */ 131 31 /* */ 132 32 /* 0x0200h ~ 0x027Fh TXDMA Configuration */ 133 33 /* */ 134 34 /* */ 135 135 - #define REG_RQPN_8723B 0x0200 136 136 - #define REG_FIFOPAGE_8723B 0x0204 137 137 - #define REG_DWBCN0_CTRL_8723B REG_TDECTRL 138 138 - #define REG_TXDMA_OFFSET_CHK_8723B 0x020C 139 139 - #define REG_TXDMA_STATUS_8723B 0x0210 140 140 - #define REG_RQPN_NPQ_8723B 0x0214 141 35 #define REG_DWBCN1_CTRL_8723B 0x0228 142 142 - 143 143 - /* */ 144 144 - /* */ 145 145 - /* 0x0280h ~ 0x02FFh RXDMA Configuration */ 146 146 - /* */ 147 147 - /* */ 148 148 - #define REG_RXDMA_AGG_PG_TH_8723B 0x0280 149 149 - #define REG_FW_UPD_RDPTR_8723B 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */ 150 150 - #define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */ 151 151 - #define REG_RXPKT_NUM_8723B 0x0287 /* The number of packets in RXPKTBUF. */ 152 152 - #define REG_RXDMA_STATUS_8723B 0x0288 153 153 - #define REG_RXDMA_PRO_8723B 0x0290 154 154 - #define REG_EARLY_MODE_CONTROL_8723B 0x02BC 155 155 - #define REG_RSVD5_8723B 0x02F0 156 156 - #define REG_RSVD6_8723B 0x02F4 157 157 - 158 158 - /* */ 159 159 - /* */ 160 160 - /* 0x0300h ~ 0x03FFh PCIe */ 161 161 - /* */ 162 162 - /* */ 163 163 - #define REG_PCIE_CTRL_REG_8723B 0x0300 164 164 - #define REG_INT_MIG_8723B 0x0304 /* Interrupt Migration */ 165 165 - #define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor Address */ 166 166 - #define REG_HQ_DESA_8723B 0x0310 /* TX High Queue Descriptor Address */ 167 167 - #define REG_MGQ_DESA_8723B 0x0318 /* TX Manage Queue Descriptor Address */ 168 168 - #define REG_VOQ_DESA_8723B 0x0320 /* TX VO Queue Descriptor Address */ 169 169 - #define REG_VIQ_DESA_8723B 0x0328 /* TX VI Queue Descriptor Address */ 170 170 - #define REG_BEQ_DESA_8723B 0x0330 /* TX BE Queue Descriptor Address */ 171 171 - #define REG_BKQ_DESA_8723B 0x0338 /* TX BK Queue Descriptor Address */ 172 172 - #define REG_RX_DESA_8723B 0x0340 /* RX Queue Descriptor Address */ 173 173 - #define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */ 174 174 - #define REG_DBI_RDATA_8723B 0x034C /* DBI Read Data */ 175 175 - #define REG_DBI_ADDR_8723B 0x0350 /* DBI Address */ 176 176 - #define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */ 177 177 - #define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */ 178 178 - #define REG_MDIO_RDATA_8723B 0x0356 /* MDIO for Reads PCIE PHY */ 179 179 - #define REG_MDIO_CTL_8723B 0x0358 /* MDIO for Control */ 180 180 - #define REG_DBG_SEL_8723B 0x0360 /* Debug Selection Register */ 181 181 - #define REG_PCIE_HRPWM_8723B 0x0361 /* PCIe RPWM */ 182 182 - #define REG_PCIE_HCPWM_8723B 0x0363 /* PCIe CPWM */ 183 183 - #define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */ 184 36 185 37 /* spec version 11 */ 186 38 /* */ ··· 40 188 /* 0x0400h ~ 0x047Fh Protocol Configuration */ 41 189 /* */ 42 190 /* */ 43 43 - #define REG_VOQ_INFORMATION_8723B 0x0400 44 44 - #define REG_VIQ_INFORMATION_8723B 0x0404 45 45 - #define REG_BEQ_INFORMATION_8723B 0x0408 46 46 - #define REG_BKQ_INFORMATION_8723B 0x040C 47 47 - #define REG_MGQ_INFORMATION_8723B 0x0410 48 48 - #define REG_HGQ_INFORMATION_8723B 0x0414 49 49 - #define REG_BCNQ_INFORMATION_8723B 0x0418 50 50 - #define REG_TXPKT_EMPTY_8723B 0x041A 51 51 - 52 191 #define REG_FWHW_TXQ_CTRL_8723B 0x0420 53 53 - #define REG_HWSEQ_CTRL_8723B 0x0423 54 54 - #define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424 55 55 - #define REG_TXPKTBUF_MGQ_BDNY_8723B 0x0425 56 56 - #define REG_LIFECTRL_CTRL_8723B 0x0426 57 57 - #define REG_MULTI_BCNQ_OFFSET_8723B 0x0427 58 58 - #define REG_SPEC_SIFS_8723B 0x0428 59 59 - #define REG_RL_8723B 0x042A 60 60 - #define REG_TXBF_CTRL_8723B 0x042C 61 61 - #define REG_DARFRC_8723B 0x0430 62 62 - #define REG_RARFRC_8723B 0x0438 63 63 - #define REG_RRSR_8723B 0x0440 64 192 #define REG_ARFR0_8723B 0x0444 65 193 #define REG_ARFR1_8723B 0x044C 66 194 #define REG_CCK_CHECK_8723B 0x0454 67 195 #define REG_AMPDU_MAX_TIME_8723B 0x0456 68 68 - #define REG_TXPKTBUF_BCNQ_BDNY1_8723B 0x0457 69 196 70 197 #define REG_AMPDU_MAX_LENGTH_8723B 0x0458 71 71 - #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B 0x045D 72 72 - #define REG_NDPA_OPT_CTRL_8723B 0x045F 73 73 - #define REG_FAST_EDCA_CTRL_8723B 0x0460 74 74 - #define REG_RD_RESP_PKT_TH_8723B 0x0463 75 198 #define REG_DATA_SC_8723B 0x0483 76 76 - #define REG_TXRPT_START_OFFSET 0x04AC 77 77 - #define REG_POWER_STAGE1_8723B 0x04B4 78 78 - #define REG_POWER_STAGE2_8723B 0x04B8 79 79 - #define REG_AMPDU_BURST_MODE_8723B 0x04BC 80 80 - #define REG_PKT_VO_VI_LIFE_TIME_8723B 0x04C0 81 81 - #define REG_PKT_BE_BK_LIFE_TIME_8723B 0x04C2 82 82 - #define REG_STBC_SETTING_8723B 0x04C4 83 83 - #define REG_HT_SINGLE_AMPDU_8723B 0x04C7 84 84 - #define REG_PROT_MODE_CTRL_8723B 0x04C8 85 199 #define REG_MAX_AGGR_NUM_8723B 0x04CA 86 86 - #define REG_RTS_MAX_AGGR_NUM_8723B 0x04CB 87 87 - #define REG_BAR_MODE_CTRL_8723B 0x04CC 88 88 - #define REG_RA_TRY_RATE_AGG_LMT_8723B 0x04CF 89 89 - #define REG_MACID_PKT_DROP0_8723B 0x04D0 90 90 - #define REG_MACID_PKT_SLEEP_8723B 0x04D4 91 200 92 201 /* */ 93 202 /* */ 94 203 /* 0x0500h ~ 0x05FFh EDCA Configuration */ 95 204 /* */ 96 205 /* */ 97 97 - #define REG_EDCA_VO_PARAM_8723B 0x0500 98 98 - #define REG_EDCA_VI_PARAM_8723B 0x0504 99 99 - #define REG_EDCA_BE_PARAM_8723B 0x0508 100 100 - #define REG_EDCA_BK_PARAM_8723B 0x050C 101 101 - #define REG_BCNTCFG_8723B 0x0510 102 206 #define REG_PIFS_8723B 0x0512 103 103 - #define REG_RDG_PIFS_8723B 0x0513 104 104 - #define REG_SIFS_CTX_8723B 0x0514 105 105 - #define REG_SIFS_TRX_8723B 0x0516 106 106 - #define REG_AGGR_BREAK_TIME_8723B 0x051A 107 107 - #define REG_SLOT_8723B 0x051B 108 108 - #define REG_TX_PTCL_CTRL_8723B 0x0520 109 109 - #define REG_TXPAUSE_8723B 0x0522 110 110 - #define REG_DIS_TXREQ_CLR_8723B 0x0523 111 111 - #define REG_RD_CTRL_8723B 0x0524 112 112 - /* */ 113 113 - /* Format for offset 540h-542h: */ 114 114 - /* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. */ 115 115 - /* [7:4]: Reserved. */ 116 116 - /* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. */ 117 117 - /* [23:20]: Reserved */ 118 118 - /* Description: */ 119 119 - /* | */ 120 120 - /* |<--Setup--|--Hold------------>| */ 121 121 - /* --------------|---------------------- */ 122 122 - /* | */ 123 123 - /* TBTT */ 124 124 - /* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. */ 125 125 - /* Described by Designer Tim and Bruce, 2011-01-14. */ 126 126 - /* */ 127 127 - #define REG_TBTT_PROHIBIT_8723B 0x0540 128 128 - #define REG_RD_NAV_NXT_8723B 0x0544 129 129 - #define REG_NAV_PROT_LEN_8723B 0x0546 130 130 - #define REG_BCN_CTRL_8723B 0x0550 131 131 - #define REG_BCN_CTRL_1_8723B 0x0551 132 132 - #define REG_MBID_NUM_8723B 0x0552 133 133 - #define REG_DUAL_TSF_RST_8723B 0x0553 134 134 - #define REG_BCN_INTERVAL_8723B 0x0554 135 135 - #define REG_DRVERLYINT_8723B 0x0558 136 136 - #define REG_BCNDMATIM_8723B 0x0559 137 137 - #define REG_ATIMWND_8723B 0x055A 138 138 - #define REG_USTIME_TSF_8723B 0x055C 139 139 - #define REG_BCN_MAX_ERR_8723B 0x055D 140 140 - #define REG_RXTSF_OFFSET_CCK_8723B 0x055E 141 141 - #define REG_RXTSF_OFFSET_OFDM_8723B 0x055F 142 142 - #define REG_TSFTR_8723B 0x0560 143 143 - #define REG_CTWND_8723B 0x0572 144 144 - #define REG_SECONDARY_CCA_CTRL_8723B 0x0577 145 145 - #define REG_PSTIMER_8723B 0x0580 146 146 - #define REG_TIMER0_8723B 0x0584 147 147 - #define REG_TIMER1_8723B 0x0588 148 148 - #define REG_ACMHWCTRL_8723B 0x05C0 149 149 - #define REG_SCH_TXCMD_8723B 0x05F8 150 207 151 208 /* 0x0600h ~ 0x07FFh WMAC Configuration */ 152 152 - #define REG_MAC_CR_8723B 0x0600 153 153 - #define REG_TCR_8723B 0x0604 154 154 - #define REG_RCR_8723B 0x0608 155 209 #define REG_RX_PKT_LIMIT_8723B 0x060C 156 156 - #define REG_RX_DLK_TIME_8723B 0x060D 157 157 - #define REG_RX_DRVINFO_SZ_8723B 0x060F 158 210 159 159 - #define REG_MACID_8723B 0x0610 160 160 - #define REG_BSSID_8723B 0x0618 161 161 - #define REG_MAR_8723B 0x0620 162 162 - #define REG_MBIDCAMCFG_8723B 0x0628 163 163 - 164 164 - #define REG_USTIME_EDCA_8723B 0x0638 165 165 - #define REG_MAC_SPEC_SIFS_8723B 0x063A 166 166 - #define REG_RESP_SIFP_CCK_8723B 0x063C 167 167 - #define REG_RESP_SIFS_OFDM_8723B 0x063E 168 168 - #define REG_ACKTO_8723B 0x0640 169 169 - #define REG_CTS2TO_8723B 0x0641 170 170 - #define REG_EIFS_8723B 0x0642 171 171 - 172 172 - #define REG_NAV_UPPER_8723B 0x0652 /* unit of 128 */ 173 211 #define REG_TRXPTCL_CTL_8723B 0x0668 174 174 - 175 175 - /* Security */ 176 176 - #define REG_CAMCMD_8723B 0x0670 177 177 - #define REG_CAMWRITE_8723B 0x0674 178 178 - #define REG_CAMREAD_8723B 0x0678 179 179 - #define REG_CAMDBG_8723B 0x067C 180 180 - #define REG_SECCFG_8723B 0x0680 181 181 - 182 182 - /* Power */ 183 183 - #define REG_WOW_CTRL_8723B 0x0690 184 184 - #define REG_PS_RX_INFO_8723B 0x0692 185 185 - #define REG_UAPSD_TID_8723B 0x0693 186 186 - #define REG_WKFMCAM_CMD_8723B 0x0698 187 187 - #define REG_WKFMCAM_NUM_8723B 0x0698 188 188 - #define REG_WKFMCAM_RWD_8723B 0x069C 189 189 - #define REG_RXFLTMAP0_8723B 0x06A0 190 190 - #define REG_RXFLTMAP1_8723B 0x06A2 191 191 - #define REG_RXFLTMAP2_8723B 0x06A4 192 192 - #define REG_BCN_PSR_RPT_8723B 0x06A8 193 193 - #define REG_BT_COEX_TABLE_8723B 0x06C0 194 194 - #define REG_BFMER0_INFO_8723B 0x06E4 195 195 - #define REG_BFMER1_INFO_8723B 0x06EC 196 196 - #define REG_CSI_RPT_PARAM_BW20_8723B 0x06F4 197 197 - #define REG_CSI_RPT_PARAM_BW40_8723B 0x06F8 198 198 - #define REG_CSI_RPT_PARAM_BW80_8723B 0x06FC 199 199 - 200 200 - /* Hardware Port 2 */ 201 201 - #define REG_MACID1_8723B 0x0700 202 202 - #define REG_BSSID1_8723B 0x0708 203 203 - #define REG_BFMEE_SEL_8723B 0x0714 204 204 - #define REG_SND_PTCL_CTRL_8723B 0x0718 205 205 - 206 206 - /* Redifine 8192C register definition for compatibility */ 207 207 - 208 208 - /* TODO: use these definition when using REG_xxx naming rule. */ 209 209 - /* NOTE: DO NOT Remove these definition. Use later. */ 210 210 - #define EFUSE_CTRL_8723B REG_EFUSE_CTRL_8723B /* E-Fuse Control. */ 211 211 - #define EFUSE_TEST_8723B REG_EFUSE_TEST_8723B /* E-Fuse Test. */ 212 212 - #define MSR_8723B (REG_CR_8723B + 2) /* Media Status register */ 213 213 - #define ISR_8723B REG_HISR0_8723B 214 214 - #define TSFR_8723B REG_TSFTR_8723B /* Timing Sync Function Timer Register. */ 215 215 - 216 216 - #define PBP_8723B REG_PBP_8723B 217 217 - 218 218 - /* Redifine MACID register, to compatible prior ICs. */ 219 219 - #define IDR0_8723B REG_MACID_8723B /* MAC ID Register, Offset 0x0050-0x0053 */ 220 220 - #define IDR4_8723B (REG_MACID_8723B + 4) /* MAC ID Register, Offset 0x0054-0x0055 */ 221 221 - 222 222 - /* 9. Security Control Registers (Offset:) */ 223 223 - #define RWCAM_8723B REG_CAMCMD_8723B /* IN 8190 Data Sheet is called CAMcmd */ 224 224 - #define WCAMI_8723B REG_CAMWRITE_8723B /* Software write CAM input content */ 225 225 - #define RCAMO_8723B REG_CAMREAD_8723B /* Software read/write CAM config */ 226 226 - #define CAMDBG_8723B REG_CAMDBG_8723B 227 227 - #define SECR_8723B REG_SECCFG_8723B /* Security Configuration Register */ 228 228 - 229 229 - /* 8195 IMR/ISR bits (offset 0xB0, 8bits) */ 230 230 - #define IMR_DISABLED_8723B 0 231 231 - /* IMR DW0(0x00B0-00B3) Bit 0-31 */ 232 232 - #define IMR_TIMER2_8723B BIT31 /* Timeout interrupt 2 */ 233 233 - #define IMR_TIMER1_8723B BIT30 /* Timeout interrupt 1 */ 234 234 - #define IMR_PSTIMEOUT_8723B BIT29 /* Power Save Time Out Interrupt */ 235 235 - #define IMR_GTINT4_8723B BIT28 /* When GTIMER4 expires, this bit is set to 1 */ 236 236 - #define IMR_GTINT3_8723B BIT27 /* When GTIMER3 expires, this bit is set to 1 */ 237 237 - #define IMR_TXBCN0ERR_8723B BIT26 /* Transmit Beacon0 Error */ 238 238 - #define IMR_TXBCN0OK_8723B BIT25 /* Transmit Beacon0 OK */ 239 239 - #define IMR_TSF_BIT32_TOGGLE_8723B BIT24 /* TSF Timer BIT32 toggle indication interrupt */ 240 240 - #define IMR_BCNDMAINT0_8723B BIT20 /* Beacon DMA Interrupt 0 */ 241 241 - #define IMR_BCNDERR0_8723B BIT16 /* Beacon Queue DMA OK0 */ 242 242 - #define IMR_HSISR_IND_ON_INT_8723B BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 243 243 - #define IMR_BCNDMAINT_E_8723B BIT14 /* Beacon DMA Interrupt Extension for Win7 */ 244 244 - #define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */ 245 245 - #define IMR_C2HCMD_8723B BIT10 /* CPU to Host Command INT Status, Write 1 clear */ 246 246 - #define IMR_CPWM2_8723B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ 247 247 - #define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ 248 248 - #define IMR_HIGHDOK_8723B BIT7 /* High Queue DMA OK */ 249 249 - #define IMR_MGNTDOK_8723B BIT6 /* Management Queue DMA OK */ 250 250 - #define IMR_BKDOK_8723B BIT5 /* AC_BK DMA OK */ 251 251 - #define IMR_BEDOK_8723B BIT4 /* AC_BE DMA OK */ 252 252 - #define IMR_VIDOK_8723B BIT3 /* AC_VI DMA OK */ 253 253 - #define IMR_VODOK_8723B BIT2 /* AC_VO DMA OK */ 254 254 - #define IMR_RDU_8723B BIT1 /* Rx Descriptor Unavailable */ 255 255 - #define IMR_ROK_8723B BIT0 /* Receive DMA OK */ 256 256 - 257 257 - /* IMR DW1(0x00B4-00B7) Bit 0-31 */ 258 258 - #define IMR_BCNDMAINT7_8723B BIT27 /* Beacon DMA Interrupt 7 */ 259 259 - #define IMR_BCNDMAINT6_8723B BIT26 /* Beacon DMA Interrupt 6 */ 260 260 - #define IMR_BCNDMAINT5_8723B BIT25 /* Beacon DMA Interrupt 5 */ 261 261 - #define IMR_BCNDMAINT4_8723B BIT24 /* Beacon DMA Interrupt 4 */ 262 262 - #define IMR_BCNDMAINT3_8723B BIT23 /* Beacon DMA Interrupt 3 */ 263 263 - #define IMR_BCNDMAINT2_8723B BIT22 /* Beacon DMA Interrupt 2 */ 264 264 - #define IMR_BCNDMAINT1_8723B BIT21 /* Beacon DMA Interrupt 1 */ 265 265 - #define IMR_BCNDOK7_8723B BIT20 /* Beacon Queue DMA OK Interrupt 7 */ 266 266 - #define IMR_BCNDOK6_8723B BIT19 /* Beacon Queue DMA OK Interrupt 6 */ 267 267 - #define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrupt 5 */ 268 268 - #define IMR_BCNDOK4_8723B BIT17 /* Beacon Queue DMA OK Interrupt 4 */ 269 269 - #define IMR_BCNDOK3_8723B BIT16 /* Beacon Queue DMA OK Interrupt 3 */ 270 270 - #define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK Interrupt 2 */ 271 271 - #define IMR_BCNDOK1_8723B BIT14 /* Beacon Queue DMA OK Interrupt 1 */ 272 272 - #define IMR_ATIMEND_E_8723B BIT13 /* ATIM Window End Extension for Win7 */ 273 273 - #define IMR_TXERR_8723B BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ 274 274 - #define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, Write 1 clear */ 275 275 - #define IMR_TXFOVW_8723B BIT9 /* Transmit FIFO Overflow */ 276 276 - #define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */ 277 277 - 278 278 - /* 2 ACMHWCTRL 0x05C0 */ 279 279 - #define ACMHW_HWEN_8723B BIT(0) 280 280 - #define ACMHW_VOQEN_8723B BIT(1) 281 281 - #define ACMHW_VIQEN_8723B BIT(2) 282 282 - #define ACMHW_BEQEN_8723B BIT(3) 283 283 - #define ACMHW_VOQSTATUS_8723B BIT(5) 284 284 - #define ACMHW_VIQSTATUS_8723B BIT(6) 285 285 - #define ACMHW_BEQSTATUS_8723B BIT(7) 286 286 - 287 287 - /* 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) */ 288 288 - #define RCR_TCPOFLD_EN BIT25 /* Enable TCP checksum offload */ 289 212 290 213 #endif /* #ifndef __INC_HAL8723BREG_H */

+2 -15

drivers/staging/rtl8723bs/hal/HalHWImg8723B_BB.c

reviewed

··· 70 70 return false; 71 71 } 72 72 73 73 - static bool CheckNegative( 74 74 - struct dm_odm_t *pDM_Odm, const u32 Condition1, const u32 Condition2 75 75 - ) 76 76 - { 77 77 - return true; 78 78 - } 79 79 - 80 73 /****************************************************************************** 81 74 * AGC_TAB.TXT 82 75 ******************************************************************************/ ··· 237 244 READ_NEXT_PAIR(v1, v2, i); 238 245 } else { 239 246 READ_NEXT_PAIR(v1, v2, i); 240 240 - if (!CheckNegative(pDM_Odm, v1, v2)) 241 241 - bMatched = false; 242 242 - else 243 243 - bMatched = true; 247 247 + bMatched = true; 244 248 READ_NEXT_PAIR(v1, v2, i); 245 249 } 246 250 ··· 496 506 READ_NEXT_PAIR(v1, v2, i); 497 507 } else { 498 508 READ_NEXT_PAIR(v1, v2, i); 499 499 - if (!CheckNegative(pDM_Odm, v1, v2)) 500 500 - bMatched = false; 501 501 - else 502 502 - bMatched = true; 509 509 + bMatched = true; 503 510 READ_NEXT_PAIR(v1, v2, i); 504 511 } 505 512

+1 -11

drivers/staging/rtl8723bs/hal/HalHWImg8723B_MAC.c

reviewed

··· 68 68 return false; 69 69 } 70 70 71 71 - static bool CheckNegative( 72 72 - struct dm_odm_t *pDM_Odm, const u32 Condition1, const u32 Condition2 73 73 - ) 74 74 - { 75 75 - return true; 76 76 - } 77 77 - 78 71 /****************************************************************************** 79 72 * MAC_REG.TXT 80 73 ******************************************************************************/ ··· 207 214 READ_NEXT_PAIR(v1, v2, i); 208 215 } else { 209 216 READ_NEXT_PAIR(v1, v2, i); 210 210 - if (!CheckNegative(pDM_Odm, v1, v2)) 211 211 - bMatched = false; 212 212 - else 213 213 - bMatched = true; 217 217 + bMatched = true; 214 218 READ_NEXT_PAIR(v1, v2, i); 215 219 } 216 220

+1 -11

drivers/staging/rtl8723bs/hal/HalHWImg8723B_RF.c

reviewed

··· 78 78 return false; 79 79 } 80 80 81 81 - static bool CheckNegative( 82 82 - struct dm_odm_t *pDM_Odm, const u32 Condition1, const u32 Condition2 83 83 - ) 84 84 - { 85 85 - return true; 86 86 - } 87 87 - 88 81 /****************************************************************************** 89 82 * RadioA.TXT 90 83 ******************************************************************************/ ··· 238 245 READ_NEXT_PAIR(v1, v2, i); 239 246 } else { 240 247 READ_NEXT_PAIR(v1, v2, i); 241 241 - if (!CheckNegative(pDM_Odm, v1, v2)) 242 242 - bMatched = false; 243 243 - else 244 244 - bMatched = true; 248 248 + bMatched = true; 245 249 READ_NEXT_PAIR(v1, v2, i); 246 250 } 247 251

+2 -2

drivers/staging/rtl8723bs/hal/odm.h

reviewed

··· 76 76 77 77 /* Remove DIG by Yuchen */ 78 78 79 79 - /* Remoce BB power saving by Yuchn */ 79 79 + /* Remove BB power saving by Yuchn */ 80 80 81 81 /* Remove DIG by yuchen */ 82 82 ··· 878 878 struct odm_mac_status_info *pMacInfo; 879 879 /* MAC_INFO_88E MacInfo; */ 880 880 881 881 - /* Different Team independt structure?? */ 881 881 + /* Different Team independent structure?? */ 882 882 883 883 /* */ 884 884 /* TX_RTP_CMN TX_retrpo; */

+2 -2

drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c

reviewed

··· 700 700 rtw_write8(padapter, REG_BCN_CTRL, val8); 701 701 702 702 /* To make sure that if there exists an adapter which would like to send beacon. */ 703 703 - /* If exists, the origianl value of 0x422[6] will be 1, we should check this to */ 703 703 + /* If exists, the original value of 0x422[6] will be 1, we should check this to */ 704 704 /* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ 705 705 /* the beacon cannot be sent by HW. */ 706 706 /* 2010.06.23. Added by tynli. */ ··· 964 964 rtw_write8(padapter, REG_BCN_CTRL, val8); 965 965 966 966 /* To make sure that if there exists an adapter which would like to send beacon. */ 967 967 - /* If exists, the origianl value of 0x422[6] will be 1, we should check this to */ 967 967 + /* If exists, the original value of 0x422[6] will be 1, we should check this to */ 968 968 /* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ 969 969 /* the beacon cannot be sent by HW. */ 970 970 /* 2010.06.23. Added by tynli. */

+1 -881

drivers/staging/rtl8723bs/include/Hal8192CPhyReg.h

reviewed

··· 46 46 /* 5. Other definition for BB/RF R/W */ 47 47 /* */ 48 48 49 49 - 50 50 - /* */ 51 51 - /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ 52 52 - /* 1. Page1(0x100) */ 53 53 - /* */ 54 54 - #define rPMAC_Reset 0x100 55 55 - #define rPMAC_TxStart 0x104 56 56 - #define rPMAC_TxLegacySIG 0x108 57 57 - #define rPMAC_TxHTSIG1 0x10c 58 58 - #define rPMAC_TxHTSIG2 0x110 59 59 - #define rPMAC_PHYDebug 0x114 60 60 - #define rPMAC_TxPacketNum 0x118 61 61 - #define rPMAC_TxIdle 0x11c 62 62 - #define rPMAC_TxMACHeader0 0x120 63 63 - #define rPMAC_TxMACHeader1 0x124 64 64 - #define rPMAC_TxMACHeader2 0x128 65 65 - #define rPMAC_TxMACHeader3 0x12c 66 66 - #define rPMAC_TxMACHeader4 0x130 67 67 - #define rPMAC_TxMACHeader5 0x134 68 68 - #define rPMAC_TxDataType 0x138 69 69 - #define rPMAC_TxRandomSeed 0x13c 70 70 - #define rPMAC_CCKPLCPPreamble 0x140 71 71 - #define rPMAC_CCKPLCPHeader 0x144 72 72 - #define rPMAC_CCKCRC16 0x148 73 73 - #define rPMAC_OFDMRxCRC32OK 0x170 74 74 - #define rPMAC_OFDMRxCRC32Er 0x174 75 75 - #define rPMAC_OFDMRxParityEr 0x178 76 76 - #define rPMAC_OFDMRxCRC8Er 0x17c 77 77 - #define rPMAC_CCKCRxRC16Er 0x180 78 78 - #define rPMAC_CCKCRxRC32Er 0x184 79 79 - #define rPMAC_CCKCRxRC32OK 0x188 80 80 - #define rPMAC_TxStatus 0x18c 81 81 - 82 82 - /* */ 83 83 - /* 2. Page2(0x200) */ 84 84 - /* */ 85 85 - /* The following two definition are only used for USB interface. */ 86 86 - #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */ 87 87 - #define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */ 88 88 - 89 49 /* */ 90 50 /* 3. Page8(0x800) */ 91 51 /* */ 92 52 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */ 93 93 - 94 94 - #define rFPGA0_TxInfo 0x804 /* Status report?? */ 95 95 - #define rFPGA0_PSDFunction 0x808 96 96 - 97 97 - #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 98 98 - 99 99 - #define rFPGA0_RFTiming1 0x810 /* Useless now */ 100 100 - #define rFPGA0_RFTiming2 0x814 101 53 102 54 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 103 55 #define rFPGA0_XA_HSSIParameter2 0x824 ··· 65 113 #define rFPGA0_XA_LSSIParameter 0x840 66 114 #define rFPGA0_XB_LSSIParameter 0x844 67 115 68 68 - #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 69 69 - #define rFPGA0_RFSleepUpParameter 0x854 70 70 - 71 71 - #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 72 116 #define rFPGA0_XCD_SwitchControl 0x85c 73 117 74 118 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ ··· 75 127 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 76 128 #define rFPGA0_XCD_RFInterfaceSW 0x874 77 129 78 78 - #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 79 79 - #define rFPGA0_XCD_RFParameter 0x87c 80 80 - 81 81 - #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 82 82 - #define rFPGA0_AnalogParameter2 0x884 83 83 - #define rFPGA0_AnalogParameter3 0x888 /* Useless now */ 84 84 - #define rFPGA0_AnalogParameter4 0x88c 85 85 - 86 130 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Transceiver LSSI Readback */ 87 131 #define rFPGA0_XB_LSSIReadBack 0x8a4 88 88 - #define rFPGA0_XC_LSSIReadBack 0x8a8 89 89 - #define rFPGA0_XD_LSSIReadBack 0x8ac 90 132 91 91 - #define rFPGA0_PSDReport 0x8b4 /* Useless now */ 92 133 #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ 93 134 #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ 94 94 - #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now RF Interface Readback Value */ 95 95 - #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 96 135 97 136 /* */ 98 137 /* 4. Page9(0x900) */ 99 138 /* */ 100 139 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC RF BW Setting?? */ 101 140 102 102 - #define rFPGA1_TxBlock 0x904 /* Useless now */ 103 103 - #define rFPGA1_DebugSelect 0x908 /* Useless now */ 104 104 - #define rFPGA1_TxInfo 0x90c /* Useless now Status report?? */ 105 141 #define rS0S1_PathSwitch 0x948 106 142 107 143 /* */ ··· 95 163 #define rCCK0_System 0xa00 96 164 97 165 #define rCCK0_AFESetting 0xa04 /* Disable init gain now Select RX path by RSSI */ 98 98 - #define rCCK0_CCA 0xa08 /* Disable init gain now Init gain */ 99 166 100 100 - #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ 101 101 - #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 102 102 - 103 103 - #define rCCK0_RxHP 0xa14 104 104 - 105 105 - #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ 106 106 - #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 107 107 - 108 108 - #define rCCK0_TxFilter1 0xa20 109 109 - #define rCCK0_TxFilter2 0xa24 110 110 - #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 111 111 - #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 112 112 - #define rCCK0_TRSSIReport 0xa50 113 113 - #define rCCK0_RxReport 0xa54 /* 0xa57 */ 114 114 - #define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 115 115 - #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 116 167 /* */ 117 168 /* PageB(0xB00) */ 118 169 /* */ 119 119 - #define rPdp_AntA 0xb00 120 120 - #define rPdp_AntA_4 0xb04 121 121 - #define rConfig_Pmpd_AntA 0xb28 122 170 #define rConfig_AntA 0xb68 123 171 #define rConfig_AntB 0xb6c 124 124 - #define rPdp_AntB 0xb70 125 125 - #define rPdp_AntB_4 0xb74 126 126 - #define rConfig_Pmpd_AntB 0xb98 127 127 - #define rAPK 0xbd8 128 172 129 173 /* */ 130 174 /* 6. PageC(0xC00) */ 131 175 /* */ 132 132 - #define rOFDM0_LSTF 0xc00 133 133 - 134 176 #define rOFDM0_TRxPathEnable 0xc04 135 177 #define rOFDM0_TRMuxPar 0xc08 136 136 - #define rOFDM0_TRSWIsolation 0xc0c 137 178 138 138 - #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 139 179 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */ 140 140 - #define rOFDM0_XBRxAFE 0xc18 141 180 #define rOFDM0_XBRxIQImbalance 0xc1c 142 142 - #define rOFDM0_XCRxAFE 0xc20 143 143 - #define rOFDM0_XCRxIQImbalance 0xc24 144 144 - #define rOFDM0_XDRxAFE 0xc28 145 145 - #define rOFDM0_XDRxIQImbalance 0xc2c 146 146 - 147 147 - #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD DM tune init gain */ 148 148 - #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 149 149 - #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 150 150 - #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 151 181 152 182 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 153 153 - #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 154 154 - #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 155 183 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 156 184 157 157 - #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 158 158 - #define rOFDM0_XAAGCCore2 0xc54 159 159 - #define rOFDM0_XBAGCCore1 0xc58 160 160 - #define rOFDM0_XBAGCCore2 0xc5c 161 161 - #define rOFDM0_XCAGCCore1 0xc60 162 162 - #define rOFDM0_XCAGCCore2 0xc64 163 163 - #define rOFDM0_XDAGCCore1 0xc68 164 164 - #define rOFDM0_XDAGCCore2 0xc6c 165 165 - 166 166 - #define rOFDM0_AGCParameter1 0xc70 167 167 - #define rOFDM0_AGCParameter2 0xc74 168 185 #define rOFDM0_AGCRSSITable 0xc78 169 169 - #define rOFDM0_HTSTFAGC 0xc7c 170 186 171 187 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 172 172 - #define rOFDM0_XATxAFE 0xc84 173 188 #define rOFDM0_XBTxIQImbalance 0xc88 174 174 - #define rOFDM0_XBTxAFE 0xc8c 175 175 - #define rOFDM0_XCTxIQImbalance 0xc90 176 189 #define rOFDM0_XCTxAFE 0xc94 177 177 - #define rOFDM0_XDTxIQImbalance 0xc98 178 190 #define rOFDM0_XDTxAFE 0xc9c 179 191 180 192 #define rOFDM0_RxIQExtAnta 0xca0 181 181 - #define rOFDM0_TxCoeff1 0xca4 182 182 - #define rOFDM0_TxCoeff2 0xca8 183 183 - #define rOFDM0_TxCoeff3 0xcac 184 184 - #define rOFDM0_TxCoeff4 0xcb0 185 185 - #define rOFDM0_TxCoeff5 0xcb4 186 186 - #define rOFDM0_TxCoeff6 0xcb8 187 187 - #define rOFDM0_RxHPParameter 0xce0 188 193 #define rOFDM0_TxPseudoNoiseWgt 0xce4 189 189 - #define rOFDM0_FrameSync 0xcf0 190 190 - #define rOFDM0_DFSReport 0xcf4 191 194 192 195 /* */ 193 196 /* 7. PageD(0xD00) */ 194 197 /* */ 195 198 #define rOFDM1_LSTF 0xd00 196 196 - #define rOFDM1_TRxPathEnable 0xd04 197 197 - 198 198 - #define rOFDM1_CFO 0xd08 /* No setting now */ 199 199 - #define rOFDM1_CSI1 0xd10 200 200 - #define rOFDM1_SBD 0xd14 201 201 - #define rOFDM1_CSI2 0xd18 202 202 - #define rOFDM1_CFOTracking 0xd2c 203 203 - #define rOFDM1_TRxMesaure1 0xd34 204 204 - #define rOFDM1_IntfDet 0xd3c 205 205 - #define rOFDM1_PseudoNoiseStateAB 0xd50 206 206 - #define rOFDM1_PseudoNoiseStateCD 0xd54 207 207 - #define rOFDM1_RxPseudoNoiseWgt 0xd58 208 208 - 209 209 - #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 210 210 - #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 211 211 - #define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 212 212 - 213 213 - #define rOFDM_ShortCFOAB 0xdac /* No setting now */ 214 214 - #define rOFDM_ShortCFOCD 0xdb0 215 215 - #define rOFDM_LongCFOAB 0xdb4 216 216 - #define rOFDM_LongCFOCD 0xdb8 217 217 - #define rOFDM_TailCFOAB 0xdbc 218 218 - #define rOFDM_TailCFOCD 0xdc0 219 219 - #define rOFDM_PWMeasure1 0xdc4 220 220 - #define rOFDM_PWMeasure2 0xdc8 221 221 - #define rOFDM_BWReport 0xdcc 222 222 - #define rOFDM_AGCReport 0xdd0 223 223 - #define rOFDM_RxSNR 0xdd4 224 224 - #define rOFDM_RxEVMCSI 0xdd8 225 225 - #define rOFDM_SIGReport 0xddc 226 226 - 227 199 228 200 /* */ 229 201 /* 8. PageE(0xE00) */ ··· 152 316 #define rRx_IQK_Tone_B 0xe54 153 317 #define rTx_IQK_PI_B 0xe58 154 318 #define rRx_IQK_PI_B 0xe5c 155 155 - #define rIQK_AGC_Cont 0xe60 156 319 157 320 #define rBlue_Tooth 0xe6c 158 321 #define rRx_Wait_CCA 0xe70 ··· 166 331 #define rTx_Power_Before_IQK_A 0xe94 167 332 #define rTx_Power_After_IQK_A 0xe9c 168 333 169 169 - #define rRx_Power_Before_IQK_A 0xea0 170 334 #define rRx_Power_Before_IQK_A_2 0xea4 171 171 - #define rRx_Power_After_IQK_A 0xea8 172 335 #define rRx_Power_After_IQK_A_2 0xeac 173 173 - 174 174 - #define rTx_Power_Before_IQK_B 0xeb4 175 175 - #define rTx_Power_After_IQK_B 0xebc 176 176 - 177 177 - #define rRx_Power_Before_IQK_B 0xec0 178 178 - #define rRx_Power_Before_IQK_B_2 0xec4 179 179 - #define rRx_Power_After_IQK_B 0xec8 180 180 - #define rRx_Power_After_IQK_B_2 0xecc 181 336 182 337 #define rRx_OFDM 0xed0 183 338 #define rRx_Wait_RIFS 0xed4 ··· 177 352 #define rPMPD_ANAEN 0xeec 178 353 179 354 /* */ 180 180 - /* 7. RF Register 0x00-0x2E (RF 8256) */ 181 181 - /* RF-0222D 0x00-3F */ 182 182 - /* */ 183 183 - /* Zebra1 */ 184 184 - #define rZebra1_HSSIEnable 0x0 /* Useless now */ 185 185 - #define rZebra1_TRxEnable1 0x1 186 186 - #define rZebra1_TRxEnable2 0x2 187 187 - #define rZebra1_AGC 0x4 188 188 - #define rZebra1_ChargePump 0x5 189 189 - #define rZebra1_Channel 0x7 /* RF channel switch */ 190 190 - 191 191 - /* endif */ 192 192 - #define rZebra1_TxGain 0x8 /* Useless now */ 193 193 - #define rZebra1_TxLPF 0x9 194 194 - #define rZebra1_RxLPF 0xb 195 195 - #define rZebra1_RxHPFCorner 0xc 196 196 - 197 197 - /* Zebra4 */ 198 198 - #define rGlobalCtrl 0 /* Useless now */ 199 199 - #define rRTL8256_TxLPF 19 200 200 - #define rRTL8256_RxLPF 11 201 201 - 202 202 - /* RTL8258 */ 203 203 - #define rRTL8258_TxLPF 0x11 /* Useless now */ 204 204 - #define rRTL8258_RxLPF 0x13 205 205 - #define rRTL8258_RSSILPF 0xa 206 206 - 207 207 - /* */ 208 355 /* RL6052 Register definition */ 209 356 /* */ 210 357 #define RF_AC 0x00 /* */ 211 358 212 212 - #define RF_IQADJ_G1 0x01 /* */ 213 213 - #define RF_IQADJ_G2 0x02 /* */ 214 214 - #define RF_BS_PA_APSET_G1_G4 0x03 215 215 - #define RF_BS_PA_APSET_G5_G8 0x04 216 216 - #define RF_POW_TRSW 0x05 /* */ 217 217 - 218 218 - #define RF_GAIN_RX 0x06 /* */ 219 219 - #define RF_GAIN_TX 0x07 /* */ 220 220 - 221 359 #define RF_TXM_IDAC 0x08 /* */ 222 222 - #define RF_IPA_G 0x09 /* */ 223 223 - #define RF_TXBIAS_G 0x0A 224 224 - #define RF_TXPA_AG 0x0B 225 225 - #define RF_IPA_A 0x0C /* */ 226 226 - #define RF_TXBIAS_A 0x0D 227 227 - #define RF_BS_PA_APSET_G9_G11 0x0E 228 228 - #define RF_BS_IQGEN 0x0F /* */ 229 360 230 230 - #define RF_MODE1 0x10 /* */ 231 231 - #define RF_MODE2 0x11 /* */ 232 232 - 233 233 - #define RF_RX_AGC_HP 0x12 /* */ 234 234 - #define RF_TX_AGC 0x13 /* */ 235 235 - #define RF_BIAS 0x14 /* */ 236 236 - #define RF_IPA 0x15 /* */ 237 237 - #define RF_TXBIAS 0x16 /* */ 238 238 - #define RF_POW_ABILITY 0x17 /* */ 239 239 - #define RF_MODE_AG 0x18 /* */ 240 240 - #define rRfChannel 0x18 /* RF channel and BW switch */ 241 361 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 242 242 - #define RF_TOP 0x19 /* */ 243 243 - 244 244 - #define RF_RX_G1 0x1A /* */ 245 245 - #define RF_RX_G2 0x1B /* */ 246 246 - 247 247 - #define RF_RX_BB2 0x1C /* */ 248 248 - #define RF_RX_BB1 0x1D /* */ 249 249 - 250 250 - #define RF_RCK1 0x1E /* */ 251 251 - #define RF_RCK2 0x1F /* */ 252 252 - 253 253 - #define RF_TX_G1 0x20 /* */ 254 254 - #define RF_TX_G2 0x21 /* */ 255 255 - #define RF_TX_G3 0x22 /* */ 256 256 - 257 257 - #define RF_TX_BB1 0x23 /* */ 258 258 - 259 259 - #define RF_T_METER 0x24 /* */ 260 260 - 261 261 - #define RF_SYN_G1 0x25 /* RF TX Power control */ 262 262 - #define RF_SYN_G2 0x26 /* RF TX Power control */ 263 263 - #define RF_SYN_G3 0x27 /* RF TX Power control */ 264 264 - #define RF_SYN_G4 0x28 /* RF TX Power control */ 265 265 - #define RF_SYN_G5 0x29 /* RF TX Power control */ 266 266 - #define RF_SYN_G6 0x2A /* RF TX Power control */ 267 267 - #define RF_SYN_G7 0x2B /* RF TX Power control */ 268 268 - #define RF_SYN_G8 0x2C /* RF TX Power control */ 269 362 270 363 #define RF_RCK_OS 0x30 /* RF TX PA control */ 271 364 272 365 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 273 366 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 274 274 - #define RF_TXPA_G3 0x33 /* RF TX PA control */ 275 275 - #define RF_TX_BIAS_A 0x35 276 276 - #define RF_TX_BIAS_D 0x36 277 277 - #define RF_LOBF_9 0x38 278 278 - #define RF_RXRF_A3 0x3C /* */ 279 279 - #define RF_TRSW 0x3F 280 367 281 281 - #define RF_TXRF_A2 0x41 282 282 - #define RF_TXPA_G4 0x46 283 283 - #define RF_TXPA_A4 0x4B 284 284 - #define RF_0x52 0x52 285 368 #define RF_WE_LUT 0xEF 286 286 - #define RF_S0S1 0xB0 287 287 - 288 288 - /* */ 289 289 - /* Bit Mask */ 290 290 - /* */ 291 291 - /* 1. Page1(0x100) */ 292 292 - #define bBBResetB 0x100 /* Useless now? */ 293 293 - #define bGlobalResetB 0x200 294 294 - #define bOFDMTxStart 0x4 295 295 - #define bCCKTxStart 0x8 296 296 - #define bCRC32Debug 0x100 297 297 - #define bPMACLoopback 0x10 298 298 - #define bTxLSIG 0xffffff 299 299 - #define bOFDMTxRate 0xf 300 300 - #define bOFDMTxReserved 0x10 301 301 - #define bOFDMTxLength 0x1ffe0 302 302 - #define bOFDMTxParity 0x20000 303 303 - #define bTxHTSIG1 0xffffff 304 304 - #define bTxHTMCSRate 0x7f 305 305 - #define bTxHTBW 0x80 306 306 - #define bTxHTLength 0xffff00 307 307 - #define bTxHTSIG2 0xffffff 308 308 - #define bTxHTSmoothing 0x1 309 309 - #define bTxHTSounding 0x2 310 310 - #define bTxHTReserved 0x4 311 311 - #define bTxHTAggreation 0x8 312 312 - #define bTxHTSTBC 0x30 313 313 - #define bTxHTAdvanceCoding 0x40 314 314 - #define bTxHTShortGI 0x80 315 315 - #define bTxHTNumberHT_LTF 0x300 316 316 - #define bTxHTCRC8 0x3fc00 317 317 - #define bCounterReset 0x10000 318 318 - #define bNumOfOFDMTx 0xffff 319 319 - #define bNumOfCCKTx 0xffff0000 320 320 - #define bTxIdleInterval 0xffff 321 321 - #define bOFDMService 0xffff0000 322 322 - #define bTxMACHeader 0xffffffff 323 323 - #define bTxDataInit 0xff 324 324 - #define bTxHTMode 0x100 325 325 - #define bTxDataType 0x30000 326 326 - #define bTxRandomSeed 0xffffffff 327 327 - #define bCCKTxPreamble 0x1 328 328 - #define bCCKTxSFD 0xffff0000 329 329 - #define bCCKTxSIG 0xff 330 330 - #define bCCKTxService 0xff00 331 331 - #define bCCKLengthExt 0x8000 332 332 - #define bCCKTxLength 0xffff0000 333 333 - #define bCCKTxCRC16 0xffff 334 334 - #define bCCKTxStatus 0x1 335 335 - #define bOFDMTxStatus 0x2 336 336 - 337 337 - #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) 338 369 339 370 /* 2. Page8(0x800) */ 340 371 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 341 341 - #define bJapanMode 0x2 342 342 - #define bCCKTxSC 0x30 343 343 - #define bCCKEn 0x1000000 344 344 - #define bOFDMEn 0x2000000 345 345 - 346 346 - #define bOFDMRxADCPhase 0x10000 /* Useless now */ 347 347 - #define bOFDMTxDACPhase 0x40000 348 348 - #define bXATxAGC 0x3f 349 349 - 350 350 - #define bAntennaSelect 0x0300 351 351 - 352 352 - #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 353 353 - #define bXCTxAGC 0xf000 354 354 - #define bXDTxAGC 0xf0000 355 355 - 356 356 - #define bPAStart 0xf0000000 /* Useless now */ 357 357 - #define bTRStart 0x00f00000 358 358 - #define bRFStart 0x0000f000 359 359 - #define bBBStart 0x000000f0 360 360 - #define bBBCCKStart 0x0000000f 361 361 - #define bPAEnd 0xf /* Reg0x814 */ 362 362 - #define bTREnd 0x0f000000 363 363 - #define bRFEnd 0x000f0000 364 364 - #define bCCAMask 0x000000f0 /* T2R */ 365 365 - #define bR2RCCAMask 0x00000f00 366 366 - #define bHSSI_R2TDelay 0xf8000000 367 367 - #define bHSSI_T2RDelay 0xf80000 368 368 - #define bContTxHSSI 0x400 /* chane gain at continue Tx */ 369 369 - #define bIGFromCCK 0x200 370 370 - #define bAGCAddress 0x3f 371 371 - #define bRxHPTx 0x7000 372 372 - #define bRxHPT2R 0x38000 373 373 - #define bRxHPCCKIni 0xc0000 374 374 - #define bAGCTxCode 0xc00000 375 375 - #define bAGCRxCode 0x300000 376 372 377 373 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 378 374 #define b3WireAddressLength 0x400 379 375 380 380 - #define b3WireRFPowerDown 0x1 /* Useless now */ 381 381 - /* define bHWSISelect 0x8 */ 382 382 - #define b2GPAPEPolarity 0x80000000 383 383 - #define bRFSW_TxDefaultAnt 0x3 384 384 - #define bRFSW_TxOptionAnt 0x30 385 385 - #define bRFSW_RxDefaultAnt 0x300 386 386 - #define bRFSW_RxOptionAnt 0x3000 387 387 - #define bRFSI_3WireData 0x1 388 388 - #define bRFSI_3WireClock 0x2 389 389 - #define bRFSI_3WireLoad 0x4 390 390 - #define bRFSI_3WireRW 0x8 391 391 - #define bRFSI_3Wire 0xf 392 392 - 393 376 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 394 394 - 395 395 - #define bRFSI_TRSW 0x20 /* Useless now */ 396 396 - #define bRFSI_TRSWB 0x40 397 397 - #define bRFSI_ANTSW 0x100 398 398 - #define bRFSI_ANTSWB 0x200 399 399 - #define bRFSI_PAPE 0x400 400 400 - #define bBandSelect 0x1 401 401 - #define bHTSIG2_GI 0x80 402 402 - #define bHTSIG2_Smoothing 0x01 403 403 - #define bHTSIG2_Sounding 0x02 404 404 - #define bHTSIG2_Aggreaton 0x08 405 405 - #define bHTSIG2_STBC 0x30 406 406 - #define bHTSIG2_AdvCoding 0x40 407 407 - #define bHTSIG2_NumOfHTLTF 0x300 408 408 - #define bHTSIG2_CRC8 0x3fc 409 409 - #define bHTSIG1_MCS 0x7f 410 410 - #define bHTSIG1_BandWidth 0x80 411 411 - #define bHTSIG1_HTLength 0xffff 412 412 - #define bLSIG_Rate 0xf 413 413 - #define bLSIG_Reserved 0x10 414 414 - #define bLSIG_Length 0x1fffe 415 415 - #define bLSIG_Parity 0x20 416 416 - #define bCCKRxPhase 0x4 417 377 418 378 #define bLSSIReadAddress 0x7f800000 /* T65 RF */ 419 379 ··· 206 596 207 597 #define bLSSIReadBackData 0xfffff /* T65 RF */ 208 598 209 209 - #define bLSSIReadOKFlag 0x1000 /* Useless now */ 210 210 - #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 211 211 - #define bRegulator0Standby 0x1 212 212 - #define bRegulatorPLLStandby 0x2 213 213 - #define bRegulator1Standby 0x4 214 214 - #define bPLLPowerUp 0x8 215 215 - #define bDPLLPowerUp 0x10 216 216 - #define bDA10PowerUp 0x20 217 217 - #define bAD7PowerUp 0x200 218 218 - #define bDA6PowerUp 0x2000 219 219 - #define bXtalPowerUp 0x4000 220 220 - #define b40MDClkPowerUP 0x8000 221 221 - #define bDA6DebugMode 0x20000 222 222 - #define bDA6Swing 0x380000 223 223 - 224 224 - #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 225 225 - 226 226 - #define b80MClkDelay 0x18000000 /* Useless */ 227 227 - #define bAFEWatchDogEnable 0x20000000 228 228 - 229 229 - #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ 230 230 - #define bXtalCap23 0x3 231 231 - #define bXtalCap92x 0x0f000000 232 232 - #define bXtalCap 0x0f000000 233 233 - 234 234 - #define bIntDifClkEnable 0x400 /* Useless */ 235 235 - #define bExtSigClkEnable 0x800 236 236 - #define bBandgapMbiasPowerUp 0x10000 237 237 - #define bAD11SHGain 0xc0000 238 238 - #define bAD11InputRange 0x700000 239 239 - #define bAD11OPCurrent 0x3800000 240 240 - #define bIPathLoopback 0x4000000 241 241 - #define bQPathLoopback 0x8000000 242 242 - #define bAFELoopback 0x10000000 243 243 - #define bDA10Swing 0x7e0 244 244 - #define bDA10Reverse 0x800 245 245 - #define bDAClkSource 0x1000 246 246 - #define bAD7InputRange 0x6000 247 247 - #define bAD7Gain 0x38000 248 248 - #define bAD7OutputCMMode 0x40000 249 249 - #define bAD7InputCMMode 0x380000 250 250 - #define bAD7Current 0xc00000 251 251 - #define bRegulatorAdjust 0x7000000 252 252 - #define bAD11PowerUpAtTx 0x1 253 253 - #define bDA10PSAtTx 0x10 254 254 - #define bAD11PowerUpAtRx 0x100 255 255 - #define bDA10PSAtRx 0x1000 256 256 - #define bCCKRxAGCFormat 0x200 257 257 - #define bPSDFFTSamplepPoint 0xc000 258 258 - #define bPSDAverageNum 0x3000 259 259 - #define bIQPathControl 0xc00 260 260 - #define bPSDFreq 0x3ff 261 261 - #define bPSDAntennaPath 0x30 262 262 - #define bPSDIQSwitch 0x40 263 263 - #define bPSDRxTrigger 0x400000 264 264 - #define bPSDTxTrigger 0x80000000 265 265 - #define bPSDSineToneScale 0x7f000000 266 266 - #define bPSDReport 0xffff 267 267 - 268 268 - /* 3. Page9(0x900) */ 269 269 - #define bOFDMTxSC 0x30000000 /* Useless */ 270 270 - #define bCCKTxOn 0x1 271 271 - #define bOFDMTxOn 0x2 272 272 - #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ 273 273 - #define bDebugItem 0xff /* reset debug page and LWord */ 274 274 - #define bAntL 0x10 275 275 - #define bAntNonHT 0x100 276 276 - #define bAntHT1 0x1000 277 277 - #define bAntHT2 0x10000 278 278 - #define bAntHT1S1 0x100000 279 279 - #define bAntNonHTS1 0x1000000 280 280 - 281 599 /* 4. PageA(0xA00) */ 282 282 - #define bCCKBBMode 0x3 /* Useless */ 283 283 - #define bCCKTxPowerSaving 0x80 284 284 - #define bCCKRxPowerSaving 0x40 285 285 - 286 600 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 287 287 - 288 288 - #define bCCKScramble 0x8 /* Useless */ 289 289 - #define bCCKAntDiversity 0x8000 290 290 - #define bCCKCarrierRecovery 0x4000 291 291 - #define bCCKTxRate 0x3000 292 292 - #define bCCKDCCancel 0x0800 293 293 - #define bCCKISICancel 0x0400 294 294 - #define bCCKMatchFilter 0x0200 295 295 - #define bCCKEqualizer 0x0100 296 296 - #define bCCKPreambleDetect 0x800000 297 297 - #define bCCKFastFalseCCA 0x400000 298 298 - #define bCCKChEstStart 0x300000 299 299 - #define bCCKCCACount 0x080000 300 300 - #define bCCKcs_lim 0x070000 301 301 - #define bCCKBistMode 0x80000000 302 302 - #define bCCKCCAMask 0x40000000 303 303 - #define bCCKTxDACPhase 0x4 304 304 - #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 305 305 - #define bCCKr_cp_mode0 0x0100 306 306 - #define bCCKTxDCOffset 0xf0 307 307 - #define bCCKRxDCOffset 0xf 308 308 - #define bCCKCCAMode 0xc000 309 309 - #define bCCKFalseCS_lim 0x3f00 310 310 - #define bCCKCS_ratio 0xc00000 311 311 - #define bCCKCorgBit_sel 0x300000 312 312 - #define bCCKPD_lim 0x0f0000 313 313 - #define bCCKNewCCA 0x80000000 314 314 - #define bCCKRxHPofIG 0x8000 315 315 - #define bCCKRxIG 0x7f00 316 316 - #define bCCKLNAPolarity 0x800000 317 317 - #define bCCKRx1stGain 0x7f0000 318 318 - #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 319 319 - #define bCCKRxAGCSatLevel 0x1f000000 320 320 - #define bCCKRxAGCSatCount 0xe0 321 321 - #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 322 322 - #define bCCKFixedRxAGC 0x8000 323 323 - #define bCCKAntennaPolarity 0x2000 324 324 - #define bCCKTxFilterType 0x0c00 325 325 - #define bCCKRxAGCReportType 0x0300 326 326 - #define bCCKRxDAGCEn 0x80000000 327 327 - #define bCCKRxDAGCPeriod 0x20000000 328 328 - #define bCCKRxDAGCSatLevel 0x1f000000 329 329 - #define bCCKTimingRecovery 0x800000 330 330 - #define bCCKTxC0 0x3f0000 331 331 - #define bCCKTxC1 0x3f000000 332 332 - #define bCCKTxC2 0x3f 333 333 - #define bCCKTxC3 0x3f00 334 334 - #define bCCKTxC4 0x3f0000 335 335 - #define bCCKTxC5 0x3f000000 336 336 - #define bCCKTxC6 0x3f 337 337 - #define bCCKTxC7 0x3f00 338 338 - #define bCCKDebugPort 0xff0000 339 339 - #define bCCKDACDebug 0x0f000000 340 340 - #define bCCKFalseAlarmEnable 0x8000 341 341 - #define bCCKFalseAlarmRead 0x4000 342 342 - #define bCCKTRSSI 0x7f 343 343 - #define bCCKRxAGCReport 0xfe 344 344 - #define bCCKRxReport_AntSel 0x80000000 345 345 - #define bCCKRxReport_MFOff 0x40000000 346 346 - #define bCCKRxRxReport_SQLoss 0x20000000 347 347 - #define bCCKRxReport_Pktloss 0x10000000 348 348 - #define bCCKRxReport_Lockedbit 0x08000000 349 349 - #define bCCKRxReport_RateError 0x04000000 350 350 - #define bCCKRxReport_RxRate 0x03000000 351 351 - #define bCCKRxFACounterLower 0xff 352 352 - #define bCCKRxFACounterUpper 0xff000000 353 353 - #define bCCKRxHPAGCStart 0xe000 354 354 - #define bCCKRxHPAGCFinal 0x1c00 355 355 - #define bCCKRxFalseAlarmEnable 0x8000 356 356 - #define bCCKFACounterFreeze 0x4000 357 357 - #define bCCKTxPathSel 0x10000000 358 358 - #define bCCKDefaultRxPath 0xc000000 359 359 - #define bCCKOptionRxPath 0x3000000 360 360 - 361 361 - /* 5. PageC(0xC00) */ 362 362 - #define bNumOfSTF 0x3 /* Useless */ 363 363 - #define bShift_L 0xc0 364 364 - #define bGI_TH 0xc 365 365 - #define bRxPathA 0x1 366 366 - #define bRxPathB 0x2 367 367 - #define bRxPathC 0x4 368 368 - #define bRxPathD 0x8 369 369 - #define bTxPathA 0x1 370 370 - #define bTxPathB 0x2 371 371 - #define bTxPathC 0x4 372 372 - #define bTxPathD 0x8 373 373 - #define bTRSSIFreq 0x200 374 374 - #define bADCBackoff 0x3000 375 375 - #define bDFIRBackoff 0xc000 376 376 - #define bTRSSILatchPhase 0x10000 377 377 - #define bRxIDCOffset 0xff 378 378 - #define bRxQDCOffset 0xff00 379 379 - #define bRxDFIRMode 0x1800000 380 380 - #define bRxDCNFType 0xe000000 381 381 - #define bRXIQImb_A 0x3ff 382 382 - #define bRXIQImb_B 0xfc00 383 383 - #define bRXIQImb_C 0x3f0000 384 384 - #define bRXIQImb_D 0xffc00000 385 385 - #define bDC_dc_Notch 0x60000 386 386 - #define bRxNBINotch 0x1f000000 387 387 - #define bPD_TH 0xf 388 388 - #define bPD_TH_Opt2 0xc000 389 389 - #define bPWED_TH 0x700 390 390 - #define bIfMF_Win_L 0x800 391 391 - #define bPD_Option 0x1000 392 392 - #define bMF_Win_L 0xe000 393 393 - #define bBW_Search_L 0x30000 394 394 - #define bwin_enh_L 0xc0000 395 395 - #define bBW_TH 0x700000 396 396 - #define bED_TH2 0x3800000 397 397 - #define bBW_option 0x4000000 398 398 - #define bRatio_TH 0x18000000 399 399 - #define bWindow_L 0xe0000000 400 400 - #define bSBD_Option 0x1 401 401 - #define bFrame_TH 0x1c 402 402 - #define bFS_Option 0x60 403 403 - #define bDC_Slope_check 0x80 404 404 - #define bFGuard_Counter_DC_L 0xe00 405 405 - #define bFrame_Weight_Short 0x7000 406 406 - #define bSub_Tune 0xe00000 407 407 - #define bFrame_DC_Length 0xe000000 408 408 - #define bSBD_start_offset 0x30000000 409 409 - #define bFrame_TH_2 0x7 410 410 - #define bFrame_GI2_TH 0x38 411 411 - #define bGI2_Sync_en 0x40 412 412 - #define bSarch_Short_Early 0x300 413 413 - #define bSarch_Short_Late 0xc00 414 414 - #define bSarch_GI2_Late 0x70000 415 415 - #define bCFOAntSum 0x1 416 416 - #define bCFOAcc 0x2 417 417 - #define bCFOStartOffset 0xc 418 418 - #define bCFOLookBack 0x70 419 419 - #define bCFOSumWeight 0x80 420 420 - #define bDAGCEnable 0x10000 421 421 - #define bTXIQImb_A 0x3ff 422 422 - #define bTXIQImb_B 0xfc00 423 423 - #define bTXIQImb_C 0x3f0000 424 424 - #define bTXIQImb_D 0xffc00000 425 425 - #define bTxIDCOffset 0xff 426 426 - #define bTxQDCOffset 0xff00 427 427 - #define bTxDFIRMode 0x10000 428 428 - #define bTxPesudoNoiseOn 0x4000000 429 429 - #define bTxPesudoNoise_A 0xff 430 430 - #define bTxPesudoNoise_B 0xff00 431 431 - #define bTxPesudoNoise_C 0xff0000 432 432 - #define bTxPesudoNoise_D 0xff000000 433 433 - #define bCCADropOption 0x20000 434 434 - #define bCCADropThres 0xfff00000 435 435 - #define bEDCCA_H 0xf 436 436 - #define bEDCCA_L 0xf0 437 437 - #define bLambda_ED 0x300 438 438 - #define bRxInitialGain 0x7f 439 439 - #define bRxAntDivEn 0x80 440 440 - #define bRxAGCAddressForLNA 0x7f00 441 441 - #define bRxHighPowerFlow 0x8000 442 442 - #define bRxAGCFreezeThres 0xc0000 443 443 - #define bRxFreezeStep_AGC1 0x300000 444 444 - #define bRxFreezeStep_AGC2 0xc00000 445 445 - #define bRxFreezeStep_AGC3 0x3000000 446 446 - #define bRxFreezeStep_AGC0 0xc000000 447 447 - #define bRxRssi_Cmp_En 0x10000000 448 448 - #define bRxQuickAGCEn 0x20000000 449 449 - #define bRxAGCFreezeThresMode 0x40000000 450 450 - #define bRxOverFlowCheckType 0x80000000 451 451 - #define bRxAGCShift 0x7f 452 452 - #define bTRSW_Tri_Only 0x80 453 453 - #define bPowerThres 0x300 454 454 - #define bRxAGCEn 0x1 455 455 - #define bRxAGCTogetherEn 0x2 456 456 - #define bRxAGCMin 0x4 457 457 - #define bRxHP_Ini 0x7 458 458 - #define bRxHP_TRLNA 0x70 459 459 - #define bRxHP_RSSI 0x700 460 460 - #define bRxHP_BBP1 0x7000 461 461 - #define bRxHP_BBP2 0x70000 462 462 - #define bRxHP_BBP3 0x700000 463 463 - #define bRSSI_H 0x7f0000 /* the threshold for high power */ 464 464 - #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ 465 465 - #define bRxSettle_TRSW 0x7 466 466 - #define bRxSettle_LNA 0x38 467 467 - #define bRxSettle_RSSI 0x1c0 468 468 - #define bRxSettle_BBP 0xe00 469 469 - #define bRxSettle_RxHP 0x7000 470 470 - #define bRxSettle_AntSW_RSSI 0x38000 471 471 - #define bRxSettle_AntSW 0xc0000 472 472 - #define bRxProcessTime_DAGC 0x300000 473 473 - #define bRxSettle_HSSI 0x400000 474 474 - #define bRxProcessTime_BBPPW 0x800000 475 475 - #define bRxAntennaPowerShift 0x3000000 476 476 - #define bRSSITableSelect 0xc000000 477 477 - #define bRxHP_Final 0x7000000 478 478 - #define bRxHTSettle_BBP 0x7 479 479 - #define bRxHTSettle_HSSI 0x8 480 480 - #define bRxHTSettle_RxHP 0x70 481 481 - #define bRxHTSettle_BBPPW 0x80 482 482 - #define bRxHTSettle_Idle 0x300 483 483 - #define bRxHTSettle_Reserved 0x1c00 484 484 - #define bRxHTRxHPEn 0x8000 485 485 - #define bRxHTAGCFreezeThres 0x30000 486 486 - #define bRxHTAGCTogetherEn 0x40000 487 487 - #define bRxHTAGCMin 0x80000 488 488 - #define bRxHTAGCEn 0x100000 489 489 - #define bRxHTDAGCEn 0x200000 490 490 - #define bRxHTRxHP_BBP 0x1c00000 491 491 - #define bRxHTRxHP_Final 0xe0000000 492 492 - #define bRxPWRatioTH 0x3 493 493 - #define bRxPWRatioEn 0x4 494 494 - #define bRxMFHold 0x3800 495 495 - #define bRxPD_Delay_TH1 0x38 496 496 - #define bRxPD_Delay_TH2 0x1c0 497 497 - #define bRxPD_DC_COUNT_MAX 0x600 498 498 - /* define bRxMF_Hold 0x3800 */ 499 499 - #define bRxPD_Delay_TH 0x8000 500 500 - #define bRxProcess_Delay 0xf0000 501 501 - #define bRxSearchrange_GI2_Early 0x700000 502 502 - #define bRxFrame_Guard_Counter_L 0x3800000 503 503 - #define bRxSGI_Guard_L 0xc000000 504 504 - #define bRxSGI_Search_L 0x30000000 505 505 - #define bRxSGI_TH 0xc0000000 506 506 - #define bDFSCnt0 0xff 507 507 - #define bDFSCnt1 0xff00 508 508 - #define bDFSFlag 0xf0000 509 509 - #define bMFWeightSum 0x300000 510 510 - #define bMinIdxTH 0x7f000000 511 511 - #define bDAFormat 0x40000 512 512 - #define bTxChEmuEnable 0x01000000 513 513 - #define bTRSWIsolation_A 0x7f 514 514 - #define bTRSWIsolation_B 0x7f00 515 515 - #define bTRSWIsolation_C 0x7f0000 516 516 - #define bTRSWIsolation_D 0x7f000000 517 517 - #define bExtLNAGain 0x7c00 518 518 - 519 519 - /* 6. PageE(0xE00) */ 520 520 - #define bSTBCEn 0x4 /* Useless */ 521 521 - #define bAntennaMapping 0x10 522 522 - #define bNss 0x20 523 523 - #define bCFOAntSumD 0x200 524 524 - #define bPHYCounterReset 0x8000000 525 525 - #define bCFOReportGet 0x4000000 526 526 - #define bOFDMContinueTx 0x10000000 527 527 - #define bOFDMSingleCarrier 0x20000000 528 528 - #define bOFDMSingleTone 0x40000000 529 529 - /* define bRxPath1 0x01 */ 530 530 - /* define bRxPath2 0x02 */ 531 531 - /* define bRxPath3 0x04 */ 532 532 - /* define bRxPath4 0x08 */ 533 533 - /* define bTxPath1 0x10 */ 534 534 - /* define bTxPath2 0x20 */ 535 535 - #define bHTDetect 0x100 536 536 - #define bCFOEn 0x10000 537 537 - #define bCFOValue 0xfff00000 538 538 - #define bSigTone_Re 0x3f 539 539 - #define bSigTone_Im 0x7f00 540 540 - #define bCounter_CCA 0xffff 541 541 - #define bCounter_ParityFail 0xffff0000 542 542 - #define bCounter_RateIllegal 0xffff 543 543 - #define bCounter_CRC8Fail 0xffff0000 544 544 - #define bCounter_MCSNoSupport 0xffff 545 545 - #define bCounter_FastSync 0xffff 546 546 - #define bShortCFO 0xfff 547 547 - #define bShortCFOTLength 12 /* total */ 548 548 - #define bShortCFOFLength 11 /* fraction */ 549 549 - #define bLongCFO 0x7ff 550 550 - #define bLongCFOTLength 11 551 551 - #define bLongCFOFLength 11 552 552 - #define bTailCFO 0x1fff 553 553 - #define bTailCFOTLength 13 554 554 - #define bTailCFOFLength 12 555 555 - #define bmax_en_pwdB 0xffff 556 556 - #define bCC_power_dB 0xffff0000 557 557 - #define bnoise_pwdB 0xffff 558 558 - #define bPowerMeasTLength 10 559 559 - #define bPowerMeasFLength 3 560 560 - #define bRx_HT_BW 0x1 561 561 - #define bRxSC 0x6 562 562 - #define bRx_HT 0x8 563 563 - #define bNB_intf_det_on 0x1 564 564 - #define bIntf_win_len_cfg 0x30 565 565 - #define bNB_Intf_TH_cfg 0x1c0 566 566 - #define bRFGain 0x3f 567 567 - #define bTableSel 0x40 568 568 - #define bTRSW 0x80 569 569 - #define bRxSNR_A 0xff 570 570 - #define bRxSNR_B 0xff00 571 571 - #define bRxSNR_C 0xff0000 572 572 - #define bRxSNR_D 0xff000000 573 573 - #define bSNREVMTLength 8 574 574 - #define bSNREVMFLength 1 575 575 - #define bCSI1st 0xff 576 576 - #define bCSI2nd 0xff00 577 577 - #define bRxEVM1st 0xff0000 578 578 - #define bRxEVM2nd 0xff000000 579 579 - #define bSIGEVM 0xff 580 580 - #define bPWDB 0xff00 581 581 - #define bSGIEN 0x10000 582 582 - 583 583 - #define bSFactorQAM1 0xf /* Useless */ 584 584 - #define bSFactorQAM2 0xf0 585 585 - #define bSFactorQAM3 0xf00 586 586 - #define bSFactorQAM4 0xf000 587 587 - #define bSFactorQAM5 0xf0000 588 588 - #define bSFactorQAM6 0xf0000 589 589 - #define bSFactorQAM7 0xf00000 590 590 - #define bSFactorQAM8 0xf000000 591 591 - #define bSFactorQAM9 0xf0000000 592 592 - #define bCSIScheme 0x100000 593 593 - 594 594 - #define bNoiseLvlTopSet 0x3 /* Useless */ 595 595 - #define bChSmooth 0x4 596 596 - #define bChSmoothCfg1 0x38 597 597 - #define bChSmoothCfg2 0x1c0 598 598 - #define bChSmoothCfg3 0xe00 599 599 - #define bChSmoothCfg4 0x7000 600 600 - #define bMRCMode 0x800000 601 601 - #define bTHEVMCfg 0x7000000 602 602 - 603 603 - #define bLoopFitType 0x1 /* Useless */ 604 604 - #define bUpdCFO 0x40 605 605 - #define bUpdCFOOffData 0x80 606 606 - #define bAdvUpdCFO 0x100 607 607 - #define bAdvTimeCtrl 0x800 608 608 - #define bUpdClko 0x1000 609 609 - #define bFC 0x6000 610 610 - #define bTrackingMode 0x8000 611 611 - #define bPhCmpEnable 0x10000 612 612 - #define bUpdClkoLTF 0x20000 613 613 - #define bComChCFO 0x40000 614 614 - #define bCSIEstiMode 0x80000 615 615 - #define bAdvUpdEqz 0x100000 616 616 - #define bUChCfg 0x7000000 617 617 - #define bUpdEqz 0x8000000 618 618 - 619 619 - /* Rx Pseduo noise */ 620 620 - #define bRxPesudoNoiseOn 0x20000000 /* Useless */ 621 621 - #define bRxPesudoNoise_A 0xff 622 622 - #define bRxPesudoNoise_B 0xff00 623 623 - #define bRxPesudoNoise_C 0xff0000 624 624 - #define bRxPesudoNoise_D 0xff000000 625 625 - #define bPesudoNoiseState_A 0xffff 626 626 - #define bPesudoNoiseState_B 0xffff0000 627 627 - #define bPesudoNoiseState_C 0xffff 628 628 - #define bPesudoNoiseState_D 0xffff0000 629 629 - 630 630 - /* 7. RF Register */ 631 631 - /* Zebra1 */ 632 632 - #define bZebra1_HSSIEnable 0x8 /* Useless */ 633 633 - #define bZebra1_TRxControl 0xc00 634 634 - #define bZebra1_TRxGainSetting 0x07f 635 635 - #define bZebra1_RxCorner 0xc00 636 636 - #define bZebra1_TxChargePump 0x38 637 637 - #define bZebra1_RxChargePump 0x7 638 638 - #define bZebra1_ChannelNum 0xf80 639 639 - #define bZebra1_TxLPFBW 0x400 640 640 - #define bZebra1_RxLPFBW 0x600 641 641 - 642 642 - /* Zebra4 */ 643 643 - #define bRTL8256RegModeCtrl1 0x100 /* Useless */ 644 644 - #define bRTL8256RegModeCtrl0 0x40 645 645 - #define bRTL8256_TxLPFBW 0x18 646 646 - #define bRTL8256_RxLPFBW 0x600 647 647 - 648 648 - /* RTL8258 */ 649 649 - #define bRTL8258_TxLPFBW 0xc /* Useless */ 650 650 - #define bRTL8258_RxLPFBW 0xc00 651 651 - #define bRTL8258_RSSILPFBW 0xc0 652 652 - 653 601 654 602 /* */ 655 603 /* Other Definition */ 656 604 /* */ 657 657 - 658 658 - /* byte endable for sb_write */ 659 659 - #define bByte0 0x1 /* Useless */ 660 660 - #define bByte1 0x2 661 661 - #define bByte2 0x4 662 662 - #define bByte3 0x8 663 663 - #define bWord0 0x3 664 664 - #define bWord1 0xc 665 665 - #define bDWord 0xf 666 605 667 606 /* for PutRegsetting & GetRegSetting BitMask */ 668 607 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ ··· 224 1065 #define bMaskH3Bytes 0xffffff00 225 1066 #define bMask12Bits 0xfff 226 1067 #define bMaskH4Bits 0xf0000000 227 227 - #define bMaskOFDM_D 0xffc00000 228 228 - #define bMaskCCK 0x3f3f3f3f 229 229 - 230 1068 231 1069 #define bEnable 0x1 /* Useless */ 232 232 - #define bDisable 0x0 233 1070 234 234 - #define LeftAntenna 0x0 /* Useless */ 235 235 - #define RightAntenna 0x1 236 236 - 237 237 - #define tCheckTxStatus 500 /* 500ms Useless */ 238 238 - #define tUpdateRxCounter 100 /* 100ms */ 239 239 - 240 240 - #define rateCCK 0 /* Useless */ 241 241 - #define rateOFDM 1 242 242 - #define rateHT 2 243 243 - 244 244 - /* define Register-End */ 245 245 - #define bPMAC_End 0x1ff /* Useless */ 246 246 - #define bFPGAPHY0_End 0x8ff 247 247 - #define bFPGAPHY1_End 0x9ff 248 248 - #define bCCKPHY0_End 0xaff 249 249 - #define bOFDMPHY0_End 0xcff 250 250 - #define bOFDMPHY1_End 0xdff 251 251 - 252 252 - /* define max debug item in each debug page */ 253 253 - /* define bMaxItem_FPGA_PHY0 0x9 */ 254 254 - /* define bMaxItem_FPGA_PHY1 0x3 */ 255 255 - /* define bMaxItem_PHY_11B 0x16 */ 256 256 - /* define bMaxItem_OFDM_PHY0 0x29 */ 257 257 - /* define bMaxItem_OFDM_PHY1 0x0 */ 258 258 - 259 259 - #define bPMACControl 0x0 /* Useless */ 260 260 - #define bWMACControl 0x1 261 261 - #define bWNICControl 0x2 262 262 - 263 263 - #define PathA 0x0 /* Useless */ 264 264 - #define PathB 0x1 265 265 - #define PathC 0x2 266 266 - #define PathD 0x3 267 267 - 268 268 - /*--------------------------Define Parameters-------------------------------*/ 269 269 - 1071 1071 + #define rDPDT_control 0x92c 270 1072 271 1073 #endif /* __INC_HAL8192SPHYREG_H */

-11

drivers/staging/rtl8723bs/include/HalPwrSeqCmd.h

reviewed

··· 49 49 /*---------------------------------------------*/ 50 50 /* define the base address of each block */ 51 51 #define PWR_BASEADDR_MAC 0x00 52 52 - #define PWR_BASEADDR_USB 0x01 53 53 - #define PWR_BASEADDR_PCIE 0x02 54 52 #define PWR_BASEADDR_SDIO 0x03 55 53 56 54 /*---------------------------------------------*/ ··· 62 64 /*---------------------------------------------*/ 63 65 /* 3 The value of fab_msk: 4 bits */ 64 66 /*---------------------------------------------*/ 65 65 - #define PWR_FAB_TSMC_MSK BIT(0) 66 66 - #define PWR_FAB_UMC_MSK BIT(1) 67 67 #define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) 68 68 69 69 /*---------------------------------------------*/ 70 70 /* 3 The value of cut_msk: 8 bits */ 71 71 /*---------------------------------------------*/ 72 72 #define PWR_CUT_TESTCHIP_MSK BIT(0) 73 73 - #define PWR_CUT_A_MSK BIT(1) 74 74 - #define PWR_CUT_B_MSK BIT(2) 75 75 - #define PWR_CUT_C_MSK BIT(3) 76 76 - #define PWR_CUT_D_MSK BIT(4) 77 77 - #define PWR_CUT_E_MSK BIT(5) 78 78 - #define PWR_CUT_F_MSK BIT(6) 79 79 - #define PWR_CUT_G_MSK BIT(7) 80 73 #define PWR_CUT_ALL_MSK 0xFF 81 74 82 75

-1

drivers/staging/rtl8723bs/include/drv_types.h

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··· 490 490 } 491 491 492 492 /* HCI Related header file */ 493 493 - #include <sdio_osintf.h> 494 493 #include <sdio_ops.h> 495 494 #include <sdio_hal.h> 496 495

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drivers/staging/rtl8723bs/include/hal_com_h2c.h

reviewed

··· 9 9 10 10 #define H2C_RSVDPAGE_LOC_LEN 5 11 11 #define H2C_MEDIA_STATUS_RPT_LEN 3 12 12 - #define H2C_KEEP_ALIVE_CTRL_LEN 2 13 13 - #define H2C_DISCON_DECISION_LEN 3 14 14 - #define H2C_AP_OFFLOAD_LEN 3 15 15 - #define H2C_AP_WOW_GPIO_CTRL_LEN 4 16 16 - #define H2C_AP_PS_LEN 2 17 12 #define H2C_PWRMODE_LEN 7 18 13 #define H2C_PSTUNEPARAM_LEN 4 19 14 #define H2C_MACID_CFG_LEN 7 20 20 - #define H2C_BTMP_OPER_LEN 4 21 21 - #define H2C_WOWLAN_LEN 4 22 22 - #define H2C_REMOTE_WAKE_CTRL_LEN 3 23 23 - #define H2C_AOAC_GLOBAL_INFO_LEN 2 24 24 - #define H2C_AOAC_RSVDPAGE_LOC_LEN 7 25 25 - #define H2C_SCAN_OFFLOAD_CTRL_LEN 4 26 26 - #define H2C_BT_FW_PATCH_LEN 6 27 15 #define H2C_RSSI_SETTING_LEN 4 28 28 - #define H2C_AP_REQ_TXRPT_LEN 2 29 29 - #define H2C_FORCE_BT_TXPWR_LEN 3 30 30 - #define H2C_BCN_RSVDPAGE_LEN 5 31 31 - #define H2C_PROBERSP_RSVDPAGE_LEN 5 32 32 - 33 33 - /* _RSVDPAGE_LOC_CMD_0x00 */ 34 34 - #define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value) 35 35 - #define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+1, 0, 8, __Value) 36 36 - #define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+2, 0, 8, __Value) 37 37 - #define SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+3, 0, 8, __Value) 38 38 - #define SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+4, 0, 8, __Value) 39 39 - 40 40 - /* _MEDIA_STATUS_RPT_PARM_CMD_0x01 */ 41 41 - #define SET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) 42 42 - #define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) 43 43 - #define SET_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+1, 0, 8, __Value) 44 44 - #define SET_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+2, 0, 8, __Value) 45 45 - 46 46 - /* _KEEP_ALIVE_CMD_0x03 */ 47 47 - #define SET_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) 48 48 - #define SET_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) 49 49 - #define SET_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) 50 50 - #define SET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+1, 0, 8, __Value) 51 51 - 52 52 - /* _DISCONNECT_DECISION_CMD_0x04 */ 53 53 - #define SET_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) 54 54 - #define SET_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) 55 55 - #define SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+1, 0, 8, __Value) 56 56 - #define SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd+2, 0, 8, __Value) 57 57 - 58 58 - /* _WoWLAN PARAM_CMD_0x80 */ 59 59 - #define SET_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) 60 60 - #define SET_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) 61 61 - #define SET_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) 62 62 - #define SET_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) 63 63 - #define SET_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) 64 64 - #define SET_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value) 65 65 - #define SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) 66 66 - #define SET_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value) 67 67 - #define SET_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 7, __Value) 68 68 - #define SET_H2CCMD_WOWLAN_DATAPIN_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 7, 1, __Value) 69 69 - #define SET_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+2, 0, 8, __Value) 70 70 - /* define SET_H2CCMD_WOWLAN_GPIO_PULSE_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 1, __Value) */ 71 71 - #define SET_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+3, 0, 8, __Value) 72 72 - 73 73 - /* _REMOTE_WAKEUP_CMD_0x81 */ 74 74 - #define SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) 75 75 - #define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) 76 76 - #define SET_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) 77 77 - #define SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) 78 78 - #define SET_H2CCMD_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) 79 79 - #define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value) 80 80 - #define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 1, __Value) 81 81 - 82 82 - /* AOAC_GLOBAL_INFO_0x82 */ 83 83 - #define SET_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value) 84 84 - #define SET_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+1, 0, 8, __Value) 85 85 - 86 86 - /* AOAC_RSVDPAGE_LOC_0x83 */ 87 87 - #define SET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd), 0, 8, __Value) 88 88 - #define SET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+1, 0, 8, __Value) 89 89 - #define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+2, 0, 8, __Value) 90 90 - #define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+3, 0, 8, __Value) 91 91 - #define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT((__pH2CCmd)+4, 0, 8, __Value) 92 16 93 17 /* */ 94 18 /* Structure -------------------------------------------------- */

-792

drivers/staging/rtl8723bs/include/hal_com_reg.h

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··· 7 7 #ifndef __HAL_COMMON_REG_H__ 8 8 #define __HAL_COMMON_REG_H__ 9 9 10 10 - 11 11 - #define MAC_ADDR_LEN 6 12 12 - 13 13 - #define HAL_NAV_UPPER_UNIT 128 /* micro-second */ 14 14 - 15 15 - /* 8188E PKT_BUFF_ACCESS_CTRL value */ 16 16 - #define TXPKT_BUF_SELECT 0x69 17 17 - #define RXPKT_BUF_SELECT 0xA5 18 18 - #define DISABLE_TRXPKT_BUF_ACCESS 0x0 19 19 - 20 20 - /* */ 21 21 - /* */ 22 22 - /* */ 23 23 - 24 10 /* */ 25 11 /* */ 26 12 /* 0x0000h ~ 0x00FFh System Configuration */ 27 13 /* */ 28 14 /* */ 29 29 - #define REG_SYS_ISO_CTRL 0x0000 30 15 #define REG_SYS_FUNC_EN 0x0002 31 16 #define REG_APS_FSMCO 0x0004 32 17 #define REG_SYS_CLKR 0x0008 33 18 #define REG_9346CR 0x000A 34 19 #define REG_SYS_EEPROM_CTRL 0x000A 35 35 - #define REG_EE_VPD 0x000C 36 36 - #define REG_AFE_MISC 0x0010 37 37 - #define REG_SPS0_CTRL 0x0011 38 38 - #define REG_SPS0_CTRL_6 0x0016 39 39 - #define REG_POWER_OFF_IN_PROCESS 0x0017 40 40 - #define REG_SPS_OCP_CFG 0x0018 41 20 #define REG_RSV_CTRL 0x001C 42 21 #define REG_RF_CTRL 0x001F 43 43 - #define REG_LDOA15_CTRL 0x0020 44 44 - #define REG_LDOV12D_CTRL 0x0021 45 45 - #define REG_LDOHCI12_CTRL 0x0022 46 46 - #define REG_LPLDO_CTRL 0x0023 47 22 #define REG_AFE_XTAL_CTRL 0x0024 48 48 - #define REG_AFE_LDO_CTRL 0x0027 /* 1.5v for 8188EE test chip, 1.4v for MP chip */ 49 49 - #define REG_AFE_PLL_CTRL 0x0028 50 23 #define REG_MAC_PHY_CTRL 0x002c /* for 92d, DMDP, SMSP, DMSP contrl */ 51 51 - #define REG_APE_PLL_CTRL_EXT 0x002c 52 24 #define REG_EFUSE_CTRL 0x0030 53 25 #define REG_EFUSE_TEST 0x0034 54 26 #define REG_PWR_DATA 0x0038 55 55 - #define REG_CAL_TIMER 0x003C 56 56 - #define REG_ACLK_MON 0x003E 57 27 #define REG_GPIO_MUXCFG 0x0040 58 58 - #define REG_GPIO_IO_SEL 0x0042 59 59 - #define REG_MAC_PINMUX_CFG 0x0043 60 60 - #define REG_GPIO_PIN_CTRL 0x0044 61 28 #define REG_GPIO_INTM 0x0048 62 29 #define REG_LEDCFG0 0x004C 63 63 - #define REG_LEDCFG1 0x004D 64 30 #define REG_LEDCFG2 0x004E 65 65 - #define REG_LEDCFG3 0x004F 66 66 - #define REG_FSIMR 0x0050 67 67 - #define REG_FSISR 0x0054 68 31 #define REG_HSIMR 0x0058 69 69 - #define REG_HSISR 0x005c 70 70 - #define REG_GPIO_PIN_CTRL_2 0x0060 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ 71 32 #define REG_GPIO_IO_SEL_2 0x0062 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ 72 33 #define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS Multi-Function control source. */ 73 73 - #define REG_GSSR 0x006c 74 74 - #define REG_AFE_XTAL_CTRL_EXT 0x0078 /* RTL8188E */ 75 34 #define REG_MCUFWDL 0x0080 76 76 - #define REG_MCUTSTCFG 0x0084 77 77 - #define REG_FDHM0 0x0088 78 35 #define REG_EFUSE_ACCESS 0x00CF /* Efuse access protection for RTL8723 */ 79 79 - #define REG_BIST_SCAN 0x00D0 80 80 - #define REG_BIST_RPT 0x00D4 81 81 - #define REG_BIST_ROM_RPT 0x00D8 82 82 - #define REG_USB_SIE_INTF 0x00E0 83 83 - #define REG_PCIE_MIO_INTF 0x00E4 84 84 - #define REG_PCIE_MIO_INTD 0x00E8 85 85 - #define REG_HPON_FSM 0x00EC 86 36 #define REG_SYS_CFG 0x00F0 87 37 #define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only. */ 88 88 - #define REG_TYPE_ID 0x00FC 89 89 - 90 90 - /* */ 91 91 - /* 2010/12/29 MH Add for 92D */ 92 92 - /* */ 93 93 - #define REG_MAC_PHY_CTRL_NORMAL 0x00f8 94 94 - 95 38 96 39 /* */ 97 40 /* */ ··· 43 100 /* */ 44 101 #define REG_CR 0x0100 45 102 #define REG_PBP 0x0104 46 46 - #define REG_PKT_BUFF_ACCESS_CTRL 0x0106 47 103 #define REG_TRXDMA_CTRL 0x010C 48 104 #define REG_TRXFF_BNDY 0x0114 49 49 - #define REG_TRXFF_STATUS 0x0118 50 50 - #define REG_RXFF_PTR 0x011C 51 105 #define REG_HIMR 0x0120 52 106 #define REG_HISR 0x0124 53 53 - #define REG_HIMRE 0x0128 54 54 - #define REG_HISRE 0x012C 55 55 - #define REG_CPWM 0x012F 56 56 - #define REG_FWIMR 0x0130 57 57 - #define REG_FWISR 0x0134 58 58 - #define REG_FTIMR 0x0138 59 59 - #define REG_PKTBUF_DBG_CTRL 0x0140 60 60 - #define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2) 61 61 - #define REG_PKTBUF_DBG_DATA_L 0x0144 62 62 - #define REG_PKTBUF_DBG_DATA_H 0x0148 63 107 64 64 - #define REG_TC0_CTRL 0x0150 65 65 - #define REG_TC1_CTRL 0x0154 66 66 - #define REG_TC2_CTRL 0x0158 67 67 - #define REG_TC3_CTRL 0x015C 68 68 - #define REG_TC4_CTRL 0x0160 69 69 - #define REG_TCUNIT_BASE 0x0164 70 70 - #define REG_MBIST_START 0x0174 71 71 - #define REG_MBIST_DONE 0x0178 72 72 - #define REG_MBIST_FAIL 0x017C 73 108 #define REG_C2HEVT_MSG_NORMAL 0x01A0 74 109 #define REG_C2HEVT_CLEAR 0x01AF 75 75 - #define REG_MCUTST_1 0x01c0 76 76 - #define REG_FMETHR 0x01C8 77 110 #define REG_HMETFR 0x01CC 78 111 #define REG_HMEBOX_0 0x01D0 79 79 - #define REG_HMEBOX_1 0x01D4 80 80 - #define REG_HMEBOX_2 0x01D8 81 81 - #define REG_HMEBOX_3 0x01DC 82 82 - #define REG_LLT_INIT 0x01E0 83 83 - 84 112 85 113 /* */ 86 114 /* */ ··· 59 145 /* */ 60 146 /* */ 61 147 #define REG_RQPN 0x0200 62 62 - #define REG_FIFOPAGE 0x0204 63 148 #define REG_TDECTRL 0x0208 64 64 - #define REG_TXDMA_OFFSET_CHK 0x020C 65 149 #define REG_TXDMA_STATUS 0x0210 66 150 #define REG_RQPN_NPQ 0x0214 67 151 #define REG_AUTO_LLT 0x0224 ··· 72 160 /* */ 73 161 #define REG_RXDMA_AGG_PG_TH 0x0280 74 162 #define REG_RXPKT_NUM 0x0284 75 75 - #define REG_RXDMA_STATUS 0x0288 76 76 - 77 77 - /* */ 78 78 - /* */ 79 79 - /* 0x0300h ~ 0x03FFh PCIe */ 80 80 - /* */ 81 81 - /* */ 82 82 - #define REG_PCIE_CTRL_REG 0x0300 83 83 - #define REG_INT_MIG 0x0304 /* Interrupt Migration */ 84 84 - #define REG_BCNQ_DESA 0x0308 /* TX Beacon Descriptor Address */ 85 85 - #define REG_HQ_DESA 0x0310 /* TX High Queue Descriptor Address */ 86 86 - #define REG_MGQ_DESA 0x0318 /* TX Manage Queue Descriptor Address */ 87 87 - #define REG_VOQ_DESA 0x0320 /* TX VO Queue Descriptor Address */ 88 88 - #define REG_VIQ_DESA 0x0328 /* TX VI Queue Descriptor Address */ 89 89 - #define REG_BEQ_DESA 0x0330 /* TX BE Queue Descriptor Address */ 90 90 - #define REG_BKQ_DESA 0x0338 /* TX BK Queue Descriptor Address */ 91 91 - #define REG_RX_DESA 0x0340 /* RX Queue Descriptor Address */ 92 92 - /* sherry added for DBI Read/Write 20091126 */ 93 93 - #define REG_DBI_WDATA 0x0348 /* Backdoor REG for Access Configuration */ 94 94 - #define REG_DBI_RDATA 0x034C /* Backdoor REG for Access Configuration */ 95 95 - #define REG_DBI_CTRL 0x0350 /* Backdoor REG for Access Configuration */ 96 96 - #define REG_DBI_FLAG 0x0352 /* Backdoor REG for Access Configuration */ 97 97 - #define REG_MDIO 0x0354 /* MDIO for Access PCIE PHY */ 98 98 - #define REG_DBG_SEL 0x0360 /* Debug Selection Register */ 99 99 - #define REG_PCIE_HRPWM 0x0361 /* PCIe RPWM */ 100 100 - #define REG_PCIE_HCPWM 0x0363 /* PCIe CPWM */ 101 101 - #define REG_WATCH_DOG 0x0368 102 102 - 103 103 - /* RTL8723 series ------------------------------- */ 104 104 - #define REG_PCIE_HISR_EN 0x0394 /* PCIE Local Interrupt Enable Register */ 105 105 - #define REG_PCIE_HISR 0x03A0 106 106 - #define REG_PCIE_HISRE 0x03A4 107 107 - #define REG_PCIE_HIMR 0x03A8 108 108 - #define REG_PCIE_HIMRE 0x03AC 109 109 - 110 110 - #define REG_USB_HIMR 0xFE38 111 111 - #define REG_USB_HIMRE 0xFE3C 112 112 - #define REG_USB_HISR 0xFE78 113 113 - #define REG_USB_HISRE 0xFE7C 114 114 - 115 163 116 164 /* */ 117 165 /* */ 118 166 /* 0x0400h ~ 0x047Fh Protocol Configuration */ 119 167 /* */ 120 168 /* */ 121 121 - #define REG_VOQ_INFORMATION 0x0400 122 122 - #define REG_VIQ_INFORMATION 0x0404 123 123 - #define REG_BEQ_INFORMATION 0x0408 124 124 - #define REG_BKQ_INFORMATION 0x040C 125 125 - #define REG_MGQ_INFORMATION 0x0410 126 126 - #define REG_HGQ_INFORMATION 0x0414 127 127 - #define REG_BCNQ_INFORMATION 0x0418 128 169 #define REG_TXPKT_EMPTY 0x041A 129 129 - #define REG_CPU_MGQ_INFORMATION 0x041C 130 170 #define REG_FWHW_TXQ_CTRL 0x0420 131 171 #define REG_HWSEQ_CTRL 0x0423 132 132 - #define REG_BCNQ_BDNY 0x0424 133 133 - #define REG_MGQ_BDNY 0x0425 134 134 - #define REG_LIFETIME_CTRL 0x0426 135 135 - #define REG_MULTI_BCNQ_OFFSET 0x0427 136 172 #define REG_SPEC_SIFS 0x0428 137 173 #define REG_RL 0x042A 138 138 - #define REG_DARFRC 0x0430 139 139 - #define REG_RARFRC 0x0438 140 174 #define REG_RRSR 0x0440 141 141 - #define REG_ARFR0 0x0444 142 142 - #define REG_ARFR1 0x0448 143 143 - #define REG_ARFR2 0x044C 144 144 - #define REG_ARFR3 0x0450 145 145 - #define REG_BCNQ1_BDNY 0x0457 146 175 147 147 - #define REG_AGGLEN_LMT 0x0458 148 148 - #define REG_AMPDU_MIN_SPACE 0x045C 149 149 - #define REG_WMAC_LBK_BF_HD 0x045D 150 150 - #define REG_FAST_EDCA_CTRL 0x0460 151 151 - #define REG_RD_RESP_PKT_TH 0x0463 152 152 - 153 153 - #define REG_INIRTS_RATE_SEL 0x0480 154 154 - #define REG_INIDATA_RATE_SEL 0x0484 155 155 - 156 156 - #define REG_POWER_STAGE1 0x04B4 157 157 - #define REG_POWER_STAGE2 0x04B8 158 176 #define REG_PKT_VO_VI_LIFE_TIME 0x04C0 159 177 #define REG_PKT_BE_BK_LIFE_TIME 0x04C2 160 160 - #define REG_STBC_SETTING 0x04C4 161 161 - #define REG_QUEUE_CTRL 0x04C6 162 162 - #define REG_SINGLE_AMPDU_CTRL 0x04c7 163 163 - #define REG_PROT_MODE_CTRL 0x04C8 164 164 - #define REG_MAX_AGGR_NUM 0x04CA 165 165 - #define REG_RTS_MAX_AGGR_NUM 0x04CB 166 178 #define REG_BAR_MODE_CTRL 0x04CC 167 167 - #define REG_RA_TRY_RATE_AGG_LMT 0x04CF 168 179 #define REG_EARLY_MODE_CONTROL 0x04D0 169 180 #define REG_MACID_SLEEP 0x04D4 170 181 #define REG_NQOS_SEQ 0x04DC 171 171 - #define REG_QOS_SEQ 0x04DE 172 172 - #define REG_NEED_CPU_HANDLE 0x04E0 173 173 - #define REG_PKT_LOSE_RPT 0x04E1 174 174 - #define REG_PTCL_ERR_STATUS 0x04E2 175 175 - #define REG_TX_RPT_CTRL 0x04EC 176 176 - #define REG_TX_RPT_TIME 0x04F0 /* 2 byte */ 177 177 - #define REG_DUMMY 0x04FC 178 182 179 183 /* */ 180 184 /* */ ··· 102 274 #define REG_EDCA_BE_PARAM 0x0508 103 275 #define REG_EDCA_BK_PARAM 0x050C 104 276 #define REG_BCNTCFG 0x0510 105 105 - #define REG_PIFS 0x0512 106 106 - #define REG_RDG_PIFS 0x0513 107 277 #define REG_SIFS_CTX 0x0514 108 278 #define REG_SIFS_TRX 0x0516 109 279 #define REG_TSFTR_SYN_OFFSET 0x0518 110 110 - #define REG_AGGR_BREAK_TIME 0x051A 111 280 #define REG_SLOT 0x051B 112 112 - #define REG_TX_PTCL_CTRL 0x0520 113 281 #define REG_TXPAUSE 0x0522 114 114 - #define REG_DIS_TXREQ_CLR 0x0523 115 282 #define REG_RD_CTRL 0x0524 116 283 /* */ 117 284 /* Format for offset 540h-542h: */ ··· 124 301 /* Described by Designer Tim and Bruce, 2011-01-14. */ 125 302 /* */ 126 303 #define REG_TBTT_PROHIBIT 0x0540 127 127 - #define REG_RD_NAV_NXT 0x0544 128 128 - #define REG_NAV_PROT_LEN 0x0546 129 304 #define REG_BCN_CTRL 0x0550 130 305 #define REG_BCN_CTRL_1 0x0551 131 131 - #define REG_MBID_NUM 0x0552 132 306 #define REG_DUAL_TSF_RST 0x0553 133 307 #define REG_BCN_INTERVAL 0x0554 /* The same as REG_MBSSID_BCN_SPACE */ 134 308 #define REG_DRVERLYINT 0x0558 135 309 #define REG_BCNDMATIM 0x0559 136 310 #define REG_ATIMWND 0x055A 137 137 - #define REG_USTIME_TSF 0x055C 138 311 #define REG_BCN_MAX_ERR 0x055D 139 312 #define REG_RXTSF_OFFSET_CCK 0x055E 140 313 #define REG_RXTSF_OFFSET_OFDM 0x055F 141 314 #define REG_TSFTR 0x0560 142 142 - #define REG_TSFTR1 0x0568 /* HW Port 1 TSF Register */ 143 143 - #define REG_ATIMWND_1 0x0570 144 144 - #define REG_P2P_CTWIN 0x0572 /* 1 Byte long (in unit of TU) */ 145 145 - #define REG_PSTIMER 0x0580 146 146 - #define REG_TIMER0 0x0584 147 147 - #define REG_TIMER1 0x0588 148 315 #define REG_ACMHWCTRL 0x05C0 149 149 - #define REG_NOA_DESC_SEL 0x05CF 150 150 - #define REG_NOA_DESC_DURATION 0x05E0 151 151 - #define REG_NOA_DESC_INTERVAL 0x05E4 152 152 - #define REG_NOA_DESC_START 0x05E8 153 153 - #define REG_NOA_DESC_COUNT 0x05EC 154 154 - 155 155 - #define REG_DMC 0x05F0 /* Dual MAC Co-Existence Register */ 156 156 - #define REG_SCH_TX_CMD 0x05F8 157 157 - 158 158 - #define REG_FW_RESET_TSF_CNT_1 0x05FC 159 159 - #define REG_FW_RESET_TSF_CNT_0 0x05FD 160 160 - #define REG_FW_BCN_DIS_CNT 0x05FE 161 316 162 317 /* */ 163 318 /* */ 164 319 /* 0x0600h ~ 0x07FFh WMAC Configuration */ 165 320 /* */ 166 321 /* */ 167 167 - #define REG_APSD_CTRL 0x0600 168 322 #define REG_BWOPMODE 0x0603 169 323 #define REG_TCR 0x0604 170 324 #define REG_RCR 0x0608 171 171 - #define REG_RX_PKT_LIMIT 0x060C 172 172 - #define REG_RX_DLK_TIME 0x060D 173 325 #define REG_RX_DRVINFO_SZ 0x060F 174 326 175 327 #define REG_MACID 0x0610 176 328 #define REG_BSSID 0x0618 177 329 #define REG_MAR 0x0620 178 178 - #define REG_MBIDCAMCFG 0x0628 179 330 180 180 - #define REG_PNO_STATUS 0x0631 181 181 - #define REG_USTIME_EDCA 0x0638 182 331 #define REG_MAC_SPEC_SIFS 0x063A 183 332 /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ 184 333 #define REG_RESP_SIFS_CCK 0x063C /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ 185 334 #define REG_RESP_SIFS_OFDM 0x063E /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ 186 335 187 336 #define REG_ACKTO 0x0640 188 188 - #define REG_CTS2TO 0x0641 189 189 - #define REG_EIFS 0x0642 190 190 - 191 191 - 192 192 - /* RXERR_RPT */ 193 193 - #define RXERR_TYPE_OFDM_PPDU 0 194 194 - #define RXERR_TYPE_OFDMfalse_ALARM 1 195 195 - #define RXERR_TYPE_OFDM_MPDU_OK 2 196 196 - #define RXERR_TYPE_OFDM_MPDU_FAIL 3 197 197 - #define RXERR_TYPE_CCK_PPDU 4 198 198 - #define RXERR_TYPE_CCKfalse_ALARM 5 199 199 - #define RXERR_TYPE_CCK_MPDU_OK 6 200 200 - #define RXERR_TYPE_CCK_MPDU_FAIL 7 201 201 - #define RXERR_TYPE_HT_PPDU 8 202 202 - #define RXERR_TYPE_HTfalse_ALARM 9 203 203 - #define RXERR_TYPE_HT_MPDU_TOTAL 10 204 204 - #define RXERR_TYPE_HT_MPDU_OK 11 205 205 - #define RXERR_TYPE_HT_MPDU_FAIL 12 206 206 - #define RXERR_TYPE_RX_FULL_DROP 15 207 207 - 208 208 - #define RXERR_COUNTER_MASK 0xFFFFF 209 209 - #define RXERR_RPT_RST BIT(27) 210 210 - #define _RXERR_RPT_SEL(type) ((type) << 28) 211 337 212 338 /* */ 213 339 /* Note: */ ··· 170 398 #define REG_NAV_UPPER 0x0652 /* unit of 128 */ 171 399 172 400 /* WMA, BA, CCX */ 173 173 - #define REG_NAV_CTRL 0x0650 174 174 - #define REG_BACAMCMD 0x0654 175 175 - #define REG_BACAMCONTENT 0x0658 176 176 - #define REG_LBDLY 0x0660 177 177 - #define REG_FWDLY 0x0661 178 401 #define REG_RXERR_RPT 0x0664 179 179 - #define REG_WMAC_TRXPTCL_CTL 0x0668 180 402 181 403 /* Security */ 182 404 #define REG_CAMCMD 0x0670 183 405 #define REG_CAMWRITE 0x0674 184 406 #define REG_CAMREAD 0x0678 185 185 - #define REG_CAMDBG 0x067C 186 407 #define REG_SECCFG 0x0680 187 408 188 409 /* Power */ 189 189 - #define REG_WOW_CTRL 0x0690 190 190 - #define REG_PS_RX_INFO 0x0692 191 191 - #define REG_UAPSD_TID 0x0693 192 192 - #define REG_WKFMCAM_CMD 0x0698 193 193 - #define REG_WKFMCAM_NUM REG_WKFMCAM_CMD 194 194 - #define REG_WKFMCAM_RWD 0x069C 195 410 #define REG_RXFLTMAP0 0x06A0 196 411 #define REG_RXFLTMAP1 0x06A2 197 412 #define REG_RXFLTMAP2 0x06A4 198 413 #define REG_BCN_PSR_RPT 0x06A8 199 199 - #define REG_BT_COEX_TABLE 0x06C0 200 200 - 201 201 - /* Hardware Port 2 */ 202 202 - #define REG_MACID1 0x0700 203 203 - #define REG_BSSID1 0x0708 204 204 - 205 205 - 206 206 - /* */ 207 207 - /* */ 208 208 - /* 0xFE00h ~ 0xFE55h USB Configuration */ 209 209 - /* */ 210 210 - /* */ 211 211 - #define REG_USB_INFO 0xFE17 212 212 - #define REG_USB_SPECIAL_OPTION 0xFE55 213 213 - #define REG_USB_DMA_AGG_TO 0xFE5B 214 214 - #define REG_USB_AGG_TO 0xFE5C 215 215 - #define REG_USB_AGG_TH 0xFE5D 216 216 - 217 217 - #define REG_USB_HRPWM 0xFE58 218 218 - #define REG_USB_HCPWM 0xFE57 219 219 - 220 220 - /* for 92DU high_Queue low_Queue Normal_Queue select */ 221 221 - #define REG_USB_High_NORMAL_Queue_Select_MAC0 0xFE44 222 222 - /* define REG_USB_LOW_Queue_Select_MAC0 0xFE45 */ 223 223 - #define REG_USB_High_NORMAL_Queue_Select_MAC1 0xFE47 224 224 - /* define REG_USB_LOW_Queue_Select_MAC1 0xFE48 */ 225 225 - 226 226 - /* For test chip */ 227 227 - #define REG_TEST_USB_TXQS 0xFE48 228 228 - #define REG_TEST_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */ 229 229 - #define REG_TEST_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */ 230 230 - #define REG_TEST_SIE_OPTIONAL 0xFE64 231 231 - #define REG_TEST_SIE_CHIRP_K 0xFE65 232 232 - #define REG_TEST_SIE_PHY 0xFE66 /* 0xFE66~0xFE6B */ 233 233 - #define REG_TEST_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ 234 234 - #define REG_TEST_SIE_STRING 0xFE80 /* 0xFE80~0xFEB9 */ 235 235 - 236 236 - 237 237 - /* For normal chip */ 238 238 - #define REG_NORMAL_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */ 239 239 - #define REG_NORMAL_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */ 240 240 - #define REG_NORMAL_SIE_OPTIONAL 0xFE64 241 241 - #define REG_NORMAL_SIE_EP 0xFE65 /* 0xFE65~0xFE67 */ 242 242 - #define REG_NORMAL_SIE_PHY 0xFE68 /* 0xFE68~0xFE6B */ 243 243 - #define REG_NORMAL_SIE_OPTIONAL2 0xFE6C 244 244 - #define REG_NORMAL_SIE_GPS_EP 0xFE6D /* 0xFE6D, for RTL8723 only. */ 245 245 - #define REG_NORMAL_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ 246 246 - #define REG_NORMAL_SIE_STRING 0xFE80 /* 0xFE80~0xFEDF */ 247 247 - 248 414 249 415 /* */ 250 416 /* */ ··· 196 486 #define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */ 197 487 #define EFUSE_TEST REG_EFUSE_TEST /* E-Fuse Test. */ 198 488 #define MSR (REG_CR + 2) /* Media Status register */ 199 199 - /* define ISR REG_HISR */ 200 200 - 201 201 - #define TSFR REG_TSFTR /* Timing Sync Function Timer Register. */ 202 202 - #define TSFR1 REG_TSFTR1 /* HW Port 1 TSF Register */ 203 489 204 490 #define PBP REG_PBP 205 205 - 206 206 - /* Redifine MACID register, to compatible prior ICs. */ 207 207 - #define IDR0 REG_MACID /* MAC ID Register, Offset 0x0050-0x0053 */ 208 208 - #define IDR4 (REG_MACID + 4) /* MAC ID Register, Offset 0x0054-0x0055 */ 209 209 - 210 491 211 492 /* */ 212 493 /* 9. Security Control Registers (Offset:) */ 213 494 /* */ 214 495 #define RWCAM REG_CAMCMD /* IN 8190 Data Sheet is called CAMcmd */ 215 496 #define WCAMI REG_CAMWRITE /* Software write CAM input content */ 216 216 - #define RCAMO REG_CAMREAD /* Software read/write CAM config */ 217 217 - #define CAMDBG REG_CAMDBG 218 218 - #define SECR REG_SECCFG /* Security Configuration Register */ 219 219 - 220 220 - /* Unused register */ 221 221 - #define UnusedRegister 0x1BF 222 222 - #define DCAM UnusedRegister 223 223 - #define PSR UnusedRegister 224 224 - #define BBAddr UnusedRegister 225 225 - #define PhyDataR UnusedRegister 226 226 - 227 227 - /* Min Spacing related settings. */ 228 228 - #define MAX_MSS_DENSITY_2T 0x13 229 229 - #define MAX_MSS_DENSITY_1T 0x0A 230 497 231 498 /* */ 232 499 /* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */ ··· 215 528 #define HSISR_GPIO9_INT BIT25 216 529 217 530 /* */ 218 218 - /* USB INTR CONTENT */ 219 219 - /* */ 220 220 - #define USB_C2H_CMDID_OFFSET 0 221 221 - #define USB_C2H_SEQ_OFFSET 1 222 222 - #define USB_C2H_EVENT_OFFSET 2 223 223 - #define USB_INTR_CPWM_OFFSET 16 224 224 - #define USB_INTR_CONTENT_C2H_OFFSET 0 225 225 - #define USB_INTR_CONTENT_CPWM1_OFFSET 16 226 226 - #define USB_INTR_CONTENT_CPWM2_OFFSET 20 227 227 - #define USB_INTR_CONTENT_HISR_OFFSET 48 228 228 - #define USB_INTR_CONTENT_HISRE_OFFSET 52 229 229 - #define USB_INTR_CONTENT_LENGTH 56 230 230 - 231 231 - /* */ 232 531 /* Response Rate Set Register (offset 0x440, 24bits) */ 233 532 /* */ 234 533 #define RRSR_1M BIT0 ··· 222 549 #define RRSR_5_5M BIT2 223 550 #define RRSR_11M BIT3 224 551 #define RRSR_6M BIT4 225 225 - #define RRSR_9M BIT5 226 552 #define RRSR_12M BIT6 227 227 - #define RRSR_18M BIT7 228 553 #define RRSR_24M BIT8 229 229 - #define RRSR_36M BIT9 230 230 - #define RRSR_48M BIT10 231 231 - #define RRSR_54M BIT11 232 232 - #define RRSR_MCS0 BIT12 233 233 - #define RRSR_MCS1 BIT13 234 234 - #define RRSR_MCS2 BIT14 235 235 - #define RRSR_MCS3 BIT15 236 236 - #define RRSR_MCS4 BIT16 237 237 - #define RRSR_MCS5 BIT17 238 238 - #define RRSR_MCS6 BIT18 239 239 - #define RRSR_MCS7 BIT19 240 554 241 555 #define RRSR_CCK_RATES (RRSR_11M|RRSR_5_5M|RRSR_2M|RRSR_1M) 242 242 - #define RRSR_OFDM_RATES (RRSR_54M|RRSR_48M|RRSR_36M|RRSR_24M|RRSR_18M|RRSR_12M|RRSR_9M|RRSR_6M) 243 243 - 244 244 - /* WOL bit information */ 245 245 - #define HAL92C_WOL_PTK_UPDATE_EVENT BIT0 246 246 - #define HAL92C_WOL_GTK_UPDATE_EVENT BIT1 247 247 - #define HAL92C_WOL_DISASSOC_EVENT BIT2 248 248 - #define HAL92C_WOL_DEAUTH_EVENT BIT3 249 249 - #define HAL92C_WOL_FW_DISCONNECT_EVENT BIT4 250 556 251 557 /* */ 252 558 /* Rate Definition */ 253 559 /* */ 254 254 - /* CCK */ 255 255 - #define RATR_1M 0x00000001 256 256 - #define RATR_2M 0x00000002 257 257 - #define RATR_55M 0x00000004 258 258 - #define RATR_11M 0x00000008 259 259 - /* OFDM */ 260 260 - #define RATR_6M 0x00000010 261 261 - #define RATR_9M 0x00000020 262 262 - #define RATR_12M 0x00000040 263 263 - #define RATR_18M 0x00000080 264 264 - #define RATR_24M 0x00000100 265 265 - #define RATR_36M 0x00000200 266 266 - #define RATR_48M 0x00000400 267 267 - #define RATR_54M 0x00000800 268 268 - /* MCS 1 Spatial Stream */ 269 269 - #define RATR_MCS0 0x00001000 270 270 - #define RATR_MCS1 0x00002000 271 271 - #define RATR_MCS2 0x00004000 272 272 - #define RATR_MCS3 0x00008000 273 273 - #define RATR_MCS4 0x00010000 274 274 - #define RATR_MCS5 0x00020000 275 275 - #define RATR_MCS6 0x00040000 276 276 - #define RATR_MCS7 0x00080000 277 277 - 278 560 /* CCK */ 279 561 #define RATE_1M BIT(0) 280 562 #define RATE_2M BIT(1) ··· 244 616 #define RATE_36M BIT(9) 245 617 #define RATE_48M BIT(10) 246 618 #define RATE_54M BIT(11) 247 247 - /* MCS 1 Spatial Stream */ 248 248 - #define RATE_MCS0 BIT(12) 249 249 - #define RATE_MCS1 BIT(13) 250 250 - #define RATE_MCS2 BIT(14) 251 251 - #define RATE_MCS3 BIT(15) 252 252 - #define RATE_MCS4 BIT(16) 253 253 - #define RATE_MCS5 BIT(17) 254 254 - #define RATE_MCS6 BIT(18) 255 255 - #define RATE_MCS7 BIT(19) 256 619 257 620 /* ALL CCK Rate */ 258 621 #define RATE_BITMAP_ALL 0xFFFFF 259 622 260 623 /* Only use CCK 1M rate for ACK */ 261 624 #define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 262 262 - #define RATE_RRSR_WITHOUT_CCK 0xFFFF0 263 625 264 626 /* */ 265 627 /* BW_OPMODE bits (Offset 0x603, 8bit) */ ··· 260 642 /* CAM Config Setting (offset 0x680, 1 byte) */ 261 643 /* */ 262 644 #define CAM_VALID BIT15 263 263 - #define CAM_NOTVALID 0x0000 264 264 - #define CAM_USEDK BIT5 265 645 266 646 #define CAM_CONTENT_COUNT 8 267 647 268 268 - #define CAM_NONE 0x0 269 269 - #define CAM_WEP40 0x01 270 270 - #define CAM_TKIP 0x02 271 648 #define CAM_AES 0x04 272 272 - #define CAM_WEP104 0x05 273 273 - #define CAM_SMS4 0x6 274 649 275 650 #define TOTAL_CAM_ENTRY 32 276 276 - #define HALF_CAM_ENTRY 16 277 277 - 278 278 - #define CAM_CONFIG_USEDK true 279 279 - #define CAM_CONFIG_NO_USEDK false 280 651 281 652 #define CAM_WRITE BIT16 282 282 - #define CAM_READ 0x00000000 283 653 #define CAM_POLLINIG BIT31 284 284 - 285 285 - /* */ 286 286 - /* 10. Power Save Control Registers */ 287 287 - /* */ 288 288 - #define WOW_PMEN BIT0 /* Power management Enable. */ 289 289 - #define WOW_WOMEN BIT1 /* WoW function on or off. */ 290 290 - #define WOW_MAGIC BIT2 /* Magic packet */ 291 291 - #define WOW_UWF BIT3 /* Unicast Wakeup frame. */ 292 654 293 655 /* */ 294 656 /* 12. Host Interrupt Status Registers */ 295 657 /* */ 296 296 - /* */ 297 297 - /* 8190 IMR/ISR bits */ 298 298 - /* */ 299 299 - #define IMR8190_DISABLED 0x0 300 300 - #define IMR_DISABLED 0x0 301 301 - /* IMR DW0 Bit 0-31 */ 302 302 - #define IMR_BCNDMAINT6 BIT31 /* Beacon DMA Interrupt 6 */ 303 303 - #define IMR_BCNDMAINT5 BIT30 /* Beacon DMA Interrupt 5 */ 304 304 - #define IMR_BCNDMAINT4 BIT29 /* Beacon DMA Interrupt 4 */ 305 305 - #define IMR_BCNDMAINT3 BIT28 /* Beacon DMA Interrupt 3 */ 306 306 - #define IMR_BCNDMAINT2 BIT27 /* Beacon DMA Interrupt 2 */ 307 307 - #define IMR_BCNDMAINT1 BIT26 /* Beacon DMA Interrupt 1 */ 308 308 - #define IMR_BCNDOK8 BIT25 /* Beacon Queue DMA OK Interrupt 8 */ 309 309 - #define IMR_BCNDOK7 BIT24 /* Beacon Queue DMA OK Interrupt 7 */ 310 310 - #define IMR_BCNDOK6 BIT23 /* Beacon Queue DMA OK Interrupt 6 */ 311 311 - #define IMR_BCNDOK5 BIT22 /* Beacon Queue DMA OK Interrupt 5 */ 312 312 - #define IMR_BCNDOK4 BIT21 /* Beacon Queue DMA OK Interrupt 4 */ 313 313 - #define IMR_BCNDOK3 BIT20 /* Beacon Queue DMA OK Interrupt 3 */ 314 314 - #define IMR_BCNDOK2 BIT19 /* Beacon Queue DMA OK Interrupt 2 */ 315 315 - #define IMR_BCNDOK1 BIT18 /* Beacon Queue DMA OK Interrupt 1 */ 316 316 - #define IMR_TIMEOUT2 BIT17 /* Timeout interrupt 2 */ 317 317 - #define IMR_TIMEOUT1 BIT16 /* Timeout interrupt 1 */ 318 318 - #define IMR_TXFOVW BIT15 /* Transmit FIFO Overflow */ 319 319 - #define IMR_PSTIMEOUT BIT14 /* Power save time out interrupt */ 320 320 - #define IMR_BcnInt BIT13 /* Beacon DMA Interrupt 0 */ 321 321 - #define IMR_RXFOVW BIT12 /* Receive FIFO Overflow */ 322 322 - #define IMR_RDU BIT11 /* Receive Descriptor Unavailable */ 323 323 - #define IMR_ATIMEND BIT10 /* For 92C, ATIM Window End Interrupt. For 8723 and later ICs, it also means P2P CTWin End interrupt. */ 324 324 - #define IMR_BDOK BIT9 /* Beacon Queue DMA OK Interrupt */ 325 325 - #define IMR_HIGHDOK BIT8 /* High Queue DMA OK Interrupt */ 326 326 - #define IMR_TBDOK BIT7 /* Transmit Beacon OK interrupt */ 327 327 - #define IMR_MGNTDOK BIT6 /* Management Queue DMA OK Interrupt */ 328 328 - #define IMR_TBDER BIT5 /* For 92C, Transmit Beacon Error Interrupt */ 329 329 - #define IMR_BKDOK BIT4 /* AC_BK DMA OK Interrupt */ 330 330 - #define IMR_BEDOK BIT3 /* AC_BE DMA OK Interrupt */ 331 331 - #define IMR_VIDOK BIT2 /* AC_VI DMA OK Interrupt */ 332 332 - #define IMR_VODOK BIT1 /* AC_VO DMA Interrupt */ 333 333 - #define IMR_ROK BIT0 /* Receive DMA OK Interrupt */ 334 334 - 335 335 - /* 13. Host Interrupt Status Extension Register (Offset: 0x012C-012Eh) */ 336 336 - #define IMR_TSF_BIT32_TOGGLE BIT15 337 337 - #define IMR_BcnInt_E BIT12 338 338 - #define IMR_TXERR BIT11 339 339 - #define IMR_RXERR BIT10 340 340 - #define IMR_C2HCMD BIT9 341 341 - #define IMR_CPWM BIT8 342 342 - /* RSVD [2-7] */ 343 343 - #define IMR_OCPINT BIT1 344 344 - #define IMR_WLANOFF BIT0 345 658 346 659 /* */ 347 660 /* 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits) */ ··· 282 733 #define RCR_APP_ICV BIT29 /* MACRX will retain the ICV at the bottom of the packet. */ 283 734 #define RCR_APP_PHYST_RXFF BIT28 /* PHY Status is appended before RX packet in RXFF */ 284 735 #define RCR_APP_BA_SSN BIT27 /* SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. */ 285 285 - #define RCR_NONQOS_VHT BIT26 /* Reserved */ 286 286 - #define RCR_RSVD_BIT25 BIT25 /* Reserved */ 287 287 - #define RCR_ENMBID BIT24 /* Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. */ 288 288 - #define RCR_LSIGEN BIT23 /* Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. */ 289 289 - #define RCR_MFBEN BIT22 /* Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. */ 290 290 - #define RCR_RSVD_BIT21 BIT21 /* Reserved */ 291 291 - #define RCR_RSVD_BIT20 BIT20 /* Reserved */ 292 292 - #define RCR_RSVD_BIT19 BIT19 /* Reserved */ 293 293 - #define RCR_TIM_PARSER_EN BIT18 /* RX Beacon TIM Parser. */ 294 294 - #define RCR_BM_DATA_EN BIT17 /* Broadcast data packet interrupt enable. */ 295 295 - #define RCR_UC_DATA_EN BIT16 /* Unicast data packet interrupt enable. */ 296 296 - #define RCR_RSVD_BIT15 BIT15 /* Reserved */ 297 736 #define RCR_HTC_LOC_CTRL BIT14 /* MFC<--HTC = 1 MFC-->HTC = 0 */ 298 737 #define RCR_AMF BIT13 /* Accept management type frame */ 299 299 - #define RCR_ACF BIT12 /* Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. */ 300 738 #define RCR_ADF BIT11 /* Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). */ 301 301 - #define RCR_RSVD_BIT10 BIT10 /* Reserved */ 302 302 - #define RCR_AICV BIT9 /* Accept ICV error packet */ 303 739 #define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */ 304 740 #define RCR_CBSSID_BCN BIT7 /* Accept BSSID match packet (Rx beacon, probe rsp) */ 305 741 #define RCR_CBSSID_DATA BIT6 /* Accept BSSID match packet (Data) */ 306 306 - #define RCR_CBSSID RCR_CBSSID_DATA /* Accept BSSID match packet */ 307 307 - #define RCR_APWRMGT BIT5 /* Accept power management packet */ 308 308 - #define RCR_ADD3 BIT4 /* Accept address 3 match packet */ 309 742 #define RCR_AB BIT3 /* Accept broadcast packet */ 310 743 #define RCR_AM BIT2 /* Accept multicast packet */ 311 744 #define RCR_APM BIT1 /* Accept physical match packet */ 312 312 - #define RCR_AAP BIT0 /* Accept all unicast packet */ 313 745 314 746 315 747 /* */ ··· 299 769 /* */ 300 770 /* */ 301 771 302 302 - /* 2 SYS_ISO_CTRL */ 303 303 - #define ISO_MD2PP BIT(0) 304 304 - #define ISO_UA2USB BIT(1) 305 305 - #define ISO_UD2CORE BIT(2) 306 306 - #define ISO_PA2PCIE BIT(3) 307 307 - #define ISO_PD2CORE BIT(4) 308 308 - #define ISO_IP2MAC BIT(5) 309 309 - #define ISO_DIOP BIT(6) 310 310 - #define ISO_DIOE BIT(7) 311 311 - #define ISO_EB2CORE BIT(8) 312 312 - #define ISO_DIOR BIT(9) 313 313 - #define PWC_EV12V BIT(15) 314 314 - 315 315 - 316 772 /* 2 SYS_FUNC_EN */ 317 773 #define FEN_BBRSTB BIT(0) 318 774 #define FEN_BB_GLB_RSTn BIT(1) 319 319 - #define FEN_USBA BIT(2) 320 320 - #define FEN_UPLL BIT(3) 321 321 - #define FEN_USBD BIT(4) 322 775 #define FEN_DIO_PCIE BIT(5) 323 776 #define FEN_PCIEA BIT(6) 324 777 #define FEN_PPLL BIT(7) 325 325 - #define FEN_PCIED BIT(8) 326 326 - #define FEN_DIOE BIT(9) 327 778 #define FEN_CPUEN BIT(10) 328 328 - #define FEN_DCORE BIT(11) 329 779 #define FEN_ELDR BIT(12) 330 330 - #define FEN_EN_25_1 BIT(13) 331 331 - #define FEN_HWPDN BIT(14) 332 332 - #define FEN_MREGEN BIT(15) 333 780 334 781 /* 2 APS_FSMCO */ 335 335 - #define PFM_LDALL BIT(0) 336 336 - #define PFM_ALDN BIT(1) 337 337 - #define PFM_LDKP BIT(2) 338 338 - #define PFM_WOWL BIT(3) 339 782 #define EnPDN BIT(4) 340 340 - #define PDN_PL BIT(5) 341 341 - #define APFM_ONMAC BIT(8) 342 342 - #define APFM_OFF BIT(9) 343 343 - #define APFM_RSM BIT(10) 344 344 - #define AFSM_HSUS BIT(11) 345 345 - #define AFSM_PCIE BIT(12) 346 346 - #define APDM_MAC BIT(13) 347 347 - #define APDM_HOST BIT(14) 348 348 - #define APDM_HPDN BIT(15) 349 349 - #define RDY_MACON BIT(16) 350 350 - #define SUS_HOST BIT(17) 351 351 - #define ROP_ALD BIT(20) 352 352 - #define ROP_PWR BIT(21) 353 353 - #define ROP_SPS BIT(22) 354 354 - #define SOP_MRST BIT(25) 355 355 - #define SOP_FUSE BIT(26) 356 356 - #define SOP_ABG BIT(27) 357 357 - #define SOP_AMB BIT(28) 358 358 - #define SOP_RCK BIT(29) 359 359 - #define SOP_A8M BIT(30) 360 360 - #define XOP_BTCK BIT(31) 361 783 362 784 /* 2 SYS_CLKR */ 363 363 - #define ANAD16V_EN BIT(0) 364 785 #define ANA8M BIT(1) 365 365 - #define MACSLP BIT(4) 366 786 #define LOADER_CLK_EN BIT(5) 367 787 368 788 369 789 /* 2 9346CR /REG_SYS_EEPROM_CTRL */ 370 790 #define BOOT_FROM_EEPROM BIT(4) 371 371 - #define EEPROMSEL BIT(4) 372 791 #define EEPROM_EN BIT(5) 373 792 374 793 ··· 326 847 #define RF_RSTB BIT(1) 327 848 #define RF_SDMRSTB BIT(2) 328 849 329 329 - 330 330 - /* 2 LDOV12D_CTRL */ 331 331 - #define LDV12_EN BIT(0) 332 332 - #define LDV12_SDBY BIT(1) 333 333 - #define LPLDO_HSM BIT(2) 334 334 - #define LPLDO_LSM_DIS BIT(3) 335 335 - #define _LDV12_VADJ(x) (((x) & 0xF) << 4) 336 336 - 337 337 - 338 338 - 339 850 /* 2 EFUSE_TEST (For RTL8723 partially) */ 340 340 - #define EF_TRPT BIT(7) 341 341 - #define EF_CELL_SEL (BIT(8)|BIT(9)) /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ 342 342 - #define LDOE25_EN BIT(31) 343 851 #define EFUSE_SEL(x) (((x) & 0x3) << 8) 344 852 #define EFUSE_SEL_MASK 0x300 345 853 #define EFUSE_WIFI_SEL_0 0x0 ··· 337 871 338 872 /* 2 8051FWDL */ 339 873 /* 2 MCUFWDL */ 340 340 - #define MCUFWDL_EN BIT(0) 341 874 #define MCUFWDL_RDY BIT(1) 342 875 #define FWDL_ChkSum_rpt BIT(2) 343 343 - #define MACINI_RDY BIT(3) 344 344 - #define BBINI_RDY BIT(4) 345 345 - #define RFINI_RDY BIT(5) 346 876 #define WINTINI_RDY BIT(6) 347 877 #define RAM_DL_SEL BIT(7) 348 348 - #define ROM_DLEN BIT(19) 349 349 - #define CPRST BIT(23) 350 350 - 351 878 352 879 /* 2 REG_SYS_CFG */ 353 353 - #define XCLK_VLD BIT(0) 354 354 - #define ACLK_VLD BIT(1) 355 355 - #define UCLK_VLD BIT(2) 356 356 - #define PCLK_VLD BIT(3) 357 357 - #define PCIRSTB BIT(4) 358 358 - #define V15_VLD BIT(5) 359 359 - #define SW_OFFLOAD_EN BIT(7) 360 360 - #define SIC_IDLE BIT(8) 361 361 - #define BD_MAC2 BIT(9) 362 362 - #define BD_MAC1 BIT(10) 363 363 - #define IC_MACPHY_MODE BIT(11) 364 364 - #define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) 365 365 - #define BT_FUNC BIT(16) 366 880 #define VENDOR_ID BIT(19) 367 367 - #define EXT_VENDOR_ID (BIT(18)|BIT(19)) /* Currently only for RTL8723B */ 368 368 - #define PAD_HWPD_IDN BIT(22) 369 369 - #define TRP_VAUX_EN BIT(23) /* RTL ID */ 370 370 - #define TRP_BT_EN BIT(24) 371 371 - #define BD_PKG_SEL BIT(25) 372 372 - #define BD_HCI_SEL BIT(26) 373 373 - #define TYPE_ID BIT(27) 374 374 - #define RF_TYPE_ID BIT(27) 375 881 376 882 #define RTL_ID BIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */ 377 883 #define SPS_SEL BIT(24) /* 1:LDO regulator mode; 0:Switching regulator mode */ ··· 351 913 352 914 #define CHIP_VER_RTL_MASK 0xF000 /* Bit 12 ~ 15 */ 353 915 #define CHIP_VER_RTL_SHIFT 12 354 354 - #define EXT_VENDOR_ID_SHIFT 18 355 916 356 917 /* 2 REG_GPIO_OUTSTS (For RTL8723 only) */ 357 357 - #define EFS_HCI_SEL (BIT(0)|BIT(1)) 358 358 - #define PAD_HCI_SEL (BIT(2)|BIT(3)) 359 359 - #define HCI_SEL (BIT(4)|BIT(5)) 360 360 - #define PKG_SEL_HCI BIT(6) 361 361 - #define FEN_GPS BIT(7) 362 362 - #define FEN_BT BIT(8) 363 363 - #define FEN_WL BIT(9) 364 364 - #define FEN_PCI BIT(10) 365 365 - #define FEN_USB BIT(11) 366 366 - #define BTRF_HWPDN_N BIT(12) 367 367 - #define WLRF_HWPDN_N BIT(13) 368 368 - #define PDN_BT_N BIT(14) 369 369 - #define PDN_GPS_N BIT(15) 370 370 - #define BT_CTL_HWPDN BIT(16) 371 371 - #define GPS_CTL_HWPDN BIT(17) 372 372 - #define PPHY_SUSB BIT(20) 373 373 - #define UPHY_SUSB BIT(21) 374 374 - #define PCI_SUSEN BIT(22) 375 375 - #define USB_SUSEN BIT(23) 376 918 #define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) 377 377 - 378 919 379 920 /* */ 380 921 /* */ ··· 378 961 /* Network type */ 379 962 #define _NETTYPE(x) (((x) & 0x3) << 16) 380 963 #define MASK_NETTYPE 0x30000 381 381 - #define NT_NO_LINK 0x0 382 964 #define NT_LINK_AD_HOC 0x1 383 965 #define NT_LINK_AP 0x2 384 384 - #define NT_AS_AP 0x3 385 966 386 967 /* 2 PBP - Page Size Register */ 387 387 - #define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 388 388 - #define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 389 389 - #define _PSRX_MASK 0xF 390 390 - #define _PSTX_MASK 0xF0 391 968 #define _PSRX(x) (x) 392 969 #define _PSTX(x) ((x) << 4) 393 970 394 394 - #define PBP_64 0x0 395 971 #define PBP_128 0x1 396 396 - #define PBP_256 0x2 397 397 - #define PBP_512 0x3 398 398 - #define PBP_1024 0x4 399 399 - 400 972 401 973 /* 2 TX/RXDMA */ 402 402 - #define RXDMA_ARBBW_EN BIT(0) 403 403 - #define RXSHFT_EN BIT(1) 404 974 #define RXDMA_AGG_EN BIT(2) 405 405 - #define QS_VO_QUEUE BIT(8) 406 406 - #define QS_VI_QUEUE BIT(9) 407 407 - #define QS_BE_QUEUE BIT(10) 408 408 - #define QS_BK_QUEUE BIT(11) 409 409 - #define QS_MANAGER_QUEUE BIT(12) 410 410 - #define QS_HIGH_QUEUE BIT(13) 411 411 - 412 412 - #define HQSEL_VOQ BIT(0) 413 413 - #define HQSEL_VIQ BIT(1) 414 414 - #define HQSEL_BEQ BIT(2) 415 415 - #define HQSEL_BKQ BIT(3) 416 416 - #define HQSEL_MGTQ BIT(4) 417 417 - #define HQSEL_HIQ BIT(5) 418 975 419 976 /* For normal driver, 0x10C */ 420 420 - #define _TXDMA_CMQ_MAP(x) (((x)&0x3) << 16) 421 977 #define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) 422 978 #define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) 423 979 #define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) ··· 398 1008 #define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) 399 1009 #define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) 400 1010 401 401 - #define QUEUE_EXTRA 0 402 1011 #define QUEUE_LOW 1 403 1012 #define QUEUE_NORMAL 2 404 1013 #define QUEUE_HIGH 3 405 405 - 406 406 - 407 407 - /* 2 TRXFF_BNDY */ 408 408 - 409 409 - 410 410 - /* 2 LLT_INIT */ 411 411 - #define _LLT_NO_ACTIVE 0x0 412 412 - #define _LLT_WRITE_ACCESS 0x1 413 413 - #define _LLT_READ_ACCESS 0x2 414 414 - 415 415 - #define _LLT_INIT_DATA(x) ((x) & 0xFF) 416 416 - #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 417 417 - #define _LLT_OP(x) (((x) & 0x3) << 30) 418 418 - #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 419 419 - 420 1014 421 1015 /* */ 422 1016 /* */ ··· 412 1038 #define _LPQ(x) (((x) & 0xFF) << 8) 413 1039 #define _PUBQ(x) (((x) & 0xFF) << 16) 414 1040 #define _NPQ(x) ((x) & 0xFF) /* NOTE: in RQPN_NPQ register */ 415 415 - #define _EPQ(x) (((x) & 0xFF) << 16) /* NOTE: in RQPN_EPQ register */ 416 1041 417 417 - 418 418 - #define HPQ_PUBLIC_DIS BIT(24) 419 419 - #define LPQ_PUBLIC_DIS BIT(25) 420 1042 #define LD_RQPN BIT(31) 421 1043 422 422 - 423 423 - /* 2 TDECTL */ 424 424 - #define BLK_DESC_NUM_SHIFT 4 425 425 - #define BLK_DESC_NUM_MASK 0xF 426 426 - 427 427 - 428 428 - /* 2 TXDMA_OFFSET_CHK */ 429 429 - #define DROP_DATA_EN BIT(9) 430 430 - 431 1044 /* 2 AUTO_LLT */ 432 432 - #define BIT_SHIFT_TXPKTNUM 24 433 433 - #define BIT_MASK_TXPKTNUM 0xff 434 434 - #define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM) 435 435 - 436 436 - #define BIT_TDE_DBG_SEL BIT(23) 437 1045 #define BIT_AUTO_INIT_LLT BIT(16) 438 438 - 439 439 - #define BIT_SHIFT_Tx_OQT_free_space 8 440 440 - #define BIT_MASK_Tx_OQT_free_space 0xff 441 441 - #define BIT_Tx_OQT_free_space(x) (((x) & BIT_MASK_Tx_OQT_free_space) << BIT_SHIFT_Tx_OQT_free_space) 442 442 - 443 1046 444 1047 /* */ 445 1048 /* */ ··· 463 1112 /* */ 464 1113 /* */ 465 1114 466 466 - /* 2 EDCA setting */ 467 467 - #define AC_PARAM_TXOP_LIMIT_OFFSET 16 468 468 - #define AC_PARAM_ECW_MAX_OFFSET 12 469 469 - #define AC_PARAM_ECW_MIN_OFFSET 8 470 470 - #define AC_PARAM_AIFS_OFFSET 0 471 471 - 472 472 - 473 1115 #define _LRL(x) ((x) & 0x3F) 474 1116 #define _SRL(x) (((x) & 0x3F) << 8) 475 1117 ··· 470 1126 /* 2 BCN_CTRL */ 471 1127 #define EN_TXBCN_RPT BIT(2) 472 1128 #define EN_BCN_FUNCTION BIT(3) 473 473 - #define STOP_BCNQ BIT(6) 474 474 - #define DIS_RX_BSSID_FIT BIT(6) 475 1129 476 1130 #define DIS_ATIM BIT(0) 477 1131 #define DIS_BCNQ_SUB BIT(1) 478 1132 #define DIS_TSF_UDT BIT(4) 479 479 - 480 480 - /* The same function but different bit field. */ 481 481 - #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) 482 482 - #define DIS_TSF_UDT0_TEST_CHIP BIT(5) 483 483 - 484 1133 485 1134 /* 2 ACMHWCTRL */ 486 1135 #define AcmHw_HwEn BIT(0) 487 1136 #define AcmHw_BeqEn BIT(1) 488 1137 #define AcmHw_ViqEn BIT(2) 489 1138 #define AcmHw_VoqEn BIT(3) 490 490 - #define AcmHw_BeqStatus BIT(4) 491 491 - #define AcmHw_ViqStatus BIT(5) 492 492 - #define AcmHw_VoqStatus BIT(6) 493 493 - 494 494 - /* 2 REG_DUAL_TSF_RST (0x553) */ 495 495 - #define DUAL_TSF_RST_P2P BIT(4) 496 496 - 497 497 - /* 2 REG_NOA_DESC_SEL (0x5CF) */ 498 498 - #define NOA_DESC_SEL_0 0 499 499 - #define NOA_DESC_SEL_1 BIT(4) 500 1139 501 1140 /* */ 502 1141 /* */ ··· 487 1160 /* */ 488 1161 /* */ 489 1162 490 490 - /* 2 APSD_CTRL */ 491 491 - #define APSDOFF BIT(6) 492 492 - 493 1163 /* 2 TCR */ 494 1164 #define TSFRST BIT(0) 495 495 - #define DIS_GCLK BIT(1) 496 496 - #define PAD_SEL BIT(2) 497 497 - #define PWR_ST BIT(6) 498 498 - #define PWRBIT_OW_EN BIT(7) 499 499 - #define ACRC BIT(8) 500 500 - #define CFENDFORM BIT(9) 501 501 - #define ICV BIT(10) 502 502 - 503 1165 504 1166 /* 2 RCR */ 505 505 - #define AAP BIT(0) 506 506 - #define APM BIT(1) 507 507 - #define AM BIT(2) 508 1167 #define AB BIT(3) 509 509 - #define ADD3 BIT(4) 510 510 - #define APWRMGT BIT(5) 511 511 - #define CBSSID BIT(6) 512 512 - #define CBSSID_DATA BIT(6) 513 513 - #define CBSSID_BCN BIT(7) 514 514 - #define ACRC32 BIT(8) 515 515 - #define AICV BIT(9) 516 516 - #define ADF BIT(11) 517 517 - #define ACF BIT(12) 518 518 - #define AMF BIT(13) 519 519 - #define HTC_LOC_CTRL BIT(14) 520 520 - #define UC_DATA_EN BIT(16) 521 521 - #define BM_DATA_EN BIT(17) 522 522 - #define MFBEN BIT(22) 523 523 - #define LSIGEN BIT(23) 524 524 - #define EnMBID BIT(24) 525 525 - #define FORCEACK BIT(26) 526 526 - #define APP_BASSN BIT(27) 527 527 - #define APP_PHYSTS BIT(28) 528 528 - #define APP_ICV BIT(29) 529 529 - #define APP_MIC BIT(30) 530 530 - #define APP_FCS BIT(31) 531 531 - 532 1168 533 1169 /* 2 SECCFG */ 534 1170 #define SCR_TxUseDK BIT(0) /* Force Tx Use Default Key */ 535 1171 #define SCR_RxUseDK BIT(1) /* Force Rx Use Default Key */ 536 1172 #define SCR_TxEncEnable BIT(2) /* Enable Tx Encryption */ 537 1173 #define SCR_RxDecEnable BIT(3) /* Enable Rx Decryption */ 538 538 - #define SCR_SKByA2 BIT(4) /* Search kEY BY A2 */ 539 539 - #define SCR_NoSKMC BIT(5) /* No Key Search Multicast */ 540 1174 #define SCR_TXBCUSEDK BIT(6) /* Force Tx Broadcast packets Use Default Key */ 541 1175 #define SCR_RXBCUSEDK BIT(7) /* Force Rx Broadcast packets Use Default Key */ 542 1176 #define SCR_CHK_KEYID BIT(8) ··· 510 1222 511 1223 /* I/O bus domain address mapping */ 512 1224 #define SDIO_LOCAL_BASE 0x10250000 513 513 - #define WLAN_IOREG_BASE 0x10260000 514 514 - #define FIRMWARE_FIFO_BASE 0x10270000 515 515 - #define TX_HIQ_BASE 0x10310000 516 516 - #define TX_MIQ_BASE 0x10320000 517 517 - #define TX_LOQ_BASE 0x10330000 518 518 - #define TX_EPQ_BASE 0x10350000 519 519 - #define RX_RX0FF_BASE 0x10340000 520 1225 521 1226 /* SDIO host local register space mapping. */ 522 1227 #define SDIO_LOCAL_MSK 0x0FFF ··· 517 1236 #define WLAN_FIFO_MSK 0x1FFF /* Aggregation Length[12:0] */ 518 1237 #define WLAN_RX0FF_MSK 0x0003 519 1238 520 520 - #define SDIO_WITHOUT_REF_DEVICE_ID 0 /* Without reference to the SDIO Device ID */ 521 1239 #define SDIO_LOCAL_DEVICE_ID 0 /* 0b[16], 000b[15:13] */ 522 1240 #define WLAN_TX_HIQ_DEVICE_ID 4 /* 0b[16], 100b[15:13] */ 523 1241 #define WLAN_TX_MIQ_DEVICE_ID 5 /* 0b[16], 101b[15:13] */ 524 1242 #define WLAN_TX_LOQ_DEVICE_ID 6 /* 0b[16], 110b[15:13] */ 525 525 - #define WLAN_TX_EXQ_DEVICE_ID 3 /* 0b[16], 011b[15:13] */ 526 1243 #define WLAN_RX0FF_DEVICE_ID 7 /* 0b[16], 111b[15:13] */ 527 1244 #define WLAN_IOREG_DEVICE_ID 8 /* 1b[16] */ 528 1245 ··· 531 1252 #define PUBLIC_QUEUE_IDX 3 532 1253 533 1254 #define SDIO_MAX_TX_QUEUE 3 /* HIQ, MIQ and LOQ */ 534 534 - #define SDIO_MAX_RX_QUEUE 1 535 1255 536 1256 #define SDIO_REG_TX_CTRL 0x0000 /* SDIO Tx Control */ 537 1257 #define SDIO_REG_HIMR 0x0014 /* SDIO Host Interrupt Mask */ 538 1258 #define SDIO_REG_HISR 0x0018 /* SDIO Host Interrupt Service Routine */ 539 539 - #define SDIO_REG_HCPWM 0x0019 /* HCI Current Power Mode */ 540 1259 #define SDIO_REG_RX0_REQ_LEN 0x001C /* RXDMA Request Length */ 541 1260 #define SDIO_REG_OQT_FREE_PG 0x001E /* OQT Free Page */ 542 1261 #define SDIO_REG_FREE_TXPG 0x0020 /* Free Tx Buffer Page */ 543 543 - #define SDIO_REG_HCPWM1 0x0024 /* HCI Current Power Mode 1 */ 544 544 - #define SDIO_REG_HCPWM2 0x0026 /* HCI Current Power Mode 2 */ 545 545 - #define SDIO_REG_FREE_TXPG_SEQ 0x0028 /* Free Tx Page Sequence */ 546 546 - #define SDIO_REG_HTSFR_INFO 0x0030 /* HTSF Informaion */ 547 1262 #define SDIO_REG_HRPWM1 0x0080 /* HCI Request Power Mode 1 */ 548 548 - #define SDIO_REG_HRPWM2 0x0082 /* HCI Request Power Mode 2 */ 549 549 - #define SDIO_REG_HPS_CLKR 0x0084 /* HCI Power Save Clock */ 550 1263 #define SDIO_REG_HSUS_CTRL 0x0086 /* SDIO HCI Suspend Control */ 551 551 - #define SDIO_REG_HIMR_ON 0x0090 /* SDIO Host Extension Interrupt Mask Always */ 552 552 - #define SDIO_REG_HISR_ON 0x0091 /* SDIO Host Extension Interrupt Status Always */ 553 1264 554 1265 #define SDIO_HIMR_DISABLED 0 555 1266 556 1267 /* RTL8723/RTL8188E SDIO Host Interrupt Mask Register */ 557 1268 #define SDIO_HIMR_RX_REQUEST_MSK BIT0 558 1269 #define SDIO_HIMR_AVAL_MSK BIT1 559 559 - #define SDIO_HIMR_TXERR_MSK BIT2 560 560 - #define SDIO_HIMR_RXERR_MSK BIT3 561 561 - #define SDIO_HIMR_TXFOVW_MSK BIT4 562 562 - #define SDIO_HIMR_RXFOVW_MSK BIT5 563 563 - #define SDIO_HIMR_TXBCNOK_MSK BIT6 564 564 - #define SDIO_HIMR_TXBCNERR_MSK BIT7 565 565 - #define SDIO_HIMR_BCNERLY_INT_MSK BIT16 566 566 - #define SDIO_HIMR_C2HCMD_MSK BIT17 567 567 - #define SDIO_HIMR_CPWM1_MSK BIT18 568 568 - #define SDIO_HIMR_CPWM2_MSK BIT19 569 569 - #define SDIO_HIMR_HSISR_IND_MSK BIT20 570 570 - #define SDIO_HIMR_GTINT3_IND_MSK BIT21 571 571 - #define SDIO_HIMR_GTINT4_IND_MSK BIT22 572 572 - #define SDIO_HIMR_PSTIMEOUT_MSK BIT23 573 573 - #define SDIO_HIMR_OCPINT_MSK BIT24 574 574 - #define SDIO_HIMR_ATIMEND_MSK BIT25 575 575 - #define SDIO_HIMR_ATIMEND_E_MSK BIT26 576 576 - #define SDIO_HIMR_CTWEND_MSK BIT27 577 1270 578 1271 /* SDIO Host Interrupt Service Routine */ 579 1272 #define SDIO_HISR_RX_REQUEST BIT0 ··· 556 1305 #define SDIO_HISR_RXFOVW BIT5 557 1306 #define SDIO_HISR_TXBCNOK BIT6 558 1307 #define SDIO_HISR_TXBCNERR BIT7 559 559 - #define SDIO_HISR_BCNERLY_INT BIT16 560 1308 #define SDIO_HISR_C2HCMD BIT17 561 1309 #define SDIO_HISR_CPWM1 BIT18 562 1310 #define SDIO_HISR_CPWM2 BIT19 ··· 564 1314 #define SDIO_HISR_GTINT4_IND BIT22 565 1315 #define SDIO_HISR_PSTIMEOUT BIT23 566 1316 #define SDIO_HISR_OCPINT BIT24 567 567 - #define SDIO_HISR_ATIMEND BIT25 568 568 - #define SDIO_HISR_ATIMEND_E BIT26 569 569 - #define SDIO_HISR_CTWEND BIT27 570 1317 571 1318 #define MASK_SDIO_HISR_CLEAR (SDIO_HISR_TXERR |\ 572 1319 SDIO_HISR_RXERR |\ ··· 580 1333 SDIO_HISR_PSTIMEOUT |\ 581 1334 SDIO_HISR_OCPINT) 582 1335 583 583 - /* SDIO HCI Suspend Control Register */ 584 584 - #define HCI_RESUME_PWR_RDY BIT1 585 585 - #define HCI_SUS_CTRL BIT0 586 586 - 587 1336 /* SDIO Tx FIFO related */ 588 1337 #define SDIO_TX_FREE_PG_QUEUE 4 /* The number of Tx FIFO free page */ 589 589 - #define SDIO_TX_FIFO_PAGE_SZ 128 590 590 - 591 591 - #define MAX_TX_AGG_PACKET_NUMBER 0x8 592 1338 593 1339 /* */ 594 1340 /* */ ··· 589 1349 /* */ 590 1350 /* */ 591 1351 592 592 - /* 2 USB Information (0xFE17) */ 593 593 - #define USB_IS_HIGH_SPEED 0 594 594 - #define USB_IS_FULL_SPEED 1 595 595 - #define USB_SPEED_MASK BIT(5) 596 596 - 597 597 - #define USB_NORMAL_SIE_EP_MASK 0xF 598 598 - #define USB_NORMAL_SIE_EP_SHIFT 4 599 599 - 600 600 - /* 2 Special Option */ 601 601 - #define USB_AGG_EN BIT(3) 602 602 - 603 603 - /* 0; Use interrupt endpoint to upload interrupt pkt */ 604 604 - /* 1; Use bulk endpoint to upload interrupt pkt, */ 605 605 - #define INT_BULK_SEL BIT(4) 606 606 - 607 1352 /* 2REG_C2HEVT_CLEAR */ 608 1353 #define C2H_EVT_HOST_CLOSE 0x00 /* Set by driver and notify FW that the driver has read the C2H command message */ 609 1354 #define C2H_EVT_FW_CLOSE 0xFF /* Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. */ 610 1355 611 611 - 612 1356 /* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */ 613 613 - #define WL_HWPDN_EN BIT0 /* Enable GPIO[9] as WiFi HW PDn source */ 614 1357 #define WL_HWPDN_SL BIT1 /* WiFi HW PDn polarity control */ 615 1358 #define WL_FUNC_EN BIT2 /* WiFi function enable */ 616 616 - #define WL_HWROF_EN BIT3 /* Enable GPIO[9] as WiFi RF HW PDn source */ 617 617 - #define BT_HWPDN_EN BIT16 /* Enable GPIO[11] as BT HW PDn source */ 618 618 - #define BT_HWPDN_SL BIT17 /* BT HW PDn polarity control */ 619 1359 #define BT_FUNC_EN BIT18 /* BT function enable */ 620 620 - #define BT_HWROF_EN BIT19 /* Enable GPIO[11] as BT/GPS RF HW PDn source */ 621 621 - #define GPS_HWPDN_EN BIT20 /* Enable GPIO[10] as GPS HW PDn source */ 622 622 - #define GPS_HWPDN_SL BIT21 /* GPS HW PDn polarity control */ 623 1360 #define GPS_FUNC_EN BIT22 /* GPS function enable */ 624 624 - 625 625 - /* */ 626 626 - /* General definitions */ 627 627 - /* */ 628 628 - 629 629 - #define LAST_ENTRY_OF_TX_PKT_BUFFER_8723B 255 630 630 - 631 631 - #define POLLING_LLT_THRESHOLD 20 632 632 - #define POLLING_READY_TIMEOUT_COUNT 1000 633 1361 634 1362 #endif /* __HAL_COMMON_H__ */

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drivers/staging/rtl8723bs/include/hal_phy_reg_8723b.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 2 - /****************************************************************************** 3 3 - * 4 4 - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 5 - * 6 6 - ******************************************************************************/ 7 7 - #ifndef __INC_HAL8723BPHYREG_H__ 8 8 - #define __INC_HAL8723BPHYREG_H__ 9 9 - 10 10 - #include <Hal8192CPhyReg.h> 11 11 - 12 12 - /* BB Register Definition */ 13 13 - /* */ 14 14 - /* 4. Page9(0x900) */ 15 15 - /* */ 16 16 - #define rDPDT_control 0x92c 17 17 - #define rfe_ctrl_anta_src 0x930 18 18 - #define rS0S1_PathSwitch 0x948 19 19 - #define AGC_table_select 0xb2c 20 20 - 21 21 - /* */ 22 22 - /* PageB(0xB00) */ 23 23 - /* */ 24 24 - #define rPdp_AntA 0xb00 25 25 - #define rPdp_AntA_4 0xb04 26 26 - #define rPdp_AntA_8 0xb08 27 27 - #define rPdp_AntA_C 0xb0c 28 28 - #define rPdp_AntA_10 0xb10 29 29 - #define rPdp_AntA_14 0xb14 30 30 - #define rPdp_AntA_18 0xb18 31 31 - #define rPdp_AntA_1C 0xb1c 32 32 - #define rPdp_AntA_20 0xb20 33 33 - #define rPdp_AntA_24 0xb24 34 34 - 35 35 - #define rConfig_Pmpd_AntA 0xb28 36 36 - #define rConfig_ram64x16 0xb2c 37 37 - 38 38 - #define rBndA 0xb30 39 39 - #define rHssiPar 0xb34 40 40 - 41 41 - #define rConfig_AntA 0xb68 42 42 - #define rConfig_AntB 0xb6c 43 43 - 44 44 - #define rPdp_AntB 0xb70 45 45 - #define rPdp_AntB_4 0xb74 46 46 - #define rPdp_AntB_8 0xb78 47 47 - #define rPdp_AntB_C 0xb7c 48 48 - #define rPdp_AntB_10 0xb80 49 49 - #define rPdp_AntB_14 0xb84 50 50 - #define rPdp_AntB_18 0xb88 51 51 - #define rPdp_AntB_1C 0xb8c 52 52 - #define rPdp_AntB_20 0xb90 53 53 - #define rPdp_AntB_24 0xb94 54 54 - 55 55 - #define rConfig_Pmpd_AntB 0xb98 56 56 - 57 57 - #define rBndB 0xba0 58 58 - 59 59 - #define rAPK 0xbd8 60 60 - #define rPm_Rx0_AntA 0xbdc 61 61 - #define rPm_Rx1_AntA 0xbe0 62 62 - #define rPm_Rx2_AntA 0xbe4 63 63 - #define rPm_Rx3_AntA 0xbe8 64 64 - #define rPm_Rx0_AntB 0xbec 65 65 - #define rPm_Rx1_AntB 0xbf0 66 66 - #define rPm_Rx2_AntB 0xbf4 67 67 - #define rPm_Rx3_AntB 0xbf8 68 68 - 69 69 - #endif

-7

drivers/staging/rtl8723bs/include/hal_pwr_seq.h

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··· 28 28 #define RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS 26 29 29 #define RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS 15 30 30 #define RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS 15 31 31 - #define RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS 15 32 31 #define RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS 15 33 33 - #define RTL8723B_TRANS_PDN_TO_CARDEMU_STEPS 15 34 32 #define RTL8723B_TRANS_ACT_TO_LPS_STEPS 15 35 33 #define RTL8723B_TRANS_LPS_TO_ACT_STEPS 15 36 34 #define RTL8723B_TRANS_ACT_TO_SWLPS_STEPS 22 ··· 125 127 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ 126 128 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ 127 129 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ 128 128 - 129 129 - #define RTL8723B_TRANS_PDN_TO_CARDEMU \ 130 130 - /* format */ \ 131 131 - /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \ 132 132 - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ 133 130 134 131 #define RTL8723B_TRANS_ACT_TO_LPS \ 135 132 /* format */ \

+1 -1

drivers/staging/rtl8723bs/include/rtl8723b_hal.h

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··· 17 17 #include "rtl8723b_cmd.h" 18 18 #include "rtw_mp.h" 19 19 #include "hal_pwr_seq.h" 20 20 - #include "hal_phy_reg_8723b.h" 20 20 + #include "Hal8192CPhyReg.h" 21 21 #include "hal_phy_cfg.h" 22 22 23 23 /* */

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drivers/staging/rtl8723bs/include/rtw_efuse.h

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··· 7 7 #ifndef __RTW_EFUSE_H__ 8 8 #define __RTW_EFUSE_H__ 9 9 10 10 - 11 11 - #define EFUSE_ERROE_HANDLE 1 12 12 - 13 13 - #define PG_STATE_HEADER 0x01 14 14 - #define PG_STATE_WORD_0 0x02 15 15 - #define PG_STATE_WORD_1 0x04 16 16 - #define PG_STATE_WORD_2 0x08 17 17 - #define PG_STATE_WORD_3 0x10 18 18 - #define PG_STATE_DATA 0x20 19 19 - 20 20 - #define PG_SWBYTE_H 0x01 21 21 - #define PG_SWBYTE_L 0x02 22 22 - 23 10 #define PGPKT_DATA_SIZE 8 24 11 25 12 #define EFUSE_WIFI 0

-22

drivers/staging/rtl8723bs/include/rtw_ht.h

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··· 63 63 64 64 #define LDPC_HT_ENABLE_RX BIT0 65 65 #define LDPC_HT_ENABLE_TX BIT1 66 66 - #define LDPC_HT_TEST_TX_ENABLE BIT2 67 66 #define LDPC_HT_CAP_TX BIT3 68 67 69 68 #define STBC_HT_ENABLE_RX BIT0 70 69 #define STBC_HT_ENABLE_TX BIT1 71 71 - #define STBC_HT_TEST_TX_ENABLE BIT2 72 70 #define STBC_HT_CAP_TX BIT3 73 71 74 72 #define BEAMFORMING_HT_BEAMFORMER_ENABLE BIT0 /* Declare our NIC supports beamformer */ 75 73 #define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT1 /* Declare our NIC supports beamformee */ 76 76 - #define BEAMFORMING_HT_BEAMFORMER_TEST BIT2 /* Transmiting Beamforming no matter the target supports it or not */ 77 77 - 78 78 - /* */ 79 79 - /* The HT Control field */ 80 80 - /* */ 81 81 - #define SET_HT_CTRL_CSI_STEERING(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 6, 2, _val) 82 82 - #define SET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+3, 0, 1, _val) 83 83 - #define GET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+3, 0, 1) 84 74 85 75 /* 20/40 BSS Coexist */ 86 76 #define SET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart), 0, 1, _val) 87 87 - #define GET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart), 0, 1) 88 88 - 89 77 90 78 #define GET_HT_CAPABILITY_ELE_LDPC_CAP(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 0, 1) 91 79 #define GET_HT_CAPABILITY_ELE_TX_STBC(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 7, 1) 92 80 93 81 #define GET_HT_CAPABILITY_ELE_RX_STBC(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+1, 0, 2) 94 94 - 95 95 - /* TXBF Capabilities */ 96 96 - #define SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 3, 1, ((u8)_val)) 97 97 - #define SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 4, 1, ((u8)_val)) 98 98 - #define SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 10, 1, ((u8)_val)) 99 99 - #define SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 15, 2, ((u8)_val)) 100 100 - #define SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 23, 2, ((u8)_val)) 101 101 - 102 102 - #define GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart) LE_BITS_TO_4BYTE((_pEleStart)+21, 10, 1) 103 103 - #define GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart) LE_BITS_TO_4BYTE((_pEleStart)+21, 15, 2) 104 82 105 83 #endif /* _RTL871X_HT_H_ */

-57

drivers/staging/rtl8723bs/include/rtw_io.h

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··· 8 8 #ifndef _RTW_IO_H_ 9 9 #define _RTW_IO_H_ 10 10 11 11 - #define NUM_IOREQ 8 12 12 - 13 13 - #define MAX_PROT_SZ (64-16) 14 14 - 15 15 - #define _IOREADY 0 16 16 - #define _IO_WAIT_COMPLETE 1 17 17 - #define _IO_WAIT_RSP 2 18 18 - 19 19 - /* IO COMMAND TYPE */ 20 20 - #define _IOSZ_MASK_ (0x7F) 21 21 - #define _IO_WRITE_ BIT(7) 22 22 - #define _IO_FIXED_ BIT(8) 23 23 - #define _IO_BURST_ BIT(9) 24 24 - #define _IO_BYTE_ BIT(10) 25 25 - #define _IO_HW_ BIT(11) 26 26 - #define _IO_WORD_ BIT(12) 27 27 - #define _IO_SYNC_ BIT(13) 28 28 - #define _IO_CMDMASK_ (0x1F80) 29 29 - 30 30 - 31 11 /* 32 12 For prompt mode accessing, caller shall free io_req 33 13 Otherwise, io_handler will free io_req 34 14 */ 35 15 36 36 - 37 37 - 38 38 - /* IO STATUS TYPE */ 39 39 - #define _IO_ERR_ BIT(2) 40 40 - #define _IO_SUCCESS_ BIT(1) 41 41 - #define _IO_DONE_ BIT(0) 42 42 - 43 43 - 44 44 - #define IO_RD32 (_IO_SYNC_ | _IO_WORD_) 45 45 - #define IO_RD16 (_IO_SYNC_ | _IO_HW_) 46 46 - #define IO_RD8 (_IO_SYNC_ | _IO_BYTE_) 47 47 - 48 48 - #define IO_RD32_ASYNC (_IO_WORD_) 49 49 - #define IO_RD16_ASYNC (_IO_HW_) 50 50 - #define IO_RD8_ASYNC (_IO_BYTE_) 51 51 - 52 52 - #define IO_WR32 (_IO_WRITE_ | _IO_SYNC_ | _IO_WORD_) 53 53 - #define IO_WR16 (_IO_WRITE_ | _IO_SYNC_ | _IO_HW_) 54 54 - #define IO_WR8 (_IO_WRITE_ | _IO_SYNC_ | _IO_BYTE_) 55 55 - 56 56 - #define IO_WR32_ASYNC (_IO_WRITE_ | _IO_WORD_) 57 57 - #define IO_WR16_ASYNC (_IO_WRITE_ | _IO_HW_) 58 58 - #define IO_WR8_ASYNC (_IO_WRITE_ | _IO_BYTE_) 59 59 - 60 60 - /* 61 61 - 62 62 - Only Sync. burst accessing is provided. 63 63 - 64 64 - */ 65 65 - 66 66 - #define IO_WR_BURST(x) (_IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_)) 67 67 - #define IO_RD_BURST(x) (_IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_)) 68 68 - 69 69 - 70 70 - 71 16 /* below is for the intf_option bit defition... */ 72 72 - 73 73 - #define _INTF_ASYNC_ BIT(0) /* support async io */ 74 17 75 18 struct intf_priv; 76 19 struct intf_hdl;

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drivers/staging/rtl8723bs/include/rtw_mlme.h

reviewed

··· 26 26 27 27 #define WIFI_NULL_STATE 0x00000000 28 28 #define WIFI_ASOC_STATE 0x00000001 /* Under Linked state... */ 29 29 - #define WIFI_REASOC_STATE 0x00000002 30 29 #define WIFI_SLEEP_STATE 0x00000004 31 30 #define WIFI_STATION_STATE 0x00000008 32 31 #define WIFI_AP_STATE 0x00000010 ··· 34 35 #define WIFI_UNDER_LINKING 0x00000080 35 36 36 37 #define WIFI_UNDER_WPS 0x00000100 37 37 - /* define WIFI_UNDER_CMD 0x00000200 */ 38 38 - /* define WIFI_UNDER_P2P 0x00000400 */ 39 38 #define WIFI_STA_ALIVE_CHK_STATE 0x00000400 40 39 #define WIFI_SITE_MONITOR 0x00000800 /* to indicate the station is under site surveying */ 41 41 - #ifdef WDS 42 42 - #define WIFI_WDS 0x00001000 43 43 - #define WIFI_WDS_RX_BEACON 0x00002000 /* already rx WDS AP beacon */ 44 44 - #endif 45 45 - #ifdef AUTO_CONFIG 46 46 - #define WIFI_AUTOCONF 0x00004000 47 47 - #define WIFI_AUTOCONF_IND 0x00008000 48 48 - #endif 49 49 - 50 50 - /** 51 51 - * ========== P2P Section Start =============== 52 52 - #define WIFI_P2P_LISTEN_STATE 0x00010000 53 53 - #define WIFI_P2P_GROUP_FORMATION_STATE 0x00020000 54 54 - ========== P2P Section End =============== 55 55 - */ 56 40 57 41 /* ifdef UNDER_MPTEST */ 58 42 #define WIFI_MP_STATE 0x00010000 59 59 - #define WIFI_MP_CTX_BACKGROUND 0x00020000 /* in continuous tx background */ 60 60 - #define WIFI_MP_CTX_ST 0x00040000 /* in continuous tx with single-tone */ 61 61 - #define WIFI_MP_CTX_BACKGROUND_PENDING 0x00080000 /* pending in continuous tx background due to out of skb */ 62 62 - #define WIFI_MP_CTX_CCK_HW 0x00100000 /* in continuous tx */ 63 63 - #define WIFI_MP_CTX_CCK_CS 0x00200000 /* in continuous tx with carrier suppression */ 64 64 - #define WIFI_MP_LPBK_STATE 0x00400000 65 43 /* endif */ 66 44 67 45 /* define _FW_UNDER_CMD WIFI_UNDER_CMD */ ··· 70 94 GHZ_MAX, 71 95 }; 72 96 73 73 - #define rtw_band_valid(band) ((band) >= GHZ24_50 && (band) < GHZ_MAX) 74 74 - 75 97 /* 76 98 77 99 there are several "locks" in mlme_priv, ··· 88 114 MUST always be first lock xmit_priv.lock and then call any queue functions 89 115 which take __queue.lock. 90 116 */ 91 91 - 92 92 - 93 93 - #define traffic_threshold 10 94 94 - #define traffic_scan_period 500 95 117 96 118 struct sitesurvey_ctrl { 97 119 u64 last_tx_pkts; ··· 109 139 /* u8 TrafficBusyState; */ 110 140 u8 TrafficTransitionCount; 111 141 u32 LowPowerTransitionCount; 112 112 - }; 113 113 - 114 114 - struct profile_info { 115 115 - u8 ssidlen; 116 116 - u8 ssid[WLAN_SSID_MAXLEN]; 117 117 - u8 peermac[ETH_ALEN]; 118 118 - }; 119 119 - 120 120 - struct tx_invite_req_info { 121 121 - u8 token; 122 122 - u8 benable; 123 123 - u8 go_ssid[WLAN_SSID_MAXLEN]; 124 124 - u8 ssidlen; 125 125 - u8 go_bssid[ETH_ALEN]; 126 126 - u8 peer_macaddr[ETH_ALEN]; 127 127 - u8 operating_ch; /* This information will be set by using the p2p_set op_ch =x */ 128 128 - u8 peer_ch; /* The listen channel for peer P2P device */ 129 129 - 130 130 - }; 131 131 - 132 132 - struct tx_invite_resp_info { 133 133 - u8 token; /* Used to record the dialog token of p2p invitation request frame. */ 134 134 - }; 135 135 - 136 136 - struct tx_provdisc_req_info { 137 137 - u16 wps_config_method_request; /* Used when sending the provisioning request frame */ 138 138 - u16 peer_channel_num[2]; /* The channel number which the receiver stands. */ 139 139 - struct ndis_802_11_ssid ssid; 140 140 - u8 peerDevAddr[ETH_ALEN]; /* Peer device address */ 141 141 - u8 peerIFAddr[ETH_ALEN]; /* Peer interface address */ 142 142 - u8 benable; /* This provision discovery request frame is trigger to send or not */ 143 143 - }; 144 144 - 145 145 - struct rx_provdisc_req_info { /* When peer device issue prov_disc_req first, we should store the following information */ 146 146 - u8 peerDevAddr[ETH_ALEN]; /* Peer device address */ 147 147 - u8 strconfig_method_desc_of_prov_disc_req[4]; /* description for the config method located in the provisioning discovery request frame. */ 148 148 - /* The UI must know this information to know which config method the remote p2p device is requiring. */ 149 149 - }; 150 150 - 151 151 - struct tx_nego_req_info { 152 152 - u16 peer_channel_num[2]; /* The channel number which the receiver stands. */ 153 153 - u8 peerDevAddr[ETH_ALEN]; /* Peer device address */ 154 154 - u8 benable; /* This negotiation request frame is trigger to send or not */ 155 155 - }; 156 156 - 157 157 - struct group_id_info { 158 158 - u8 go_device_addr[ETH_ALEN]; /* The GO's device address of this P2P group */ 159 159 - u8 ssid[WLAN_SSID_MAXLEN]; /* The SSID of this P2P group */ 160 160 - }; 161 161 - 162 162 - struct scan_limit_info { 163 163 - u8 scan_op_ch_only; /* When this flag is set, the driver should just scan the operation channel */ 164 164 - u8 operation_ch[2]; /* Store the operation channel of invitation request frame */ 165 165 - }; 166 166 - 167 167 - struct wifidirect_info { 168 168 - struct adapter *padapter; 169 169 - struct timer_list find_phase_timer; 170 170 - struct timer_list restore_p2p_state_timer; 171 171 - 172 172 - /* Used to do the scanning. After confirming the peer is availalble, the driver transmits the P2P frame to peer. */ 173 173 - struct timer_list pre_tx_scan_timer; 174 174 - struct timer_list reset_ch_sitesurvey; 175 175 - struct timer_list reset_ch_sitesurvey2; /* Just for resetting the scan limit function by using p2p nego */ 176 176 - struct tx_provdisc_req_info tx_prov_disc_info; 177 177 - struct rx_provdisc_req_info rx_prov_disc_info; 178 178 - struct tx_invite_req_info invitereq_info; 179 179 - struct profile_info profileinfo[P2P_MAX_PERSISTENT_GROUP_NUM]; /* Store the profile information of persistent group */ 180 180 - struct tx_invite_resp_info inviteresp_info; 181 181 - struct tx_nego_req_info nego_req_info; 182 182 - struct group_id_info groupid_info; /* Store the group id information when doing the group negotiation handshake. */ 183 183 - struct scan_limit_info rx_invitereq_info; /* Used for get the limit scan channel from the Invitation procedure */ 184 184 - struct scan_limit_info p2p_info; /* Used for get the limit scan channel from the P2P negotiation handshake */ 185 185 - enum p2p_role role; 186 186 - enum p2p_state pre_p2p_state; 187 187 - enum p2p_state p2p_state; 188 188 - u8 device_addr[ETH_ALEN]; /* The device address should be the mac address of this device. */ 189 189 - u8 interface_addr[ETH_ALEN]; 190 190 - u8 social_chan[4]; 191 191 - u8 listen_channel; 192 192 - u8 operating_channel; 193 193 - u8 listen_dwell; /* This value should be between 1 and 3 */ 194 194 - u8 support_rate[8]; 195 195 - u8 p2p_wildcard_ssid[P2P_WILDCARD_SSID_LEN]; 196 196 - u8 intent; /* should only include the intent value. */ 197 197 - u8 p2p_peer_interface_addr[ETH_ALEN]; 198 198 - u8 p2p_peer_device_addr[ETH_ALEN]; 199 199 - u8 peer_intent; /* Included the intent value and tie breaker value. */ 200 200 - u8 device_name[WPS_MAX_DEVICE_NAME_LEN]; /* Device name for displaying on searching device screen */ 201 201 - u8 device_name_len; 202 202 - u8 profileindex; /* Used to point to the index of profileinfo array */ 203 203 - u8 peer_operating_ch; 204 204 - u8 find_phase_state_exchange_cnt; 205 205 - u16 device_password_id_for_nego; /* The device password ID for group negotiation */ 206 206 - u8 negotiation_dialog_token; 207 207 - u8 nego_ssid[WLAN_SSID_MAXLEN]; /* SSID information for group negotiation */ 208 208 - u8 nego_ssidlen; 209 209 - u8 p2p_group_ssid[WLAN_SSID_MAXLEN]; 210 210 - u8 p2p_group_ssid_len; 211 211 - u8 persistent_supported; /* Flag to know the persistent function should be supported or not. */ 212 212 - /* In the Sigma test, the Sigma will provide this enable from the sta_set_p2p CAPI. */ 213 213 - /* 0: disable */ 214 214 - /* 1: enable */ 215 215 - u8 session_available; /* Flag to set the WFD session available to enable or disable "by Sigma" */ 216 216 - /* In the Sigma test, the Sigma will disable the session available by using the sta_preset CAPI. */ 217 217 - /* 0: disable */ 218 218 - /* 1: enable */ 219 219 - 220 220 - u8 wfd_tdls_enable; /* Flag to enable or disable the TDLS by WFD Sigma */ 221 221 - /* 0: disable */ 222 222 - /* 1: enable */ 223 223 - u8 wfd_tdls_weaksec; /* Flag to enable or disable the weak security function for TDLS by WFD Sigma */ 224 224 - /* 0: disable */ 225 225 - /* In this case, the driver can't issue the tdsl setup request frame. */ 226 226 - /* 1: enable */ 227 227 - /* In this case, the driver can issue the tdls setup request frame */ 228 228 - /* even the current security is weak security. */ 229 229 - 230 230 - enum p2p_wpsinfo ui_got_wps_info; /* This field will store the WPS value (PIN value or PBC) that UI had got from the user. */ 231 231 - u16 supported_wps_cm; /* This field describes the WPS config method which this driver supported. */ 232 232 - /* The value should be the combination of config method defined in page104 of WPS v2.0 spec. */ 233 233 - u8 external_uuid; /* UUID flag */ 234 234 - u8 uuid[16]; /* UUID */ 235 235 - uint channel_list_attr_len; /* This field will contain the length of body of P2P Channel List attribute of group negotitation response frame. */ 236 236 - u8 channel_list_attr[100]; /* This field will contain the body of P2P Channel List attribute of group negotitation response frame. */ 237 237 - /* We will use the channel_cnt and channel_list fields when constructing the group negotitation confirm frame. */ 238 238 - u8 driver_interface; /* Indicate DRIVER_WEXT or DRIVER_CFG80211 */ 239 239 - }; 240 240 - 241 241 - struct tdls_ss_record { /* signal strength record */ 242 242 - u8 macaddr[ETH_ALEN]; 243 243 - u8 rx_pwd_ba11; 244 244 - u8 is_tdls_sta; /* true: direct link sta, false: else */ 245 142 }; 246 143 247 144 /* used for mlme_priv.roam_flags */ ··· 244 407 u8 NumOfBcnInfoChkFail; 245 408 unsigned long timeBcnInfoChkStart; 246 409 }; 247 247 - 248 248 - #define rtw_mlme_set_auto_scan_int(adapter, ms) \ 249 249 - do { \ 250 250 - adapter->mlmepriv.auto_scan_int_ms = ms; \ 251 251 - while (0) 252 410 253 411 void rtw_mlme_reset_auto_scan_int(struct adapter *adapter); 254 412 ··· 388 556 389 557 #define rtw_roam_flags(adapter) ((adapter)->mlmepriv.roam_flags) 390 558 #define rtw_chk_roam_flags(adapter, flags) ((adapter)->mlmepriv.roam_flags & flags) 391 391 - #define rtw_clr_roam_flags(adapter, flags) \ 392 392 - do { \ 393 393 - ((adapter)->mlmepriv.roam_flags &= ~flags); \ 394 394 - } while (0) 395 395 - 396 396 - #define rtw_set_roam_flags(adapter, flags) \ 397 397 - do { \ 398 398 - ((adapter)->mlmepriv.roam_flags |= flags); \ 399 399 - } while (0) 400 400 - 401 401 - #define rtw_assign_roam_flags(adapter, flags) \ 402 402 - do { \ 403 403 - ((adapter)->mlmepriv.roam_flags = flags); \ 404 404 - } while (0) 405 559 406 560 void _rtw_roaming(struct adapter *adapter, struct wlan_network *tgt_network); 407 561 void rtw_roaming(struct adapter *adapter, struct wlan_network *tgt_network);

-37

drivers/staging/rtl8723bs/include/rtw_mlme_ext.h

reviewed

··· 20 20 /* define DISCONNECT_TO (3000) */ 21 21 #define ADDBA_TO (2000) 22 22 23 23 - #define LINKED_TO (1) /* unit:2 sec, 1x2 =2 sec */ 24 24 - 25 23 #define REAUTH_LIMIT (4) 26 24 #define REASSOC_LIMIT (4) 27 27 - #define READDBA_LIMIT (2) 28 28 - 29 29 - #define ROAMING_LIMIT 8 30 30 - /* define IOCMD_REG0 0x10250370 */ 31 31 - /* define IOCMD_REG1 0x10250374 */ 32 32 - /* define IOCMD_REG2 0x10250378 */ 33 33 - 34 34 - /* define FW_DYNAMIC_FUN_SWITCH 0x10250364 */ 35 35 - 36 36 - /* define WRITE_BB_CMD 0xF0000001 */ 37 37 - /* define SET_CHANNEL_CMD 0xF3000000 */ 38 38 - /* define UPDATE_RA_CMD 0xFD0000A2 */ 39 25 40 26 #define DYNAMIC_FUNC_DISABLE (0x0) 41 27 42 28 /* ====== ODM_ABILITY_E ======== */ 43 29 /* BB ODM section BIT 0-15 */ 44 30 #define DYNAMIC_BB_DIG BIT0 /* ODM_BB_DIG */ 45 45 - #define DYNAMIC_BB_RA_MASK BIT1 /* ODM_BB_RA_MASK */ 46 31 #define DYNAMIC_BB_DYNAMIC_TXPWR BIT2 /* ODM_BB_DYNAMIC_TXPWR */ 47 47 - #define DYNAMIC_BB_BB_FA_CNT BIT3 /* ODM_BB_FA_CNT */ 48 48 - #define DYNAMIC_BB_RSSI_MONITOR BIT4 /* ODM_BB_RSSI_MONITOR */ 49 49 - #define DYNAMIC_BB_CCK_PD BIT5 /* ODM_BB_CCK_PD */ 50 32 #define DYNAMIC_BB_ANT_DIV BIT6 /* ODM_BB_ANT_DIV */ 51 51 - #define DYNAMIC_BB_PWR_SAVE BIT7 /* ODM_BB_PWR_SAVE */ 52 52 - #define DYNAMIC_BB_PWR_TRAIN BIT8 /* ODM_BB_PWR_TRAIN */ 53 53 - #define DYNAMIC_BB_RATE_ADAPTIVE BIT9 /* ODM_BB_RATE_ADAPTIVE */ 54 54 - #define DYNAMIC_BB_PATH_DIV BIT10/* ODM_BB_PATH_DIV */ 55 55 - #define DYNAMIC_BB_PSD BIT11/* ODM_BB_PSD */ 56 56 - #define DYNAMIC_BB_RXHP BIT12/* ODM_BB_RXHP */ 57 57 - #define DYNAMIC_BB_ADAPTIVITY BIT13/* ODM_BB_ADAPTIVITY */ 58 58 - #define DYNAMIC_BB_DYNAMIC_ATC BIT14/* ODM_BB_DYNAMIC_ATC */ 59 59 - 60 60 - /* MAC DM section BIT 16-23 */ 61 61 - #define DYNAMIC_MAC_EDCA_TURBO BIT16/* ODM_MAC_EDCA_TURBO */ 62 62 - #define DYNAMIC_MAC_EARLY_MODE BIT17/* ODM_MAC_EARLY_MODE */ 63 33 64 34 /* RF ODM section BIT 24-31 */ 65 65 - #define DYNAMIC_RF_TX_PWR_TRACK BIT24/* ODM_RF_TX_PWR_TRACK */ 66 66 - #define DYNAMIC_RF_RX_GAIN_TRACK BIT25/* ODM_RF_RX_GAIN_TRACK */ 67 35 #define DYNAMIC_RF_CALIBRATION BIT26/* ODM_RF_CALIBRATION */ 68 36 69 37 #define DYNAMIC_ALL_FUNC_ENABLE 0xFFFFFFF ··· 59 91 MCS rate definitions 60 92 *********************************************************/ 61 93 #define MCS_RATE_1R (0x000000ff) 62 62 - #define MCS_RATE_2R (0x0000ffff) 63 63 - #define MCS_RATE_3R (0x00ffffff) 64 64 - #define MCS_RATE_4R (0xffffffff) 65 65 - #define MCS_RATE_2R_13TO15_OFF (0x00001fff) 66 66 - 67 94 68 95 extern unsigned char RTW_WPA_OUI[]; 69 96 extern unsigned char WMM_OUI[];

-29

drivers/staging/rtl8723bs/include/rtw_mp.h

reviewed

··· 8 8 #define _RTW_MP_H_ 9 9 10 10 #define MAX_MP_XMITBUF_SZ 2048 11 11 - #define NR_MP_XMITFRAME 8 12 11 13 12 struct mp_xmit_frame { 14 13 struct list_head list; ··· 150 151 }; 151 152 /* endif */ 152 153 153 153 - /* E-Fuse */ 154 154 - #define EFUSE_MAP_SIZE 512 155 155 - 156 156 - #define EFUSE_MAX_SIZE 512 157 157 - /* end of E-Fuse */ 158 158 - 159 154 /* define RTPRIV_IOCTL_MP (SIOCIWFIRSTPRIV + 0x17) */ 160 155 enum { 161 156 WRITE_REG = 1, ··· 252 259 u8 *TXradomBuffer; 253 260 }; 254 261 255 255 - #define LOWER true 256 256 - #define RAISE false 257 257 - 258 262 /* Hardware Registers */ 259 259 - #define BB_REG_BASE_ADDR 0x800 260 260 - 261 261 - #define MAX_RF_PATH_NUMS RF_PATH_MAX 262 262 - 263 263 extern u8 mpdatarate[NumRates]; 264 264 265 265 #define MAX_TX_PWR_INDEX_N_MODE 64 /* 0x3F */ 266 266 - 267 267 - #define RX_PKT_BROADCAST 1 268 268 - #define RX_PKT_DEST_ADDR 2 269 269 - #define RX_PKT_PHY_MATCH 3 270 270 - 271 271 - #define Mac_OFDM_OK 0x00000000 272 272 - #define Mac_OFDM_Fail 0x10000000 273 273 - #define Mac_OFDM_FasleAlarm 0x20000000 274 274 - #define Mac_CCK_OK 0x30000000 275 275 - #define Mac_CCK_Fail 0x40000000 276 276 - #define Mac_CCK_FasleAlarm 0x50000000 277 277 - #define Mac_HT_OK 0x60000000 278 278 - #define Mac_HT_Fail 0x70000000 279 279 - #define Mac_HT_FasleAlarm 0x90000000 280 280 - #define Mac_DropPacket 0xA0000000 281 266 282 267 #define REG_RF_BB_GAIN_OFFSET 0x7f 283 268 #define RF_GAIN_OFFSET_MASK 0xfffff

-38

drivers/staging/rtl8723bs/include/rtw_pwrctrl.h

reviewed

··· 9 9 10 10 #include <linux/mutex.h> 11 11 12 12 - #define FW_PWR0 0 13 13 - #define FW_PWR1 1 14 14 - #define FW_PWR2 2 15 15 - #define FW_PWR3 3 16 16 - 17 17 - 18 18 - #define HW_PWR0 7 19 19 - #define HW_PWR1 6 20 20 - #define HW_PWR2 2 21 21 - #define HW_PWR3 0 22 22 - #define HW_PWR4 8 23 23 - 24 24 - #define FW_PWRMSK 0x7 25 25 - 26 26 - 27 12 #define XMIT_ALIVE BIT(0) 28 28 - #define RECV_ALIVE BIT(1) 29 13 #define CMD_ALIVE BIT(2) 30 30 - #define EVT_ALIVE BIT(3) 31 14 #define BTCOEX_ALIVE BIT(4) 32 15 33 16 ··· 41 58 #define PS_ALL_ON BIT(2) 42 59 #define PS_ST_ACTIVE BIT(3) 43 60 44 44 - #define PS_ISR_ENABLE BIT(4) 45 45 - #define PS_IMR_ENABLE BIT(5) 46 61 #define PS_ACK BIT(6) 47 62 #define PS_TOGGLE BIT(7) 48 63 49 64 #define PS_STATE_MASK (0x0F) 50 50 - #define PS_STATE_HW_MASK (0x07) 51 51 - #define PS_SEQ_MASK (0xc0) 52 65 53 66 #define PS_STATE(x) (PS_STATE_MASK & (x)) 54 54 - #define PS_STATE_HW(x) (PS_STATE_HW_MASK & (x)) 55 55 - #define PS_SEQ(x) (PS_SEQ_MASK & (x)) 56 67 57 68 #define PS_STATE_S0 (PS_DPS) 58 58 - #define PS_STATE_S1 (PS_LCLK) 59 69 #define PS_STATE_S2 (PS_RF_OFF) 60 60 - #define PS_STATE_S3 (PS_ALL_ON) 61 70 #define PS_STATE_S4 ((PS_ST_ACTIVE) | (PS_ALL_ON)) 62 62 - 63 63 - 64 64 - #define PS_IS_RF_ON(x) ((x) & (PS_ALL_ON)) 65 65 - #define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE)) 66 66 - #define CLR_PS_STATE(x) ((x) = ((x) & (0xF0))) 67 67 - 68 71 69 72 struct reportpwrstate_parm { 70 73 unsigned char mode; ··· 59 90 }; 60 91 61 92 #define LPS_DELAY_TIME (1 * HZ) /* 1 sec */ 62 62 - 63 63 - #define EXE_PWR_NONE 0x01 64 64 - #define EXE_PWR_IPS 0x02 65 65 - #define EXE_PWR_LPS 0x04 66 93 67 94 /* RF state. */ 68 95 enum rt_rf_power_state { ··· 211 246 do { \ 212 247 _set_timer(&(pwrctl)->pwr_state_check_timer, (ms)); \ 213 248 } while (0) 214 214 - 215 215 - #define rtw_set_pwr_state_check_timer(pwrctl) \ 216 216 - _rtw_set_pwr_state_check_timer((pwrctl), (pwrctl)->pwr_state_check_interval) 217 249 218 250 extern void rtw_init_pwrctrl_priv(struct adapter *adapter); 219 251 extern void rtw_free_pwrctrl_priv(struct adapter *adapter);

-16

drivers/staging/rtl8723bs/include/rtw_recv.h

reviewed

··· 9 9 10 10 #define NR_RECVBUFF (8) 11 11 12 12 - #define NR_PREALLOC_RECV_SKB (8) 13 13 - 14 12 #define NR_RECVFRAME 256 15 13 16 14 #define RXFRAME_ALIGN 8 ··· 16 18 17 19 #define DRVINFO_SZ 4 /* unit is 8bytes */ 18 20 19 19 - #define MAX_RXFRAME_CNT 512 20 21 #define MAX_RX_NUMBLKS (32) 21 22 #define RECVFRAME_HDR_ALIGN 128 22 23 23 23 - 24 24 - #define PHY_RSSI_SLID_WIN_MAX 100 25 25 - #define PHY_LINKQUALITY_SLID_WIN_MAX 20 26 26 - 27 27 - 28 24 #define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) 29 29 - 30 30 - #define RX_MPDU_QUEUE 0 31 31 - #define RX_CMD_QUEUE 1 32 32 - #define RX_MAX_QUEUE 2 33 25 34 26 #define MAX_SUBFRAME_COUNT 64 35 27 ··· 166 178 #define RECVBUFF_ALIGN_SZ 8 167 179 168 180 #define RXDESC_SIZE 24 169 169 - #define RXDESC_OFFSET RXDESC_SIZE 170 181 171 182 struct recv_stat { 172 183 __le32 rxdw0; ··· 177 190 __le32 rxdw5; 178 191 #endif /* if BUF_DESC_ARCH is defined, rx_buf_desc occupy 4 double words */ 179 192 }; 180 180 - 181 181 - #define EOR BIT(30) 182 193 183 194 /* 184 195 accesser of recv_priv: rtw_recv_entry(dispatch / passive level); recv_thread(passive) ; returnpkt(dispatch) ··· 348 363 extern union recv_frame *rtw_alloc_recvframe(struct __queue *pfree_recv_queue); /* get a free recv_frame from pfree_recv_queue */ 349 364 extern int rtw_free_recvframe(union recv_frame *precvframe, struct __queue *pfree_recv_queue); 350 365 351 351 - #define rtw_dequeue_recvframe(queue) rtw_alloc_recvframe(queue) 352 366 extern int _rtw_enqueue_recvframe(union recv_frame *precvframe, struct __queue *queue); 353 367 extern int rtw_enqueue_recvframe(union recv_frame *precvframe, struct __queue *queue); 354 368

-5

drivers/staging/rtl8723bs/include/rtw_security.h

reviewed

··· 22 22 23 23 const char *security_type_str(u8 value); 24 24 25 25 - #define SHA256_MAC_LEN 32 26 25 #define AES_BLOCK_SIZE 16 27 26 #define AES_PRIV_SIZE (4 * 44) 28 28 - 29 29 - #define RTW_KEK_LEN 16 30 30 - #define RTW_KCK_LEN 16 31 31 - #define RTW_REPLAY_CTR_LEN 8 32 27 33 28 enum { 34 29 ENCRYP_PROTOCOL_OPENSYS, /* open system */

-10

drivers/staging/rtl8723bs/include/rtw_xmit.h

reviewed

··· 35 35 #define BCN_QUEUE_INX 4 36 36 #define MGT_QUEUE_INX 5 37 37 #define HIGH_QUEUE_INX 6 38 38 - #define TXCMD_QUEUE_INX 7 39 38 40 39 #define HW_QUEUE_ENTRY 8 41 40 ··· 191 192 192 193 #define NULL_FRAMETAG (0x0) 193 194 #define DATA_FRAMETAG 0x01 194 194 - #define L2_FRAMETAG 0x02 195 195 #define MGNT_FRAMETAG 0x03 196 196 - #define AMSDU_FRAMETAG 0x04 197 197 - 198 198 - #define EII_FRAMETAG 0x05 199 199 - #define IEEE8023_FRAMETAG 0x06 200 200 - 201 201 - #define MP_FRAMETAG 0x07 202 202 - 203 203 - #define TXAGG_FRAMETAG 0x08 204 196 205 197 enum { 206 198 XMITBUF_DATA = 0,

-4

drivers/staging/rtl8723bs/include/sdio_hal.h

reviewed

··· 7 7 #ifndef __SDIO_HAL_H__ 8 8 #define __SDIO_HAL_H__ 9 9 10 10 - 11 11 - extern u8 sd_hal_bus_init(struct adapter *padapter); 12 12 - extern u8 sd_hal_bus_deinit(struct adapter *padapter); 13 13 - 14 10 u8 sd_int_isr(struct adapter *padapter); 15 11 void sd_int_dpc(struct adapter *padapter); 16 12 void rtw_set_hal_ops(struct adapter *padapter);

-16

drivers/staging/rtl8723bs/include/sdio_osintf.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 2 - /****************************************************************************** 3 3 - * 4 4 - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 5 - * 6 6 - ******************************************************************************/ 7 7 - #ifndef __SDIO_OSINTF_H__ 8 8 - #define __SDIO_OSINTF_H__ 9 9 - 10 10 - 11 11 - 12 12 - u8 sd_hal_bus_init(struct adapter *padapter); 13 13 - u8 sd_hal_bus_deinit(struct adapter *padapter); 14 14 - void sd_c2h_hdl(struct adapter *padapter); 15 15 - 16 16 - #endif

-44

drivers/staging/rtl8723bs/include/sta_info.h

reviewed

··· 222 222 + sta->sta_stats.rx_ctrl_pkts \ 223 223 + sta->sta_stats.rx_data_pkts) 224 224 225 225 - #define sta_last_rx_pkts(sta) \ 226 226 - (sta->sta_stats.last_rx_mgnt_pkts \ 227 227 - + sta->sta_stats.last_rx_ctrl_pkts \ 228 228 - + sta->sta_stats.last_rx_data_pkts) 229 229 - 230 225 #define sta_rx_data_pkts(sta) \ 231 226 (sta->sta_stats.rx_data_pkts) 232 227 233 228 #define sta_last_rx_data_pkts(sta) \ 234 229 (sta->sta_stats.last_rx_data_pkts) 235 235 - 236 236 - #define sta_rx_mgnt_pkts(sta) \ 237 237 - (sta->sta_stats.rx_mgnt_pkts) 238 238 - 239 239 - #define sta_last_rx_mgnt_pkts(sta) \ 240 240 - (sta->sta_stats.last_rx_mgnt_pkts) 241 230 242 231 #define sta_rx_beacon_pkts(sta) \ 243 232 (sta->sta_stats.rx_beacon_pkts) ··· 234 245 #define sta_last_rx_beacon_pkts(sta) \ 235 246 (sta->sta_stats.last_rx_beacon_pkts) 236 247 237 237 - #define sta_rx_probereq_pkts(sta) \ 238 238 - (sta->sta_stats.rx_probereq_pkts) 239 239 - 240 240 - #define sta_last_rx_probereq_pkts(sta) \ 241 241 - (sta->sta_stats.last_rx_probereq_pkts) 242 242 - 243 248 #define sta_rx_probersp_pkts(sta) \ 244 249 (sta->sta_stats.rx_probersp_pkts) 245 250 246 251 #define sta_last_rx_probersp_pkts(sta) \ 247 252 (sta->sta_stats.last_rx_probersp_pkts) 248 248 - 249 249 - #define sta_rx_probersp_bm_pkts(sta) \ 250 250 - (sta->sta_stats.rx_probersp_bm_pkts) 251 251 - 252 252 - #define sta_last_rx_probersp_bm_pkts(sta) \ 253 253 - (sta->sta_stats.last_rx_probersp_bm_pkts) 254 254 - 255 255 - #define sta_rx_probersp_uo_pkts(sta) \ 256 256 - (sta->sta_stats.rx_probersp_uo_pkts) 257 257 - 258 258 - #define sta_last_rx_probersp_uo_pkts(sta) \ 259 259 - (sta->sta_stats.last_rx_probersp_uo_pkts) 260 253 261 254 #define sta_update_last_rx_pkts(sta) \ 262 255 do { \ ··· 251 280 sta->sta_stats.last_rx_ctrl_pkts = sta->sta_stats.rx_ctrl_pkts; \ 252 281 sta->sta_stats.last_rx_data_pkts = sta->sta_stats.rx_data_pkts; \ 253 282 } while (0) 254 254 - 255 255 - #define STA_RX_PKTS_ARG(sta) \ 256 256 - sta->sta_stats.rx_mgnt_pkts \ 257 257 - , sta->sta_stats.rx_ctrl_pkts \ 258 258 - , sta->sta_stats.rx_data_pkts 259 259 - 260 260 - #define STA_LAST_RX_PKTS_ARG(sta) \ 261 261 - sta->sta_stats.last_rx_mgnt_pkts \ 262 262 - , sta->sta_stats.last_rx_ctrl_pkts \ 263 263 - , sta->sta_stats.last_rx_data_pkts 264 264 - 265 265 - #define STA_RX_PKTS_DIFF_ARG(sta) \ 266 266 - sta->sta_stats.rx_mgnt_pkts - sta->sta_stats.last_rx_mgnt_pkts \ 267 267 - , sta->sta_stats.rx_ctrl_pkts - sta->sta_stats.last_rx_ctrl_pkts \ 268 268 - , sta->sta_stats.rx_data_pkts - sta->sta_stats.last_rx_data_pkts 269 283 270 284 #define STA_PKTS_FMT "(m:%llu, c:%llu, d:%llu)" 271 285

-299

drivers/staging/rtl8723bs/include/wifi.h

reviewed

··· 7 7 #ifndef _WIFI_H_ 8 8 #define _WIFI_H_ 9 9 10 10 - #define WLAN_ETHHDR_LEN 14 11 11 - #define WLAN_ETHADDR_LEN 6 12 12 - #define WLAN_IEEE_OUI_LEN 3 13 13 - #define WLAN_ADDR_LEN 6 14 14 - #define WLAN_CRC_LEN 4 15 15 - #define WLAN_BSSID_LEN 6 16 16 - #define WLAN_BSS_TS_LEN 8 17 10 #define WLAN_HDR_A3_LEN 24 18 18 - #define WLAN_HDR_A4_LEN 30 19 11 #define WLAN_HDR_A3_QOS_LEN 26 20 20 - #define WLAN_HDR_A4_QOS_LEN 32 21 21 - #define WLAN_SSID_MAXLEN 32 22 22 - #define WLAN_DATA_MAXLEN 2312 23 12 24 24 - #define WLAN_A3_PN_OFFSET 24 25 25 - #define WLAN_A4_PN_OFFSET 30 26 26 - 27 27 - #define WLAN_MIN_ETHFRM_LEN 60 28 28 - #define WLAN_MAX_ETHFRM_LEN 1514 29 29 - #define WLAN_ETHHDR_LEN 14 30 13 #define WLAN_WMM_LEN 24 31 31 - 32 32 - #define P80211CAPTURE_VERSION 0x80211001 33 14 34 15 /* This value is tested by WiFi 11n Test Plan 5.2.3. */ 35 16 /* This test verifies the WLAN NIC can update the NAV through sending the CTS with large duration. */ ··· 144 163 145 164 #define GetFragNum(pbuf) \ 146 165 (le16_to_cpu(*(__le16 *)((size_t)(pbuf) + 22)) & 0x0f) 147 147 - 148 148 - #define GetTupleCache(pbuf) \ 149 149 - (cpu_to_le16(*(unsigned short *)((size_t)(pbuf) + 22))) 150 166 151 167 #define SetFragNum(pbuf, num) \ 152 168 do { \ ··· 283 305 /*----------------------------------------------------------------------------- 284 306 Below is for the security related definition 285 307 ------------------------------------------------------------------------------*/ 286 286 - #define _RESERVED_FRAME_TYPE_ 0 287 287 - #define _SKB_FRAME_TYPE_ 2 288 288 - #define _PRE_ALLOCMEM_ 1 289 289 - #define _PRE_ALLOCHDR_ 3 290 290 - #define _PRE_ALLOCLLCHDR_ 4 291 291 - #define _PRE_ALLOCICVHDR_ 5 292 292 - #define _PRE_ALLOCMICHDR_ 6 293 293 - 294 294 - #define _ACKCTSLNG_ 14 /* 14 bytes long, including crclng */ 295 295 - #define _CRCLNG_ 4 296 308 297 309 #define _ASOCREQ_IE_OFFSET_ 4 /* excluding wlan_hdr */ 298 298 - #define _ASOCRSP_IE_OFFSET_ 6 299 310 #define _REASOCREQ_IE_OFFSET_ 10 300 300 - #define _REASOCRSP_IE_OFFSET_ 6 301 311 #define _PROBEREQ_IE_OFFSET_ 0 302 312 #define _PROBERSP_IE_OFFSET_ 12 303 313 #define _AUTH_IE_OFFSET_ 6 304 304 - #define _DEAUTH_IE_OFFSET_ 0 305 314 #define _BEACON_IE_OFFSET_ 12 306 306 - #define _PUBLIC_ACTION_IE_OFFSET_ 8 307 315 308 316 #define _FIXED_IE_LENGTH_ _BEACON_IE_OFFSET_ 309 317 ··· 300 336 #define _AUTH_SEQ_NUM_ 2 301 337 #define _BEACON_ITERVAL_ 2 302 338 #define _CAPABILITY_ 2 303 303 - #define _CURRENT_APADDR_ 6 304 304 - #define _LISTEN_INTERVAL_ 2 305 339 #define _RSON_CODE_ 2 306 340 #define _ASOC_ID_ 2 307 341 #define _STATUS_CODE_ 2 308 342 #define _TIMESTAMP_ 8 309 309 - 310 310 - #define AUTH_ODD_TO 0 311 311 - #define AUTH_EVEN_TO 1 312 312 - 313 313 - #define WLAN_ETHCONV_ENCAP 1 314 314 - #define WLAN_ETHCONV_RFC1042 2 315 315 - #define WLAN_ETHCONV_8021h 3 316 343 317 344 /*----------------------------------------------------------------------------- 318 345 Below is the definition for 802.11i / 802.1x ··· 316 361 Below is the definition for WMM 317 362 ------------------------------------------------------------------------------*/ 318 363 #define _WMM_IE_Length_ 7 /* for WMM STA */ 319 319 - #define _WMM_Para_Element_Length_ 24 320 320 - 321 364 322 365 /*----------------------------------------------------------------------------- 323 366 Below is the definition for 802.11n 324 367 ------------------------------------------------------------------------------*/ 325 325 - 326 326 - #define SetOrderBit(pbuf) \ 327 327 - do { \ 328 328 - *(unsigned short *)(pbuf) |= cpu_to_le16(_ORDER_); \ 329 329 - } while (0) 330 330 - 331 368 #define GetOrderBit(pbuf) (((*(unsigned short *)(pbuf)) & cpu_to_le16(_ORDER_)) != 0) 332 369 333 370 #define ACT_CAT_VENDOR 0x7F/* 127 */ ··· 387 440 #define IEEE80211_HT_CAP_SGI_40 0x0040 388 441 #define IEEE80211_HT_CAP_TX_STBC 0x0080 389 442 #define IEEE80211_HT_CAP_RX_STBC_1R 0x0100 390 390 - #define IEEE80211_HT_CAP_RX_STBC_2R 0x0200 391 443 #define IEEE80211_HT_CAP_RX_STBC_3R 0x0300 392 392 - #define IEEE80211_HT_CAP_DELAY_BA 0x0400 393 444 #define IEEE80211_HT_CAP_MAX_AMSDU 0x0800 394 445 #define IEEE80211_HT_CAP_DSSSCCK40 0x1000 395 446 /* 802.11n HT capability AMPDU settings */ 396 447 #define IEEE80211_HT_CAP_AMPDU_FACTOR 0x03 397 448 #define IEEE80211_HT_CAP_AMPDU_DENSITY 0x1C 398 398 - /* 802.11n HT capability MSC set */ 399 399 - #define IEEE80211_SUPP_MCS_SET_UEQM 4 400 400 - #define IEEE80211_HT_CAP_MAX_STREAMS 4 401 401 - #define IEEE80211_SUPP_MCS_SET_LEN 10 402 402 - /* maximum streams the spec allows */ 403 403 - #define IEEE80211_HT_CAP_MCS_TX_DEFINED 0x01 404 404 - #define IEEE80211_HT_CAP_MCS_TX_RX_DIFF 0x02 405 405 - #define IEEE80211_HT_CAP_MCS_TX_STREAMS 0x0C 406 406 - #define IEEE80211_HT_CAP_MCS_TX_UEQM 0x10 407 407 - /* 802.11n HT capability TXBF capability */ 408 408 - #define IEEE80211_HT_CAP_TXBF_RX_NDP 0x00000008 409 409 - #define IEEE80211_HT_CAP_TXBF_TX_NDP 0x00000010 410 410 - #define IEEE80211_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP 0x00000400 411 449 412 450 /* endif */ 413 451 414 452 /* ===============WPS Section =============== */ 415 415 - /* For WPSv1.0 */ 416 416 - #define WPSOUI 0x0050f204 417 453 /* WPS attribute ID */ 418 418 - #define WPS_ATTR_VER1 0x104A 419 419 - #define WPS_ATTR_SIMPLE_CONF_STATE 0x1044 420 420 - #define WPS_ATTR_RESP_TYPE 0x103B 421 421 - #define WPS_ATTR_UUID_E 0x1047 422 422 - #define WPS_ATTR_MANUFACTURER 0x1021 423 423 - #define WPS_ATTR_MODEL_NAME 0x1023 424 424 - #define WPS_ATTR_MODEL_NUMBER 0x1024 425 425 - #define WPS_ATTR_SERIAL_NUMBER 0x1042 426 426 - #define WPS_ATTR_PRIMARY_DEV_TYPE 0x1054 427 427 - #define WPS_ATTR_SEC_DEV_TYPE_LIST 0x1055 428 428 - #define WPS_ATTR_DEVICE_NAME 0x1011 429 429 - #define WPS_ATTR_CONF_METHOD 0x1008 430 430 - #define WPS_ATTR_RF_BANDS 0x103C 431 431 - #define WPS_ATTR_DEVICE_PWID 0x1012 432 432 - #define WPS_ATTR_REQUEST_TYPE 0x103A 433 433 - #define WPS_ATTR_ASSOCIATION_STATE 0x1002 434 434 - #define WPS_ATTR_CONFIG_ERROR 0x1009 435 435 - #define WPS_ATTR_VENDOR_EXT 0x1049 436 454 #define WPS_ATTR_SELECTED_REGISTRAR 0x1041 437 455 438 438 - /* Value of WPS attribute "WPS_ATTR_DEVICE_NAME */ 439 439 - #define WPS_MAX_DEVICE_NAME_LEN 32 440 440 - 441 441 - /* Value of WPS Request Type Attribute */ 442 442 - #define WPS_REQ_TYPE_ENROLLEE_INFO_ONLY 0x00 443 443 - #define WPS_REQ_TYPE_ENROLLEE_OPEN_8021X 0x01 444 444 - #define WPS_REQ_TYPE_REGISTRAR 0x02 445 445 - #define WPS_REQ_TYPE_WLAN_MANAGER_REGISTRAR 0x03 446 446 - 447 447 - /* Value of WPS Response Type Attribute */ 448 448 - #define WPS_RESPONSE_TYPE_INFO_ONLY 0x00 449 449 - #define WPS_RESPONSE_TYPE_8021X 0x01 450 450 - #define WPS_RESPONSE_TYPE_REGISTRAR 0x02 451 451 - #define WPS_RESPONSE_TYPE_AP 0x03 452 452 - 453 453 - /* Value of WPS WiFi Simple Configuration State Attribute */ 454 454 - #define WPS_WSC_STATE_NOT_CONFIG 0x01 455 455 - #define WPS_WSC_STATE_CONFIG 0x02 456 456 - 457 457 - /* Value of WPS Version Attribute */ 458 458 - #define WPS_VERSION_1 0x10 459 459 - 460 460 - /* Value of WPS Configuration Method Attribute */ 461 461 - #define WPS_CONFIG_METHOD_FLASH 0x0001 462 462 - #define WPS_CONFIG_METHOD_ETHERNET 0x0002 463 463 - #define WPS_CONFIG_METHOD_LABEL 0x0004 464 464 - #define WPS_CONFIG_METHOD_DISPLAY 0x0008 465 465 - #define WPS_CONFIG_METHOD_E_NFC 0x0010 466 466 - #define WPS_CONFIG_METHOD_I_NFC 0x0020 467 467 - #define WPS_CONFIG_METHOD_NFC 0x0040 468 468 - #define WPS_CONFIG_METHOD_PBC 0x0080 469 469 - #define WPS_CONFIG_METHOD_KEYPAD 0x0100 470 470 - #define WPS_CONFIG_METHOD_VPBC 0x0280 471 471 - #define WPS_CONFIG_METHOD_PPBC 0x0480 472 472 - #define WPS_CONFIG_METHOD_VDISPLAY 0x2008 473 473 - #define WPS_CONFIG_METHOD_PDISPLAY 0x4008 474 474 - 475 475 - /* Value of Category ID of WPS Primary Device Type Attribute */ 476 476 - #define WPS_PDT_CID_DISPLAYS 0x0007 477 477 - #define WPS_PDT_CID_MULIT_MEDIA 0x0008 478 478 - #define WPS_PDT_CID_RTK_WIDI WPS_PDT_CID_MULIT_MEDIA 479 479 - 480 480 - /* Value of Sub Category ID of WPS Primary Device Type Attribute */ 481 481 - #define WPS_PDT_SCID_MEDIA_SERVER 0x0005 482 482 - #define WPS_PDT_SCID_RTK_DMP WPS_PDT_SCID_MEDIA_SERVER 483 483 - 484 484 - /* Value of Device Password ID */ 485 485 - #define WPS_DPID_PIN 0x0000 486 486 - #define WPS_DPID_USER_SPEC 0x0001 487 487 - #define WPS_DPID_MACHINE_SPEC 0x0002 488 488 - #define WPS_DPID_REKEY 0x0003 489 489 - #define WPS_DPID_PBC 0x0004 490 490 - #define WPS_DPID_REGISTRAR_SPEC 0x0005 491 491 - 492 492 - /* Value of WPS RF Bands Attribute */ 493 493 - #define WPS_RF_BANDS_2_4_GHZ 0x01 494 494 - #define WPS_RF_BANDS_5_GHZ 0x02 495 495 - 496 496 - /* Value of WPS Association State Attribute */ 497 497 - #define WPS_ASSOC_STATE_NOT_ASSOCIATED 0x00 498 498 - #define WPS_ASSOC_STATE_CONNECTION_SUCCESS 0x01 499 499 - #define WPS_ASSOC_STATE_CONFIGURATION_FAILURE 0x02 500 500 - #define WPS_ASSOC_STATE_ASSOCIATION_FAILURE 0x03 501 501 - #define WPS_ASSOC_STATE_IP_FAILURE 0x04 502 502 - 503 456 /* =====================P2P Section ===================== */ 504 504 - /* For P2P */ 505 505 - #define P2POUI 0x506F9A09 506 506 - 507 507 - /* P2P Attribute ID */ 508 508 - #define P2P_ATTR_STATUS 0x00 509 509 - #define P2P_ATTR_MINOR_REASON_CODE 0x01 510 510 - #define P2P_ATTR_CAPABILITY 0x02 511 511 - #define P2P_ATTR_DEVICE_ID 0x03 512 512 - #define P2P_ATTR_GO_INTENT 0x04 513 513 - #define P2P_ATTR_CONF_TIMEOUT 0x05 514 514 - #define P2P_ATTR_LISTEN_CH 0x06 515 515 - #define P2P_ATTR_GROUP_BSSID 0x07 516 516 - #define P2P_ATTR_EX_LISTEN_TIMING 0x08 517 517 - #define P2P_ATTR_INTENTED_IF_ADDR 0x09 518 518 - #define P2P_ATTR_MANAGEABILITY 0x0A 519 519 - #define P2P_ATTR_CH_LIST 0x0B 520 520 - #define P2P_ATTR_NOA 0x0C 521 521 - #define P2P_ATTR_DEVICE_INFO 0x0D 522 522 - #define P2P_ATTR_GROUP_INFO 0x0E 523 523 - #define P2P_ATTR_GROUP_ID 0x0F 524 524 - #define P2P_ATTR_INTERFACE 0x10 525 525 - #define P2P_ATTR_OPERATING_CH 0x11 526 526 - #define P2P_ATTR_INVITATION_FLAGS 0x12 527 527 - 528 528 - /* Value of Status Attribute */ 529 529 - #define P2P_STATUS_SUCCESS 0x00 530 530 - #define P2P_STATUS_FAIL_INFO_UNAVAILABLE 0x01 531 531 - #define P2P_STATUS_FAIL_INCOMPATIBLE_PARAM 0x02 532 532 - #define P2P_STATUS_FAIL_LIMIT_REACHED 0x03 533 533 - #define P2P_STATUS_FAIL_INVALID_PARAM 0x04 534 534 - #define P2P_STATUS_FAIL_REQUEST_UNABLE 0x05 535 535 - #define P2P_STATUS_FAIL_PREVOUS_PROTO_ERR 0x06 536 536 - #define P2P_STATUS_FAIL_NO_COMMON_CH 0x07 537 537 - #define P2P_STATUS_FAIL_UNKNOWN_P2PGROUP 0x08 538 538 - #define P2P_STATUS_FAIL_BOTH_GOINTENT_15 0x09 539 539 - #define P2P_STATUS_FAIL_INCOMPATIBLE_PROVSION 0x0A 540 540 - #define P2P_STATUS_FAIL_USER_REJECT 0x0B 541 541 - 542 542 - /* Value of Invitation Flags Attribute */ 543 543 - #define P2P_INVITATION_FLAGS_PERSISTENT BIT(0) 544 544 - 545 545 - #define DMP_P2P_DEVCAP_SUPPORT (P2P_DEVCAP_SERVICE_DISCOVERY | \ 546 546 - P2P_DEVCAP_CLIENT_DISCOVERABILITY | \ 547 547 - P2P_DEVCAP_CONCURRENT_OPERATION | \ 548 548 - P2P_DEVCAP_INVITATION_PROC) 549 549 - 550 550 - #define DMP_P2P_GRPCAP_SUPPORT (P2P_GRPCAP_INTRABSS) 551 551 - 552 552 - /* Value of Device Capability Bitmap */ 553 553 - #define P2P_DEVCAP_SERVICE_DISCOVERY BIT(0) 554 554 - #define P2P_DEVCAP_CLIENT_DISCOVERABILITY BIT(1) 555 555 - #define P2P_DEVCAP_CONCURRENT_OPERATION BIT(2) 556 556 - #define P2P_DEVCAP_INFRA_MANAGED BIT(3) 557 557 - #define P2P_DEVCAP_DEVICE_LIMIT BIT(4) 558 558 - #define P2P_DEVCAP_INVITATION_PROC BIT(5) 559 559 - 560 560 - /* Value of Group Capability Bitmap */ 561 561 - #define P2P_GRPCAP_GO BIT(0) 562 562 - #define P2P_GRPCAP_PERSISTENT_GROUP BIT(1) 563 563 - #define P2P_GRPCAP_GROUP_LIMIT BIT(2) 564 564 - #define P2P_GRPCAP_INTRABSS BIT(3) 565 565 - #define P2P_GRPCAP_CROSS_CONN BIT(4) 566 566 - #define P2P_GRPCAP_PERSISTENT_RECONN BIT(5) 567 567 - #define P2P_GRPCAP_GROUP_FORMATION BIT(6) 568 568 - 569 569 - /* P2P Public Action Frame (Management Frame) */ 570 570 - #define P2P_PUB_ACTION_ACTION 0x09 571 571 - 572 572 - /* P2P Public Action Frame Type */ 573 573 - #define P2P_GO_NEGO_REQ 0 574 574 - #define P2P_GO_NEGO_RESP 1 575 575 - #define P2P_GO_NEGO_CONF 2 576 576 - #define P2P_INVIT_REQ 3 577 577 - #define P2P_INVIT_RESP 4 578 578 - #define P2P_DEVDISC_REQ 5 579 579 - #define P2P_DEVDISC_RESP 6 580 580 - #define P2P_PROVISION_DISC_REQ 7 581 581 - #define P2P_PROVISION_DISC_RESP 8 582 582 - 583 583 - /* P2P Action Frame Type */ 584 584 - #define P2P_NOTICE_OF_ABSENCE 0 585 585 - #define P2P_PRESENCE_REQUEST 1 586 586 - #define P2P_PRESENCE_RESPONSE 2 587 587 - #define P2P_GO_DISC_REQUEST 3 588 588 - 589 589 - 590 590 - #define P2P_MAX_PERSISTENT_GROUP_NUM 10 591 591 - 592 592 - #define P2P_PROVISIONING_SCAN_CNT 3 593 593 - 594 594 - #define P2P_WILDCARD_SSID_LEN 7 595 595 - 596 596 - #define P2P_FINDPHASE_EX_NONE 0 /* default value, used when: (1)p2p disabled or (2)p2p enabled but only do 1 scan phase */ 597 597 - #define P2P_FINDPHASE_EX_FULL 1 /* used when p2p enabled and want to do 1 scan phase and P2P_FINDPHASE_EX_MAX-1 find phase */ 598 598 - #define P2P_FINDPHASE_EX_SOCIAL_FIRST (P2P_FINDPHASE_EX_FULL+1) 599 599 - #define P2P_FINDPHASE_EX_MAX 4 600 600 - #define P2P_FINDPHASE_EX_SOCIAL_LAST P2P_FINDPHASE_EX_MAX 601 601 - 602 602 - #define P2P_PROVISION_TIMEOUT 5000 /* 5 seconds timeout for sending the provision discovery request */ 603 603 - #define P2P_CONCURRENT_PROVISION_TIMEOUT 3000 /* 3 seconds timeout for sending the provision discovery request under concurrent mode */ 604 604 - #define P2P_GO_NEGO_TIMEOUT 5000 /* 5 seconds timeout for receiving the group negotiation response */ 605 605 - #define P2P_CONCURRENT_GO_NEGO_TIMEOUT 3000 /* 3 seconds timeout for sending the negotiation request under concurrent mode */ 606 606 - #define P2P_TX_PRESCAN_TIMEOUT 100 /* 100ms */ 607 607 - #define P2P_INVITE_TIMEOUT 5000 /* 5 seconds timeout for sending the invitation request */ 608 608 - #define P2P_CONCURRENT_INVITE_TIMEOUT 3000 /* 3 seconds timeout for sending the invitation request under concurrent mode */ 609 609 - #define P2P_RESET_SCAN_CH 25000 /* 25 seconds timeout to reset the scan channel (based on channel plan) */ 610 610 - #define P2P_MAX_INTENT 15 611 611 - 612 612 - #define P2P_MAX_NOA_NUM 2 613 613 - 614 614 - /* WPS Configuration Method */ 615 615 - #define WPS_CM_NONE 0x0000 616 616 - #define WPS_CM_LABEL 0x0004 617 617 - #define WPS_CM_DISPLYA 0x0008 618 618 - #define WPS_CM_EXTERNAL_NFC_TOKEN 0x0010 619 619 - #define WPS_CM_INTEGRATED_NFC_TOKEN 0x0020 620 620 - #define WPS_CM_NFC_INTERFACE 0x0040 621 621 - #define WPS_CM_PUSH_BUTTON 0x0080 622 622 - #define WPS_CM_KEYPAD 0x0100 623 623 - #define WPS_CM_SW_PUHS_BUTTON 0x0280 624 624 - #define WPS_CM_HW_PUHS_BUTTON 0x0480 625 625 - #define WPS_CM_SW_DISPLAY_PIN 0x2008 626 626 - #define WPS_CM_LCD_DISPLAY_PIN 0x4008 627 627 - 628 457 enum p2p_role { 629 458 P2P_ROLE_DISABLE = 0, 630 459 P2P_ROLE_DEVICE = 1, ··· 440 717 P2P_GOT_WPSINFO_SELF_DISPLAY_PIN = 2, 441 718 P2P_GOT_WPSINFO_PBC = 3, 442 719 }; 443 443 - 444 444 - #define P2P_PRIVATE_IOCTL_SET_LEN 64 445 445 - 446 446 - /* =====================WFD Section ===================== */ 447 447 - /* For Wi-Fi Display */ 448 448 - #define WFD_ATTR_DEVICE_INFO 0x00 449 449 - #define WFD_ATTR_ASSOC_BSSID 0x01 450 450 - #define WFD_ATTR_COUPLED_SINK_INFO 0x06 451 451 - #define WFD_ATTR_LOCAL_IP_ADDR 0x08 452 452 - #define WFD_ATTR_SESSION_INFO 0x09 453 453 - #define WFD_ATTR_ALTER_MAC 0x0a 454 454 - 455 455 - /* For WFD Device Information Attribute */ 456 456 - #define WFD_DEVINFO_SOURCE 0x0000 457 457 - #define WFD_DEVINFO_PSINK 0x0001 458 458 - #define WFD_DEVINFO_SSINK 0x0002 459 459 - #define WFD_DEVINFO_DUAL 0x0003 460 460 - 461 461 - #define WFD_DEVINFO_SESSION_AVAIL 0x0010 462 462 - #define WFD_DEVINFO_WSD 0x0040 463 463 - #define WFD_DEVINFO_PC_TDLS 0x0080 464 464 - #define WFD_DEVINFO_HDCP_SUPPORT 0x0100 465 720 466 721 #define IP_MCAST_MAC(mac) ((mac[0] == 0x01) && (mac[1] == 0x00) && (mac[2] == 0x5e)) 467 722 #define ICMPV6_MCAST_MAC(mac) ((mac[0] == 0x33) && (mac[1] == 0x33) && (mac[2] != 0xff))

-17

drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c

reviewed

··· 2549 2549 bool ack = true; 2550 2550 u8 tx_ch = (u8)ieee80211_frequency_to_channel(chan->center_freq); 2551 2551 u8 category, action; 2552 2552 - int type = (-1); 2553 2552 struct adapter *padapter; 2554 2554 - struct rtw_wdev_priv *pwdev_priv; 2555 2553 2556 2554 if (!ndev) { 2557 2555 ret = -EINVAL; ··· 2557 2559 } 2558 2560 2559 2561 padapter = rtw_netdev_priv(ndev); 2560 2560 - pwdev_priv = adapter_wdev_data(padapter); 2561 2562 2562 2563 /* cookie generation */ 2563 2564 *cookie = (unsigned long)buf; ··· 2578 2581 tx_ret = _cfg80211_rtw_mgmt_tx(padapter, tx_ch, buf, len); 2579 2582 } while (dump_cnt < dump_limit && tx_ret != _SUCCESS); 2580 2583 2581 2581 - switch (type) { 2582 2582 - case P2P_GO_NEGO_CONF: 2583 2583 - rtw_clear_scan_deny(padapter); 2584 2584 - break; 2585 2585 - case P2P_INVIT_RESP: 2586 2586 - if (pwdev_priv->invit_info.flags & BIT(0) && pwdev_priv->invit_info.status == 0) { 2587 2587 - rtw_set_scan_deny(padapter, 5000); 2588 2588 - rtw_pwr_wakeup_ex(padapter, 5000); 2589 2589 - rtw_clear_scan_deny(padapter); 2590 2590 - } 2591 2591 - break; 2592 2592 - } 2593 2593 - 2594 2584 cancel_ps_deny: 2595 2585 rtw_ps_deny_cancel(padapter, PS_DENY_MGNT_TX); 2596 2586 exit: ··· 2586 2602 2587 2603 static void rtw_cfg80211_init_ht_capab(struct ieee80211_sta_ht_cap *ht_cap, enum nl80211_band band) 2588 2604 { 2589 2589 - #define MAX_BIT_RATE_40MHZ_MCS15 300 /* Mbps */ 2590 2605 #define MAX_BIT_RATE_40MHZ_MCS7 150 /* Mbps */ 2591 2606 2592 2607 ht_cap->ht_supported = true;

+4 -4

drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c

reviewed

··· 591 591 static void stop_streaming(struct vb2_queue *vq) 592 592 { 593 593 int ret; 594 594 - unsigned long timeout; 594 594 + unsigned long time_left; 595 595 struct bcm2835_mmal_dev *dev = vb2_get_drv_priv(vq); 596 596 struct vchiq_mmal_port *port = dev->capture.port; 597 597 ··· 636 636 v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, 637 637 "%s: Waiting for buffers to be returned - %d outstanding\n", 638 638 __func__, atomic_read(&port->buffers_with_vpu)); 639 639 - timeout = wait_for_completion_timeout(&dev->capture.frame_cmplt, 640 640 - HZ); 641 641 - if (timeout == 0) { 639 639 + time_left = wait_for_completion_timeout(&dev->capture.frame_cmplt, 640 640 + HZ); 641 641 + if (time_left == 0) { 642 642 v4l2_err(&dev->v4l2_dev, "%s: Timeout waiting for buffers to be returned - %d outstanding\n", 643 643 __func__, 644 644 atomic_read(&port->buffers_with_vpu));

+44 -1

drivers/staging/vc04_services/interface/TESTING

reviewed

··· 31 31 32 32 3. BCM2837 target SoC (ARM 64 bit) 33 33 34 34 - Use the defconfig as a base and then enable all VCHIQ options. 34 34 + Use the defconfig which has most of the VCHIQ options enabled. 35 35 36 36 * Scenarios 37 37 ··· 80 80 vchi ping (size 0, 100 async, 100 oneway) -> infus 81 81 vchi ping (size 0, 200 async, 0 oneway) -> infus 82 82 ... 83 83 + 84 84 + * Debugfs test 85 85 + 86 86 + Command: cat /sys/kernel/debug/vchiq/state 87 87 + 88 88 + Example output: 89 89 + State 0: CONNECTED 90 90 + tx_pos=0x1e8(@43b0acda), rx_pos=0x170(@05493af8) 91 91 + Version: 8 (min 3) 92 92 + Stats: ctrl_tx_count=7, ctrl_rx_count=7, error_count=0 93 93 + Slots: 30 available (29 data), 0 recyclable, 0 stalls (0 data) 94 94 + Platform: 2835 (VC master) 95 95 + Local: slots 34-64 tx_pos=0x1e8 recycle=0x1f 96 96 + Slots claimed: 97 97 + DEBUG: SLOT_HANDLER_COUNT = 20(0x14) 98 98 + DEBUG: SLOT_HANDLER_LINE = 1937(0x791) 99 99 + DEBUG: PARSE_LINE = 1864(0x748) 100 100 + DEBUG: PARSE_HEADER = -249155224(0xf1263168) 101 101 + DEBUG: PARSE_MSGID = 67362817(0x403e001) 102 102 + DEBUG: AWAIT_COMPLETION_LINE = 0(0x0) 103 103 + DEBUG: DEQUEUE_MESSAGE_LINE = 0(0x0) 104 104 + DEBUG: SERVICE_CALLBACK_LINE = 0(0x0) 105 105 + DEBUG: MSG_QUEUE_FULL_COUNT = 0(0x0) 106 106 + DEBUG: COMPLETION_QUEUE_FULL_COUNT = 0(0x0) 107 107 + Remote: slots 2-32 tx_pos=0x170 recycle=0x1f 108 108 + Slots claimed: 109 109 + 2: 10/9 110 110 + DEBUG: SLOT_HANDLER_COUNT = 20(0x14) 111 111 + DEBUG: SLOT_HANDLER_LINE = 1851(0x73b) 112 112 + DEBUG: PARSE_LINE = 1827(0x723) 113 113 + DEBUG: PARSE_HEADER = -150330912(0xf70a21e0) 114 114 + DEBUG: PARSE_MSGID = 67113022(0x400103e) 115 115 + DEBUG: AWAIT_COMPLETION_LINE = 0(0x0) 116 116 + DEBUG: DEQUEUE_MESSAGE_LINE = 0(0x0) 117 117 + DEBUG: SERVICE_CALLBACK_LINE = 0(0x0) 118 118 + DEBUG: MSG_QUEUE_FULL_COUNT = 0(0x0) 119 119 + DEBUG: COMPLETION_QUEUE_FULL_COUNT = 0(0x0) 120 120 + Service 0: LISTENING (ref 1) 'PEEK little-endian (0x4b454550)' remote n/a (msg use 0/3840, slot use 0/15) 121 121 + Bulk: tx_pending=0 (size 0), rx_pending=0 (size 0) 122 122 + Ctrl: tx_count=0, tx_bytes=0, rx_count=0, rx_bytes=0 123 123 + Bulk: tx_count=0, tx_bytes=0, rx_count=0, rx_bytes=0 124 124 + 0 quota stalls, 0 slot stalls, 0 bulk stalls, 0 aborted, 0 errors 125 125 + instance b511f60b

-7

drivers/staging/vc04_services/interface/TODO

reviewed

··· 16 16 to manage these buffers as dmabufs so that we can zero-copy import 17 17 camera images into vc4 for rendering/display. 18 18 19 19 - * Fix kernel module support 20 20 - 21 21 - Even the VPU firmware doesn't support a VCHI re-connect, the driver 22 22 - should properly handle a module unload. This also includes that all 23 23 - resources must be freed (kthreads, debugfs entries, ...) and global 24 24 - variables avoided. 25 25 - 26 19 * Documentation 27 20 28 21 A short top-down description of this driver's architecture (function of

+132 -136

drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c

reviewed

··· 109 109 int first_connect; 110 110 }; 111 111 112 112 - struct vchiq_2835_state { 113 113 - int inited; 114 114 - struct vchiq_arm_state arm_state; 115 115 - }; 116 116 - 117 112 struct vchiq_pagelist_info { 118 113 struct pagelist *pagelist; 119 114 size_t pagelist_buffer_size; ··· 162 167 } 163 168 164 169 static inline bool 165 165 - is_adjacent_block(u32 *addrs, u32 addr, unsigned int k) 170 170 + is_adjacent_block(u32 *addrs, dma_addr_t addr, unsigned int k) 166 171 { 167 172 u32 tmp; 168 173 ··· 377 382 /* Combine adjacent blocks for performance */ 378 383 k = 0; 379 384 for_each_sg(scatterlist, sg, dma_buffers, i) { 380 380 - u32 len = sg_dma_len(sg); 381 381 - u32 addr = sg_dma_address(sg); 385 385 + unsigned int len = sg_dma_len(sg); 386 386 + dma_addr_t addr = sg_dma_address(sg); 382 387 383 388 /* Note: addrs is the address + page_count - 1 384 389 * The firmware expects blocks after the first to be page- ··· 588 593 return 0; 589 594 } 590 595 591 591 - static void 592 592 - vchiq_arm_init_state(struct vchiq_state *state, 593 593 - struct vchiq_arm_state *arm_state) 594 594 - { 595 595 - if (arm_state) { 596 596 - rwlock_init(&arm_state->susp_res_lock); 597 597 - 598 598 - init_completion(&arm_state->ka_evt); 599 599 - atomic_set(&arm_state->ka_use_count, 0); 600 600 - atomic_set(&arm_state->ka_use_ack_count, 0); 601 601 - atomic_set(&arm_state->ka_release_count, 0); 602 602 - 603 603 - arm_state->state = state; 604 604 - arm_state->first_connect = 0; 605 605 - } 606 606 - } 607 607 - 608 596 int 609 597 vchiq_platform_init_state(struct vchiq_state *state) 610 598 { 611 611 - struct vchiq_2835_state *platform_state; 599 599 + struct vchiq_arm_state *platform_state; 612 600 613 613 - state->platform_state = kzalloc(sizeof(*platform_state), GFP_KERNEL); 614 614 - if (!state->platform_state) 601 601 + platform_state = kzalloc(sizeof(*platform_state), GFP_KERNEL); 602 602 + if (!platform_state) 615 603 return -ENOMEM; 616 604 617 617 - platform_state = (struct vchiq_2835_state *)state->platform_state; 605 605 + rwlock_init(&platform_state->susp_res_lock); 618 606 619 619 - platform_state->inited = 1; 620 620 - vchiq_arm_init_state(state, &platform_state->arm_state); 607 607 + init_completion(&platform_state->ka_evt); 608 608 + atomic_set(&platform_state->ka_use_count, 0); 609 609 + atomic_set(&platform_state->ka_use_ack_count, 0); 610 610 + atomic_set(&platform_state->ka_release_count, 0); 611 611 + 612 612 + platform_state->state = state; 613 613 + 614 614 + state->platform_state = (struct opaque_platform_state *)platform_state; 621 615 622 616 return 0; 623 617 } 624 618 625 619 static struct vchiq_arm_state *vchiq_platform_get_arm_state(struct vchiq_state *state) 626 620 { 627 627 - struct vchiq_2835_state *platform_state; 628 628 - 629 629 - platform_state = (struct vchiq_2835_state *)state->platform_state; 630 630 - 631 631 - WARN_ON_ONCE(!platform_state->inited); 632 632 - 633 633 - return &platform_state->arm_state; 621 621 + return (struct vchiq_arm_state *)state->platform_state; 634 622 } 635 623 636 624 void ··· 736 758 737 759 int vchiq_shutdown(struct vchiq_instance *instance) 738 760 { 739 739 - int status = 0; 740 761 struct vchiq_state *state = instance->state; 762 762 + int ret = 0; 741 763 742 764 if (mutex_lock_killable(&state->mutex)) 743 765 return -EAGAIN; ··· 747 769 748 770 mutex_unlock(&state->mutex); 749 771 750 750 - dev_dbg(state->dev, "core: (%p): returning %d\n", instance, status); 772 772 + dev_dbg(state->dev, "core: (%p): returning %d\n", instance, ret); 751 773 752 774 free_bulk_waiter(instance); 753 775 kfree(instance); 754 776 755 755 - return status; 777 777 + return ret; 756 778 } 757 779 EXPORT_SYMBOL(vchiq_shutdown); 758 780 ··· 763 785 764 786 int vchiq_connect(struct vchiq_instance *instance) 765 787 { 766 766 - int status; 767 788 struct vchiq_state *state = instance->state; 789 789 + int ret; 768 790 769 791 if (mutex_lock_killable(&state->mutex)) { 770 792 dev_dbg(state->dev, 771 793 "core: call to mutex_lock failed\n"); 772 772 - status = -EAGAIN; 794 794 + ret = -EAGAIN; 773 795 goto failed; 774 796 } 775 775 - status = vchiq_connect_internal(state, instance); 797 797 + ret = vchiq_connect_internal(state, instance); 776 798 777 777 - if (!status) 799 799 + if (!ret) 778 800 instance->connected = 1; 779 801 780 802 mutex_unlock(&state->mutex); 781 803 782 804 failed: 783 783 - dev_dbg(state->dev, "core: (%p): returning %d\n", instance, status); 805 805 + dev_dbg(state->dev, "core: (%p): returning %d\n", instance, ret); 784 806 785 785 - return status; 807 807 + return ret; 786 808 } 787 809 EXPORT_SYMBOL(vchiq_connect); 788 810 ··· 791 813 const struct vchiq_service_params_kernel *params, 792 814 unsigned int *phandle) 793 815 { 794 794 - int status; 795 816 struct vchiq_state *state = instance->state; 796 817 struct vchiq_service *service = NULL; 797 797 - int srvstate; 818 818 + int srvstate, ret; 798 819 799 820 *phandle = VCHIQ_SERVICE_HANDLE_INVALID; 800 821 ··· 805 828 806 829 if (service) { 807 830 *phandle = service->handle; 808 808 - status = 0; 831 831 + ret = 0; 809 832 } else { 810 810 - status = -EINVAL; 833 833 + ret = -EINVAL; 811 834 } 812 835 813 813 - dev_dbg(state->dev, "core: (%p): returning %d\n", instance, status); 836 836 + dev_dbg(state->dev, "core: (%p): returning %d\n", instance, ret); 814 837 815 815 - return status; 838 838 + return ret; 816 839 } 817 840 818 841 int ··· 820 843 const struct vchiq_service_params_kernel *params, 821 844 unsigned int *phandle) 822 845 { 823 823 - int status = -EINVAL; 824 846 struct vchiq_state *state = instance->state; 825 847 struct vchiq_service *service = NULL; 848 848 + int ret = -EINVAL; 826 849 827 850 *phandle = VCHIQ_SERVICE_HANDLE_INVALID; 828 851 ··· 833 856 834 857 if (service) { 835 858 *phandle = service->handle; 836 836 - status = vchiq_open_service_internal(service, current->pid); 837 837 - if (status) { 859 859 + ret = vchiq_open_service_internal(service, current->pid); 860 860 + if (ret) { 838 861 vchiq_remove_service(instance, service->handle); 839 862 *phandle = VCHIQ_SERVICE_HANDLE_INVALID; 840 863 } 841 864 } 842 865 843 866 failed: 844 844 - dev_dbg(state->dev, "core: (%p): returning %d\n", instance, status); 867 867 + dev_dbg(state->dev, "core: (%p): returning %d\n", instance, ret); 845 868 846 846 - return status; 869 869 + return ret; 847 870 } 848 871 EXPORT_SYMBOL(vchiq_open_service); 849 872 ··· 851 874 vchiq_bulk_transmit(struct vchiq_instance *instance, unsigned int handle, const void *data, 852 875 unsigned int size, void *userdata, enum vchiq_bulk_mode mode) 853 876 { 854 854 - int status; 877 877 + int ret; 855 878 856 879 while (1) { 857 880 switch (mode) { 858 881 case VCHIQ_BULK_MODE_NOCALLBACK: 859 882 case VCHIQ_BULK_MODE_CALLBACK: 860 860 - status = vchiq_bulk_transfer(instance, handle, 861 861 - (void *)data, NULL, 862 862 - size, userdata, mode, 863 863 - VCHIQ_BULK_TRANSMIT); 883 883 + ret = vchiq_bulk_transfer(instance, handle, 884 884 + (void *)data, NULL, 885 885 + size, userdata, mode, 886 886 + VCHIQ_BULK_TRANSMIT); 864 887 break; 865 888 case VCHIQ_BULK_MODE_BLOCKING: 866 866 - status = vchiq_blocking_bulk_transfer(instance, handle, (void *)data, size, 867 867 - VCHIQ_BULK_TRANSMIT); 889 889 + ret = vchiq_blocking_bulk_transfer(instance, handle, (void *)data, size, 890 890 + VCHIQ_BULK_TRANSMIT); 868 891 break; 869 892 default: 870 893 return -EINVAL; ··· 875 898 * to implement a retry mechanism since this function is 876 899 * supposed to block until queued 877 900 */ 878 878 - if (status != -EAGAIN) 901 901 + if (ret != -EAGAIN) 879 902 break; 880 903 881 904 msleep(1); 882 905 } 883 906 884 884 - return status; 907 907 + return ret; 885 908 } 886 909 EXPORT_SYMBOL(vchiq_bulk_transmit); 887 910 ··· 889 912 void *data, unsigned int size, void *userdata, 890 913 enum vchiq_bulk_mode mode) 891 914 { 892 892 - int status; 915 915 + int ret; 893 916 894 917 while (1) { 895 918 switch (mode) { 896 919 case VCHIQ_BULK_MODE_NOCALLBACK: 897 920 case VCHIQ_BULK_MODE_CALLBACK: 898 898 - status = vchiq_bulk_transfer(instance, handle, data, NULL, 899 899 - size, userdata, 900 900 - mode, VCHIQ_BULK_RECEIVE); 921 921 + ret = vchiq_bulk_transfer(instance, handle, data, NULL, 922 922 + size, userdata, 923 923 + mode, VCHIQ_BULK_RECEIVE); 901 924 break; 902 925 case VCHIQ_BULK_MODE_BLOCKING: 903 903 - status = vchiq_blocking_bulk_transfer(instance, handle, (void *)data, size, 904 904 - VCHIQ_BULK_RECEIVE); 926 926 + ret = vchiq_blocking_bulk_transfer(instance, handle, (void *)data, size, 927 927 + VCHIQ_BULK_RECEIVE); 905 928 break; 906 929 default: 907 930 return -EINVAL; ··· 912 935 * to implement a retry mechanism since this function is 913 936 * supposed to block until queued 914 937 */ 915 915 - if (status != -EAGAIN) 938 938 + if (ret != -EAGAIN) 916 939 break; 917 940 918 941 msleep(1); 919 942 } 920 943 921 921 - return status; 944 944 + return ret; 922 945 } 923 946 EXPORT_SYMBOL(vchiq_bulk_receive); 924 947 ··· 927 950 unsigned int size, enum vchiq_bulk_dir dir) 928 951 { 929 952 struct vchiq_service *service; 930 930 - int status; 931 953 struct bulk_waiter_node *waiter = NULL, *iter; 954 954 + int ret; 932 955 933 956 service = find_service_by_handle(instance, handle); 934 957 if (!service) ··· 968 991 return -ENOMEM; 969 992 } 970 993 971 971 - status = vchiq_bulk_transfer(instance, handle, data, NULL, size, 972 972 - &waiter->bulk_waiter, 973 973 - VCHIQ_BULK_MODE_BLOCKING, dir); 974 974 - if ((status != -EAGAIN) || fatal_signal_pending(current) || !waiter->bulk_waiter.bulk) { 994 994 + ret = vchiq_bulk_transfer(instance, handle, data, NULL, size, 995 995 + &waiter->bulk_waiter, 996 996 + VCHIQ_BULK_MODE_BLOCKING, dir); 997 997 + if ((ret != -EAGAIN) || fatal_signal_pending(current) || !waiter->bulk_waiter.bulk) { 975 998 struct vchiq_bulk *bulk = waiter->bulk_waiter.bulk; 976 999 977 1000 if (bulk) { ··· 990 1013 waiter, current->pid); 991 1014 } 992 1015 993 993 - return status; 1016 1016 + return ret; 994 1017 } 995 1018 996 1019 static int ··· 1055 1078 return 0; 1056 1079 } 1057 1080 1081 1081 + static int 1082 1082 + service_single_message(struct vchiq_instance *instance, 1083 1083 + enum vchiq_reason reason, 1084 1084 + struct vchiq_service *service, void *bulk_userdata) 1085 1085 + { 1086 1086 + struct user_service *user_service; 1087 1087 + 1088 1088 + user_service = (struct user_service *)service->base.userdata; 1089 1089 + 1090 1090 + dev_dbg(service->state->dev, "arm: msg queue full\n"); 1091 1091 + /* 1092 1092 + * If there is no MESSAGE_AVAILABLE in the completion 1093 1093 + * queue, add one 1094 1094 + */ 1095 1095 + if ((user_service->message_available_pos - 1096 1096 + instance->completion_remove) < 0) { 1097 1097 + int ret; 1098 1098 + 1099 1099 + dev_dbg(instance->state->dev, 1100 1100 + "arm: Inserting extra MESSAGE_AVAILABLE\n"); 1101 1101 + ret = add_completion(instance, reason, NULL, user_service, 1102 1102 + bulk_userdata); 1103 1103 + if (ret) 1104 1104 + return ret; 1105 1105 + } 1106 1106 + 1107 1107 + if (wait_for_completion_interruptible(&user_service->remove_event)) { 1108 1108 + dev_dbg(instance->state->dev, "arm: interrupted\n"); 1109 1109 + return -EAGAIN; 1110 1110 + } else if (instance->closing) { 1111 1111 + dev_dbg(instance->state->dev, "arm: closing\n"); 1112 1112 + return -EINVAL; 1113 1113 + } 1114 1114 + 1115 1115 + return 0; 1116 1116 + } 1117 1117 + 1058 1118 int 1059 1119 service_callback(struct vchiq_instance *instance, enum vchiq_reason reason, 1060 1120 struct vchiq_header *header, unsigned int handle, void *bulk_userdata) ··· 1141 1127 spin_lock(&service->state->msg_queue_spinlock); 1142 1128 while (user_service->msg_insert == 1143 1129 (user_service->msg_remove + MSG_QUEUE_SIZE)) { 1130 1130 + int ret; 1131 1131 + 1144 1132 spin_unlock(&service->state->msg_queue_spinlock); 1145 1133 DEBUG_TRACE(SERVICE_CALLBACK_LINE); 1146 1134 DEBUG_COUNT(MSG_QUEUE_FULL_COUNT); 1147 1147 - dev_dbg(service->state->dev, "arm: msg queue full\n"); 1148 1148 - /* 1149 1149 - * If there is no MESSAGE_AVAILABLE in the completion 1150 1150 - * queue, add one 1151 1151 - */ 1152 1152 - if ((user_service->message_available_pos - 1153 1153 - instance->completion_remove) < 0) { 1154 1154 - int status; 1155 1135 1156 1156 - dev_dbg(instance->state->dev, 1157 1157 - "arm: Inserting extra MESSAGE_AVAILABLE\n"); 1158 1158 - DEBUG_TRACE(SERVICE_CALLBACK_LINE); 1159 1159 - status = add_completion(instance, reason, NULL, user_service, 1160 1160 - bulk_userdata); 1161 1161 - if (status) { 1162 1162 - DEBUG_TRACE(SERVICE_CALLBACK_LINE); 1163 1163 - vchiq_service_put(service); 1164 1164 - return status; 1165 1165 - } 1166 1166 - } 1167 1167 - 1168 1168 - DEBUG_TRACE(SERVICE_CALLBACK_LINE); 1169 1169 - if (wait_for_completion_interruptible(&user_service->remove_event)) { 1170 1170 - dev_dbg(instance->state->dev, "arm: interrupted\n"); 1136 1136 + ret = service_single_message(instance, reason, 1137 1137 + service, bulk_userdata); 1138 1138 + if (ret) { 1171 1139 DEBUG_TRACE(SERVICE_CALLBACK_LINE); 1172 1140 vchiq_service_put(service); 1173 1173 - return -EAGAIN; 1174 1174 - } else if (instance->closing) { 1175 1175 - dev_dbg(instance->state->dev, "arm: closing\n"); 1176 1176 - DEBUG_TRACE(SERVICE_CALLBACK_LINE); 1177 1177 - vchiq_service_put(service); 1178 1178 - return -EINVAL; 1141 1141 + return ret; 1179 1142 } 1180 1143 DEBUG_TRACE(SERVICE_CALLBACK_LINE); 1181 1144 spin_lock(&service->state->msg_queue_spinlock); ··· 1285 1294 { 1286 1295 struct vchiq_state *state = (struct vchiq_state *)v; 1287 1296 struct vchiq_arm_state *arm_state = vchiq_platform_get_arm_state(state); 1288 1288 - 1289 1289 - int status; 1290 1297 struct vchiq_instance *instance; 1291 1298 unsigned int ka_handle; 1292 1299 int ret; ··· 1302 1313 goto exit; 1303 1314 } 1304 1315 1305 1305 - status = vchiq_connect(instance); 1306 1306 - if (status) { 1307 1307 - dev_err(state->dev, "suspend: %s: vchiq_connect failed %d\n", __func__, status); 1316 1316 + ret = vchiq_connect(instance); 1317 1317 + if (ret) { 1318 1318 + dev_err(state->dev, "suspend: %s: vchiq_connect failed %d\n", __func__, ret); 1308 1319 goto shutdown; 1309 1320 } 1310 1321 1311 1311 - status = vchiq_add_service(instance, &params, &ka_handle); 1312 1312 - if (status) { 1322 1322 + ret = vchiq_add_service(instance, &params, &ka_handle); 1323 1323 + if (ret) { 1313 1324 dev_err(state->dev, "suspend: %s: vchiq_open_service failed %d\n", 1314 1314 - __func__, status); 1325 1325 + __func__, ret); 1315 1326 goto shutdown; 1316 1327 } 1317 1328 1318 1318 - while (1) { 1329 1329 + while (!kthread_should_stop()) { 1319 1330 long rc = 0, uc = 0; 1320 1331 1321 1332 if (wait_for_completion_interruptible(&arm_state->ka_evt)) { ··· 1337 1348 */ 1338 1349 while (uc--) { 1339 1350 atomic_inc(&arm_state->ka_use_ack_count); 1340 1340 - status = vchiq_use_service(instance, ka_handle); 1341 1341 - if (status) { 1351 1351 + ret = vchiq_use_service(instance, ka_handle); 1352 1352 + if (ret) { 1342 1353 dev_err(state->dev, "suspend: %s: vchiq_use_service error %d\n", 1343 1343 - __func__, status); 1354 1354 + __func__, ret); 1344 1355 } 1345 1356 } 1346 1357 while (rc--) { 1347 1347 - status = vchiq_release_service(instance, ka_handle); 1348 1348 - if (status) { 1358 1358 + ret = vchiq_release_service(instance, ka_handle); 1359 1359 + if (ret) { 1349 1360 dev_err(state->dev, "suspend: %s: vchiq_release_service error %d\n", 1350 1350 - __func__, status); 1361 1361 + __func__, ret); 1351 1362 } 1352 1363 } 1353 1364 } ··· 1397 1408 write_unlock_bh(&arm_state->susp_res_lock); 1398 1409 1399 1410 if (!ret) { 1400 1400 - int status = 0; 1411 1411 + int ret = 0; 1401 1412 long ack_cnt = atomic_xchg(&arm_state->ka_use_ack_count, 0); 1402 1413 1403 1403 - while (ack_cnt && !status) { 1414 1414 + while (ack_cnt && !ret) { 1404 1415 /* Send the use notify to videocore */ 1405 1405 - status = vchiq_send_remote_use_active(state); 1406 1406 - if (!status) 1416 1416 + ret = vchiq_send_remote_use_active(state); 1417 1417 + if (!ret) 1407 1418 ack_cnt--; 1408 1419 else 1409 1420 atomic_add(ack_cnt, &arm_state->ka_use_ack_count); ··· 1440 1451 1441 1452 write_lock_bh(&arm_state->susp_res_lock); 1442 1453 if (!arm_state->videocore_use_count || !(*entity_uc)) { 1443 1443 - /* Don't use BUG_ON - don't allow user thread to crash kernel */ 1444 1454 WARN_ON(!arm_state->videocore_use_count); 1445 1455 WARN_ON(!(*entity_uc)); 1446 1456 ret = -EINVAL; ··· 1718 1730 struct device_node *fw_node; 1719 1731 const struct vchiq_platform_info *info; 1720 1732 struct vchiq_drv_mgmt *mgmt; 1721 1721 - int err; 1733 1733 + int ret; 1722 1734 1723 1735 info = of_device_get_match_data(&pdev->dev); 1724 1736 if (!info) ··· 1743 1755 mgmt->info = info; 1744 1756 platform_set_drvdata(pdev, mgmt); 1745 1757 1746 1746 - err = vchiq_platform_init(pdev, &mgmt->state); 1747 1747 - if (err) 1758 1758 + ret = vchiq_platform_init(pdev, &mgmt->state); 1759 1759 + if (ret) 1748 1760 goto failed_platform_init; 1749 1761 1750 1762 vchiq_debugfs_init(&mgmt->state); ··· 1756 1768 * Simply exit on error since the function handles cleanup in 1757 1769 * cases of failure. 1758 1770 */ 1759 1759 - err = vchiq_register_chrdev(&pdev->dev); 1760 1760 - if (err) { 1771 1771 + ret = vchiq_register_chrdev(&pdev->dev); 1772 1772 + if (ret) { 1761 1773 dev_err(&pdev->dev, "arm: Failed to initialize vchiq cdev\n"); 1762 1774 goto error_exit; 1763 1775 } ··· 1770 1782 failed_platform_init: 1771 1783 dev_err(&pdev->dev, "arm: Could not initialize vchiq platform\n"); 1772 1784 error_exit: 1773 1773 - return err; 1785 1785 + return ret; 1774 1786 } 1775 1787 1776 1788 static void vchiq_remove(struct platform_device *pdev) 1777 1789 { 1778 1790 struct vchiq_drv_mgmt *mgmt = dev_get_drvdata(&pdev->dev); 1791 1791 + struct vchiq_arm_state *arm_state; 1779 1792 1780 1793 vchiq_device_unregister(bcm2835_audio); 1781 1794 vchiq_device_unregister(bcm2835_camera); 1782 1795 vchiq_debugfs_deinit(); 1783 1796 vchiq_deregister_chrdev(); 1797 1797 + 1798 1798 + kthread_stop(mgmt->state.sync_thread); 1799 1799 + kthread_stop(mgmt->state.recycle_thread); 1800 1800 + kthread_stop(mgmt->state.slot_handler_thread); 1801 1801 + 1802 1802 + arm_state = vchiq_platform_get_arm_state(&mgmt->state); 1803 1803 + kthread_stop(arm_state->ka_thread); 1784 1804 1785 1805 kfree(mgmt); 1786 1806 }

-3

drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.h

reviewed

··· 110 110 vchiq_check_service(struct vchiq_service *service); 111 111 112 112 extern void 113 113 - vchiq_dump_platform_use_state(struct vchiq_state *state); 114 114 - 115 115 - extern void 116 113 vchiq_dump_service_use_state(struct vchiq_state *state); 117 114 118 115 extern int

+31 -16

drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c

reviewed

··· 501 501 * routines where switched to the "interruptible" family of functions, as the 502 502 * former was deemed unjustified and the use "killable" set all VCHIQ's 503 503 * threads in D state. 504 504 + * 505 505 + * Returns: 0 on success, a negative error code on failure 504 506 */ 505 507 static inline int 506 508 remote_event_wait(wait_queue_head_t *wq, struct remote_event *event) 507 509 { 510 510 + int ret = 0; 511 511 + 508 512 if (!event->fired) { 509 513 event->armed = 1; 510 514 dsb(sy); 511 511 - if (wait_event_interruptible(*wq, event->fired)) { 515 515 + ret = wait_event_interruptible(*wq, event->fired); 516 516 + if (ret) { 512 517 event->armed = 0; 513 513 - return 0; 518 518 + return ret; 514 519 } 515 520 event->armed = 0; 516 521 /* Ensure that the peer sees that we are not waiting (armed == 0). */ ··· 523 518 } 524 519 525 520 event->fired = 0; 526 526 - return 1; 521 521 + return ret; 527 522 } 528 523 529 524 /* ··· 1145 1140 struct vchiq_header *header; 1146 1141 ssize_t callback_result; 1147 1142 int svc_fourcc; 1143 1143 + int ret; 1148 1144 1149 1145 local = state->local; 1150 1146 ··· 1153 1147 mutex_lock_killable(&state->sync_mutex)) 1154 1148 return -EAGAIN; 1155 1149 1156 1156 - remote_event_wait(&state->sync_release_event, &local->sync_release); 1150 1150 + ret = remote_event_wait(&state->sync_release_event, &local->sync_release); 1151 1151 + if (ret) 1152 1152 + return ret; 1157 1153 1158 1154 /* Ensure that reads don't overtake the remote_event_wait. */ 1159 1155 rmb(); ··· 1937 1929 { 1938 1930 struct vchiq_state *state = v; 1939 1931 struct vchiq_shared_state *local = state->local; 1932 1932 + int ret; 1940 1933 1941 1934 DEBUG_INITIALISE(local); 1942 1935 1943 1943 - while (1) { 1936 1936 + while (!kthread_should_stop()) { 1944 1937 DEBUG_COUNT(SLOT_HANDLER_COUNT); 1945 1938 DEBUG_TRACE(SLOT_HANDLER_LINE); 1946 1946 - remote_event_wait(&state->trigger_event, &local->trigger); 1939 1939 + ret = remote_event_wait(&state->trigger_event, &local->trigger); 1940 1940 + if (ret) 1941 1941 + return ret; 1947 1942 1948 1943 /* Ensure that reads don't overtake the remote_event_wait. */ 1949 1944 rmb(); ··· 1977 1966 struct vchiq_shared_state *local = state->local; 1978 1967 u32 *found; 1979 1968 size_t length; 1969 1969 + int ret; 1980 1970 1981 1971 length = sizeof(*found) * BITSET_SIZE(VCHIQ_MAX_SERVICES); 1982 1972 ··· 1986 1974 if (!found) 1987 1975 return -ENOMEM; 1988 1976 1989 1989 - while (1) { 1990 1990 - remote_event_wait(&state->recycle_event, &local->recycle); 1977 1977 + while (!kthread_should_stop()) { 1978 1978 + ret = remote_event_wait(&state->recycle_event, &local->recycle); 1979 1979 + if (ret) 1980 1980 + return ret; 1991 1981 1992 1982 process_free_queue(state, found, length); 1993 1983 } ··· 2006 1992 (struct vchiq_header *)SLOT_DATA_FROM_INDEX(state, 2007 1993 state->remote->slot_sync); 2008 1994 int svc_fourcc; 1995 1995 + int ret; 2009 1996 2010 2010 - while (1) { 1997 1997 + while (!kthread_should_stop()) { 2011 1998 struct vchiq_service *service; 2012 1999 int msgid, size; 2013 2000 int type; 2014 2001 unsigned int localport, remoteport; 2015 2002 2016 2016 - remote_event_wait(&state->sync_trigger_event, &local->sync_trigger); 2003 2003 + ret = remote_event_wait(&state->sync_trigger_event, &local->sync_trigger); 2004 2004 + if (ret) 2005 2005 + return ret; 2017 2006 2018 2007 /* Ensure that reads don't overtake the remote_event_wait. */ 2019 2008 rmb(); ··· 2180 2163 mutex_init(&state->slot_mutex); 2181 2164 mutex_init(&state->recycle_mutex); 2182 2165 mutex_init(&state->sync_mutex); 2183 2183 - mutex_init(&state->bulk_transfer_mutex); 2184 2166 2185 2167 spin_lock_init(&state->msg_queue_spinlock); 2186 2168 spin_lock_init(&state->bulk_waiter_spinlock); 2187 2169 spin_lock_init(&state->quota_spinlock); 2188 2170 2189 2171 init_completion(&state->slot_available_event); 2190 2190 - init_completion(&state->slot_remove_event); 2191 2172 init_completion(&state->data_quota_event); 2192 2173 2193 2174 state->slot_queue_available = 0; ··· 3387 3372 }; 3388 3373 int i; 3389 3374 3390 3390 - seq_printf(f, " %s: slots %d-%d tx_pos=%x recycle=%x\n", 3375 3375 + seq_printf(f, " %s: slots %d-%d tx_pos=0x%x recycle=0x%x\n", 3391 3376 label, shared->slot_first, shared->slot_last, 3392 3377 shared->tx_pos, shared->slot_queue_recycle); 3393 3378 ··· 3403 3388 } 3404 3389 3405 3390 for (i = 1; i < shared->debug[DEBUG_ENTRIES]; i++) { 3406 3406 - seq_printf(f, " DEBUG: %s = %d(%x)\n", 3391 3391 + seq_printf(f, " DEBUG: %s = %d(0x%x)\n", 3407 3392 debug_names[i], shared->debug[i], shared->debug[i]); 3408 3393 } 3409 3394 } ··· 3431 3416 3432 3417 if (service->public_fourcc != VCHIQ_FOURCC_INVALID) 3433 3418 scnprintf(remoteport + len2, sizeof(remoteport) - len2, 3434 3434 - " (client %x)", service->client_id); 3419 3419 + " (client 0x%x)", service->client_id); 3435 3420 } else { 3436 3421 strscpy(remoteport, "n/a", sizeof(remoteport)); 3437 3422 } ··· 3492 3477 seq_printf(f, "State %d: %s\n", state->id, 3493 3478 conn_state_names[state->conn_state]); 3494 3479 3495 3495 - seq_printf(f, " tx_pos=%x(@%pK), rx_pos=%x(@%pK)\n", 3480 3480 + seq_printf(f, " tx_pos=0x%x(@%pK), rx_pos=0x%x(@%pK)\n", 3496 3481 state->local->tx_pos, 3497 3482 state->tx_data + (state->local_tx_pos & VCHIQ_SLOT_MASK), 3498 3483 state->rx_pos,

-6

drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.h

reviewed

··· 347 347 348 348 struct mutex sync_mutex; 349 349 350 350 - struct mutex bulk_transfer_mutex; 351 351 - 352 350 spinlock_t msg_queue_spinlock; 353 351 354 352 spinlock_t bulk_waiter_spinlock; ··· 390 392 391 393 /* Signalled when a free slot becomes available. */ 392 394 struct completion slot_available_event; 393 393 - 394 394 - struct completion slot_remove_event; 395 395 396 396 /* Signalled when a free data slot becomes available. */ 397 397 struct completion data_quota_event; ··· 543 547 int vchiq_platform_init_state(struct vchiq_state *state); 544 548 545 549 int vchiq_check_service(struct vchiq_service *service); 546 546 - 547 547 - void vchiq_on_remote_use_active(struct vchiq_state *state); 548 550 549 551 int vchiq_send_remote_use(struct vchiq_state *state); 550 552

+1 -1

drivers/staging/vc04_services/interface/vchiq_arm/vchiq_dev.c

reviewed

··· 1324 1324 * vchiq_register_chrdev - Register the char driver for vchiq 1325 1325 * and create the necessary class and 1326 1326 * device files in userspace. 1327 1327 - * @parent The parent of the char device. 1327 1327 + * @parent: The parent of the char device. 1328 1328 * 1329 1329 * Returns 0 on success else returns the error code. 1330 1330 */

+4 -4

drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c

reviewed

··· 655 655 { 656 656 struct mmal_msg_context *msg_context; 657 657 int ret; 658 658 - unsigned long timeout; 658 658 + unsigned long time_left; 659 659 660 660 /* payload size must not cause message to exceed max size */ 661 661 if (payload_len > ··· 693 693 return ret; 694 694 } 695 695 696 696 - timeout = wait_for_completion_timeout(&msg_context->u.sync.cmplt, 697 697 - SYNC_MSG_TIMEOUT * HZ); 698 698 - if (timeout == 0) { 696 696 + time_left = wait_for_completion_timeout(&msg_context->u.sync.cmplt, 697 697 + SYNC_MSG_TIMEOUT * HZ); 698 698 + if (time_left == 0) { 699 699 pr_err("timed out waiting for sync completion\n"); 700 700 ret = -ETIME; 701 701 /* todo: what happens if the message arrives after aborting */

+1

drivers/staging/vme_user/vme_user.c

reviewed

··· 106 106 static const struct class vme_user_sysfs_class = { 107 107 .name = DRIVER_NAME, 108 108 }; 109 109 + 109 110 static const int type[VME_DEVS] = { MASTER_MINOR, MASTER_MINOR, 110 111 MASTER_MINOR, MASTER_MINOR, 111 112 SLAVE_MINOR, SLAVE_MINOR,

-1

drivers/staging/vt6656/TODO

reviewed

··· 11 11 - switch to use LIB80211 12 12 - switch to use MAC80211 13 13 - use kernel coding style 14 14 - - checkpatch.pl fixes 15 14 - sparse fixes 16 15 - integrate with drivers/net/wireless 17 16