Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2023-01-06' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Daniel Vetter:
"Still not much, but more than last week. Dave should be back next week
from the beaching.
drivers:
- i915-gvt fixes
- amdgpu/kfd fixes
- panfrost bo refcounting fix
- meson afbc corruption fix
- imx plane width fix
core:
- drm/sched fixes
- drm/mm kunit test fix
- dma-buf export error handling fixes"
* tag 'drm-fixes-2023-01-06' of git://anongit.freedesktop.org/drm/drm:
Revert "drm/amd/display: Enable Freesync Video Mode by default"
drm/i915/gvt: fix double free bug in split_2MB_gtt_entry
drm/i915/gvt: use atomic operations to change the vGPU status
drm/i915/gvt: fix vgpu debugfs clean in remove
drm/i915/gvt: fix gvt debugfs destroy
drm/i915: unpin on error in intel_vgpu_shadow_mm_pin()
drm/amd/display: Uninitialized variables causing 4k60 UCLK to stay at DPM1 and not DPM0
drm/amdkfd: Fix kernel warning during topology setup
drm/scheduler: Fix lockup in drm_sched_entity_kill()
drm/imx: ipuv3-plane: Fix overlay plane width
drm/scheduler: Fix lockup in drm_sched_entity_kill()
drm/virtio: Fix memory leak in virtio_gpu_object_create()
drm/meson: Reduce the FIFO lines held when AFBC is not used
drm/tests: reduce drm_mm_test stack usage
drm/panfrost: Fix GEM handle creation ref-counting
drm/plane-helper: Add the missing declaration of drm_atomic_state
dma-buf: fix dma_buf_export init order v2
+204
-153
+2
-5
drivers/dma-buf/dma-buf-sysfs-stats.c
+2
-5
drivers/dma-buf/dma-buf-sysfs-stats.c
···
168
168
kset_unregister(dma_buf_stats_kset);
169
169
}
170
170
171
-
int dma_buf_stats_setup(struct dma_buf *dmabuf)
171
+
int dma_buf_stats_setup(struct dma_buf *dmabuf, struct file *file)
172
172
{
173
173
struct dma_buf_sysfs_entry *sysfs_entry;
174
174
int ret;
175
-
176
-
if (!dmabuf || !dmabuf->file)
177
-
return -EINVAL;
178
175
179
176
if (!dmabuf->exp_name) {
180
177
pr_err("exporter name must not be empty if stats needed\n");
···
189
192
190
193
/* create the directory for buffer stats */
191
194
ret = kobject_init_and_add(&sysfs_entry->kobj, &dma_buf_ktype, NULL,
192
-
"%lu", file_inode(dmabuf->file)->i_ino);
195
+
"%lu", file_inode(file)->i_ino);
193
196
if (ret)
194
197
goto err_sysfs_dmabuf;
195
198
+2
-2
drivers/dma-buf/dma-buf-sysfs-stats.h
+2
-2
drivers/dma-buf/dma-buf-sysfs-stats.h
···
13
13
int dma_buf_init_sysfs_statistics(void);
14
14
void dma_buf_uninit_sysfs_statistics(void);
15
15
16
-
int dma_buf_stats_setup(struct dma_buf *dmabuf);
16
+
int dma_buf_stats_setup(struct dma_buf *dmabuf, struct file *file);
17
17
18
18
void dma_buf_stats_teardown(struct dma_buf *dmabuf);
19
19
#else
···
25
25
26
26
static inline void dma_buf_uninit_sysfs_statistics(void) {}
27
27
28
-
static inline int dma_buf_stats_setup(struct dma_buf *dmabuf)
28
+
static inline int dma_buf_stats_setup(struct dma_buf *dmabuf, struct file *file)
29
29
{
30
30
return 0;
31
31
}
+38
-44
drivers/dma-buf/dma-buf.c
+38
-44
drivers/dma-buf/dma-buf.c
···
95
95
return -EINVAL;
96
96
97
97
dmabuf = file->private_data;
98
-
99
-
mutex_lock(&db_list.lock);
100
-
list_del(&dmabuf->list_node);
101
-
mutex_unlock(&db_list.lock);
98
+
if (dmabuf) {
99
+
mutex_lock(&db_list.lock);
100
+
list_del(&dmabuf->list_node);
101
+
mutex_unlock(&db_list.lock);
102
+
}
102
103
103
104
return 0;
104
105
}
···
529
528
return file->f_op == &dma_buf_fops;
530
529
}
531
530
532
-
static struct file *dma_buf_getfile(struct dma_buf *dmabuf, int flags)
531
+
static struct file *dma_buf_getfile(size_t size, int flags)
533
532
{
534
533
static atomic64_t dmabuf_inode = ATOMIC64_INIT(0);
535
-
struct file *file;
536
534
struct inode *inode = alloc_anon_inode(dma_buf_mnt->mnt_sb);
535
+
struct file *file;
537
536
538
537
if (IS_ERR(inode))
539
538
return ERR_CAST(inode);
540
539
541
-
inode->i_size = dmabuf->size;
542
-
inode_set_bytes(inode, dmabuf->size);
540
+
inode->i_size = size;
541
+
inode_set_bytes(inode, size);
543
542
544
543
/*
545
544
* The ->i_ino acquired from get_next_ino() is not unique thus
···
553
552
flags, &dma_buf_fops);
554
553
if (IS_ERR(file))
555
554
goto err_alloc_file;
556
-
file->private_data = dmabuf;
557
-
file->f_path.dentry->d_fsdata = dmabuf;
558
555
559
556
return file;
560
557
···
618
619
size_t alloc_size = sizeof(struct dma_buf);
619
620
int ret;
620
621
621
-
if (!exp_info->resv)
622
-
alloc_size += sizeof(struct dma_resv);
623
-
else
624
-
/* prevent &dma_buf[1] == dma_buf->resv */
625
-
alloc_size += 1;
626
-
627
-
if (WARN_ON(!exp_info->priv
628
-
|| !exp_info->ops
629
-
|| !exp_info->ops->map_dma_buf
630
-
|| !exp_info->ops->unmap_dma_buf
631
-
|| !exp_info->ops->release)) {
622
+
if (WARN_ON(!exp_info->priv || !exp_info->ops
623
+
|| !exp_info->ops->map_dma_buf
624
+
|| !exp_info->ops->unmap_dma_buf
625
+
|| !exp_info->ops->release))
632
626
return ERR_PTR(-EINVAL);
633
-
}
634
627
635
628
if (WARN_ON(exp_info->ops->cache_sgt_mapping &&
636
629
(exp_info->ops->pin || exp_info->ops->unpin)))
···
634
643
if (!try_module_get(exp_info->owner))
635
644
return ERR_PTR(-ENOENT);
636
645
646
+
file = dma_buf_getfile(exp_info->size, exp_info->flags);
647
+
if (IS_ERR(file)) {
648
+
ret = PTR_ERR(file);
649
+
goto err_module;
650
+
}
651
+
652
+
if (!exp_info->resv)
653
+
alloc_size += sizeof(struct dma_resv);
654
+
else
655
+
/* prevent &dma_buf[1] == dma_buf->resv */
656
+
alloc_size += 1;
637
657
dmabuf = kzalloc(alloc_size, GFP_KERNEL);
638
658
if (!dmabuf) {
639
659
ret = -ENOMEM;
640
-
goto err_module;
660
+
goto err_file;
641
661
}
642
662
643
663
dmabuf->priv = exp_info->priv;
···
660
658
init_waitqueue_head(&dmabuf->poll);
661
659
dmabuf->cb_in.poll = dmabuf->cb_out.poll = &dmabuf->poll;
662
660
dmabuf->cb_in.active = dmabuf->cb_out.active = 0;
661
+
INIT_LIST_HEAD(&dmabuf->attachments);
663
662
664
663
if (!resv) {
665
-
resv = (struct dma_resv *)&dmabuf[1];
666
-
dma_resv_init(resv);
664
+
dmabuf->resv = (struct dma_resv *)&dmabuf[1];
665
+
dma_resv_init(dmabuf->resv);
666
+
} else {
667
+
dmabuf->resv = resv;
667
668
}
668
-
dmabuf->resv = resv;
669
669
670
-
file = dma_buf_getfile(dmabuf, exp_info->flags);
671
-
if (IS_ERR(file)) {
672
-
ret = PTR_ERR(file);
670
+
ret = dma_buf_stats_setup(dmabuf, file);
671
+
if (ret)
673
672
goto err_dmabuf;
674
-
}
675
673
674
+
file->private_data = dmabuf;
675
+
file->f_path.dentry->d_fsdata = dmabuf;
676
676
dmabuf->file = file;
677
-
678
-
INIT_LIST_HEAD(&dmabuf->attachments);
679
677
680
678
mutex_lock(&db_list.lock);
681
679
list_add(&dmabuf->list_node, &db_list.head);
682
680
mutex_unlock(&db_list.lock);
683
681
684
-
ret = dma_buf_stats_setup(dmabuf);
685
-
if (ret)
686
-
goto err_sysfs;
687
-
688
682
return dmabuf;
689
683
690
-
err_sysfs:
691
-
/*
692
-
* Set file->f_path.dentry->d_fsdata to NULL so that when
693
-
* dma_buf_release() gets invoked by dentry_ops, it exits
694
-
* early before calling the release() dma_buf op.
695
-
*/
696
-
file->f_path.dentry->d_fsdata = NULL;
697
-
fput(file);
698
684
err_dmabuf:
685
+
if (!resv)
686
+
dma_resv_fini(dmabuf->resv);
699
687
kfree(dmabuf);
688
+
err_file:
689
+
fput(file);
700
690
err_module:
701
691
module_put(exp_info->owner);
702
692
return ERR_PTR(ret);
+1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
+1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
···
195
195
extern uint amdgpu_smu_memory_pool_size;
196
196
extern int amdgpu_smu_pptable_id;
197
197
extern uint amdgpu_dc_feature_mask;
198
+
extern uint amdgpu_freesync_vid_mode;
198
199
extern uint amdgpu_dc_debug_mask;
199
200
extern uint amdgpu_dc_visual_confirm;
200
201
extern uint amdgpu_dm_abm_level;
+27
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+27
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
···
181
181
int amdgpu_noretry = -1;
182
182
int amdgpu_force_asic_type = -1;
183
183
int amdgpu_tmz = -1; /* auto */
184
+
uint amdgpu_freesync_vid_mode;
184
185
int amdgpu_reset_method = -1; /* auto */
185
186
int amdgpu_num_kcq = -1;
186
187
int amdgpu_smartshift_bias;
···
879
878
*/
880
879
MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
881
880
module_param_named(tmz, amdgpu_tmz, int, 0444);
881
+
882
+
/**
883
+
* DOC: freesync_video (uint)
884
+
* Enable the optimization to adjust front porch timing to achieve seamless
885
+
* mode change experience when setting a freesync supported mode for which full
886
+
* modeset is not needed.
887
+
*
888
+
* The Display Core will add a set of modes derived from the base FreeSync
889
+
* video mode into the corresponding connector's mode list based on commonly
890
+
* used refresh rates and VRR range of the connected display, when users enable
891
+
* this feature. From the userspace perspective, they can see a seamless mode
892
+
* change experience when the change between different refresh rates under the
893
+
* same resolution. Additionally, userspace applications such as Video playback
894
+
* can read this modeset list and change the refresh rate based on the video
895
+
* frame rate. Finally, the userspace can also derive an appropriate mode for a
896
+
* particular refresh rate based on the FreeSync Mode and add it to the
897
+
* connector's mode list.
898
+
*
899
+
* Note: This is an experimental feature.
900
+
*
901
+
* The default value: 0 (off).
902
+
*/
903
+
MODULE_PARM_DESC(
904
+
freesync_video,
905
+
"Enable freesync modesetting optimization feature (0 = off (default), 1 = on)");
906
+
module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
882
907
883
908
/**
884
909
* DOC: reset_method (int)
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+7
-5
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+7
-5
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
5835
5835
*/
5836
5836
DRM_DEBUG_DRIVER("No preferred mode found\n");
5837
5837
} else {
5838
-
recalculate_timing = is_freesync_video_mode(&mode, aconnector);
5838
+
recalculate_timing = amdgpu_freesync_vid_mode &&
5839
+
is_freesync_video_mode(&mode, aconnector);
5839
5840
if (recalculate_timing) {
5840
5841
freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
5841
5842
drm_mode_copy(&saved_mode, &mode);
···
6987
6986
struct amdgpu_dm_connector *amdgpu_dm_connector =
6988
6987
to_amdgpu_dm_connector(connector);
6989
6988
6990
-
if (!edid)
6989
+
if (!(amdgpu_freesync_vid_mode && edid))
6991
6990
return;
6992
6991
6993
6992
if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
···
8851
8850
* TODO: Refactor this function to allow this check to work
8852
8851
* in all conditions.
8853
8852
*/
8854
-
if (dm_new_crtc_state->stream &&
8853
+
if (amdgpu_freesync_vid_mode &&
8854
+
dm_new_crtc_state->stream &&
8855
8855
is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
8856
8856
goto skip_modeset;
8857
8857
···
8887
8885
if (!dm_old_crtc_state->stream)
8888
8886
goto skip_modeset;
8889
8887
8890
-
if (dm_new_crtc_state->stream &&
8888
+
if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
8891
8889
is_timing_unchanged_for_freesync(new_crtc_state,
8892
8890
old_crtc_state)) {
8893
8891
new_crtc_state->mode_changed = false;
···
8899
8897
set_freesync_fixed_config(dm_new_crtc_state);
8900
8898
8901
8899
goto skip_modeset;
8902
-
} else if (aconnector &&
8900
+
} else if (amdgpu_freesync_vid_mode && aconnector &&
8903
8901
is_freesync_video_mode(&new_crtc_state->mode,
8904
8902
aconnector)) {
8905
8903
struct drm_display_mode *high_mode;
+3
-3
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+3
-3
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
···
6257
6257
double SwathSizePerSurfaceC[DC__NUM_DPP__MAX];
6258
6258
bool NotEnoughDETSwathFillLatencyHiding = false;
6259
6259
6260
-
/* calculate sum of single swath size for all pipes in bytes*/
6260
+
/* calculate sum of single swath size for all pipes in bytes */
6261
6261
for (k = 0; k < NumberOfActiveSurfaces; k++) {
6262
-
SwathSizePerSurfaceY[k] += SwathHeightY[k] * SwathWidthY[k] * BytePerPixelInDETY[k] * NumOfDPP[k];
6262
+
SwathSizePerSurfaceY[k] = SwathHeightY[k] * SwathWidthY[k] * BytePerPixelInDETY[k] * NumOfDPP[k];
6263
6263
6264
6264
if (SwathHeightC[k] != 0)
6265
-
SwathSizePerSurfaceC[k] += SwathHeightC[k] * SwathWidthC[k] * BytePerPixelInDETC[k] * NumOfDPP[k];
6265
+
SwathSizePerSurfaceC[k] = SwathHeightC[k] * SwathWidthC[k] * BytePerPixelInDETC[k] * NumOfDPP[k];
6266
6266
else
6267
6267
SwathSizePerSurfaceC[k] = 0;
6268
6268
+31
-5
drivers/gpu/drm/i915/gvt/debugfs.c
+31
-5
drivers/gpu/drm/i915/gvt/debugfs.c
···
151
151
vgpu_scan_nonprivbb_get, vgpu_scan_nonprivbb_set,
152
152
"0x%llx\n");
153
153
154
+
static int vgpu_status_get(void *data, u64 *val)
155
+
{
156
+
struct intel_vgpu *vgpu = (struct intel_vgpu *)data;
157
+
158
+
*val = 0;
159
+
160
+
if (test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
161
+
*val |= (1 << INTEL_VGPU_STATUS_ATTACHED);
162
+
if (test_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status))
163
+
*val |= (1 << INTEL_VGPU_STATUS_ACTIVE);
164
+
165
+
return 0;
166
+
}
167
+
168
+
DEFINE_SIMPLE_ATTRIBUTE(vgpu_status_fops, vgpu_status_get, NULL, "0x%llx\n");
169
+
154
170
/**
155
171
* intel_gvt_debugfs_add_vgpu - register debugfs entries for a vGPU
156
172
* @vgpu: a vGPU
···
178
162
snprintf(name, 16, "vgpu%d", vgpu->id);
179
163
vgpu->debugfs = debugfs_create_dir(name, vgpu->gvt->debugfs_root);
180
164
181
-
debugfs_create_bool("active", 0444, vgpu->debugfs, &vgpu->active);
182
165
debugfs_create_file("mmio_diff", 0444, vgpu->debugfs, vgpu,
183
166
&vgpu_mmio_diff_fops);
184
167
debugfs_create_file("scan_nonprivbb", 0644, vgpu->debugfs, vgpu,
185
168
&vgpu_scan_nonprivbb_fops);
169
+
debugfs_create_file("status", 0644, vgpu->debugfs, vgpu,
170
+
&vgpu_status_fops);
186
171
}
187
172
188
173
/**
···
192
175
*/
193
176
void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu)
194
177
{
195
-
debugfs_remove_recursive(vgpu->debugfs);
196
-
vgpu->debugfs = NULL;
178
+
struct intel_gvt *gvt = vgpu->gvt;
179
+
struct drm_minor *minor = gvt->gt->i915->drm.primary;
180
+
181
+
if (minor->debugfs_root && gvt->debugfs_root) {
182
+
debugfs_remove_recursive(vgpu->debugfs);
183
+
vgpu->debugfs = NULL;
184
+
}
197
185
}
198
186
199
187
/**
···
221
199
*/
222
200
void intel_gvt_debugfs_clean(struct intel_gvt *gvt)
223
201
{
224
-
debugfs_remove_recursive(gvt->debugfs_root);
225
-
gvt->debugfs_root = NULL;
202
+
struct drm_minor *minor = gvt->gt->i915->drm.primary;
203
+
204
+
if (minor->debugfs_root) {
205
+
debugfs_remove_recursive(gvt->debugfs_root);
206
+
gvt->debugfs_root = NULL;
207
+
}
226
208
}
+2
-1
drivers/gpu/drm/i915/gvt/dmabuf.c
+2
-1
drivers/gpu/drm/i915/gvt/dmabuf.c
···
134
134
struct list_head *pos;
135
135
struct intel_vgpu_dmabuf_obj *dmabuf_obj;
136
136
137
-
if (vgpu && vgpu->active && !list_empty(&vgpu->dmabuf_obj_list_head)) {
137
+
if (vgpu && test_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status) &&
138
+
!list_empty(&vgpu->dmabuf_obj_list_head)) {
138
139
list_for_each(pos, &vgpu->dmabuf_obj_list_head) {
139
140
dmabuf_obj = list_entry(pos, struct intel_vgpu_dmabuf_obj, list);
140
141
if (dmabuf_obj == obj) {
+15
-6
drivers/gpu/drm/i915/gvt/gtt.c
+15
-6
drivers/gpu/drm/i915/gvt/gtt.c
···
55
55
int idx;
56
56
bool ret;
57
57
58
-
if (!vgpu->attached)
58
+
if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
59
59
return false;
60
60
61
61
idx = srcu_read_lock(&kvm->srcu);
···
1178
1178
if (!HAS_PAGE_SIZES(vgpu->gvt->gt->i915, I915_GTT_PAGE_SIZE_2M))
1179
1179
return 0;
1180
1180
1181
-
if (!vgpu->attached)
1181
+
if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
1182
1182
return -EINVAL;
1183
1183
pfn = gfn_to_pfn(vgpu->vfio_device.kvm, ops->get_pfn(entry));
1184
1184
if (is_error_noslot_pfn(pfn))
···
1209
1209
for_each_shadow_entry(sub_spt, &sub_se, sub_index) {
1210
1210
ret = intel_gvt_dma_map_guest_page(vgpu, start_gfn + sub_index,
1211
1211
PAGE_SIZE, &dma_addr);
1212
-
if (ret) {
1213
-
ppgtt_invalidate_spt(spt);
1214
-
return ret;
1215
-
}
1212
+
if (ret)
1213
+
goto err;
1216
1214
sub_se.val64 = se->val64;
1217
1215
1218
1216
/* Copy the PAT field from PDE. */
···
1229
1231
ops->set_pfn(se, sub_spt->shadow_page.mfn);
1230
1232
ppgtt_set_shadow_entry(spt, se, index);
1231
1233
return 0;
1234
+
err:
1235
+
/* Cancel the existing addess mappings of DMA addr. */
1236
+
for_each_present_shadow_entry(sub_spt, &sub_se, sub_index) {
1237
+
gvt_vdbg_mm("invalidate 4K entry\n");
1238
+
ppgtt_invalidate_pte(sub_spt, &sub_se);
1239
+
}
1240
+
/* Release the new allocated spt. */
1241
+
trace_spt_change(sub_spt->vgpu->id, "release", sub_spt,
1242
+
sub_spt->guest_page.gfn, sub_spt->shadow_page.type);
1243
+
ppgtt_free_spt(sub_spt);
1244
+
return ret;
1232
1245
}
1233
1246
1234
1247
static int split_64KB_gtt_entry(struct intel_vgpu *vgpu,
+10
-5
drivers/gpu/drm/i915/gvt/gvt.h
+10
-5
drivers/gpu/drm/i915/gvt/gvt.h
···
172
172
173
173
#define KVMGT_DEBUGFS_FILENAME "kvmgt_nr_cache_entries"
174
174
175
+
enum {
176
+
INTEL_VGPU_STATUS_ATTACHED = 0,
177
+
INTEL_VGPU_STATUS_ACTIVE,
178
+
INTEL_VGPU_STATUS_NR_BITS,
179
+
};
180
+
175
181
struct intel_vgpu {
176
182
struct vfio_device vfio_device;
177
183
struct intel_gvt *gvt;
178
184
struct mutex vgpu_lock;
179
185
int id;
180
-
bool active;
181
-
bool attached;
186
+
DECLARE_BITMAP(status, INTEL_VGPU_STATUS_NR_BITS);
182
187
bool pv_notified;
183
188
bool failsafe;
184
189
unsigned int resetting_eng;
···
472
467
473
468
#define for_each_active_vgpu(gvt, vgpu, id) \
474
469
idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
475
-
for_each_if(vgpu->active)
470
+
for_each_if(test_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status))
476
471
477
472
static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,
478
473
u32 offset, u32 val, bool low)
···
730
725
static inline int intel_gvt_read_gpa(struct intel_vgpu *vgpu, unsigned long gpa,
731
726
void *buf, unsigned long len)
732
727
{
733
-
if (!vgpu->attached)
728
+
if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
734
729
return -ESRCH;
735
730
return vfio_dma_rw(&vgpu->vfio_device, gpa, buf, len, false);
736
731
}
···
748
743
static inline int intel_gvt_write_gpa(struct intel_vgpu *vgpu,
749
744
unsigned long gpa, void *buf, unsigned long len)
750
745
{
751
-
if (!vgpu->attached)
746
+
if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
752
747
return -ESRCH;
753
748
return vfio_dma_rw(&vgpu->vfio_device, gpa, buf, len, true);
754
749
}
+1
-1
drivers/gpu/drm/i915/gvt/interrupt.c
+1
-1
drivers/gpu/drm/i915/gvt/interrupt.c
···
433
433
* enabled by guest. so if msi_trigger is null, success is still
434
434
* returned and don't inject interrupt into guest.
435
435
*/
436
-
if (!vgpu->attached)
436
+
if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
437
437
return -ESRCH;
438
438
if (vgpu->msi_trigger && eventfd_signal(vgpu->msi_trigger, 1) != 1)
439
439
return -EFAULT;
+13
-22
drivers/gpu/drm/i915/gvt/kvmgt.c
+13
-22
drivers/gpu/drm/i915/gvt/kvmgt.c
···
638
638
639
639
mutex_lock(&vgpu->gvt->lock);
640
640
for_each_active_vgpu(vgpu->gvt, itr, id) {
641
-
if (!itr->attached)
641
+
if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, itr->status))
642
642
continue;
643
643
644
644
if (vgpu->vfio_device.kvm == itr->vfio_device.kvm) {
···
655
655
{
656
656
struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev);
657
657
658
-
if (vgpu->attached)
659
-
return -EEXIST;
660
-
661
658
if (!vgpu->vfio_device.kvm ||
662
659
vgpu->vfio_device.kvm->mm != current->mm) {
663
660
gvt_vgpu_err("KVM is required to use Intel vGPU\n");
···
664
667
if (__kvmgt_vgpu_exist(vgpu))
665
668
return -EEXIST;
666
669
667
-
vgpu->attached = true;
668
-
669
670
vgpu->track_node.track_write = kvmgt_page_track_write;
670
671
vgpu->track_node.track_flush_slot = kvmgt_page_track_flush_slot;
671
672
kvm_get_kvm(vgpu->vfio_device.kvm);
672
673
kvm_page_track_register_notifier(vgpu->vfio_device.kvm,
673
674
&vgpu->track_node);
675
+
676
+
set_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status);
674
677
675
678
debugfs_create_ulong(KVMGT_DEBUGFS_FILENAME, 0444, vgpu->debugfs,
676
679
&vgpu->nr_cache_entries);
···
695
698
{
696
699
struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev);
697
700
698
-
if (!vgpu->attached)
699
-
return;
700
-
701
701
intel_gvt_release_vgpu(vgpu);
702
+
703
+
clear_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status);
702
704
703
705
debugfs_remove(debugfs_lookup(KVMGT_DEBUGFS_FILENAME, vgpu->debugfs));
704
706
···
714
718
vgpu->dma_addr_cache = RB_ROOT;
715
719
716
720
intel_vgpu_release_msi_eventfd_ctx(vgpu);
717
-
718
-
vgpu->attached = false;
719
721
}
720
722
721
723
static u64 intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar)
···
1506
1512
{
1507
1513
struct intel_vgpu *vgpu = dev_get_drvdata(&mdev->dev);
1508
1514
1509
-
if (WARN_ON_ONCE(vgpu->attached))
1510
-
return;
1511
-
1512
1515
vfio_unregister_group_dev(&vgpu->vfio_device);
1513
1516
vfio_put_device(&vgpu->vfio_device);
1514
1517
}
···
1550
1559
struct kvm_memory_slot *slot;
1551
1560
int idx;
1552
1561
1553
-
if (!info->attached)
1562
+
if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, info->status))
1554
1563
return -ESRCH;
1555
1564
1556
1565
idx = srcu_read_lock(&kvm->srcu);
···
1580
1589
struct kvm_memory_slot *slot;
1581
1590
int idx;
1582
1591
1583
-
if (!info->attached)
1584
-
return 0;
1592
+
if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, info->status))
1593
+
return -ESRCH;
1585
1594
1586
1595
idx = srcu_read_lock(&kvm->srcu);
1587
1596
slot = gfn_to_memslot(kvm, gfn);
···
1659
1668
struct gvt_dma *entry;
1660
1669
int ret;
1661
1670
1662
-
if (!vgpu->attached)
1671
+
if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
1663
1672
return -EINVAL;
1664
1673
1665
1674
mutex_lock(&vgpu->cache_lock);
···
1705
1714
struct gvt_dma *entry;
1706
1715
int ret = 0;
1707
1716
1708
-
if (!vgpu->attached)
1709
-
return -ENODEV;
1717
+
if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
1718
+
return -EINVAL;
1710
1719
1711
1720
mutex_lock(&vgpu->cache_lock);
1712
1721
entry = __gvt_cache_find_dma_addr(vgpu, dma_addr);
···
1733
1742
{
1734
1743
struct gvt_dma *entry;
1735
1744
1736
-
if (!vgpu->attached)
1745
+
if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
1737
1746
return;
1738
1747
1739
1748
mutex_lock(&vgpu->cache_lock);
···
1769
1778
idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) {
1770
1779
if (test_and_clear_bit(INTEL_GVT_REQUEST_EMULATE_VBLANK + id,
1771
1780
(void *)&gvt->service_request)) {
1772
-
if (vgpu->active)
1781
+
if (test_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status))
1773
1782
intel_vgpu_emulate_vblank(vgpu);
1774
1783
}
1775
1784
}
+3
-1
drivers/gpu/drm/i915/gvt/scheduler.c
+3
-1
drivers/gpu/drm/i915/gvt/scheduler.c
···
695
695
696
696
if (workload->shadow_mm->type != INTEL_GVT_MM_PPGTT ||
697
697
!workload->shadow_mm->ppgtt_mm.shadowed) {
698
+
intel_vgpu_unpin_mm(workload->shadow_mm);
698
699
gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
699
700
return -EINVAL;
700
701
}
···
866
865
goto out;
867
866
}
868
867
869
-
if (!scheduler->current_vgpu->active ||
868
+
if (!test_bit(INTEL_VGPU_STATUS_ACTIVE,
869
+
scheduler->current_vgpu->status) ||
870
870
list_empty(workload_q_head(scheduler->current_vgpu, engine)))
871
871
goto out;
872
872
+5
-7
drivers/gpu/drm/i915/gvt/vgpu.c
+5
-7
drivers/gpu/drm/i915/gvt/vgpu.c
···
166
166
*/
167
167
void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu)
168
168
{
169
-
mutex_lock(&vgpu->vgpu_lock);
170
-
vgpu->active = true;
171
-
mutex_unlock(&vgpu->vgpu_lock);
169
+
set_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status);
172
170
}
173
171
174
172
/**
···
181
183
{
182
184
mutex_lock(&vgpu->vgpu_lock);
183
185
184
-
vgpu->active = false;
186
+
clear_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status);
185
187
186
188
if (atomic_read(&vgpu->submission.running_workload_num)) {
187
189
mutex_unlock(&vgpu->vgpu_lock);
···
226
228
struct intel_gvt *gvt = vgpu->gvt;
227
229
struct drm_i915_private *i915 = gvt->gt->i915;
228
230
229
-
drm_WARN(&i915->drm, vgpu->active, "vGPU is still active!\n");
231
+
drm_WARN(&i915->drm, test_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status),
232
+
"vGPU is still active!\n");
230
233
231
234
/*
232
235
* remove idr first so later clean can judge if need to stop
···
284
285
if (ret)
285
286
goto out_free_vgpu;
286
287
287
-
vgpu->active = false;
288
-
288
+
clear_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status);
289
289
return vgpu;
290
290
291
291
out_free_vgpu:
+8
-6
drivers/gpu/drm/imx/ipuv3-plane.c
+8
-6
drivers/gpu/drm/imx/ipuv3-plane.c
···
614
614
break;
615
615
}
616
616
617
+
if (ipu_plane->dp_flow == IPU_DP_FLOW_SYNC_BG)
618
+
width = ipu_src_rect_width(new_state);
619
+
else
620
+
width = drm_rect_width(&new_state->src) >> 16;
621
+
617
622
eba = drm_plane_state_to_eba(new_state, 0);
618
623
619
624
/*
···
627
622
*/
628
623
if (ipu_state->use_pre) {
629
624
axi_id = ipu_chan_assign_axi_id(ipu_plane->dma);
630
-
ipu_prg_channel_configure(ipu_plane->ipu_ch, axi_id,
631
-
ipu_src_rect_width(new_state),
625
+
ipu_prg_channel_configure(ipu_plane->ipu_ch, axi_id, width,
632
626
drm_rect_height(&new_state->src) >> 16,
633
627
fb->pitches[0], fb->format->format,
634
628
fb->modifier, &eba);
···
682
678
break;
683
679
}
684
680
685
-
ipu_dmfc_config_wait4eot(ipu_plane->dmfc, ALIGN(drm_rect_width(dst), 8));
681
+
ipu_dmfc_config_wait4eot(ipu_plane->dmfc, width);
686
682
687
-
width = ipu_src_rect_width(new_state);
688
683
height = drm_rect_height(&new_state->src) >> 16;
689
684
info = drm_format_info(fb->format->format);
690
685
ipu_calculate_bursts(width, info->cpp[0], fb->pitches[0],
···
747
744
ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, 16);
748
745
749
746
ipu_cpmem_zero(ipu_plane->alpha_ch);
750
-
ipu_cpmem_set_resolution(ipu_plane->alpha_ch,
751
-
ipu_src_rect_width(new_state),
747
+
ipu_cpmem_set_resolution(ipu_plane->alpha_ch, width,
752
748
drm_rect_height(&new_state->src) >> 16);
753
749
ipu_cpmem_set_format_passthrough(ipu_plane->alpha_ch, 8);
754
750
ipu_cpmem_set_high_priority(ipu_plane->alpha_ch);
+2
-3
drivers/gpu/drm/meson/meson_viu.c
+2
-3
drivers/gpu/drm/meson/meson_viu.c
···
436
436
437
437
/* Initialize OSD1 fifo control register */
438
438
reg = VIU_OSD_DDR_PRIORITY_URGENT |
439
-
VIU_OSD_HOLD_FIFO_LINES(31) |
440
439
VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */
441
440
VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */
442
441
VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */
443
442
444
443
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
445
-
reg |= VIU_OSD_BURST_LENGTH_32;
444
+
reg |= (VIU_OSD_BURST_LENGTH_32 | VIU_OSD_HOLD_FIFO_LINES(31));
446
445
else
447
-
reg |= VIU_OSD_BURST_LENGTH_64;
446
+
reg |= (VIU_OSD_BURST_LENGTH_64 | VIU_OSD_HOLD_FIFO_LINES(4));
448
447
449
448
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
450
449
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));
+18
-9
drivers/gpu/drm/panfrost/panfrost_drv.c
+18
-9
drivers/gpu/drm/panfrost/panfrost_drv.c
···
82
82
struct panfrost_gem_object *bo;
83
83
struct drm_panfrost_create_bo *args = data;
84
84
struct panfrost_gem_mapping *mapping;
85
+
int ret;
85
86
86
87
if (!args->size || args->pad ||
87
88
(args->flags & ~(PANFROST_BO_NOEXEC | PANFROST_BO_HEAP)))
···
93
92
!(args->flags & PANFROST_BO_NOEXEC))
94
93
return -EINVAL;
95
94
96
-
bo = panfrost_gem_create_with_handle(file, dev, args->size, args->flags,
97
-
&args->handle);
95
+
bo = panfrost_gem_create(dev, args->size, args->flags);
98
96
if (IS_ERR(bo))
99
97
return PTR_ERR(bo);
100
98
99
+
ret = drm_gem_handle_create(file, &bo->base.base, &args->handle);
100
+
if (ret)
101
+
goto out;
102
+
101
103
mapping = panfrost_gem_mapping_get(bo, priv);
102
-
if (!mapping) {
103
-
drm_gem_object_put(&bo->base.base);
104
-
return -EINVAL;
104
+
if (mapping) {
105
+
args->offset = mapping->mmnode.start << PAGE_SHIFT;
106
+
panfrost_gem_mapping_put(mapping);
107
+
} else {
108
+
/* This can only happen if the handle from
109
+
* drm_gem_handle_create() has already been guessed and freed
110
+
* by user space
111
+
*/
112
+
ret = -EINVAL;
105
113
}
106
114
107
-
args->offset = mapping->mmnode.start << PAGE_SHIFT;
108
-
panfrost_gem_mapping_put(mapping);
109
-
110
-
return 0;
115
+
out:
116
+
drm_gem_object_put(&bo->base.base);
117
+
return ret;
111
118
}
112
119
113
120
/**
+1
-15
drivers/gpu/drm/panfrost/panfrost_gem.c
+1
-15
drivers/gpu/drm/panfrost/panfrost_gem.c
···
235
235
}
236
236
237
237
struct panfrost_gem_object *
238
-
panfrost_gem_create_with_handle(struct drm_file *file_priv,
239
-
struct drm_device *dev, size_t size,
240
-
u32 flags,
241
-
uint32_t *handle)
238
+
panfrost_gem_create(struct drm_device *dev, size_t size, u32 flags)
242
239
{
243
-
int ret;
244
240
struct drm_gem_shmem_object *shmem;
245
241
struct panfrost_gem_object *bo;
246
242
···
251
255
bo = to_panfrost_bo(&shmem->base);
252
256
bo->noexec = !!(flags & PANFROST_BO_NOEXEC);
253
257
bo->is_heap = !!(flags & PANFROST_BO_HEAP);
254
-
255
-
/*
256
-
* Allocate an id of idr table where the obj is registered
257
-
* and handle has the id what user can see.
258
-
*/
259
-
ret = drm_gem_handle_create(file_priv, &shmem->base, handle);
260
-
/* drop reference from allocate - handle holds it now. */
261
-
drm_gem_object_put(&shmem->base);
262
-
if (ret)
263
-
return ERR_PTR(ret);
264
258
265
259
return bo;
266
260
}
+1
-4
drivers/gpu/drm/panfrost/panfrost_gem.h
+1
-4
drivers/gpu/drm/panfrost/panfrost_gem.h
···
69
69
struct sg_table *sgt);
70
70
71
71
struct panfrost_gem_object *
72
-
panfrost_gem_create_with_handle(struct drm_file *file_priv,
73
-
struct drm_device *dev, size_t size,
74
-
u32 flags,
75
-
uint32_t *handle);
72
+
panfrost_gem_create(struct drm_device *dev, size_t size, u32 flags);
76
73
77
74
int panfrost_gem_open(struct drm_gem_object *obj, struct drm_file *file_priv);
78
75
void panfrost_gem_close(struct drm_gem_object *obj,
+1
-1
drivers/gpu/drm/scheduler/sched_entity.c
+1
-1
drivers/gpu/drm/scheduler/sched_entity.c
+2
-2
drivers/gpu/drm/scheduler/sched_main.c
+2
-2
drivers/gpu/drm/scheduler/sched_main.c
···
987
987
sched_job = drm_sched_entity_pop_job(entity);
988
988
989
989
if (!sched_job) {
990
-
complete(&entity->entity_idle);
990
+
complete_all(&entity->entity_idle);
991
991
continue;
992
992
}
993
993
···
998
998
999
999
trace_drm_run_job(sched_job, entity);
1000
1000
fence = sched->ops->run_job(sched_job);
1001
-
complete(&entity->entity_idle);
1001
+
complete_all(&entity->entity_idle);
1002
1002
drm_sched_fence_scheduled(s_fence);
1003
1003
1004
1004
if (!IS_ERR_OR_NULL(fence)) {
+2
drivers/gpu/drm/tests/Makefile
+2
drivers/gpu/drm/tests/Makefile
+3
-3
drivers/gpu/drm/tests/drm_mm_test.c
+3
-3
drivers/gpu/drm/tests/drm_mm_test.c
···
298
298
return false;
299
299
}
300
300
301
-
static bool check_reserve_boundaries(struct kunit *test, struct drm_mm *mm,
302
-
unsigned int count,
303
-
u64 size)
301
+
static bool noinline_for_stack check_reserve_boundaries(struct kunit *test, struct drm_mm *mm,
302
+
unsigned int count,
303
+
u64 size)
304
304
{
305
305
const struct boundary {
306
306
u64 start, size;
+4
-2
drivers/gpu/drm/virtio/virtgpu_object.c
+4
-2
drivers/gpu/drm/virtio/virtgpu_object.c
···
184
184
struct virtio_gpu_object_array *objs = NULL;
185
185
struct drm_gem_shmem_object *shmem_obj;
186
186
struct virtio_gpu_object *bo;
187
-
struct virtio_gpu_mem_entry *ents;
187
+
struct virtio_gpu_mem_entry *ents = NULL;
188
188
unsigned int nents;
189
189
int ret;
190
190
···
210
210
ret = -ENOMEM;
211
211
objs = virtio_gpu_array_alloc(1);
212
212
if (!objs)
213
-
goto err_put_id;
213
+
goto err_free_entry;
214
214
virtio_gpu_array_add_obj(objs, &bo->base.base);
215
215
216
216
ret = virtio_gpu_array_lock_resv(objs);
···
239
239
240
240
err_put_objs:
241
241
virtio_gpu_array_put_free(objs);
242
+
err_free_entry:
243
+
kvfree(ents);
242
244
err_put_id:
243
245
virtio_gpu_resource_id_put(vgdev, bo->hw_res_handle);
244
246
err_free_gem: