tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull more arm64 fixes from Will Deacon:

- Fix incorrect LDADD instruction encoding in our disassembly macros

- Disable the broken ARM64_PSEUDO_NMI support for now

- Add workaround for Cortex-A76 CPU erratum #1463225

- Handle Cortex-A76/Neoverse-N1 erratum #1418040 w/ existing workaround

- Fix IORT build failure if IOMMU_SUPPORT=n

- Fix place-relative module relocation range checking and its
interaction with KASLR

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: insn: Add BUILD_BUG_ON() for invalid masks
arm64: insn: Fix ldadd instruction encoding
arm64: Kconfig: Make ARM64_PSEUDO_NMI depend on BROKEN for now
arm64: Handle erratum 1418040 as a superset of erratum 1188873
arm64/module: deal with ambiguity in PRELxx relocation ranges
ACPI/IORT: Fix build error when IOMMU_SUPPORT is disabled
arm64/kernel: kaslr: reduce module randomization range to 2 GB
arm64: errata: Add workaround for Cortex-A76 erratum #1463225
arm64: Remove useless message during oops

Linus Torvalds 0a72ef89 c50bbf61

+284 -156
+5 -4
Documentation/arm64/silicon-errata.txt
··· 58 58 | ARM | Cortex-A72 | #853709 | N/A | 59 59 | ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 | 60 60 | ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 | 61 - | ARM | Cortex-A76 | #1188873 | ARM64_ERRATUM_1188873 | 61 + | ARM | Cortex-A76 | #1188873,1418040| ARM64_ERRATUM_1418040 | 62 62 | ARM | Cortex-A76 | #1165522 | ARM64_ERRATUM_1165522 | 63 63 | ARM | Cortex-A76 | #1286807 | ARM64_ERRATUM_1286807 | 64 - | ARM | Neoverse-N1 | #1188873 | ARM64_ERRATUM_1188873 | 65 - | ARM | MMU-500 | #841119,#826419 | N/A | 64 + | ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 | 65 + | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | 66 + | ARM | MMU-500 | #841119,826419 | N/A | 66 67 | | | | | 67 - | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | 68 + | Cavium | ThunderX ITS | #22375,24313 | CAVIUM_ERRATUM_22375 | 68 69 | Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 | 69 70 | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | 70 71 | Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
+22 -4
arch/arm64/Kconfig
··· 476 476 477 477 If unsure, say Y. 478 478 479 - config ARM64_ERRATUM_1188873 479 + config ARM64_ERRATUM_1418040 480 480 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 481 481 default y 482 482 depends on COMPAT 483 - select ARM_ARCH_TIMER_OOL_WORKAROUND 484 483 help 485 484 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 486 - erratum 1188873. 485 + errata 1188873 and 1418040. 487 486 488 - Affected Cortex-A76/Neoverse-N1 cores (r0p0, r1p0, r2p0) could 487 + Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 489 488 cause register corruption when accessing the timer registers 490 489 from AArch32 userspace. 491 490 ··· 517 518 TLBI+DSB completes before a read using the translation being 518 519 invalidated has been observed by other observers. The 519 520 workaround repeats the TLBI+DSB operation. 521 + 522 + If unsure, say Y. 523 + 524 + config ARM64_ERRATUM_1463225 525 + bool "Cortex-A76: Software Step might prevent interrupt recognition" 526 + default y 527 + help 528 + This option adds a workaround for Arm Cortex-A76 erratum 1463225. 529 + 530 + On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 531 + of a system call instruction (SVC) can prevent recognition of 532 + subsequent interrupts when software stepping is disabled in the 533 + exception handler of the system call and either kernel debugging 534 + is enabled or VHE is in use. 535 + 536 + Work around the erratum by triggering a dummy step exception 537 + when handling a system call from a task that is being stepped 538 + in a VHE configuration of the kernel. 520 539 521 540 If unsure, say Y. 522 541 ··· 1423 1406 1424 1407 config ARM64_PSEUDO_NMI 1425 1408 bool "Support for NMI-like interrupts" 1409 + depends on BROKEN # 1556553607-46531-1-git-send-email-julien.thierry@arm.com 1426 1410 select CONFIG_ARM_GIC_V3 1427 1411 help 1428 1412 Adds support for mimicking Non-Maskable Interrupts through the use of
+3 -2
arch/arm64/include/asm/cpucaps.h
··· 53 53 #define ARM64_HAS_STAGE2_FWB 32 54 54 #define ARM64_HAS_CRC32 33 55 55 #define ARM64_SSBS 34 56 - #define ARM64_WORKAROUND_1188873 35 56 + #define ARM64_WORKAROUND_1418040 35 57 57 #define ARM64_HAS_SB 36 58 58 #define ARM64_WORKAROUND_1165522 37 59 59 #define ARM64_HAS_ADDRESS_AUTH_ARCH 38 ··· 62 62 #define ARM64_HAS_GENERIC_AUTH_IMP_DEF 41 63 63 #define ARM64_HAS_IRQ_PRIO_MASKING 42 64 64 #define ARM64_HAS_DCPODP 43 65 + #define ARM64_WORKAROUND_1463225 44 65 66 66 - #define ARM64_NCAPS 44 67 + #define ARM64_NCAPS 45 67 68 68 69 #endif /* __ASM_CPUCAPS_H */
+12 -6
arch/arm64/include/asm/insn.h
··· 18 18 */ 19 19 #ifndef __ASM_INSN_H 20 20 #define __ASM_INSN_H 21 + #include <linux/build_bug.h> 21 22 #include <linux/types.h> 22 23 23 24 /* A64 instructions are always 32 bits. */ ··· 267 266 AARCH64_INSN_ADR_TYPE_ADR, 268 267 }; 269 268 270 - #define __AARCH64_INSN_FUNCS(abbr, mask, val) \ 271 - static __always_inline bool aarch64_insn_is_##abbr(u32 code) \ 272 - { return (code & (mask)) == (val); } \ 273 - static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \ 274 - { return (val); } 269 + #define __AARCH64_INSN_FUNCS(abbr, mask, val) \ 270 + static __always_inline bool aarch64_insn_is_##abbr(u32 code) \ 271 + { \ 272 + BUILD_BUG_ON(~(mask) & (val)); \ 273 + return (code & (mask)) == (val); \ 274 + } \ 275 + static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \ 276 + { \ 277 + return (val); \ 278 + } 275 279 276 280 __AARCH64_INSN_FUNCS(adr, 0x9F000000, 0x10000000) 277 281 __AARCH64_INSN_FUNCS(adrp, 0x9F000000, 0x90000000) 278 282 __AARCH64_INSN_FUNCS(prfm, 0x3FC00000, 0x39800000) 279 283 __AARCH64_INSN_FUNCS(prfm_lit, 0xFF000000, 0xD8000000) 280 284 __AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800) 281 - __AARCH64_INSN_FUNCS(ldadd, 0x3F20FC00, 0xB8200000) 285 + __AARCH64_INSN_FUNCS(ldadd, 0x3F20FC00, 0x38200000) 282 286 __AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800) 283 287 __AARCH64_INSN_FUNCS(ldr_lit, 0xBF000000, 0x18000000) 284 288 __AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000)
+38 -10
arch/arm64/kernel/cpu_errata.c
··· 502 502 {}, 503 503 }; 504 504 505 + #ifdef CONFIG_ARM64_ERRATUM_1463225 506 + DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa); 507 + 508 + static bool 509 + has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry, 510 + int scope) 511 + { 512 + u32 midr = read_cpuid_id(); 513 + /* Cortex-A76 r0p0 - r3p1 */ 514 + struct midr_range range = MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1); 515 + 516 + WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 517 + return is_midr_in_range(midr, &range) && is_kernel_in_hyp_mode(); 518 + } 519 + #endif 520 + 505 521 static void __maybe_unused 506 522 cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) 507 523 { ··· 698 682 }; 699 683 #endif 700 684 701 - #ifdef CONFIG_ARM64_ERRATUM_1188873 702 - static const struct midr_range erratum_1188873_list[] = { 703 - /* Cortex-A76 r0p0 to r2p0 */ 704 - MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0), 705 - /* Neoverse-N1 r0p0 to r2p0 */ 706 - MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 2, 0), 685 + #ifdef CONFIG_ARM64_ERRATUM_1418040 686 + /* 687 + * - 1188873 affects r0p0 to r2p0 688 + * - 1418040 affects r0p0 to r3p1 689 + */ 690 + static const struct midr_range erratum_1418040_list[] = { 691 + /* Cortex-A76 r0p0 to r3p1 */ 692 + MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 693 + /* Neoverse-N1 r0p0 to r3p1 */ 694 + MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1), 707 695 {}, 708 696 }; 709 697 #endif ··· 829 809 .matches = has_ssbd_mitigation, 830 810 .midr_range_list = arm64_ssb_cpus, 831 811 }, 832 - #ifdef CONFIG_ARM64_ERRATUM_1188873 812 + #ifdef CONFIG_ARM64_ERRATUM_1418040 833 813 { 834 - .desc = "ARM erratum 1188873", 835 - .capability = ARM64_WORKAROUND_1188873, 836 - ERRATA_MIDR_RANGE_LIST(erratum_1188873_list), 814 + .desc = "ARM erratum 1418040", 815 + .capability = ARM64_WORKAROUND_1418040, 816 + ERRATA_MIDR_RANGE_LIST(erratum_1418040_list), 837 817 }, 838 818 #endif 839 819 #ifdef CONFIG_ARM64_ERRATUM_1165522 ··· 842 822 .desc = "ARM erratum 1165522", 843 823 .capability = ARM64_WORKAROUND_1165522, 844 824 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0), 825 + }, 826 + #endif 827 + #ifdef CONFIG_ARM64_ERRATUM_1463225 828 + { 829 + .desc = "ARM erratum 1463225", 830 + .capability = ARM64_WORKAROUND_1463225, 831 + .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 832 + .matches = has_cortex_a76_erratum_1463225, 845 833 }, 846 834 #endif 847 835 {
+2 -2
arch/arm64/kernel/entry.S
··· 336 336 alternative_else_nop_endif 337 337 #endif 338 338 3: 339 - #ifdef CONFIG_ARM64_ERRATUM_1188873 340 - alternative_if_not ARM64_WORKAROUND_1188873 339 + #ifdef CONFIG_ARM64_ERRATUM_1418040 340 + alternative_if_not ARM64_WORKAROUND_1418040 341 341 b 4f 342 342 alternative_else_nop_endif 343 343 /*
+3 -3
arch/arm64/kernel/kaslr.c
··· 145 145 146 146 if (IS_ENABLED(CONFIG_RANDOMIZE_MODULE_REGION_FULL)) { 147 147 /* 148 - * Randomize the module region over a 4 GB window covering the 148 + * Randomize the module region over a 2 GB window covering the 149 149 * kernel. This reduces the risk of modules leaking information 150 150 * about the address of the kernel itself, but results in 151 151 * branches between modules and the core kernel that are 152 152 * resolved via PLTs. (Branches between modules will be 153 153 * resolved normally.) 154 154 */ 155 - module_range = SZ_4G - (u64)(_end - _stext); 156 - module_alloc_base = max((u64)_end + offset - SZ_4G, 155 + module_range = SZ_2G - (u64)(_end - _stext); 156 + module_alloc_base = max((u64)_end + offset - SZ_2G, 157 157 (u64)MODULES_VADDR); 158 158 } else { 159 159 /*
+15 -3
arch/arm64/kernel/module.c
··· 56 56 * can simply omit this fallback in that case. 57 57 */ 58 58 p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base, 59 - module_alloc_base + SZ_4G, GFP_KERNEL, 59 + module_alloc_base + SZ_2G, GFP_KERNEL, 60 60 PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE, 61 61 __builtin_return_address(0)); 62 62 ··· 96 96 { 97 97 s64 sval = do_reloc(op, place, val); 98 98 99 + /* 100 + * The ELF psABI for AArch64 documents the 16-bit and 32-bit place 101 + * relative relocations as having a range of [-2^15, 2^16) or 102 + * [-2^31, 2^32), respectively. However, in order to be able to detect 103 + * overflows reliably, we have to choose whether we interpret such 104 + * quantities as signed or as unsigned, and stick with it. 105 + * The way we organize our address space requires a signed 106 + * interpretation of 32-bit relative references, so let's use that 107 + * for all R_AARCH64_PRELxx relocations. This means our upper 108 + * bound for overflow detection should be Sxx_MAX rather than Uxx_MAX. 109 + */ 110 + 99 111 switch (len) { 100 112 case 16: 101 113 *(s16 *)place = sval; 102 - if (sval < S16_MIN || sval > U16_MAX) 114 + if (sval < S16_MIN || sval > S16_MAX) 103 115 return -ERANGE; 104 116 break; 105 117 case 32: 106 118 *(s32 *)place = sval; 107 - if (sval < S32_MIN || sval > U32_MAX) 119 + if (sval < S32_MIN || sval > S32_MAX) 108 120 return -ERANGE; 109 121 break; 110 122 case 64:
+31
arch/arm64/kernel/syscall.c
··· 8 8 #include <linux/syscalls.h> 9 9 10 10 #include <asm/daifflags.h> 11 + #include <asm/debug-monitors.h> 11 12 #include <asm/fpsimd.h> 12 13 #include <asm/syscall.h> 13 14 #include <asm/thread_info.h> ··· 61 60 int syscall_trace_enter(struct pt_regs *regs); 62 61 void syscall_trace_exit(struct pt_regs *regs); 63 62 63 + #ifdef CONFIG_ARM64_ERRATUM_1463225 64 + DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa); 65 + 66 + static void cortex_a76_erratum_1463225_svc_handler(void) 67 + { 68 + u32 reg, val; 69 + 70 + if (!unlikely(test_thread_flag(TIF_SINGLESTEP))) 71 + return; 72 + 73 + if (!unlikely(this_cpu_has_cap(ARM64_WORKAROUND_1463225))) 74 + return; 75 + 76 + __this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 1); 77 + reg = read_sysreg(mdscr_el1); 78 + val = reg | DBG_MDSCR_SS | DBG_MDSCR_KDE; 79 + write_sysreg(val, mdscr_el1); 80 + asm volatile("msr daifclr, #8"); 81 + isb(); 82 + 83 + /* We will have taken a single-step exception by this point */ 84 + 85 + write_sysreg(reg, mdscr_el1); 86 + __this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 0); 87 + } 88 + #else 89 + static void cortex_a76_erratum_1463225_svc_handler(void) { } 90 + #endif /* CONFIG_ARM64_ERRATUM_1463225 */ 91 + 64 92 static void el0_svc_common(struct pt_regs *regs, int scno, int sc_nr, 65 93 const syscall_fn_t syscall_table[]) 66 94 { ··· 98 68 regs->orig_x0 = regs->regs[0]; 99 69 regs->syscallno = scno; 100 70 71 + cortex_a76_erratum_1463225_svc_handler(); 101 72 local_daif_restore(DAIF_PROCCTX); 102 73 user_exit(); 103 74
-4
arch/arm64/kernel/traps.c
··· 168 168 169 169 static int __die(const char *str, int err, struct pt_regs *regs) 170 170 { 171 - struct task_struct *tsk = current; 172 171 static int die_counter; 173 172 int ret; 174 173 ··· 180 181 return ret; 181 182 182 183 print_modules(); 183 - pr_emerg("Process %.*s (pid: %d, stack limit = 0x%p)\n", 184 - TASK_COMM_LEN, tsk->comm, task_pid_nr(tsk), 185 - end_of_stack(tsk)); 186 184 show_regs(regs); 187 185 188 186 if (!user_mode(regs))
+33
arch/arm64/mm/fault.c
··· 811 811 debug_fault_info[nr].name = name; 812 812 } 813 813 814 + #ifdef CONFIG_ARM64_ERRATUM_1463225 815 + DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa); 816 + 817 + static int __exception 818 + cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs) 819 + { 820 + if (user_mode(regs)) 821 + return 0; 822 + 823 + if (!__this_cpu_read(__in_cortex_a76_erratum_1463225_wa)) 824 + return 0; 825 + 826 + /* 827 + * We've taken a dummy step exception from the kernel to ensure 828 + * that interrupts are re-enabled on the syscall path. Return back 829 + * to cortex_a76_erratum_1463225_svc_handler() with debug exceptions 830 + * masked so that we can safely restore the mdscr and get on with 831 + * handling the syscall. 832 + */ 833 + regs->pstate |= PSR_D_BIT; 834 + return 1; 835 + } 836 + #else 837 + static int __exception 838 + cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs) 839 + { 840 + return 0; 841 + } 842 + #endif /* CONFIG_ARM64_ERRATUM_1463225 */ 843 + 814 844 asmlinkage void __exception do_debug_exception(unsigned long addr_if_watchpoint, 815 845 unsigned int esr, 816 846 struct pt_regs *regs) 817 847 { 818 848 const struct fault_info *inf = esr_to_debug_fault_info(esr); 819 849 unsigned long pc = instruction_pointer(regs); 850 + 851 + if (cortex_a76_erratum_1463225_debug_handler(regs)) 852 + return; 820 853 821 854 /* 822 855 * Tell lockdep we disabled irqs in entry.S. Do nothing if they were
+120 -118
drivers/acpi/arm64/iort.c
··· 753 753 return 0; 754 754 } 755 755 756 - static int arm_smmu_iort_xlate(struct device *dev, u32 streamid, 757 - struct fwnode_handle *fwnode, 758 - const struct iommu_ops *ops) 759 - { 760 - int ret = iommu_fwspec_init(dev, fwnode, ops); 761 - 762 - if (!ret) 763 - ret = iommu_fwspec_add_ids(dev, &streamid, 1); 764 - 765 - return ret; 766 - } 767 - 768 - static inline bool iort_iommu_driver_enabled(u8 type) 769 - { 770 - switch (type) { 771 - case ACPI_IORT_NODE_SMMU_V3: 772 - return IS_BUILTIN(CONFIG_ARM_SMMU_V3); 773 - case ACPI_IORT_NODE_SMMU: 774 - return IS_BUILTIN(CONFIG_ARM_SMMU); 775 - default: 776 - pr_warn("IORT node type %u does not describe an SMMU\n", type); 777 - return false; 778 - } 779 - } 780 - 781 756 #ifdef CONFIG_IOMMU_API 782 757 static struct acpi_iort_node *iort_get_msi_resv_iommu(struct device *dev) 783 758 { ··· 853 878 854 879 return (resv == its->its_count) ? resv : -ENODEV; 855 880 } 856 - #else 857 - static inline const struct iommu_ops *iort_fwspec_iommu_ops(struct device *dev) 858 - { return NULL; } 859 - static inline int iort_add_device_replay(const struct iommu_ops *ops, 860 - struct device *dev) 861 - { return 0; } 862 - int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head) 863 - { return 0; } 864 - #endif 881 + 882 + static inline bool iort_iommu_driver_enabled(u8 type) 883 + { 884 + switch (type) { 885 + case ACPI_IORT_NODE_SMMU_V3: 886 + return IS_BUILTIN(CONFIG_ARM_SMMU_V3); 887 + case ACPI_IORT_NODE_SMMU: 888 + return IS_BUILTIN(CONFIG_ARM_SMMU); 889 + default: 890 + pr_warn("IORT node type %u does not describe an SMMU\n", type); 891 + return false; 892 + } 893 + } 894 + 895 + static int arm_smmu_iort_xlate(struct device *dev, u32 streamid, 896 + struct fwnode_handle *fwnode, 897 + const struct iommu_ops *ops) 898 + { 899 + int ret = iommu_fwspec_init(dev, fwnode, ops); 900 + 901 + if (!ret) 902 + ret = iommu_fwspec_add_ids(dev, &streamid, 1); 903 + 904 + return ret; 905 + } 906 + 907 + static bool iort_pci_rc_supports_ats(struct acpi_iort_node *node) 908 + { 909 + struct acpi_iort_root_complex *pci_rc; 910 + 911 + pci_rc = (struct acpi_iort_root_complex *)node->node_data; 912 + return pci_rc->ats_attribute & ACPI_IORT_ATS_SUPPORTED; 913 + } 865 914 866 915 static int iort_iommu_xlate(struct device *dev, struct acpi_iort_node *node, 867 916 u32 streamid) ··· 931 932 IORT_IOMMU_TYPE); 932 933 return iort_iommu_xlate(info->dev, parent, streamid); 933 934 } 935 + 936 + /** 937 + * iort_iommu_configure - Set-up IOMMU configuration for a device. 938 + * 939 + * @dev: device to configure 940 + * 941 + * Returns: iommu_ops pointer on configuration success 942 + * NULL on configuration failure 943 + */ 944 + const struct iommu_ops *iort_iommu_configure(struct device *dev) 945 + { 946 + struct acpi_iort_node *node, *parent; 947 + const struct iommu_ops *ops; 948 + u32 streamid = 0; 949 + int err = -ENODEV; 950 + 951 + /* 952 + * If we already translated the fwspec there 953 + * is nothing left to do, return the iommu_ops. 954 + */ 955 + ops = iort_fwspec_iommu_ops(dev); 956 + if (ops) 957 + return ops; 958 + 959 + if (dev_is_pci(dev)) { 960 + struct pci_bus *bus = to_pci_dev(dev)->bus; 961 + struct iort_pci_alias_info info = { .dev = dev }; 962 + 963 + node = iort_scan_node(ACPI_IORT_NODE_PCI_ROOT_COMPLEX, 964 + iort_match_node_callback, &bus->dev); 965 + if (!node) 966 + return NULL; 967 + 968 + info.node = node; 969 + err = pci_for_each_dma_alias(to_pci_dev(dev), 970 + iort_pci_iommu_init, &info); 971 + 972 + if (!err && iort_pci_rc_supports_ats(node)) 973 + dev->iommu_fwspec->flags |= IOMMU_FWSPEC_PCI_RC_ATS; 974 + } else { 975 + int i = 0; 976 + 977 + node = iort_scan_node(ACPI_IORT_NODE_NAMED_COMPONENT, 978 + iort_match_node_callback, dev); 979 + if (!node) 980 + return NULL; 981 + 982 + do { 983 + parent = iort_node_map_platform_id(node, &streamid, 984 + IORT_IOMMU_TYPE, 985 + i++); 986 + 987 + if (parent) 988 + err = iort_iommu_xlate(dev, parent, streamid); 989 + } while (parent && !err); 990 + } 991 + 992 + /* 993 + * If we have reason to believe the IOMMU driver missed the initial 994 + * add_device callback for dev, replay it to get things in order. 995 + */ 996 + if (!err) { 997 + ops = iort_fwspec_iommu_ops(dev); 998 + err = iort_add_device_replay(ops, dev); 999 + } 1000 + 1001 + /* Ignore all other errors apart from EPROBE_DEFER */ 1002 + if (err == -EPROBE_DEFER) { 1003 + ops = ERR_PTR(err); 1004 + } else if (err) { 1005 + dev_dbg(dev, "Adding to IOMMU failed: %d\n", err); 1006 + ops = NULL; 1007 + } 1008 + 1009 + return ops; 1010 + } 1011 + #else 1012 + static inline const struct iommu_ops *iort_fwspec_iommu_ops(struct device *dev) 1013 + { return NULL; } 1014 + static inline int iort_add_device_replay(const struct iommu_ops *ops, 1015 + struct device *dev) 1016 + { return 0; } 1017 + int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head) 1018 + { return 0; } 1019 + const struct iommu_ops *iort_iommu_configure(struct device *dev) 1020 + { return NULL; } 1021 + #endif 934 1022 935 1023 static int nc_dma_get_range(struct device *dev, u64 *size) 936 1024 { ··· 1115 1029 1116 1030 dev->dma_pfn_offset = PFN_DOWN(offset); 1117 1031 dev_dbg(dev, "dma_pfn_offset(%#08llx)\n", offset); 1118 - } 1119 - 1120 - static bool iort_pci_rc_supports_ats(struct acpi_iort_node *node) 1121 - { 1122 - struct acpi_iort_root_complex *pci_rc; 1123 - 1124 - pci_rc = (struct acpi_iort_root_complex *)node->node_data; 1125 - return pci_rc->ats_attribute & ACPI_IORT_ATS_SUPPORTED; 1126 - } 1127 - 1128 - /** 1129 - * iort_iommu_configure - Set-up IOMMU configuration for a device. 1130 - * 1131 - * @dev: device to configure 1132 - * 1133 - * Returns: iommu_ops pointer on configuration success 1134 - * NULL on configuration failure 1135 - */ 1136 - const struct iommu_ops *iort_iommu_configure(struct device *dev) 1137 - { 1138 - struct acpi_iort_node *node, *parent; 1139 - const struct iommu_ops *ops; 1140 - u32 streamid = 0; 1141 - int err = -ENODEV; 1142 - 1143 - /* 1144 - * If we already translated the fwspec there 1145 - * is nothing left to do, return the iommu_ops. 1146 - */ 1147 - ops = iort_fwspec_iommu_ops(dev); 1148 - if (ops) 1149 - return ops; 1150 - 1151 - if (dev_is_pci(dev)) { 1152 - struct pci_bus *bus = to_pci_dev(dev)->bus; 1153 - struct iort_pci_alias_info info = { .dev = dev }; 1154 - 1155 - node = iort_scan_node(ACPI_IORT_NODE_PCI_ROOT_COMPLEX, 1156 - iort_match_node_callback, &bus->dev); 1157 - if (!node) 1158 - return NULL; 1159 - 1160 - info.node = node; 1161 - err = pci_for_each_dma_alias(to_pci_dev(dev), 1162 - iort_pci_iommu_init, &info); 1163 - 1164 - if (!err && iort_pci_rc_supports_ats(node)) 1165 - dev->iommu_fwspec->flags |= IOMMU_FWSPEC_PCI_RC_ATS; 1166 - } else { 1167 - int i = 0; 1168 - 1169 - node = iort_scan_node(ACPI_IORT_NODE_NAMED_COMPONENT, 1170 - iort_match_node_callback, dev); 1171 - if (!node) 1172 - return NULL; 1173 - 1174 - do { 1175 - parent = iort_node_map_platform_id(node, &streamid, 1176 - IORT_IOMMU_TYPE, 1177 - i++); 1178 - 1179 - if (parent) 1180 - err = iort_iommu_xlate(dev, parent, streamid); 1181 - } while (parent && !err); 1182 - } 1183 - 1184 - /* 1185 - * If we have reason to believe the IOMMU driver missed the initial 1186 - * add_device callback for dev, replay it to get things in order. 1187 - */ 1188 - if (!err) { 1189 - ops = iort_fwspec_iommu_ops(dev); 1190 - err = iort_add_device_replay(ops, dev); 1191 - } 1192 - 1193 - /* Ignore all other errors apart from EPROBE_DEFER */ 1194 - if (err == -EPROBE_DEFER) { 1195 - ops = ERR_PTR(err); 1196 - } else if (err) { 1197 - dev_dbg(dev, "Adding to IOMMU failed: %d\n", err); 1198 - ops = NULL; 1199 - } 1200 - 1201 - return ops; 1202 1032 } 1203 1033 1204 1034 static void __init acpi_iort_register_irq(int hwirq, const char *name,