Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'regulator-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
Pull regulator updates from Mark Brown:
"This is a relatively busy release for the regulator API, as well as a
good collection of new drivers we've got a little bit of core work and
a bunch of cleanup throughout the subsystem:
- Support for propagating undervoltage events to child regulators
- Undo enables done on supplies when setting enabling regulators via
constraints fails
- Pull in some gpiolib changes adding support for shared GPIOs to the
gpiolib core, using them to replace the open coded variant of this
that we've had in the regulator API for a long time
- Support for Fitipower FP9931 and JD9330, Mediatek MT6316, MT6363
and MT6373, NXP PF1550 and Qualcomm PMH01XX and PMCX0102
The PF1550 support was originally going to go via the MFD tree but
Krzysztof's cleanup work overlapped with it so I pulled in Lee's
signed tag with support for the device"
* tag 'regulator-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator: (50 commits)
regulator: fp9931: Fix spelling mistake "failid" -> "failed"
regulator: core: Protect regulator_supply_alias_list with regulator_list_mutex
regulator: pf9453: Constify pointers to 'regulator_desc' wrap struct
regulator: pca9450: Constify pointers to 'regulator_desc' wrap struct
regulator: mt6358: Constify pointers to 'regulator_desc' wrap struct
regulator: bd96801: Constify pointers to 'regulator_desc' wrap struct
regulator: bd718x7: Constify pointers to 'regulator_desc' wrap struct
regulator: bd71828: Constify pointers to 'regulator_desc' wrap struct
regulator: bd71815: Constify pointers to 'regulator_desc' wrap struct
regulator: Use container_of_const() when all types are const
regulator: pca9450: Fix error code in probe()
regulator: qcomm-labibb: replace use of system_wq with system_dfl_wq
regulator: Add FP9931/JD9930 driver
dt-bindings: regulator: Add Fitipower FP9931/JD9930
dt-bindings: vendor-prefixes: Add Fitipower
regulator: make the subsystem aware of shared GPIOs
regulator: renesas-usb-vbus-regulator: Remove unused headers
regulator: pca9450: Add support for setting debounce settings
regulator: dt-bindings: pca9540: add debounce timer configuration
regulator: core: disable supply if enabling main regulator fails
...
+6245
-859
+161
Documentation/devicetree/bindings/mfd/nxp,pf1550.yaml
+161
Documentation/devicetree/bindings/mfd/nxp,pf1550.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mfd/nxp,pf1550.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NXP PF1550 Power Management IC
8
+
9
+
maintainers:
10
+
- Samuel Kayode <samuel.kayode@savoirfairelinux.com>
11
+
12
+
description:
13
+
PF1550 PMIC provides battery charging and power supply for low power IoT and
14
+
wearable applications. This device consists of an i2c controlled MFD that
15
+
includes regulators, battery charging and an onkey/power button.
16
+
17
+
$ref: /schemas/power/supply/power-supply.yaml
18
+
19
+
properties:
20
+
compatible:
21
+
const: nxp,pf1550
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
interrupts:
27
+
maxItems: 1
28
+
29
+
wakeup-source: true
30
+
31
+
regulators:
32
+
type: object
33
+
additionalProperties: false
34
+
35
+
patternProperties:
36
+
"^(ldo[1-3]|sw[1-3]|vrefddr)$":
37
+
type: object
38
+
$ref: /schemas/regulator/regulator.yaml
39
+
description:
40
+
regulator configuration for ldo1-3, buck converters(sw1-3)
41
+
and DDR termination reference voltage (vrefddr)
42
+
unevaluatedProperties: false
43
+
44
+
monitored-battery:
45
+
description: |
46
+
A phandle to a monitored battery node that contains a valid value
47
+
for:
48
+
constant-charge-voltage-max-microvolt.
49
+
50
+
nxp,thermal-regulation-celsius:
51
+
description:
52
+
Temperature threshold for thermal regulation of charger in celsius.
53
+
enum: [ 80, 95, 110, 125 ]
54
+
55
+
nxp,min-system-microvolt:
56
+
description:
57
+
System specific lower limit voltage.
58
+
enum: [ 3500000, 3700000, 4300000 ]
59
+
60
+
nxp,disable-key-power:
61
+
type: boolean
62
+
description:
63
+
Disable power-down using a long key-press. The onkey driver will remove
64
+
support for the KEY_POWER key press when triggered using a long press of
65
+
the onkey.
66
+
67
+
required:
68
+
- compatible
69
+
- reg
70
+
- interrupts
71
+
72
+
unevaluatedProperties: false
73
+
74
+
examples:
75
+
- |
76
+
#include <dt-bindings/interrupt-controller/irq.h>
77
+
#include <dt-bindings/input/linux-event-codes.h>
78
+
79
+
battery: battery-cell {
80
+
compatible = "simple-battery";
81
+
constant-charge-voltage-max-microvolt = <4400000>;
82
+
};
83
+
84
+
i2c {
85
+
#address-cells = <1>;
86
+
#size-cells = <0>;
87
+
88
+
pmic@8 {
89
+
compatible = "nxp,pf1550";
90
+
reg = <0x8>;
91
+
92
+
interrupt-parent = <&gpio1>;
93
+
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
94
+
wakeup-source;
95
+
monitored-battery = <&battery>;
96
+
nxp,min-system-microvolt = <4300000>;
97
+
nxp,thermal-regulation-celsius = <80>;
98
+
99
+
regulators {
100
+
sw1_reg: sw1 {
101
+
regulator-name = "sw1";
102
+
regulator-min-microvolt = <600000>;
103
+
regulator-max-microvolt = <1387500>;
104
+
regulator-always-on;
105
+
regulator-ramp-delay = <6250>;
106
+
107
+
regulator-state-mem {
108
+
regulator-on-in-suspend;
109
+
regulator-suspend-min-microvolt = <1270000>;
110
+
};
111
+
};
112
+
113
+
sw2_reg: sw2 {
114
+
regulator-name = "sw2";
115
+
regulator-min-microvolt = <600000>;
116
+
regulator-max-microvolt = <1387500>;
117
+
regulator-always-on;
118
+
119
+
regulator-state-mem {
120
+
regulator-on-in-suspend;
121
+
};
122
+
};
123
+
124
+
sw3_reg: sw3 {
125
+
regulator-name = "sw3";
126
+
regulator-min-microvolt = <1800000>;
127
+
regulator-max-microvolt = <3300000>;
128
+
regulator-always-on;
129
+
130
+
regulator-state-mem {
131
+
regulator-on-in-suspend;
132
+
};
133
+
};
134
+
135
+
vldo1_reg: ldo1 {
136
+
regulator-name = "ldo1";
137
+
regulator-min-microvolt = <750000>;
138
+
regulator-max-microvolt = <3300000>;
139
+
regulator-always-on;
140
+
141
+
regulator-state-mem {
142
+
regulator-off-in-suspend;
143
+
};
144
+
};
145
+
146
+
vldo2_reg: ldo2 {
147
+
regulator-name = "ldo2";
148
+
regulator-min-microvolt = <1800000>;
149
+
regulator-max-microvolt = <3300000>;
150
+
regulator-always-on;
151
+
};
152
+
153
+
vldo3_reg: ldo3 {
154
+
regulator-name = "ldo3";
155
+
regulator-min-microvolt = <750000>;
156
+
regulator-max-microvolt = <3300000>;
157
+
regulator-always-on;
158
+
};
159
+
};
160
+
};
161
+
};
-205
Documentation/devicetree/bindings/regulator/da9211.txt
-205
Documentation/devicetree/bindings/regulator/da9211.txt
···
1
-
* Dialog Semiconductor DA9211/DA9212/DA9213/DA9223/DA9214/DA9224/DA9215/DA9225
2
-
Voltage Regulator
3
-
4
-
Required properties:
5
-
- compatible: "dlg,da9211" or "dlg,da9212" or "dlg,da9213" or "dlg,da9223"
6
-
or "dlg,da9214" or "dlg,da9224" or "dlg,da9215" or "dlg,da9225"
7
-
- reg: I2C slave address, usually 0x68.
8
-
- interrupts: the interrupt outputs of the controller
9
-
- regulators: A node that houses a sub-node for each regulator within the
10
-
device. Each sub-node is identified using the node's name, with valid
11
-
values listed below. The content of each sub-node is defined by the
12
-
standard binding for regulators; see regulator.txt.
13
-
BUCKA and BUCKB.
14
-
15
-
Optional properties:
16
-
- enable-gpios: platform gpio for control of BUCKA/BUCKB.
17
-
- Any optional property defined in regulator.txt
18
-
- regulator-initial-mode and regulator-allowed-modes may be specified using
19
-
mode values from dt-bindings/regulator/dlg,da9211-regulator.h
20
-
21
-
Example 1) DA9211
22
-
pmic: da9211@68 {
23
-
compatible = "dlg,da9211";
24
-
reg = <0x68>;
25
-
interrupts = <3 27>;
26
-
27
-
regulators {
28
-
BUCKA {
29
-
regulator-name = "VBUCKA";
30
-
regulator-min-microvolt = < 300000>;
31
-
regulator-max-microvolt = <1570000>;
32
-
regulator-min-microamp = <2000000>;
33
-
regulator-max-microamp = <5000000>;
34
-
enable-gpios = <&gpio 27 0>;
35
-
regulator-allowed-modes = <DA9211_BUCK_MODE_SYNC
36
-
DA9211_BUCK_MODE_AUTO>;
37
-
};
38
-
};
39
-
};
40
-
41
-
Example 2) DA9212
42
-
pmic: da9212@68 {
43
-
compatible = "dlg,da9212";
44
-
reg = <0x68>;
45
-
interrupts = <3 27>;
46
-
47
-
regulators {
48
-
BUCKA {
49
-
regulator-name = "VBUCKA";
50
-
regulator-min-microvolt = < 300000>;
51
-
regulator-max-microvolt = <1570000>;
52
-
regulator-min-microamp = <2000000>;
53
-
regulator-max-microamp = <5000000>;
54
-
enable-gpios = <&gpio 27 0>;
55
-
};
56
-
BUCKB {
57
-
regulator-name = "VBUCKB";
58
-
regulator-min-microvolt = < 300000>;
59
-
regulator-max-microvolt = <1570000>;
60
-
regulator-min-microamp = <2000000>;
61
-
regulator-max-microamp = <5000000>;
62
-
enable-gpios = <&gpio 17 0>;
63
-
};
64
-
};
65
-
};
66
-
67
-
Example 3) DA9213
68
-
pmic: da9213@68 {
69
-
compatible = "dlg,da9213";
70
-
reg = <0x68>;
71
-
interrupts = <3 27>;
72
-
73
-
regulators {
74
-
BUCKA {
75
-
regulator-name = "VBUCKA";
76
-
regulator-min-microvolt = < 300000>;
77
-
regulator-max-microvolt = <1570000>;
78
-
regulator-min-microamp = <3000000>;
79
-
regulator-max-microamp = <6000000>;
80
-
enable-gpios = <&gpio 27 0>;
81
-
};
82
-
};
83
-
};
84
-
85
-
Example 4) DA9223
86
-
pmic: da9223@68 {
87
-
compatible = "dlg,da9223";
88
-
reg = <0x68>;
89
-
interrupts = <3 27>;
90
-
91
-
regulators {
92
-
BUCKA {
93
-
regulator-name = "VBUCKA";
94
-
regulator-min-microvolt = < 300000>;
95
-
regulator-max-microvolt = <1570000>;
96
-
regulator-min-microamp = <3000000>;
97
-
regulator-max-microamp = <6000000>;
98
-
enable-gpios = <&gpio 27 0>;
99
-
};
100
-
};
101
-
};
102
-
103
-
Example 5) DA9214
104
-
pmic: da9214@68 {
105
-
compatible = "dlg,da9214";
106
-
reg = <0x68>;
107
-
interrupts = <3 27>;
108
-
109
-
regulators {
110
-
BUCKA {
111
-
regulator-name = "VBUCKA";
112
-
regulator-min-microvolt = < 300000>;
113
-
regulator-max-microvolt = <1570000>;
114
-
regulator-min-microamp = <3000000>;
115
-
regulator-max-microamp = <6000000>;
116
-
enable-gpios = <&gpio 27 0>;
117
-
};
118
-
BUCKB {
119
-
regulator-name = "VBUCKB";
120
-
regulator-min-microvolt = < 300000>;
121
-
regulator-max-microvolt = <1570000>;
122
-
regulator-min-microamp = <3000000>;
123
-
regulator-max-microamp = <6000000>;
124
-
enable-gpios = <&gpio 17 0>;
125
-
};
126
-
};
127
-
};
128
-
129
-
Example 6) DA9224
130
-
pmic: da9224@68 {
131
-
compatible = "dlg,da9224";
132
-
reg = <0x68>;
133
-
interrupts = <3 27>;
134
-
135
-
regulators {
136
-
BUCKA {
137
-
regulator-name = "VBUCKA";
138
-
regulator-min-microvolt = < 300000>;
139
-
regulator-max-microvolt = <1570000>;
140
-
regulator-min-microamp = <3000000>;
141
-
regulator-max-microamp = <6000000>;
142
-
enable-gpios = <&gpio 27 0>;
143
-
};
144
-
BUCKB {
145
-
regulator-name = "VBUCKB";
146
-
regulator-min-microvolt = < 300000>;
147
-
regulator-max-microvolt = <1570000>;
148
-
regulator-min-microamp = <3000000>;
149
-
regulator-max-microamp = <6000000>;
150
-
enable-gpios = <&gpio 17 0>;
151
-
};
152
-
};
153
-
};
154
-
155
-
Example 7) DA9215
156
-
pmic: da9215@68 {
157
-
compatible = "dlg,da9215";
158
-
reg = <0x68>;
159
-
interrupts = <3 27>;
160
-
161
-
regulators {
162
-
BUCKA {
163
-
regulator-name = "VBUCKA";
164
-
regulator-min-microvolt = < 300000>;
165
-
regulator-max-microvolt = <1570000>;
166
-
regulator-min-microamp = <4000000>;
167
-
regulator-max-microamp = <7000000>;
168
-
enable-gpios = <&gpio 27 0>;
169
-
};
170
-
BUCKB {
171
-
regulator-name = "VBUCKB";
172
-
regulator-min-microvolt = < 300000>;
173
-
regulator-max-microvolt = <1570000>;
174
-
regulator-min-microamp = <4000000>;
175
-
regulator-max-microamp = <7000000>;
176
-
enable-gpios = <&gpio 17 0>;
177
-
};
178
-
};
179
-
};
180
-
181
-
Example 8) DA9225
182
-
pmic: da9225@68 {
183
-
compatible = "dlg,da9225";
184
-
reg = <0x68>;
185
-
interrupts = <3 27>;
186
-
187
-
regulators {
188
-
BUCKA {
189
-
regulator-name = "VBUCKA";
190
-
regulator-min-microvolt = < 300000>;
191
-
regulator-max-microvolt = <1570000>;
192
-
regulator-min-microamp = <4000000>;
193
-
regulator-max-microamp = <7000000>;
194
-
enable-gpios = <&gpio 27 0>;
195
-
};
196
-
BUCKB {
197
-
regulator-name = "VBUCKB";
198
-
regulator-min-microvolt = < 300000>;
199
-
regulator-max-microvolt = <1570000>;
200
-
regulator-min-microamp = <4000000>;
201
-
regulator-max-microamp = <7000000>;
202
-
enable-gpios = <&gpio 17 0>;
203
-
};
204
-
};
205
-
};
+103
Documentation/devicetree/bindings/regulator/dlg,da9211.yaml
+103
Documentation/devicetree/bindings/regulator/dlg,da9211.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/regulator/dlg,da9211.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title:
8
+
Dialog Semiconductor DA9211-9215, DA9223-9225 Voltage Regulators
9
+
10
+
maintainers:
11
+
- Ariel D'Alessandro <ariel.dalessandro@collabora.com>
12
+
13
+
properties:
14
+
compatible:
15
+
enum:
16
+
- dlg,da9211
17
+
- dlg,da9212
18
+
- dlg,da9213
19
+
- dlg,da9214
20
+
- dlg,da9215
21
+
- dlg,da9223
22
+
- dlg,da9224
23
+
- dlg,da9225
24
+
25
+
reg:
26
+
maxItems: 1
27
+
28
+
interrupts:
29
+
maxItems: 1
30
+
31
+
regulators:
32
+
type: object
33
+
additionalProperties: false
34
+
description:
35
+
List of regulators provided by the device
36
+
37
+
patternProperties:
38
+
"^BUCK([AB])$":
39
+
type: object
40
+
$ref: regulator.yaml#
41
+
unevaluatedProperties: false
42
+
description:
43
+
Properties for a single BUCK regulator
44
+
45
+
properties:
46
+
regulator-initial-mode:
47
+
items:
48
+
enum: [ 1, 2, 3 ]
49
+
description:
50
+
Defined in include/dt-bindings/regulator/dlg,da9211-regulator.h
51
+
52
+
regulator-allowed-modes:
53
+
items:
54
+
enum: [ 1, 2, 3 ]
55
+
description:
56
+
Defined in include/dt-bindings/regulator/dlg,da9211-regulator.h
57
+
58
+
enable-gpios:
59
+
maxItems: 1
60
+
61
+
required:
62
+
- compatible
63
+
- reg
64
+
- interrupts
65
+
- regulators
66
+
67
+
additionalProperties: false
68
+
69
+
examples:
70
+
- |
71
+
#include <dt-bindings/regulator/dlg,da9211-regulator.h>
72
+
73
+
i2c {
74
+
#address-cells = <1>;
75
+
#size-cells = <0>;
76
+
77
+
regulator@68 {
78
+
compatible = "dlg,da9212";
79
+
reg = <0x68>;
80
+
interrupts = <3 27>;
81
+
82
+
regulators {
83
+
BUCKA {
84
+
regulator-name = "VBUCKA";
85
+
regulator-min-microvolt = < 300000>;
86
+
regulator-max-microvolt = <1570000>;
87
+
regulator-min-microamp = <2000000>;
88
+
regulator-max-microamp = <5000000>;
89
+
enable-gpios = <&gpio 27 0>;
90
+
};
91
+
BUCKB {
92
+
regulator-name = "VBUCKB";
93
+
regulator-min-microvolt = < 300000>;
94
+
regulator-max-microvolt = <1570000>;
95
+
regulator-min-microamp = <2000000>;
96
+
regulator-max-microamp = <5000000>;
97
+
enable-gpios = <&gpio 17 0>;
98
+
};
99
+
};
100
+
};
101
+
};
102
+
103
+
...
+110
Documentation/devicetree/bindings/regulator/fitipower,fp9931.yaml
+110
Documentation/devicetree/bindings/regulator/fitipower,fp9931.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/regulator/fitipower,fp9931.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: FitiPower FP9931/JD9930 Power Management Integrated Circuit
8
+
9
+
maintainers:
10
+
- Andreas Kemnade <andreas@kemnade.info>
11
+
12
+
description:
13
+
FP9931 is a Power Management IC to provide Power for EPDs with one 3.3V
14
+
switch, 2 symmetric LDOs behind 2 DC/DC converters, and one unsymmetric
15
+
regulator for a compensation voltage.
16
+
JD9930 has in addition some kind of night mode.
17
+
18
+
properties:
19
+
compatible:
20
+
oneOf:
21
+
- const: fitipower,fp9931
22
+
23
+
- items:
24
+
- const: fitipower,jd9930
25
+
- const: fitipower,fp9931
26
+
27
+
reg:
28
+
maxItems: 1
29
+
30
+
enable-gpios:
31
+
maxItems: 1
32
+
33
+
pg-gpios:
34
+
maxItems: 1
35
+
36
+
en-ts-gpios:
37
+
maxItems: 1
38
+
39
+
xon-gpios:
40
+
maxItems: 1
41
+
42
+
vin-supply:
43
+
description:
44
+
Supply for the whole chip. Some vendor kernels and devicetrees
45
+
declare this as a non-existing GPIO named "pwrall".
46
+
47
+
fitipower,tdly-ms:
48
+
description:
49
+
Power up soft start delay settings tDLY1-4 bitfields in the
50
+
POWERON_DELAY register
51
+
items:
52
+
- enum: [0, 1, 2, 4]
53
+
- enum: [0, 1, 2, 4]
54
+
- enum: [0, 1, 2, 4]
55
+
- enum: [0, 1, 2, 4]
56
+
57
+
regulators:
58
+
type: object
59
+
additionalProperties: false
60
+
patternProperties:
61
+
"^(vcom|vposneg|v3p3)$":
62
+
unevaluatedProperties: false
63
+
type: object
64
+
$ref: /schemas/regulator/regulator.yaml
65
+
66
+
required:
67
+
- compatible
68
+
- reg
69
+
- pg-gpios
70
+
- enable-gpios
71
+
72
+
additionalProperties: false
73
+
74
+
examples:
75
+
- |
76
+
#include <dt-bindings/gpio/gpio.h>
77
+
i2c {
78
+
#address-cells = <1>;
79
+
#size-cells = <0>;
80
+
81
+
pmic@18 {
82
+
compatible = "fitipower,fp9931";
83
+
reg = <0x18>;
84
+
pinctrl-names = "default";
85
+
pinctrl-0 = <&pinctrl_fp9931_gpio>;
86
+
vin-supply = <&epd_pmic_supply>;
87
+
pg-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
88
+
en-ts-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
89
+
enable-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
90
+
fitipower,tdly-ms = <2 2 4 4>;
91
+
92
+
regulators {
93
+
vcom {
94
+
regulator-name = "vcom";
95
+
regulator-min-microvolt = <2352840>;
96
+
regulator-max-microvolt = <2352840>;
97
+
};
98
+
99
+
vposneg {
100
+
regulator-name = "vposneg";
101
+
regulator-min-microvolt = <15060000>;
102
+
regulator-max-microvolt = <15060000>;
103
+
};
104
+
105
+
v3p3 {
106
+
regulator-name = "v3p3";
107
+
};
108
+
};
109
+
};
110
+
};
+76
Documentation/devicetree/bindings/regulator/mediatek,mt6316b-regulator.yaml
+76
Documentation/devicetree/bindings/regulator/mediatek,mt6316b-regulator.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/regulator/mediatek,mt6316b-regulator.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MediaTek MT6316 BP/VP SPMI PMIC Regulators
8
+
9
+
maintainers:
10
+
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11
+
12
+
description:
13
+
The MediaTek MT6316BP/VP PMICs are fully controlled by SPMI interface, both
14
+
feature four step-down DC/DC (buck) converters, and provides 2+2 Phases,
15
+
joining Buck 1+2 for the first phase, and Buck 3+4 for the second phase.
16
+
17
+
properties:
18
+
compatible:
19
+
const: mediatek,mt6316b-regulator
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
patternProperties:
25
+
"^vbuck(12|34)$":
26
+
type: object
27
+
$ref: regulator.yaml#
28
+
unevaluatedProperties: false
29
+
properties:
30
+
regulator-allowed-modes:
31
+
description: |
32
+
Allowed Buck regulator operating modes allowed. Valid values below.
33
+
0 - Normal mode with automatic power saving, reducing the switching
34
+
frequency when light load conditions are detected
35
+
1 - Forced Continuous Conduction mode (FCCM) for improved voltage
36
+
regulation accuracy with constant switching frequency but lower
37
+
regulator efficiency
38
+
2 - Forced Low Power mode for improved regulator efficiency, used
39
+
when no heavy load is expected, will shut down unnecessary IP
40
+
blocks and secondary phases to reduce quiescent current.
41
+
This mode does not limit the maximum output current but unless
42
+
only a light load is applied, there will be regulation accuracy
43
+
and efficiency losses.
44
+
minItems: 1
45
+
maxItems: 3
46
+
items:
47
+
enum: [ 0, 1, 2 ]
48
+
49
+
required:
50
+
- compatible
51
+
- reg
52
+
53
+
additionalProperties: false
54
+
55
+
examples:
56
+
- |
57
+
#include <dt-bindings/spmi/spmi.h>
58
+
59
+
spmi {
60
+
#address-cells = <2>;
61
+
#size-cells = <0>;
62
+
63
+
pmic@8 {
64
+
compatible = "mediatek,mt6316b-regulator";
65
+
reg = <0x8 SPMI_USID>;
66
+
67
+
vbuck12 {
68
+
regulator-name = "dvdd_core";
69
+
regulator-min-microvolt = <450000>;
70
+
regulator-max-microvolt = <965000>;
71
+
regulator-allowed-modes = <0 1 2>;
72
+
regulator-enable-ramp-delay = <256>;
73
+
};
74
+
};
75
+
};
76
+
...
+76
Documentation/devicetree/bindings/regulator/mediatek,mt6316c-regulator.yaml
+76
Documentation/devicetree/bindings/regulator/mediatek,mt6316c-regulator.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/regulator/mediatek,mt6316c-regulator.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MediaTek MT6316 CP/HP/KP SPMI PMIC Regulators
8
+
9
+
maintainers:
10
+
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11
+
12
+
description:
13
+
The MediaTek MT6316CP/HP/KP PMICs are fully controlled by SPMI interface,
14
+
features four step-down DC/DC (buck) converters, and provides 3+1 Phases,
15
+
joining Buck 1+2+4 for the first phase, and uses Buck 3 for the second.
16
+
17
+
properties:
18
+
compatible:
19
+
const: mediatek,mt6316c-regulator
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
patternProperties:
25
+
"^vbuck(124|3)$":
26
+
type: object
27
+
$ref: regulator.yaml#
28
+
unevaluatedProperties: false
29
+
properties:
30
+
regulator-allowed-modes:
31
+
description: |
32
+
Allowed Buck regulator operating modes allowed. Valid values below.
33
+
0 - Normal mode with automatic power saving, reducing the switching
34
+
frequency when light load conditions are detected
35
+
1 - Forced Continuous Conduction mode (FCCM) for improved voltage
36
+
regulation accuracy with constant switching frequency but lower
37
+
regulator efficiency
38
+
2 - Forced Low Power mode for improved regulator efficiency, used
39
+
when no heavy load is expected, will shut down unnecessary IP
40
+
blocks and secondary phases to reduce quiescent current.
41
+
This mode does not limit the maximum output current but unless
42
+
only a light load is applied, there will be regulation accuracy
43
+
and efficiency losses.
44
+
minItems: 1
45
+
maxItems: 3
46
+
items:
47
+
enum: [ 0, 1, 2 ]
48
+
49
+
required:
50
+
- compatible
51
+
- reg
52
+
53
+
additionalProperties: false
54
+
55
+
examples:
56
+
- |
57
+
#include <dt-bindings/spmi/spmi.h>
58
+
59
+
spmi {
60
+
#address-cells = <2>;
61
+
#size-cells = <0>;
62
+
63
+
pmic@6 {
64
+
compatible = "mediatek,mt6316c-regulator";
65
+
reg = <0x6 SPMI_USID>;
66
+
67
+
vbuck124 {
68
+
regulator-name = "dvdd_proc_m";
69
+
regulator-min-microvolt = <450000>;
70
+
regulator-max-microvolt = <1277500>;
71
+
regulator-allowed-modes = <0 1 2>;
72
+
regulator-enable-ramp-delay = <256>;
73
+
};
74
+
};
75
+
};
76
+
...
+75
Documentation/devicetree/bindings/regulator/mediatek,mt6316d-regulator.yaml
+75
Documentation/devicetree/bindings/regulator/mediatek,mt6316d-regulator.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/regulator/mediatek,mt6316d-regulator.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MediaTek MT6316 DP/TP SPMI PMIC Regulators
8
+
9
+
maintainers:
10
+
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11
+
12
+
description:
13
+
The MediaTek MT6316DP/TP PMICs are fully controlled by SPMI interface, both
14
+
feature four step-down DC/DC (buck) converters, and provides a single Phase,
15
+
joining Buck 1+2+3+4.
16
+
17
+
properties:
18
+
compatible:
19
+
const: mediatek,mt6316d-regulator
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
vbuck1234:
25
+
type: object
26
+
$ref: regulator.yaml#
27
+
unevaluatedProperties: false
28
+
properties:
29
+
regulator-allowed-modes:
30
+
description: |
31
+
Allowed Buck regulator operating modes allowed. Valid values below.
32
+
0 - Normal mode with automatic power saving, reducing the switching
33
+
frequency when light load conditions are detected
34
+
1 - Forced Continuous Conduction mode (FCCM) for improved voltage
35
+
regulation accuracy with constant switching frequency but lower
36
+
regulator efficiency
37
+
2 - Forced Low Power mode for improved regulator efficiency, used
38
+
when no heavy load is expected, will shut down unnecessary IP
39
+
blocks and secondary phases to reduce quiescent current.
40
+
This mode does not limit the maximum output current but unless
41
+
only a light load is applied, there will be regulation accuracy
42
+
and efficiency losses.
43
+
minItems: 1
44
+
maxItems: 3
45
+
items:
46
+
enum: [ 0, 1, 2 ]
47
+
48
+
required:
49
+
- compatible
50
+
- reg
51
+
52
+
additionalProperties: false
53
+
54
+
examples:
55
+
- |
56
+
#include <dt-bindings/spmi/spmi.h>
57
+
58
+
spmi {
59
+
#address-cells = <2>;
60
+
#size-cells = <0>;
61
+
62
+
pmic@7 {
63
+
compatible = "mediatek,mt6316d-regulator";
64
+
reg = <0x7 SPMI_USID>;
65
+
66
+
vbuck1234 {
67
+
regulator-name = "dvdd_gpustack";
68
+
regulator-min-microvolt = <400000>;
69
+
regulator-max-microvolt = <1277500>;
70
+
regulator-allowed-modes = <0 1 2>;
71
+
regulator-enable-ramp-delay = <256>;
72
+
};
73
+
};
74
+
};
75
+
...
+146
Documentation/devicetree/bindings/regulator/mediatek,mt6363-regulator.yaml
+146
Documentation/devicetree/bindings/regulator/mediatek,mt6363-regulator.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/regulator/mediatek,mt6363-regulator.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MediaTek MT6363 PMIC Regulators
8
+
9
+
maintainers:
10
+
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11
+
12
+
description:
13
+
The MT6363 SPMI PMIC provides 10 BUCK and 25 LDO (Low DropOut) regulators
14
+
and can optionally provide overcurrent warnings with one ocp interrupt
15
+
for each voltage regulator.
16
+
17
+
properties:
18
+
compatible:
19
+
const: mediatek,mt6363-regulator
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
vsys-vbuck1-supply:
25
+
description: Input supply for vbuck1
26
+
27
+
vsys-vbuck2-supply:
28
+
description: Input supply for vbuck2
29
+
30
+
vsys-vbuck3-supply:
31
+
description: Input supply for vbuck3
32
+
33
+
vsys-vbuck4-supply:
34
+
description: Input supply for vbuck4
35
+
36
+
vsys-vbuck5-supply:
37
+
description: Input supply for vbuck5
38
+
39
+
vsys-vbuck6-supply:
40
+
description: Input supply for vbuck6
41
+
42
+
vsys-vbuck7-supply:
43
+
description: Input supply for vbuck7
44
+
45
+
vsys-vs1-supply:
46
+
description: Input supply for vs1
47
+
48
+
vsys-vs2-supply:
49
+
description: Input supply for vs2
50
+
51
+
vsys-vs3-supply:
52
+
description: Input supply for vs3
53
+
54
+
vs1-ldo1-supply:
55
+
description: Input supply for va15, vio0p75, vm18, vrf18, vrf-io18
56
+
57
+
vs1-ldo2-supply:
58
+
description: Input supply for vcn15, vio18, vufs18
59
+
60
+
vs2-ldo1-supply:
61
+
description: Input supply for vsram-cpub, vsram-cpum, vrf12, vrf13, vufs12
62
+
63
+
vs2-ldo2-supply:
64
+
description: Input supply for va12-1, va12-2, vcn13, vsram-cpul
65
+
66
+
vs3-ldo1-supply:
67
+
description: Input supply for vsram-apu, vsram-digrf, vsram-mdfe
68
+
69
+
vs3-ldo2-supply:
70
+
description: Input supply for vsram-modem, vrf0p9
71
+
72
+
vsys-ldo1-supply:
73
+
description: Input supply for vaux18, vemc, vtref18
74
+
75
+
patternProperties:
76
+
"^v(buck[1-7]|s[1-3])$":
77
+
description: Buck regulators
78
+
type: object
79
+
$ref: regulator.yaml#
80
+
unevaluatedProperties: false
81
+
properties:
82
+
regulator-allowed-modes:
83
+
description: |
84
+
Allowed Buck regulator operating modes allowed. Valid values below.
85
+
0 - Normal mode with automatic power saving, reducing the switching
86
+
frequency when light load conditions are detected
87
+
1 - Forced Continuous Conduction mode (FCCM) for improved voltage
88
+
regulation accuracy with constant switching frequency but lower
89
+
regulator efficiency
90
+
2 - Forced Low Power mode for improved regulator efficiency, used
91
+
when no heavy load is expected, does not limit the maximum out
92
+
current but unless only a light load is applied, there will be
93
+
regulation accuracy and efficiency losses.
94
+
3 - Forced Ultra Low Power mode for ultra low load, this greatly
95
+
reduces the maximum output power, makes the regulator to be
96
+
efficient only for ultra light load, and greatly reduces the
97
+
quiescent current (Iq) of the buck.
98
+
maxItems: 3
99
+
items:
100
+
enum: [ 0, 1, 2, 3 ]
101
+
102
+
"^va(12-1|12-2|15)$":
103
+
$ref: "#/$defs/ldo-common"
104
+
105
+
"^v(aux|m|rf-io|tref)18$":
106
+
$ref: "#/$defs/ldo-common"
107
+
108
+
"^v(cn13|cn15|emc)$":
109
+
$ref: "#/$defs/ldo-common"
110
+
111
+
"^vio(0p75|18)$":
112
+
$ref: "#/$defs/ldo-common"
113
+
114
+
"^vrf(0p9|12|13|18)$":
115
+
$ref: "#/$defs/ldo-common"
116
+
117
+
"^vsram-(apu|cpub|cpum|cpul|digrf|mdfe|modem)$":
118
+
$ref: "#/$defs/ldo-common"
119
+
120
+
"^vufs(12|18)$":
121
+
$ref: "#/$defs/ldo-common"
122
+
123
+
$defs:
124
+
ldo-common:
125
+
type: object
126
+
$ref: regulator.yaml#
127
+
unevaluatedProperties: false
128
+
properties:
129
+
regulator-allowed-modes:
130
+
description: |
131
+
Allowed LDO regulator operating modes allowed. Valid values below.
132
+
0 - Normal mode with automatic power saving, reducing the switching
133
+
frequency when light load conditions are detected
134
+
2 - Forced Low Power mode for improved regulator efficiency, used
135
+
when no heavy load is expected, does not limit the maximum out
136
+
current but unless only a light load is applied, there will be
137
+
regulation accuracy and efficiency losses.
138
+
maxItems: 2
139
+
items:
140
+
enum: [ 0, 2 ]
141
+
142
+
required:
143
+
- compatible
144
+
- reg
145
+
146
+
additionalProperties: false
+39
Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml
+39
Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml
···
41
41
interrupts:
42
42
maxItems: 1
43
43
44
+
inl1-supply:
45
+
description: Regulator supply for the INL1 pin group, powering LDOx
46
+
47
+
inb13-supply:
48
+
description:
49
+
Regulator supply for the INB13 pin group, powering BUCK1 and BUCK3.
50
+
51
+
inb26-supply:
52
+
description:
53
+
Regulator supply for the INB26 pin group, powering BUCK2 and BUCK6.
54
+
55
+
inb45-supply:
56
+
description:
57
+
Regulator supply for the INB45 pin group, powering BUCK4 and BUCK5.
58
+
44
59
regulators:
45
60
type: object
46
61
description: |
···
138
123
description:
139
124
When WDOG_B signal is asserted a warm reset will be done instead of cold
140
125
reset.
126
+
127
+
nxp,pmic-on-req-on-debounce-us:
128
+
enum: [ 120, 20000, 100000, 750000 ]
129
+
description: Debounce time for PMIC_ON_REQ high.
130
+
131
+
nxp,pmic-on-req-off-debounce-us:
132
+
enum: [ 120, 2000 ]
133
+
description: Debounce time for PMIC_ON_REQ is asserted low
134
+
135
+
nxp,power-on-step-ms:
136
+
enum: [ 1, 2, 4, 8]
137
+
description: Time step configuration during power on sequence
138
+
139
+
nxp,power-down-step-ms:
140
+
enum: [ 2, 4, 8, 16 ]
141
+
description: Time step configuration during power down sequence
142
+
143
+
nxp,restart-ms:
144
+
enum: [ 250, 500 ]
145
+
description: Time to stay off regulators during Cold reset
146
+
147
+
npx,pmic-rst-b-debounce-ms:
148
+
enum: [ 10, 50, 100, 500, 1000, 2000, 4000, 8000 ]
149
+
description: PMIC_RST_B debounce time
141
150
142
151
required:
143
152
- compatible
+52
-1
Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml
+52
-1
Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml
···
51
51
For PM8450, smps1 - smps6, ldo1 - ldo4
52
52
For PM8550, smps1 - smps6, ldo1 - ldo17, bob1 - bob2
53
53
For PM8998, smps1 - smps13, ldo1 - ldo28, lvs1 - lvs2
54
+
For PMH0101, ldo1 - ldo18, bob1 - bob2
55
+
For PMH0104, smps1 - smps4
56
+
For PMH0110, smps1 - smps10, ldo1 - ldo4
54
57
For PMI8998, bob
55
58
For PMC8380, smps1 - smps8, ldo1 - lodo3
59
+
For PMCX0102, smps1 - smps10, ldo1 - ldo4
56
60
For PMR735A, smps1 - smps3, ldo1 - ldo7
57
61
For PMR735B, ldo1 - ldo12
62
+
For PMR735D, ldo1 - ldo7
58
63
For PMX55, smps1 - smps7, ldo1 - ldo16
59
64
For PMX65, smps1 - smps8, ldo1 - ldo21
60
65
For PMX75, smps1 - smps10, ldo1 - ldo21
···
90
85
- qcom,pmc8180-rpmh-regulators
91
86
- qcom,pmc8180c-rpmh-regulators
92
87
- qcom,pmc8380-rpmh-regulators
88
+
- qcom,pmcx0102-rpmh-regulators
93
89
- qcom,pmg1110-rpmh-regulators
90
+
- qcom,pmh0101-rpmh-regulators
91
+
- qcom,pmh0104-rpmh-regulators
92
+
- qcom,pmh0110-rpmh-regulators
94
93
- qcom,pmi8998-rpmh-regulators
95
94
- qcom,pmm8155au-rpmh-regulators
96
95
- qcom,pmm8654au-rpmh-regulators
97
96
- qcom,pmr735a-rpmh-regulators
98
97
- qcom,pmr735b-rpmh-regulators
98
+
- qcom,pmr735d-rpmh-regulators
99
99
- qcom,pmx55-rpmh-regulators
100
100
- qcom,pmx65-rpmh-regulators
101
101
- qcom,pmx75-rpmh-regulators
···
110
100
RPMh resource name suffix used for the regulators found
111
101
on this PMIC.
112
102
$ref: /schemas/types.yaml#/definitions/string
113
-
enum: [a, b, c, d, e, f, g, h, i, j, k, l, m, n]
103
+
pattern: "^[a-n]|[A-N]_E[0-3]+$"
114
104
115
105
qcom,always-wait-for-ack:
116
106
description: |
···
256
246
compatible:
257
247
enum:
258
248
- qcom,pm8005-rpmh-regulators
249
+
- qcom,pmh0104-rpmh-regulators
259
250
then:
260
251
patternProperties:
261
252
"^vdd-s[1-4]-supply$": true
···
437
426
properties:
438
427
compatible:
439
428
enum:
429
+
- qcom,pmh0101-rpmh-regulators
430
+
then:
431
+
properties:
432
+
vdd-l1-l4-l10-supply: true
433
+
vdd-l2-l13-l14-supply: true
434
+
vdd-l3-l11-supply: true
435
+
vdd-l5-l16-supply: true
436
+
vdd-l6-l7-supply: true
437
+
vdd-l8-l9-supply: true
438
+
patternProperties:
439
+
"^vdd-l(1[2578])-supply$": true
440
+
"^vdd-bob[1-2]-supply$": true
441
+
442
+
- if:
443
+
properties:
444
+
compatible:
445
+
enum:
446
+
- qcom,pmcx0102-rpmh-regulators
447
+
- qcom,pmh0110-rpmh-regulators
448
+
then:
449
+
patternProperties:
450
+
"^vdd-l[1-4]-supply$": true
451
+
"^vdd-s([1-9]|10)-supply$": true
452
+
453
+
- if:
454
+
properties:
455
+
compatible:
456
+
enum:
440
457
- qcom,pmi8998-rpmh-regulators
441
458
then:
442
459
properties:
···
497
458
vdd-l7-l8-supply: true
498
459
patternProperties:
499
460
"^vdd-l([3-6]|9|1[0-2])-supply$": true
461
+
462
+
- if:
463
+
properties:
464
+
compatible:
465
+
enum:
466
+
- qcom,pmr735d-rpmh-regulators
467
+
then:
468
+
properties:
469
+
vdd-l1-l2-l5-supply: true
470
+
vdd-l3-l4-supply: true
471
+
patternProperties:
472
+
"^vdd-l[6-7]-supply$": true
500
473
501
474
- if:
502
475
properties:
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
+11
-1
MAINTAINERS
+11
-1
MAINTAINERS
···
7223
7223
F: Documentation/devicetree/bindings/input/dlg,da9062-onkey.yaml
7224
7224
F: Documentation/devicetree/bindings/mfd/da90*.txt
7225
7225
F: Documentation/devicetree/bindings/mfd/dlg,da90*.yaml
7226
-
F: Documentation/devicetree/bindings/regulator/da92*.txt
7227
7226
F: Documentation/devicetree/bindings/regulator/dlg,da9*.yaml
7228
7227
F: Documentation/devicetree/bindings/regulator/dlg,slg51000.yaml
7229
7228
F: Documentation/devicetree/bindings/sound/da[79]*.txt
···
18708
18709
S: Maintained
18709
18710
F: Documentation/devicetree/bindings/regulator/nxp,pf5300.yaml
18710
18711
F: drivers/regulator/pf530x-regulator.c
18712
+
18713
+
NXP PF1550 PMIC MFD DRIVER
18714
+
M: Samuel Kayode <samuel.kayode@savoirfairelinux.com>
18715
+
L: imx@lists.linux.dev
18716
+
S: Maintained
18717
+
F: Documentation/devicetree/bindings/mfd/nxp,pf1550.yaml
18718
+
F: drivers/input/misc/pf1550-onkey.c
18719
+
F: drivers/mfd/pf1550.c
18720
+
F: drivers/power/supply/pf1550-charger.c
18721
+
F: drivers/regulator/pf1550-regulator.c
18722
+
F: include/linux/mfd/pfd1550.h
18711
18723
18712
18724
NXP PF8100/PF8121A/PF8200 PMIC REGULATOR DEVICE DRIVER
18713
18725
M: Jagan Teki <jagan@amarulasolutions.com>
+11
drivers/input/misc/Kconfig
+11
drivers/input/misc/Kconfig
···
190
190
To compile this driver as a module, choose M here: the
191
191
module will be called pcspkr.
192
192
193
+
config INPUT_PF1550_ONKEY
194
+
tristate "NXP PF1550 Onkey support"
195
+
depends on MFD_PF1550
196
+
help
197
+
Say Y here if you want support for PF1550 PMIC. Onkey can trigger
198
+
release and 1s(push hold), 2s, 3s, 4s, 8s interrupt for long press
199
+
detect.
200
+
201
+
To compile this driver as a module, choose M here. The module will be
202
+
called pf1550-onkey.
203
+
193
204
config INPUT_PM8941_PWRKEY
194
205
tristate "Qualcomm PM8941 power key support"
195
206
depends on MFD_SPMI_PMIC
+1
drivers/input/misc/Makefile
+1
drivers/input/misc/Makefile
···
63
63
obj-$(CONFIG_INPUT_PCAP) += pcap_keys.o
64
64
obj-$(CONFIG_INPUT_PCF8574) += pcf8574_keypad.o
65
65
obj-$(CONFIG_INPUT_PCSPKR) += pcspkr.o
66
+
obj-$(CONFIG_INPUT_PF1550_ONKEY) += pf1550-onkey.o
66
67
obj-$(CONFIG_INPUT_PM8941_PWRKEY) += pm8941-pwrkey.o
67
68
obj-$(CONFIG_INPUT_PM8XXX_VIBRATOR) += pm8xxx-vibrator.o
68
69
obj-$(CONFIG_INPUT_PMIC8XXX_PWRKEY) += pmic8xxx-pwrkey.o
+197
drivers/input/misc/pf1550-onkey.c
+197
drivers/input/misc/pf1550-onkey.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Driver for the PF1550 ONKEY
4
+
* Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved.
5
+
*
6
+
* Portions Copyright (c) 2025 Savoir-faire Linux Inc.
7
+
* Samuel Kayode <samuel.kayode@savoirfairelinux.com>
8
+
*/
9
+
10
+
#include <linux/err.h>
11
+
#include <linux/input.h>
12
+
#include <linux/interrupt.h>
13
+
#include <linux/kernel.h>
14
+
#include <linux/module.h>
15
+
#include <linux/mfd/pf1550.h>
16
+
#include <linux/platform_device.h>
17
+
18
+
#define PF1550_ONKEY_IRQ_NR 6
19
+
20
+
struct onkey_drv_data {
21
+
struct device *dev;
22
+
const struct pf1550_ddata *pf1550;
23
+
bool wakeup;
24
+
struct input_dev *input;
25
+
};
26
+
27
+
static irqreturn_t pf1550_onkey_irq_handler(int irq, void *data)
28
+
{
29
+
struct onkey_drv_data *onkey = data;
30
+
struct platform_device *pdev = to_platform_device(onkey->dev);
31
+
int i, state, irq_type = -1;
32
+
33
+
for (i = 0; i < PF1550_ONKEY_IRQ_NR; i++)
34
+
if (irq == platform_get_irq(pdev, i))
35
+
irq_type = i;
36
+
37
+
switch (irq_type) {
38
+
case PF1550_ONKEY_IRQ_PUSHI:
39
+
state = 0;
40
+
break;
41
+
case PF1550_ONKEY_IRQ_1SI:
42
+
case PF1550_ONKEY_IRQ_2SI:
43
+
case PF1550_ONKEY_IRQ_3SI:
44
+
case PF1550_ONKEY_IRQ_4SI:
45
+
case PF1550_ONKEY_IRQ_8SI:
46
+
state = 1;
47
+
break;
48
+
default:
49
+
dev_err(onkey->dev, "onkey interrupt: irq %d occurred\n",
50
+
irq_type);
51
+
return IRQ_HANDLED;
52
+
}
53
+
54
+
input_event(onkey->input, EV_KEY, KEY_POWER, state);
55
+
input_sync(onkey->input);
56
+
57
+
return IRQ_HANDLED;
58
+
}
59
+
60
+
static int pf1550_onkey_probe(struct platform_device *pdev)
61
+
{
62
+
struct onkey_drv_data *onkey;
63
+
struct input_dev *input;
64
+
bool key_power = false;
65
+
int i, irq, error;
66
+
67
+
onkey = devm_kzalloc(&pdev->dev, sizeof(*onkey), GFP_KERNEL);
68
+
if (!onkey)
69
+
return -ENOMEM;
70
+
71
+
onkey->dev = &pdev->dev;
72
+
73
+
onkey->pf1550 = dev_get_drvdata(pdev->dev.parent);
74
+
if (!onkey->pf1550->regmap)
75
+
return dev_err_probe(&pdev->dev, -ENODEV,
76
+
"failed to get regmap\n");
77
+
78
+
onkey->wakeup = device_property_read_bool(pdev->dev.parent,
79
+
"wakeup-source");
80
+
81
+
if (device_property_read_bool(pdev->dev.parent,
82
+
"nxp,disable-key-power")) {
83
+
error = regmap_clear_bits(onkey->pf1550->regmap,
84
+
PF1550_PMIC_REG_PWRCTRL1,
85
+
PF1550_ONKEY_RST_EN);
86
+
if (error)
87
+
return dev_err_probe(&pdev->dev, error,
88
+
"failed: disable turn system off");
89
+
} else {
90
+
key_power = true;
91
+
}
92
+
93
+
input = devm_input_allocate_device(&pdev->dev);
94
+
if (!input)
95
+
return dev_err_probe(&pdev->dev, -ENOMEM,
96
+
"failed to allocate the input device\n");
97
+
98
+
input->name = pdev->name;
99
+
input->phys = "pf1550-onkey/input0";
100
+
input->id.bustype = BUS_HOST;
101
+
102
+
if (key_power)
103
+
input_set_capability(input, EV_KEY, KEY_POWER);
104
+
105
+
onkey->input = input;
106
+
platform_set_drvdata(pdev, onkey);
107
+
108
+
for (i = 0; i < PF1550_ONKEY_IRQ_NR; i++) {
109
+
irq = platform_get_irq(pdev, i);
110
+
if (irq < 0)
111
+
return irq;
112
+
113
+
error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
114
+
pf1550_onkey_irq_handler,
115
+
IRQF_NO_SUSPEND,
116
+
"pf1550-onkey", onkey);
117
+
if (error)
118
+
return dev_err_probe(&pdev->dev, error,
119
+
"failed: irq request (IRQ: %d)\n",
120
+
i);
121
+
}
122
+
123
+
error = input_register_device(input);
124
+
if (error)
125
+
return dev_err_probe(&pdev->dev, error,
126
+
"failed to register input device\n");
127
+
128
+
device_init_wakeup(&pdev->dev, onkey->wakeup);
129
+
130
+
return 0;
131
+
}
132
+
133
+
static int pf1550_onkey_suspend(struct device *dev)
134
+
{
135
+
struct platform_device *pdev = to_platform_device(dev);
136
+
struct onkey_drv_data *onkey = platform_get_drvdata(pdev);
137
+
int i, irq;
138
+
139
+
if (!device_may_wakeup(&pdev->dev))
140
+
regmap_write(onkey->pf1550->regmap,
141
+
PF1550_PMIC_REG_ONKEY_INT_MASK0,
142
+
ONKEY_IRQ_PUSHI | ONKEY_IRQ_1SI | ONKEY_IRQ_2SI |
143
+
ONKEY_IRQ_3SI | ONKEY_IRQ_4SI | ONKEY_IRQ_8SI);
144
+
else
145
+
for (i = 0; i < PF1550_ONKEY_IRQ_NR; i++) {
146
+
irq = platform_get_irq(pdev, i);
147
+
if (irq > 0)
148
+
enable_irq_wake(irq);
149
+
}
150
+
151
+
return 0;
152
+
}
153
+
154
+
static int pf1550_onkey_resume(struct device *dev)
155
+
{
156
+
struct platform_device *pdev = to_platform_device(dev);
157
+
struct onkey_drv_data *onkey = platform_get_drvdata(pdev);
158
+
int i, irq;
159
+
160
+
if (!device_may_wakeup(&pdev->dev))
161
+
regmap_write(onkey->pf1550->regmap,
162
+
PF1550_PMIC_REG_ONKEY_INT_MASK0,
163
+
~((u8)(ONKEY_IRQ_PUSHI | ONKEY_IRQ_1SI |
164
+
ONKEY_IRQ_2SI | ONKEY_IRQ_3SI | ONKEY_IRQ_4SI |
165
+
ONKEY_IRQ_8SI)));
166
+
else
167
+
for (i = 0; i < PF1550_ONKEY_IRQ_NR; i++) {
168
+
irq = platform_get_irq(pdev, i);
169
+
if (irq > 0)
170
+
disable_irq_wake(irq);
171
+
}
172
+
173
+
return 0;
174
+
}
175
+
176
+
static SIMPLE_DEV_PM_OPS(pf1550_onkey_pm_ops, pf1550_onkey_suspend,
177
+
pf1550_onkey_resume);
178
+
179
+
static const struct platform_device_id pf1550_onkey_id[] = {
180
+
{ "pf1550-onkey", },
181
+
{ /* sentinel */ }
182
+
};
183
+
MODULE_DEVICE_TABLE(platform, pf1550_onkey_id);
184
+
185
+
static struct platform_driver pf1550_onkey_driver = {
186
+
.driver = {
187
+
.name = "pf1550-onkey",
188
+
.pm = pm_sleep_ptr(&pf1550_onkey_pm_ops),
189
+
},
190
+
.probe = pf1550_onkey_probe,
191
+
.id_table = pf1550_onkey_id,
192
+
};
193
+
module_platform_driver(pf1550_onkey_driver);
194
+
195
+
MODULE_AUTHOR("Freescale Semiconductor");
196
+
MODULE_DESCRIPTION("PF1550 onkey Driver");
197
+
MODULE_LICENSE("GPL");
+16
drivers/mfd/Kconfig
+16
drivers/mfd/Kconfig
···
605
605
i.MX25 processors. They consist of a conversion queue for general
606
606
purpose ADC and a queue for Touchscreens.
607
607
608
+
config MFD_PF1550
609
+
tristate "NXP PF1550 PMIC Support"
610
+
depends on I2C=y && OF
611
+
select MFD_CORE
612
+
select REGMAP_I2C
613
+
select REGMAP_IRQ
614
+
help
615
+
Say yes here to add support for NXP PF1550. This is a companion Power
616
+
Management IC with regulators, onkey, and charger control on chip.
617
+
This driver provides common support for accessing the device;
618
+
additional drivers must be enabled in order to use the functionality
619
+
of the device.
620
+
621
+
This driver can also be built as a module and if so will be called
622
+
pf1550.
623
+
608
624
config MFD_HI6421_PMIC
609
625
tristate "HiSilicon Hi6421 PMU/Codec IC"
610
626
depends on OF
+2
drivers/mfd/Makefile
+2
drivers/mfd/Makefile
+367
drivers/mfd/pf1550.c
+367
drivers/mfd/pf1550.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Core driver for the PF1550
4
+
*
5
+
* Copyright (C) 2016 Freescale Semiconductor, Inc.
6
+
* Robin Gong <yibin.gong@freescale.com>
7
+
*
8
+
* Portions Copyright (c) 2025 Savoir-faire Linux Inc.
9
+
* Samuel Kayode <samuel.kayode@savoirfairelinux.com>
10
+
*/
11
+
12
+
#include <linux/err.h>
13
+
#include <linux/i2c.h>
14
+
#include <linux/interrupt.h>
15
+
#include <linux/mfd/core.h>
16
+
#include <linux/mfd/pf1550.h>
17
+
#include <linux/module.h>
18
+
#include <linux/of.h>
19
+
#include <linux/regmap.h>
20
+
21
+
static const struct regmap_config pf1550_regmap_config = {
22
+
.reg_bits = 8,
23
+
.val_bits = 8,
24
+
.max_register = PF1550_PMIC_REG_END,
25
+
};
26
+
27
+
static const struct regmap_irq pf1550_irqs[] = {
28
+
REGMAP_IRQ_REG(PF1550_IRQ_CHG, 0, IRQ_CHG),
29
+
REGMAP_IRQ_REG(PF1550_IRQ_REGULATOR, 0, IRQ_REGULATOR),
30
+
REGMAP_IRQ_REG(PF1550_IRQ_ONKEY, 0, IRQ_ONKEY),
31
+
};
32
+
33
+
static const struct regmap_irq_chip pf1550_irq_chip = {
34
+
.name = "pf1550",
35
+
.status_base = PF1550_PMIC_REG_INT_CATEGORY,
36
+
.init_ack_masked = 1,
37
+
.num_regs = 1,
38
+
.irqs = pf1550_irqs,
39
+
.num_irqs = ARRAY_SIZE(pf1550_irqs),
40
+
};
41
+
42
+
static const struct regmap_irq pf1550_regulator_irqs[] = {
43
+
REGMAP_IRQ_REG(PF1550_PMIC_IRQ_SW1_LS, 0, PMIC_IRQ_SW1_LS),
44
+
REGMAP_IRQ_REG(PF1550_PMIC_IRQ_SW2_LS, 0, PMIC_IRQ_SW2_LS),
45
+
REGMAP_IRQ_REG(PF1550_PMIC_IRQ_SW3_LS, 0, PMIC_IRQ_SW3_LS),
46
+
REGMAP_IRQ_REG(PF1550_PMIC_IRQ_SW1_HS, 3, PMIC_IRQ_SW1_HS),
47
+
REGMAP_IRQ_REG(PF1550_PMIC_IRQ_SW2_HS, 3, PMIC_IRQ_SW2_HS),
48
+
REGMAP_IRQ_REG(PF1550_PMIC_IRQ_SW3_HS, 3, PMIC_IRQ_SW3_HS),
49
+
REGMAP_IRQ_REG(PF1550_PMIC_IRQ_LDO1_FAULT, 16, PMIC_IRQ_LDO1_FAULT),
50
+
REGMAP_IRQ_REG(PF1550_PMIC_IRQ_LDO2_FAULT, 16, PMIC_IRQ_LDO2_FAULT),
51
+
REGMAP_IRQ_REG(PF1550_PMIC_IRQ_LDO3_FAULT, 16, PMIC_IRQ_LDO3_FAULT),
52
+
REGMAP_IRQ_REG(PF1550_PMIC_IRQ_TEMP_110, 24, PMIC_IRQ_TEMP_110),
53
+
REGMAP_IRQ_REG(PF1550_PMIC_IRQ_TEMP_125, 24, PMIC_IRQ_TEMP_125),
54
+
};
55
+
56
+
static const struct regmap_irq_chip pf1550_regulator_irq_chip = {
57
+
.name = "pf1550-regulator",
58
+
.status_base = PF1550_PMIC_REG_SW_INT_STAT0,
59
+
.ack_base = PF1550_PMIC_REG_SW_INT_STAT0,
60
+
.mask_base = PF1550_PMIC_REG_SW_INT_MASK0,
61
+
.use_ack = 1,
62
+
.init_ack_masked = 1,
63
+
.num_regs = 25,
64
+
.irqs = pf1550_regulator_irqs,
65
+
.num_irqs = ARRAY_SIZE(pf1550_regulator_irqs),
66
+
};
67
+
68
+
static const struct resource regulator_resources[] = {
69
+
DEFINE_RES_IRQ(PF1550_PMIC_IRQ_SW1_LS),
70
+
DEFINE_RES_IRQ(PF1550_PMIC_IRQ_SW2_LS),
71
+
DEFINE_RES_IRQ(PF1550_PMIC_IRQ_SW3_LS),
72
+
DEFINE_RES_IRQ(PF1550_PMIC_IRQ_SW1_HS),
73
+
DEFINE_RES_IRQ(PF1550_PMIC_IRQ_SW2_HS),
74
+
DEFINE_RES_IRQ(PF1550_PMIC_IRQ_SW3_HS),
75
+
DEFINE_RES_IRQ(PF1550_PMIC_IRQ_LDO1_FAULT),
76
+
DEFINE_RES_IRQ(PF1550_PMIC_IRQ_LDO2_FAULT),
77
+
DEFINE_RES_IRQ(PF1550_PMIC_IRQ_LDO3_FAULT),
78
+
DEFINE_RES_IRQ(PF1550_PMIC_IRQ_TEMP_110),
79
+
DEFINE_RES_IRQ(PF1550_PMIC_IRQ_TEMP_125),
80
+
};
81
+
82
+
static const struct regmap_irq pf1550_onkey_irqs[] = {
83
+
REGMAP_IRQ_REG(PF1550_ONKEY_IRQ_PUSHI, 0, ONKEY_IRQ_PUSHI),
84
+
REGMAP_IRQ_REG(PF1550_ONKEY_IRQ_1SI, 0, ONKEY_IRQ_1SI),
85
+
REGMAP_IRQ_REG(PF1550_ONKEY_IRQ_2SI, 0, ONKEY_IRQ_2SI),
86
+
REGMAP_IRQ_REG(PF1550_ONKEY_IRQ_3SI, 0, ONKEY_IRQ_3SI),
87
+
REGMAP_IRQ_REG(PF1550_ONKEY_IRQ_4SI, 0, ONKEY_IRQ_4SI),
88
+
REGMAP_IRQ_REG(PF1550_ONKEY_IRQ_8SI, 0, ONKEY_IRQ_8SI),
89
+
};
90
+
91
+
static const struct regmap_irq_chip pf1550_onkey_irq_chip = {
92
+
.name = "pf1550-onkey",
93
+
.status_base = PF1550_PMIC_REG_ONKEY_INT_STAT0,
94
+
.ack_base = PF1550_PMIC_REG_ONKEY_INT_STAT0,
95
+
.mask_base = PF1550_PMIC_REG_ONKEY_INT_MASK0,
96
+
.use_ack = 1,
97
+
.init_ack_masked = 1,
98
+
.num_regs = 1,
99
+
.irqs = pf1550_onkey_irqs,
100
+
.num_irqs = ARRAY_SIZE(pf1550_onkey_irqs),
101
+
};
102
+
103
+
static const struct resource onkey_resources[] = {
104
+
DEFINE_RES_IRQ(PF1550_ONKEY_IRQ_PUSHI),
105
+
DEFINE_RES_IRQ(PF1550_ONKEY_IRQ_1SI),
106
+
DEFINE_RES_IRQ(PF1550_ONKEY_IRQ_2SI),
107
+
DEFINE_RES_IRQ(PF1550_ONKEY_IRQ_3SI),
108
+
DEFINE_RES_IRQ(PF1550_ONKEY_IRQ_4SI),
109
+
DEFINE_RES_IRQ(PF1550_ONKEY_IRQ_8SI),
110
+
};
111
+
112
+
static const struct regmap_irq pf1550_charger_irqs[] = {
113
+
REGMAP_IRQ_REG(PF1550_CHARG_IRQ_BAT2SOCI, 0, CHARG_IRQ_BAT2SOCI),
114
+
REGMAP_IRQ_REG(PF1550_CHARG_IRQ_BATI, 0, CHARG_IRQ_BATI),
115
+
REGMAP_IRQ_REG(PF1550_CHARG_IRQ_CHGI, 0, CHARG_IRQ_CHGI),
116
+
REGMAP_IRQ_REG(PF1550_CHARG_IRQ_VBUSI, 0, CHARG_IRQ_VBUSI),
117
+
REGMAP_IRQ_REG(PF1550_CHARG_IRQ_THMI, 0, CHARG_IRQ_THMI),
118
+
};
119
+
120
+
static const struct regmap_irq_chip pf1550_charger_irq_chip = {
121
+
.name = "pf1550-charger",
122
+
.status_base = PF1550_CHARG_REG_CHG_INT,
123
+
.ack_base = PF1550_CHARG_REG_CHG_INT,
124
+
.mask_base = PF1550_CHARG_REG_CHG_INT_MASK,
125
+
.use_ack = 1,
126
+
.init_ack_masked = 1,
127
+
.num_regs = 1,
128
+
.irqs = pf1550_charger_irqs,
129
+
.num_irqs = ARRAY_SIZE(pf1550_charger_irqs),
130
+
};
131
+
132
+
static const struct resource charger_resources[] = {
133
+
DEFINE_RES_IRQ(PF1550_CHARG_IRQ_BAT2SOCI),
134
+
DEFINE_RES_IRQ(PF1550_CHARG_IRQ_BATI),
135
+
DEFINE_RES_IRQ(PF1550_CHARG_IRQ_CHGI),
136
+
DEFINE_RES_IRQ(PF1550_CHARG_IRQ_VBUSI),
137
+
DEFINE_RES_IRQ(PF1550_CHARG_IRQ_THMI),
138
+
};
139
+
140
+
static const struct mfd_cell pf1550_regulator_cell = {
141
+
.name = "pf1550-regulator",
142
+
.num_resources = ARRAY_SIZE(regulator_resources),
143
+
.resources = regulator_resources,
144
+
};
145
+
146
+
static const struct mfd_cell pf1550_onkey_cell = {
147
+
.name = "pf1550-onkey",
148
+
.num_resources = ARRAY_SIZE(onkey_resources),
149
+
.resources = onkey_resources,
150
+
};
151
+
152
+
static const struct mfd_cell pf1550_charger_cell = {
153
+
.name = "pf1550-charger",
154
+
.num_resources = ARRAY_SIZE(charger_resources),
155
+
.resources = charger_resources,
156
+
};
157
+
158
+
/*
159
+
* The PF1550 is shipped in variants of A0, A1,...A9. Each variant defines a
160
+
* configuration of the PMIC in a One-Time Programmable (OTP) memory.
161
+
* This memory is accessed indirectly by writing valid keys to specific
162
+
* registers of the PMIC. To read the OTP memory after writing the valid keys,
163
+
* the OTP register address to be read is written to pf1550 register 0xc4 and
164
+
* its value read from pf1550 register 0xc5.
165
+
*/
166
+
static int pf1550_read_otp(const struct pf1550_ddata *pf1550, unsigned int index,
167
+
unsigned int *val)
168
+
{
169
+
int ret = 0;
170
+
171
+
ret = regmap_write(pf1550->regmap, PF1550_PMIC_REG_KEY, PF1550_OTP_PMIC_KEY);
172
+
if (ret)
173
+
goto read_err;
174
+
175
+
ret = regmap_write(pf1550->regmap, PF1550_CHARG_REG_CHGR_KEY2, PF1550_OTP_CHGR_KEY);
176
+
if (ret)
177
+
goto read_err;
178
+
179
+
ret = regmap_write(pf1550->regmap, PF1550_TEST_REG_KEY3, PF1550_OTP_TEST_KEY);
180
+
if (ret)
181
+
goto read_err;
182
+
183
+
ret = regmap_write(pf1550->regmap, PF1550_TEST_REG_FMRADDR, index);
184
+
if (ret)
185
+
goto read_err;
186
+
187
+
ret = regmap_read(pf1550->regmap, PF1550_TEST_REG_FMRDATA, val);
188
+
if (ret)
189
+
goto read_err;
190
+
191
+
return 0;
192
+
193
+
read_err:
194
+
return dev_err_probe(pf1550->dev, ret, "OTP reg %x not found!\n", index);
195
+
}
196
+
197
+
static int pf1550_i2c_probe(struct i2c_client *i2c)
198
+
{
199
+
const struct mfd_cell *regulator = &pf1550_regulator_cell;
200
+
const struct mfd_cell *charger = &pf1550_charger_cell;
201
+
const struct mfd_cell *onkey = &pf1550_onkey_cell;
202
+
unsigned int reg_data = 0, otp_data = 0;
203
+
struct pf1550_ddata *pf1550;
204
+
struct irq_domain *domain;
205
+
int irq, ret = 0;
206
+
207
+
pf1550 = devm_kzalloc(&i2c->dev, sizeof(*pf1550), GFP_KERNEL);
208
+
if (!pf1550)
209
+
return -ENOMEM;
210
+
211
+
i2c_set_clientdata(i2c, pf1550);
212
+
pf1550->dev = &i2c->dev;
213
+
pf1550->irq = i2c->irq;
214
+
215
+
pf1550->regmap = devm_regmap_init_i2c(i2c, &pf1550_regmap_config);
216
+
if (IS_ERR(pf1550->regmap))
217
+
return dev_err_probe(pf1550->dev, PTR_ERR(pf1550->regmap),
218
+
"failed to allocate register map\n");
219
+
220
+
ret = regmap_read(pf1550->regmap, PF1550_PMIC_REG_DEVICE_ID, ®_data);
221
+
if (ret < 0)
222
+
return dev_err_probe(pf1550->dev, ret, "cannot read chip ID\n");
223
+
if (reg_data != PF1550_DEVICE_ID)
224
+
return dev_err_probe(pf1550->dev, -ENODEV, "invalid device ID: 0x%02x\n", reg_data);
225
+
226
+
/* Regulator DVS for SW2 */
227
+
ret = pf1550_read_otp(pf1550, PF1550_OTP_SW2_SW3, &otp_data);
228
+
if (ret)
229
+
return ret;
230
+
231
+
/* When clear, DVS should be enabled */
232
+
if (!(otp_data & OTP_SW2_DVS_ENB))
233
+
pf1550->dvs2_enable = true;
234
+
235
+
/* Regulator DVS for SW1 */
236
+
ret = pf1550_read_otp(pf1550, PF1550_OTP_SW1_SW2, &otp_data);
237
+
if (ret)
238
+
return ret;
239
+
240
+
if (!(otp_data & OTP_SW1_DVS_ENB))
241
+
pf1550->dvs1_enable = true;
242
+
243
+
/* Add top level interrupts */
244
+
ret = devm_regmap_add_irq_chip(pf1550->dev, pf1550->regmap, pf1550->irq,
245
+
IRQF_ONESHOT | IRQF_SHARED |
246
+
IRQF_TRIGGER_FALLING,
247
+
0, &pf1550_irq_chip,
248
+
&pf1550->irq_data);
249
+
if (ret)
250
+
return ret;
251
+
252
+
/* Add regulator */
253
+
irq = regmap_irq_get_virq(pf1550->irq_data, PF1550_IRQ_REGULATOR);
254
+
if (irq < 0)
255
+
return dev_err_probe(pf1550->dev, irq,
256
+
"Failed to get parent vIRQ(%d) for chip %s\n",
257
+
PF1550_IRQ_REGULATOR, pf1550_irq_chip.name);
258
+
259
+
ret = devm_regmap_add_irq_chip(pf1550->dev, pf1550->regmap, irq,
260
+
IRQF_ONESHOT | IRQF_SHARED |
261
+
IRQF_TRIGGER_FALLING, 0,
262
+
&pf1550_regulator_irq_chip,
263
+
&pf1550->irq_data_regulator);
264
+
if (ret)
265
+
return dev_err_probe(pf1550->dev, ret, "Failed to add %s IRQ chip\n",
266
+
pf1550_regulator_irq_chip.name);
267
+
268
+
domain = regmap_irq_get_domain(pf1550->irq_data_regulator);
269
+
270
+
ret = devm_mfd_add_devices(pf1550->dev, PLATFORM_DEVID_NONE, regulator, 1, NULL, 0, domain);
271
+
if (ret)
272
+
return ret;
273
+
274
+
/* Add onkey */
275
+
irq = regmap_irq_get_virq(pf1550->irq_data, PF1550_IRQ_ONKEY);
276
+
if (irq < 0)
277
+
return dev_err_probe(pf1550->dev, irq,
278
+
"Failed to get parent vIRQ(%d) for chip %s\n",
279
+
PF1550_IRQ_ONKEY, pf1550_irq_chip.name);
280
+
281
+
ret = devm_regmap_add_irq_chip(pf1550->dev, pf1550->regmap, irq,
282
+
IRQF_ONESHOT | IRQF_SHARED |
283
+
IRQF_TRIGGER_FALLING, 0,
284
+
&pf1550_onkey_irq_chip,
285
+
&pf1550->irq_data_onkey);
286
+
if (ret)
287
+
return dev_err_probe(pf1550->dev, ret, "Failed to add %s IRQ chip\n",
288
+
pf1550_onkey_irq_chip.name);
289
+
290
+
domain = regmap_irq_get_domain(pf1550->irq_data_onkey);
291
+
292
+
ret = devm_mfd_add_devices(pf1550->dev, PLATFORM_DEVID_NONE, onkey, 1, NULL, 0, domain);
293
+
if (ret)
294
+
return ret;
295
+
296
+
/* Add battery charger */
297
+
irq = regmap_irq_get_virq(pf1550->irq_data, PF1550_IRQ_CHG);
298
+
if (irq < 0)
299
+
return dev_err_probe(pf1550->dev, irq,
300
+
"Failed to get parent vIRQ(%d) for chip %s\n",
301
+
PF1550_IRQ_CHG, pf1550_irq_chip.name);
302
+
303
+
ret = devm_regmap_add_irq_chip(pf1550->dev, pf1550->regmap, irq,
304
+
IRQF_ONESHOT | IRQF_SHARED |
305
+
IRQF_TRIGGER_FALLING, 0,
306
+
&pf1550_charger_irq_chip,
307
+
&pf1550->irq_data_charger);
308
+
if (ret)
309
+
return dev_err_probe(pf1550->dev, ret, "Failed to add %s IRQ chip\n",
310
+
pf1550_charger_irq_chip.name);
311
+
312
+
domain = regmap_irq_get_domain(pf1550->irq_data_charger);
313
+
314
+
return devm_mfd_add_devices(pf1550->dev, PLATFORM_DEVID_NONE, charger, 1, NULL, 0, domain);
315
+
}
316
+
317
+
static int pf1550_suspend(struct device *dev)
318
+
{
319
+
struct pf1550_ddata *pf1550 = dev_get_drvdata(dev);
320
+
321
+
if (device_may_wakeup(dev)) {
322
+
enable_irq_wake(pf1550->irq);
323
+
disable_irq(pf1550->irq);
324
+
}
325
+
326
+
return 0;
327
+
}
328
+
329
+
static int pf1550_resume(struct device *dev)
330
+
{
331
+
struct pf1550_ddata *pf1550 = dev_get_drvdata(dev);
332
+
333
+
if (device_may_wakeup(dev)) {
334
+
disable_irq_wake(pf1550->irq);
335
+
enable_irq(pf1550->irq);
336
+
}
337
+
338
+
return 0;
339
+
}
340
+
static DEFINE_SIMPLE_DEV_PM_OPS(pf1550_pm, pf1550_suspend, pf1550_resume);
341
+
342
+
static const struct i2c_device_id pf1550_i2c_id[] = {
343
+
{ "pf1550" },
344
+
{ /* sentinel */ }
345
+
};
346
+
MODULE_DEVICE_TABLE(i2c, pf1550_i2c_id);
347
+
348
+
static const struct of_device_id pf1550_dt_match[] = {
349
+
{ .compatible = "nxp,pf1550" },
350
+
{ /* sentinel */ }
351
+
};
352
+
MODULE_DEVICE_TABLE(of, pf1550_dt_match);
353
+
354
+
static struct i2c_driver pf1550_i2c_driver = {
355
+
.driver = {
356
+
.name = "pf1550",
357
+
.pm = pm_sleep_ptr(&pf1550_pm),
358
+
.of_match_table = pf1550_dt_match,
359
+
},
360
+
.probe = pf1550_i2c_probe,
361
+
.id_table = pf1550_i2c_id,
362
+
};
363
+
module_i2c_driver(pf1550_i2c_driver);
364
+
365
+
MODULE_DESCRIPTION("NXP PF1550 core driver");
366
+
MODULE_AUTHOR("Robin Gong <yibin.gong@freescale.com>");
367
+
MODULE_LICENSE("GPL");
+11
drivers/power/supply/Kconfig
+11
drivers/power/supply/Kconfig
···
486
486
help
487
487
Say Y here to enable charger for Marvell 88PM860x chip.
488
488
489
+
config CHARGER_PF1550
490
+
tristate "NXP PF1550 battery charger driver"
491
+
depends on MFD_PF1550
492
+
help
493
+
Say Y to enable support for the NXP PF1550 battery charger.
494
+
The device is a single cell Li-Ion/Li-Polymer battery charger for
495
+
portable application.
496
+
497
+
This driver can also be built as a module. If so, the module will be
498
+
called pf1550-charger.
499
+
489
500
config BATTERY_RX51
490
501
tristate "Nokia RX-51 (N900) battery driver"
491
502
depends on TWL4030_MADC
+1
drivers/power/supply/Makefile
+1
drivers/power/supply/Makefile
···
66
66
obj-$(CONFIG_CHARGER_RT9471) += rt9471.o
67
67
obj-$(CONFIG_BATTERY_TWL4030_MADC) += twl4030_madc_battery.o
68
68
obj-$(CONFIG_CHARGER_88PM860X) += 88pm860x_charger.o
69
+
obj-$(CONFIG_CHARGER_PF1550) += pf1550-charger.o
69
70
obj-$(CONFIG_BATTERY_RX51) += rx51_battery.o
70
71
obj-$(CONFIG_AB8500_BM) += ab8500_bmdata.o ab8500_charger.o ab8500_fg.o ab8500_btemp.o ab8500_chargalg.o
71
72
obj-$(CONFIG_CHARGER_CPCAP) += cpcap-charger.o
+641
drivers/power/supply/pf1550-charger.c
+641
drivers/power/supply/pf1550-charger.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* charger driver for the PF1550
4
+
*
5
+
* Copyright (C) 2016 Freescale Semiconductor, Inc.
6
+
* Robin Gong <yibin.gong@freescale.com>
7
+
*
8
+
* Portions Copyright (c) 2025 Savoir-faire Linux Inc.
9
+
* Samuel Kayode <samuel.kayode@savoirfairelinux.com>
10
+
*/
11
+
12
+
#include <linux/devm-helpers.h>
13
+
#include <linux/interrupt.h>
14
+
#include <linux/mfd/pf1550.h>
15
+
#include <linux/module.h>
16
+
#include <linux/platform_device.h>
17
+
#include <linux/power_supply.h>
18
+
19
+
#define PF1550_DEFAULT_CONSTANT_VOLT 4200000
20
+
#define PF1550_DEFAULT_MIN_SYSTEM_VOLT 3500000
21
+
#define PF1550_DEFAULT_THERMAL_TEMP 95
22
+
#define PF1550_CHARGER_IRQ_NR 5
23
+
24
+
struct pf1550_charger {
25
+
struct device *dev;
26
+
const struct pf1550_ddata *pf1550;
27
+
struct power_supply *charger;
28
+
struct power_supply *battery;
29
+
struct delayed_work vbus_sense_work;
30
+
struct delayed_work chg_sense_work;
31
+
struct delayed_work bat_sense_work;
32
+
int virqs[PF1550_CHARGER_IRQ_NR];
33
+
34
+
u32 constant_volt;
35
+
u32 min_system_volt;
36
+
u32 thermal_regulation_temp;
37
+
};
38
+
39
+
static int pf1550_get_charger_state(struct regmap *regmap, int *val)
40
+
{
41
+
unsigned int data;
42
+
int ret;
43
+
44
+
ret = regmap_read(regmap, PF1550_CHARG_REG_CHG_SNS, &data);
45
+
if (ret < 0)
46
+
return ret;
47
+
48
+
data &= PF1550_CHG_SNS_MASK;
49
+
50
+
switch (data) {
51
+
case PF1550_CHG_PRECHARGE:
52
+
case PF1550_CHG_CONSTANT_CURRENT:
53
+
case PF1550_CHG_CONSTANT_VOL:
54
+
case PF1550_CHG_EOC:
55
+
*val = POWER_SUPPLY_STATUS_CHARGING;
56
+
break;
57
+
case PF1550_CHG_DONE:
58
+
*val = POWER_SUPPLY_STATUS_FULL;
59
+
break;
60
+
case PF1550_CHG_TIMER_FAULT:
61
+
case PF1550_CHG_SUSPEND:
62
+
*val = POWER_SUPPLY_STATUS_NOT_CHARGING;
63
+
break;
64
+
case PF1550_CHG_OFF_INV:
65
+
case PF1550_CHG_OFF_TEMP:
66
+
case PF1550_CHG_LINEAR_ONLY:
67
+
*val = POWER_SUPPLY_STATUS_DISCHARGING;
68
+
break;
69
+
default:
70
+
*val = POWER_SUPPLY_STATUS_UNKNOWN;
71
+
}
72
+
73
+
return 0;
74
+
}
75
+
76
+
static int pf1550_get_charge_type(struct regmap *regmap, int *val)
77
+
{
78
+
unsigned int data;
79
+
int ret;
80
+
81
+
ret = regmap_read(regmap, PF1550_CHARG_REG_CHG_SNS, &data);
82
+
if (ret < 0)
83
+
return ret;
84
+
85
+
data &= PF1550_CHG_SNS_MASK;
86
+
87
+
switch (data) {
88
+
case PF1550_CHG_SNS_MASK:
89
+
*val = POWER_SUPPLY_CHARGE_TYPE_TRICKLE;
90
+
break;
91
+
case PF1550_CHG_CONSTANT_CURRENT:
92
+
case PF1550_CHG_CONSTANT_VOL:
93
+
case PF1550_CHG_EOC:
94
+
*val = POWER_SUPPLY_CHARGE_TYPE_FAST;
95
+
break;
96
+
case PF1550_CHG_DONE:
97
+
case PF1550_CHG_TIMER_FAULT:
98
+
case PF1550_CHG_SUSPEND:
99
+
case PF1550_CHG_OFF_INV:
100
+
case PF1550_CHG_BAT_OVER:
101
+
case PF1550_CHG_OFF_TEMP:
102
+
case PF1550_CHG_LINEAR_ONLY:
103
+
*val = POWER_SUPPLY_CHARGE_TYPE_NONE;
104
+
break;
105
+
default:
106
+
*val = POWER_SUPPLY_CHARGE_TYPE_UNKNOWN;
107
+
}
108
+
109
+
return 0;
110
+
}
111
+
112
+
/*
113
+
* Supported health statuses:
114
+
* - POWER_SUPPLY_HEALTH_DEAD
115
+
* - POWER_SUPPLY_HEALTH_GOOD
116
+
* - POWER_SUPPLY_HEALTH_OVERVOLTAGE
117
+
* - POWER_SUPPLY_HEALTH_UNKNOWN
118
+
*/
119
+
static int pf1550_get_battery_health(struct regmap *regmap, int *val)
120
+
{
121
+
unsigned int data;
122
+
int ret;
123
+
124
+
ret = regmap_read(regmap, PF1550_CHARG_REG_BATT_SNS, &data);
125
+
if (ret < 0)
126
+
return ret;
127
+
128
+
data &= PF1550_BAT_SNS_MASK;
129
+
130
+
switch (data) {
131
+
case PF1550_BAT_NO_DETECT:
132
+
*val = POWER_SUPPLY_HEALTH_NO_BATTERY;
133
+
break;
134
+
case PF1550_BAT_NO_VBUS:
135
+
case PF1550_BAT_LOW_THAN_PRECHARG:
136
+
case PF1550_BAT_CHARG_FAIL:
137
+
case PF1550_BAT_HIGH_THAN_PRECHARG:
138
+
*val = POWER_SUPPLY_HEALTH_GOOD;
139
+
break;
140
+
case PF1550_BAT_OVER_VOL:
141
+
*val = POWER_SUPPLY_HEALTH_OVERVOLTAGE;
142
+
break;
143
+
default:
144
+
*val = POWER_SUPPLY_HEALTH_UNKNOWN;
145
+
break;
146
+
}
147
+
148
+
return 0;
149
+
}
150
+
151
+
static int pf1550_get_present(struct regmap *regmap, int *val)
152
+
{
153
+
unsigned int data;
154
+
int ret;
155
+
156
+
ret = regmap_read(regmap, PF1550_CHARG_REG_BATT_SNS, &data);
157
+
if (ret < 0)
158
+
return ret;
159
+
160
+
data &= PF1550_BAT_SNS_MASK;
161
+
*val = (data == PF1550_BAT_NO_DETECT) ? 0 : 1;
162
+
163
+
return 0;
164
+
}
165
+
166
+
static int pf1550_get_online(struct regmap *regmap, int *val)
167
+
{
168
+
unsigned int data;
169
+
int ret;
170
+
171
+
ret = regmap_read(regmap, PF1550_CHARG_REG_VBUS_SNS, &data);
172
+
if (ret < 0)
173
+
return ret;
174
+
175
+
*val = (data & PF1550_VBUS_VALID) ? 1 : 0;
176
+
177
+
return 0;
178
+
}
179
+
180
+
static void pf1550_chg_bat_work(struct work_struct *work)
181
+
{
182
+
struct pf1550_charger *chg = container_of(to_delayed_work(work),
183
+
struct pf1550_charger,
184
+
bat_sense_work);
185
+
unsigned int data;
186
+
187
+
if (regmap_read(chg->pf1550->regmap, PF1550_CHARG_REG_BATT_SNS, &data)) {
188
+
dev_err(chg->dev, "Read BATT_SNS error.\n");
189
+
return;
190
+
}
191
+
192
+
switch (data & PF1550_BAT_SNS_MASK) {
193
+
case PF1550_BAT_NO_VBUS:
194
+
dev_dbg(chg->dev, "No valid VBUS input.\n");
195
+
break;
196
+
case PF1550_BAT_LOW_THAN_PRECHARG:
197
+
dev_dbg(chg->dev, "VBAT < VPRECHG.LB.\n");
198
+
break;
199
+
case PF1550_BAT_CHARG_FAIL:
200
+
dev_dbg(chg->dev, "Battery charging failed.\n");
201
+
break;
202
+
case PF1550_BAT_HIGH_THAN_PRECHARG:
203
+
dev_dbg(chg->dev, "VBAT > VPRECHG.LB.\n");
204
+
break;
205
+
case PF1550_BAT_OVER_VOL:
206
+
dev_dbg(chg->dev, "VBAT > VBATOV.\n");
207
+
break;
208
+
case PF1550_BAT_NO_DETECT:
209
+
dev_dbg(chg->dev, "Battery not detected.\n");
210
+
break;
211
+
default:
212
+
dev_err(chg->dev, "Unknown value read:%x\n",
213
+
data & PF1550_CHG_SNS_MASK);
214
+
}
215
+
}
216
+
217
+
static void pf1550_chg_chg_work(struct work_struct *work)
218
+
{
219
+
struct pf1550_charger *chg = container_of(to_delayed_work(work),
220
+
struct pf1550_charger,
221
+
chg_sense_work);
222
+
unsigned int data;
223
+
224
+
if (regmap_read(chg->pf1550->regmap, PF1550_CHARG_REG_CHG_SNS, &data)) {
225
+
dev_err(chg->dev, "Read CHG_SNS error.\n");
226
+
return;
227
+
}
228
+
229
+
switch (data & PF1550_CHG_SNS_MASK) {
230
+
case PF1550_CHG_PRECHARGE:
231
+
dev_dbg(chg->dev, "In pre-charger mode.\n");
232
+
break;
233
+
case PF1550_CHG_CONSTANT_CURRENT:
234
+
dev_dbg(chg->dev, "In fast-charge constant current mode.\n");
235
+
break;
236
+
case PF1550_CHG_CONSTANT_VOL:
237
+
dev_dbg(chg->dev, "In fast-charge constant voltage mode.\n");
238
+
break;
239
+
case PF1550_CHG_EOC:
240
+
dev_dbg(chg->dev, "In EOC mode.\n");
241
+
break;
242
+
case PF1550_CHG_DONE:
243
+
dev_dbg(chg->dev, "In DONE mode.\n");
244
+
break;
245
+
case PF1550_CHG_TIMER_FAULT:
246
+
dev_info(chg->dev, "In timer fault mode.\n");
247
+
break;
248
+
case PF1550_CHG_SUSPEND:
249
+
dev_info(chg->dev, "In thermistor suspend mode.\n");
250
+
break;
251
+
case PF1550_CHG_OFF_INV:
252
+
dev_info(chg->dev, "Input invalid, charger off.\n");
253
+
break;
254
+
case PF1550_CHG_BAT_OVER:
255
+
dev_warn(chg->dev, "Battery over-voltage.\n");
256
+
break;
257
+
case PF1550_CHG_OFF_TEMP:
258
+
dev_info(chg->dev, "Temp high, charger off.\n");
259
+
break;
260
+
case PF1550_CHG_LINEAR_ONLY:
261
+
dev_dbg(chg->dev, "In Linear mode, not charging.\n");
262
+
break;
263
+
default:
264
+
dev_err(chg->dev, "Unknown value read:%x\n",
265
+
data & PF1550_CHG_SNS_MASK);
266
+
}
267
+
}
268
+
269
+
static void pf1550_chg_vbus_work(struct work_struct *work)
270
+
{
271
+
struct pf1550_charger *chg = container_of(to_delayed_work(work),
272
+
struct pf1550_charger,
273
+
vbus_sense_work);
274
+
unsigned int data;
275
+
276
+
if (regmap_read(chg->pf1550->regmap, PF1550_CHARG_REG_VBUS_SNS, &data)) {
277
+
dev_err(chg->dev, "Read VBUS_SNS error.\n");
278
+
return;
279
+
}
280
+
281
+
if (data & PF1550_VBUS_UVLO) {
282
+
dev_dbg(chg->dev, "VBUS detached.\n");
283
+
power_supply_changed(chg->battery);
284
+
}
285
+
if (data & PF1550_VBUS_IN2SYS)
286
+
dev_dbg(chg->dev, "VBUS_IN2SYS_SNS.\n");
287
+
if (data & PF1550_VBUS_OVLO)
288
+
dev_dbg(chg->dev, "VBUS_OVLO_SNS.\n");
289
+
if (data & PF1550_VBUS_VALID) {
290
+
dev_dbg(chg->dev, "VBUS attached.\n");
291
+
power_supply_changed(chg->charger);
292
+
}
293
+
}
294
+
295
+
static irqreturn_t pf1550_charger_irq_handler(int irq, void *data)
296
+
{
297
+
struct pf1550_charger *chg = data;
298
+
struct device *dev = chg->dev;
299
+
int i, irq_type = -1;
300
+
301
+
for (i = 0; i < PF1550_CHARGER_IRQ_NR; i++)
302
+
if (irq == chg->virqs[i])
303
+
irq_type = i;
304
+
305
+
switch (irq_type) {
306
+
case PF1550_CHARG_IRQ_BAT2SOCI:
307
+
dev_info(dev, "BAT to SYS Overcurrent interrupt.\n");
308
+
break;
309
+
case PF1550_CHARG_IRQ_BATI:
310
+
schedule_delayed_work(&chg->bat_sense_work,
311
+
msecs_to_jiffies(10));
312
+
break;
313
+
case PF1550_CHARG_IRQ_CHGI:
314
+
schedule_delayed_work(&chg->chg_sense_work,
315
+
msecs_to_jiffies(10));
316
+
break;
317
+
case PF1550_CHARG_IRQ_VBUSI:
318
+
schedule_delayed_work(&chg->vbus_sense_work,
319
+
msecs_to_jiffies(10));
320
+
break;
321
+
case PF1550_CHARG_IRQ_THMI:
322
+
dev_info(dev, "Thermal interrupt.\n");
323
+
break;
324
+
default:
325
+
dev_err(dev, "unknown interrupt occurred.\n");
326
+
}
327
+
328
+
return IRQ_HANDLED;
329
+
}
330
+
331
+
static enum power_supply_property pf1550_charger_props[] = {
332
+
POWER_SUPPLY_PROP_ONLINE,
333
+
POWER_SUPPLY_PROP_MODEL_NAME,
334
+
POWER_SUPPLY_PROP_MANUFACTURER,
335
+
};
336
+
337
+
static enum power_supply_property pf1550_battery_props[] = {
338
+
POWER_SUPPLY_PROP_STATUS,
339
+
POWER_SUPPLY_PROP_CHARGE_TYPE,
340
+
POWER_SUPPLY_PROP_HEALTH,
341
+
POWER_SUPPLY_PROP_PRESENT,
342
+
POWER_SUPPLY_PROP_MODEL_NAME,
343
+
POWER_SUPPLY_PROP_MANUFACTURER,
344
+
};
345
+
346
+
static int pf1550_charger_get_property(struct power_supply *psy,
347
+
enum power_supply_property psp,
348
+
union power_supply_propval *val)
349
+
{
350
+
struct pf1550_charger *chg = power_supply_get_drvdata(psy);
351
+
struct regmap *regmap = chg->pf1550->regmap;
352
+
int ret = 0;
353
+
354
+
switch (psp) {
355
+
case POWER_SUPPLY_PROP_STATUS:
356
+
ret = pf1550_get_charger_state(regmap, &val->intval);
357
+
break;
358
+
case POWER_SUPPLY_PROP_CHARGE_TYPE:
359
+
ret = pf1550_get_charge_type(regmap, &val->intval);
360
+
break;
361
+
case POWER_SUPPLY_PROP_HEALTH:
362
+
ret = pf1550_get_battery_health(regmap, &val->intval);
363
+
break;
364
+
case POWER_SUPPLY_PROP_PRESENT:
365
+
ret = pf1550_get_present(regmap, &val->intval);
366
+
break;
367
+
case POWER_SUPPLY_PROP_ONLINE:
368
+
ret = pf1550_get_online(regmap, &val->intval);
369
+
break;
370
+
case POWER_SUPPLY_PROP_MODEL_NAME:
371
+
val->strval = "PF1550";
372
+
break;
373
+
case POWER_SUPPLY_PROP_MANUFACTURER:
374
+
val->strval = "NXP";
375
+
break;
376
+
default:
377
+
return -EINVAL;
378
+
}
379
+
380
+
return ret;
381
+
}
382
+
383
+
static const struct power_supply_desc pf1550_charger_desc = {
384
+
.name = "pf1550-charger",
385
+
.type = POWER_SUPPLY_TYPE_MAINS,
386
+
.properties = pf1550_charger_props,
387
+
.num_properties = ARRAY_SIZE(pf1550_charger_props),
388
+
.get_property = pf1550_charger_get_property,
389
+
};
390
+
391
+
static const struct power_supply_desc pf1550_battery_desc = {
392
+
.name = "pf1550-battery",
393
+
.type = POWER_SUPPLY_TYPE_BATTERY,
394
+
.properties = pf1550_battery_props,
395
+
.num_properties = ARRAY_SIZE(pf1550_battery_props),
396
+
.get_property = pf1550_charger_get_property,
397
+
};
398
+
399
+
static int pf1550_set_constant_volt(struct pf1550_charger *chg,
400
+
unsigned int uvolt)
401
+
{
402
+
unsigned int data;
403
+
404
+
if (uvolt >= 3500000 && uvolt <= 4440000)
405
+
data = 8 + (uvolt - 3500000) / 20000;
406
+
else
407
+
return dev_err_probe(chg->dev, -EINVAL,
408
+
"Wrong value for constant voltage\n");
409
+
410
+
dev_dbg(chg->dev, "Charging constant voltage: %u (0x%x)\n", uvolt,
411
+
data);
412
+
413
+
return regmap_update_bits(chg->pf1550->regmap,
414
+
PF1550_CHARG_REG_BATT_REG,
415
+
PF1550_CHARG_REG_BATT_REG_CHGCV_MASK, data);
416
+
}
417
+
418
+
static int pf1550_set_min_system_volt(struct pf1550_charger *chg,
419
+
unsigned int uvolt)
420
+
{
421
+
unsigned int data;
422
+
423
+
switch (uvolt) {
424
+
case 3500000:
425
+
data = 0x0;
426
+
break;
427
+
case 3700000:
428
+
data = 0x1;
429
+
break;
430
+
case 4300000:
431
+
data = 0x2;
432
+
break;
433
+
default:
434
+
return dev_err_probe(chg->dev, -EINVAL,
435
+
"Wrong value for minimum system voltage\n");
436
+
}
437
+
438
+
data <<= PF1550_CHARG_REG_BATT_REG_VMINSYS_SHIFT;
439
+
440
+
dev_dbg(chg->dev, "Minimum system regulation voltage: %u (0x%x)\n",
441
+
uvolt, data);
442
+
443
+
return regmap_update_bits(chg->pf1550->regmap,
444
+
PF1550_CHARG_REG_BATT_REG,
445
+
PF1550_CHARG_REG_BATT_REG_VMINSYS_MASK, data);
446
+
}
447
+
448
+
static int pf1550_set_thermal_regulation_temp(struct pf1550_charger *chg,
449
+
unsigned int cells)
450
+
{
451
+
unsigned int data;
452
+
453
+
switch (cells) {
454
+
case 80:
455
+
data = 0x0;
456
+
break;
457
+
case 95:
458
+
data = 0x1;
459
+
break;
460
+
case 110:
461
+
data = 0x2;
462
+
break;
463
+
case 125:
464
+
data = 0x3;
465
+
break;
466
+
default:
467
+
return dev_err_probe(chg->dev, -EINVAL,
468
+
"Wrong value for thermal temperature\n");
469
+
}
470
+
471
+
data <<= PF1550_CHARG_REG_THM_REG_CNFG_REGTEMP_SHIFT;
472
+
473
+
dev_dbg(chg->dev, "Thermal regulation loop temperature: %u (0x%x)\n",
474
+
cells, data);
475
+
476
+
return regmap_update_bits(chg->pf1550->regmap,
477
+
PF1550_CHARG_REG_THM_REG_CNFG,
478
+
PF1550_CHARG_REG_THM_REG_CNFG_REGTEMP_MASK,
479
+
data);
480
+
}
481
+
482
+
/*
483
+
* Sets charger registers to proper and safe default values.
484
+
*/
485
+
static int pf1550_reg_init(struct pf1550_charger *chg)
486
+
{
487
+
struct power_supply_battery_info *info;
488
+
struct device *dev = chg->dev;
489
+
int ret;
490
+
491
+
/* Unmask charger interrupt, mask DPMI and reserved bit */
492
+
ret = regmap_write(chg->pf1550->regmap, PF1550_CHARG_REG_CHG_INT_MASK,
493
+
PF1550_CHG_INT_MASK);
494
+
if (ret)
495
+
return dev_err_probe(dev, ret,
496
+
"Error unmask charger interrupt\n");
497
+
498
+
ret = pf1550_set_constant_volt(chg, chg->constant_volt);
499
+
if (ret)
500
+
return ret;
501
+
502
+
ret = pf1550_set_min_system_volt(chg, chg->min_system_volt);
503
+
if (ret)
504
+
return ret;
505
+
506
+
ret = pf1550_set_thermal_regulation_temp(chg,
507
+
chg->thermal_regulation_temp);
508
+
if (ret)
509
+
return ret;
510
+
511
+
/*
512
+
* The PF1550 charger has 3 modes of operation. By default, the charger
513
+
* is in mode 1; it remains off. Appropriate for applications not using
514
+
* a battery. The other supported mode is mode 2, the charger is turned
515
+
* on to charge a battery when present.
516
+
*/
517
+
if (power_supply_get_battery_info(chg->charger, &info)) {
518
+
ret = regmap_write(chg->pf1550->regmap,
519
+
PF1550_CHARG_REG_CHG_OPER,
520
+
PF1550_CHG_BAT_ON);
521
+
if (ret)
522
+
return dev_err_probe(dev, ret,
523
+
"Error turn on charger\n");
524
+
}
525
+
526
+
return 0;
527
+
}
528
+
529
+
static void pf1550_dt_parse_dev_info(struct pf1550_charger *chg)
530
+
{
531
+
struct power_supply_battery_info *info;
532
+
struct device *dev = chg->dev;
533
+
534
+
if (device_property_read_u32(dev->parent, "nxp,min-system-microvolt",
535
+
&chg->min_system_volt))
536
+
chg->min_system_volt = PF1550_DEFAULT_MIN_SYSTEM_VOLT;
537
+
538
+
if (device_property_read_u32(dev->parent,
539
+
"nxp,thermal-regulation-celsius",
540
+
&chg->thermal_regulation_temp))
541
+
chg->thermal_regulation_temp = PF1550_DEFAULT_THERMAL_TEMP;
542
+
543
+
if (power_supply_get_battery_info(chg->charger, &info))
544
+
chg->constant_volt = PF1550_DEFAULT_CONSTANT_VOLT;
545
+
else
546
+
chg->constant_volt = info->constant_charge_voltage_max_uv;
547
+
}
548
+
549
+
static int pf1550_charger_probe(struct platform_device *pdev)
550
+
{
551
+
const struct pf1550_ddata *pf1550 = dev_get_drvdata(pdev->dev.parent);
552
+
struct power_supply_config psy_cfg = {};
553
+
struct pf1550_charger *chg;
554
+
int i, irq, ret;
555
+
556
+
chg = devm_kzalloc(&pdev->dev, sizeof(*chg), GFP_KERNEL);
557
+
if (!chg)
558
+
return -ENOMEM;
559
+
560
+
chg->dev = &pdev->dev;
561
+
chg->pf1550 = pf1550;
562
+
563
+
if (!chg->pf1550->regmap)
564
+
return dev_err_probe(&pdev->dev, -ENODEV,
565
+
"failed to get regmap\n");
566
+
567
+
platform_set_drvdata(pdev, chg);
568
+
569
+
ret = devm_delayed_work_autocancel(chg->dev, &chg->vbus_sense_work,
570
+
pf1550_chg_vbus_work);
571
+
if (ret)
572
+
return dev_err_probe(chg->dev, ret,
573
+
"failed to add vbus sense work\n");
574
+
575
+
ret = devm_delayed_work_autocancel(chg->dev, &chg->chg_sense_work,
576
+
pf1550_chg_chg_work);
577
+
if (ret)
578
+
return dev_err_probe(chg->dev, ret,
579
+
"failed to add charger sense work\n");
580
+
581
+
ret = devm_delayed_work_autocancel(chg->dev, &chg->bat_sense_work,
582
+
pf1550_chg_bat_work);
583
+
if (ret)
584
+
return dev_err_probe(chg->dev, ret,
585
+
"failed to add battery sense work\n");
586
+
587
+
for (i = 0; i < PF1550_CHARGER_IRQ_NR; i++) {
588
+
irq = platform_get_irq(pdev, i);
589
+
if (irq < 0)
590
+
return irq;
591
+
592
+
chg->virqs[i] = irq;
593
+
594
+
ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
595
+
pf1550_charger_irq_handler,
596
+
IRQF_NO_SUSPEND,
597
+
"pf1550-charger", chg);
598
+
if (ret)
599
+
return dev_err_probe(&pdev->dev, ret,
600
+
"failed irq request\n");
601
+
}
602
+
603
+
psy_cfg.drv_data = chg;
604
+
605
+
chg->charger = devm_power_supply_register(&pdev->dev,
606
+
&pf1550_charger_desc,
607
+
&psy_cfg);
608
+
if (IS_ERR(chg->charger))
609
+
return dev_err_probe(&pdev->dev, PTR_ERR(chg->charger),
610
+
"failed: power supply register\n");
611
+
612
+
chg->battery = devm_power_supply_register(&pdev->dev,
613
+
&pf1550_battery_desc,
614
+
&psy_cfg);
615
+
if (IS_ERR(chg->battery))
616
+
return dev_err_probe(&pdev->dev, PTR_ERR(chg->battery),
617
+
"failed: power supply register\n");
618
+
619
+
pf1550_dt_parse_dev_info(chg);
620
+
621
+
return pf1550_reg_init(chg);
622
+
}
623
+
624
+
static const struct platform_device_id pf1550_charger_id[] = {
625
+
{ "pf1550-charger", },
626
+
{ /* sentinel */ }
627
+
};
628
+
MODULE_DEVICE_TABLE(platform, pf1550_charger_id);
629
+
630
+
static struct platform_driver pf1550_charger_driver = {
631
+
.driver = {
632
+
.name = "pf1550-charger",
633
+
},
634
+
.probe = pf1550_charger_probe,
635
+
.id_table = pf1550_charger_id,
636
+
};
637
+
module_platform_driver(pf1550_charger_driver);
638
+
639
+
MODULE_AUTHOR("Robin Gong <yibin.gong@freescale.com>");
640
+
MODULE_DESCRIPTION("PF1550 charger driver");
641
+
MODULE_LICENSE("GPL");
+41
drivers/regulator/Kconfig
+41
drivers/regulator/Kconfig
···
500
500
help
501
501
This driver supports ISL6271A voltage regulator chip.
502
502
503
+
config REGULATOR_FP9931
504
+
tristate "FitiPower FP9931/JD9930 EPD regulator"
505
+
depends on I2C
506
+
select REGMAP_I2C
507
+
help
508
+
This driver supports the FP9931/JD9930 voltage regulator chip
509
+
which is used to provide power to Electronic Paper Displays
510
+
so it is found in E-Book readers.
511
+
If HWWON is enabled, it also provides temperature measurement.
512
+
503
513
config REGULATOR_LM363X
504
514
tristate "TI LM363X voltage regulators"
505
515
depends on MFD_TI_LMU
···
891
881
This driver supports the control of different power rails of device
892
882
through regulator interface.
893
883
884
+
config REGULATOR_MT6316
885
+
tristate "MT6316 SPMI PMIC regulator driver"
886
+
depends on SPMI
887
+
select REGMAP_SPMI
888
+
help
889
+
Say Y here to enable support for 2+2, 3+1 and 4 phase regulators
890
+
found in the MediaTek MT6316 BP, CP, DP, HP, VP and TP SPMI PMICs.
891
+
This driver supports the control of different power rails of device
892
+
through regulator interface.
893
+
894
894
config REGULATOR_MT6323
895
895
tristate "MediaTek MT6323 PMIC"
896
896
depends on MFD_MT6397
···
963
943
This is support MT6360 PMIC/LDO part include
964
944
2-channel buck with Thermal Shutdown and Overload Protection
965
945
6-channel High PSRR and Low Dropout LDO.
946
+
947
+
config REGULATOR_MT6363
948
+
tristate "MT6363 SPMI PMIC regulator driver"
949
+
depends on SPMI
950
+
select REGMAP_SPMI
951
+
help
952
+
Say Y here to enable support for regulators found in the MediaTek
953
+
MT6363 SPMI PMIC.
954
+
This driver supports the control of different power rails of device
955
+
through regulator interface.
966
956
967
957
config REGULATOR_MT6370
968
958
tristate "MT6370 SubPMIC Regulator"
···
1116
1086
Say y here to support the voltage regulators and convertors
1117
1087
on PV88090
1118
1088
1089
+
config REGULATOR_PF1550
1090
+
tristate "NXP PF1550 regulator"
1091
+
depends on MFD_PF1550
1092
+
help
1093
+
Say y here to select this option to enable the regulators on
1094
+
the PF1550 PMICs.
1095
+
This driver controls the PF1550 regulators via I2C bus.
1096
+
The regulators include three bucks and three ldos.
1097
+
1119
1098
config REGULATOR_PWM
1120
1099
tristate "PWM voltage regulator"
1121
1100
depends on PWM
···
1220
1181
1221
1182
config REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY
1222
1183
tristate "Raspberry Pi 7-inch touchscreen panel ATTINY regulator"
1184
+
depends on ARM || ARM64 || COMPILE_TEST
1223
1185
depends on BACKLIGHT_CLASS_DEVICE
1224
1186
depends on I2C
1225
1187
depends on OF_GPIO
···
1232
1192
1233
1193
config REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2
1234
1194
tristate "Raspberry Pi 7-inch touchscreen panel V2 regulator"
1195
+
depends on ARM || ARM64 || COMPILE_TEST
1235
1196
depends on GPIOLIB
1236
1197
depends on I2C && OF
1237
1198
select GPIO_REGMAP
+4
drivers/regulator/Makefile
+4
drivers/regulator/Makefile
···
59
59
obj-$(CONFIG_REGULATOR_HI655X) += hi655x-regulator.o
60
60
obj-$(CONFIG_REGULATOR_ISL6271A) += isl6271a-regulator.o
61
61
obj-$(CONFIG_REGULATOR_ISL9305) += isl9305.o
62
+
obj-$(CONFIG_REGULATOR_FP9931) += fp9931.o
62
63
obj-$(CONFIG_REGULATOR_LM363X) += lm363x-regulator.o
63
64
obj-$(CONFIG_REGULATOR_LOCHNAGAR) += lochnagar-regulator.o
64
65
obj-$(CONFIG_REGULATOR_LP3971) += lp3971.o
···
106
105
obj-$(CONFIG_REGULATOR_MPQ7920) += mpq7920.o
107
106
obj-$(CONFIG_REGULATOR_MT6311) += mt6311-regulator.o
108
107
obj-$(CONFIG_REGULATOR_MT6315) += mt6315-regulator.o
108
+
obj-$(CONFIG_REGULATOR_MT6315) += mt6316-regulator.o
109
109
obj-$(CONFIG_REGULATOR_MT6323) += mt6323-regulator.o
110
110
obj-$(CONFIG_REGULATOR_MT6331) += mt6331-regulator.o
111
111
obj-$(CONFIG_REGULATOR_MT6332) += mt6332-regulator.o
···
114
112
obj-$(CONFIG_REGULATOR_MT6358) += mt6358-regulator.o
115
113
obj-$(CONFIG_REGULATOR_MT6359) += mt6359-regulator.o
116
114
obj-$(CONFIG_REGULATOR_MT6360) += mt6360-regulator.o
115
+
obj-$(CONFIG_REGULATOR_MT6363) += mt6363-regulator.o
117
116
obj-$(CONFIG_REGULATOR_MT6370) += mt6370-regulator.o
118
117
obj-$(CONFIG_REGULATOR_MT6380) += mt6380-regulator.o
119
118
obj-$(CONFIG_REGULATOR_MT6397) += mt6397-regulator.o
···
131
128
obj-$(CONFIG_REGULATOR_PCA9450) += pca9450-regulator.o
132
129
obj-$(CONFIG_REGULATOR_PF0900) += pf0900-regulator.o
133
130
obj-$(CONFIG_REGULATOR_PF9453) += pf9453-regulator.o
131
+
obj-$(CONFIG_REGULATOR_PF1550) += pf1550-regulator.o
134
132
obj-$(CONFIG_REGULATOR_PF530X) += pf530x-regulator.o
135
133
obj-$(CONFIG_REGULATOR_PF8X00) += pf8x00-regulator.o
136
134
obj-$(CONFIG_REGULATOR_PFUZE100) += pfuze100-regulator.o
+4
-4
drivers/regulator/bd71815-regulator.c
+4
-4
drivers/regulator/bd71815-regulator.c
···
173
173
const struct regulator_desc *desc,
174
174
struct regulator_config *cfg)
175
175
{
176
-
struct bd71815_regulator *data;
176
+
const struct bd71815_regulator *data;
177
177
178
-
data = container_of(desc, struct bd71815_regulator, desc);
178
+
data = container_of_const(desc, struct bd71815_regulator, desc);
179
179
return rohm_regulator_set_dvs_levels(data->dvs, np, desc, cfg->regmap);
180
180
}
181
181
···
195
195
const struct regulator_desc *desc,
196
196
struct regulator_config *cfg)
197
197
{
198
-
struct bd71815_regulator *data;
198
+
const struct bd71815_regulator *data;
199
199
int ret = 0, val;
200
200
201
-
data = container_of(desc, struct bd71815_regulator, desc);
201
+
data = container_of_const(desc, struct bd71815_regulator, desc);
202
202
203
203
if (of_property_present(np, "rohm,dvs-run-voltage") ||
204
204
of_property_present(np, "rohm,dvs-suspend-voltage") ||
+2
-2
drivers/regulator/bd71828-regulator.c
+2
-2
drivers/regulator/bd71828-regulator.c
···
95
95
const struct regulator_desc *desc,
96
96
struct regulator_config *cfg)
97
97
{
98
-
struct bd71828_regulator_data *data;
98
+
const struct bd71828_regulator_data *data;
99
99
100
-
data = container_of(desc, struct bd71828_regulator_data, desc);
100
+
data = container_of_const(desc, struct bd71828_regulator_data, desc);
101
101
102
102
return rohm_regulator_set_dvs_levels(&data->dvs, np, desc, cfg->regmap);
103
103
}
+2
-2
drivers/regulator/bd718x7-regulator.c
+2
-2
drivers/regulator/bd718x7-regulator.c
···
698
698
const struct regulator_desc *desc,
699
699
struct regulator_config *cfg)
700
700
{
701
-
struct bd718xx_regulator_data *data;
701
+
const struct bd718xx_regulator_data *data;
702
702
703
-
data = container_of(desc, struct bd718xx_regulator_data, desc);
703
+
data = container_of_const(desc, struct bd718xx_regulator_data, desc);
704
704
705
705
return rohm_regulator_set_dvs_levels(&data->dvs, np, desc, cfg->regmap);
706
706
}
+5
-5
drivers/regulator/bd96801-regulator.c
+5
-5
drivers/regulator/bd96801-regulator.c
···
337
337
int i;
338
338
339
339
for (i = 0; i < rid->num_states; i++) {
340
-
struct bd96801_regulator_data *rdata;
340
+
const struct bd96801_regulator_data *rdata;
341
341
struct regulator_dev *rdev;
342
342
343
343
rdev = rid->states[i].rdev;
344
-
rdata = container_of(rdev->desc, struct bd96801_regulator_data,
345
-
desc);
344
+
rdata = container_of_const(rdev->desc, struct bd96801_regulator_data,
345
+
desc);
346
346
rid->states[i].notifs = regulator_err2notif(rdata->ldo_errs);
347
347
rid->states[i].errors = rdata->ldo_errs;
348
348
*dev_mask |= BIT(i);
···
354
354
unsigned int selector)
355
355
{
356
356
int voltage;
357
-
struct bd96801_regulator_data *data;
357
+
const struct bd96801_regulator_data *data;
358
358
359
-
data = container_of(rdev->desc, struct bd96801_regulator_data, desc);
359
+
data = container_of_const(rdev->desc, struct bd96801_regulator_data, desc);
360
360
361
361
/*
362
362
* The BD096801 has voltage setting in two registers. One giving the
+157
-12
drivers/regulator/core.c
+157
-12
drivers/regulator/core.c
···
83
83
const char *alias_supply;
84
84
};
85
85
86
+
/*
87
+
* Work item used to forward regulator events.
88
+
*
89
+
* @work: workqueue entry
90
+
* @rdev: regulator device to notify (consumer receiving the forwarded event)
91
+
* @event: event code to be forwarded
92
+
*/
93
+
struct regulator_event_work {
94
+
struct work_struct work;
95
+
struct regulator_dev *rdev;
96
+
unsigned long event;
97
+
};
98
+
86
99
static int _regulator_is_enabled(struct regulator_dev *rdev);
87
100
static int _regulator_disable(struct regulator *regulator);
88
101
static int _regulator_get_error_flags(struct regulator_dev *rdev, unsigned int *flags);
···
1631
1618
* and we have control then make sure it is enabled.
1632
1619
*/
1633
1620
if (rdev->constraints->always_on || rdev->constraints->boot_on) {
1621
+
bool supply_enabled = false;
1622
+
1634
1623
/* If we want to enable this regulator, make sure that we know
1635
1624
* the supplying regulator.
1636
1625
*/
···
1652
1637
rdev->supply = NULL;
1653
1638
return ret;
1654
1639
}
1640
+
supply_enabled = true;
1655
1641
}
1656
1642
1657
1643
ret = _regulator_do_enable(rdev);
1658
1644
if (ret < 0 && ret != -EINVAL) {
1659
1645
rdev_err(rdev, "failed to enable: %pe\n", ERR_PTR(ret));
1646
+
if (supply_enabled)
1647
+
regulator_disable(rdev->supply);
1660
1648
return ret;
1661
1649
}
1662
1650
···
1673
1655
rdev->constraints->pw_budget_mW = INT_MAX;
1674
1656
1675
1657
print_constraints(rdev);
1658
+
return 0;
1659
+
}
1660
+
1661
+
/**
1662
+
* regulator_event_work_fn - process a deferred regulator event
1663
+
* @work: work_struct queued by the notifier
1664
+
*
1665
+
* Calls the regulator's notifier chain in process context while holding
1666
+
* the rdev lock, then releases the device reference.
1667
+
*/
1668
+
static void regulator_event_work_fn(struct work_struct *work)
1669
+
{
1670
+
struct regulator_event_work *rew =
1671
+
container_of(work, struct regulator_event_work, work);
1672
+
struct regulator_dev *rdev = rew->rdev;
1673
+
int ret;
1674
+
1675
+
regulator_lock(rdev);
1676
+
ret = regulator_notifier_call_chain(rdev, rew->event, NULL);
1677
+
regulator_unlock(rdev);
1678
+
if (ret == NOTIFY_BAD)
1679
+
dev_err(rdev_get_dev(rdev), "failed to forward regulator event\n");
1680
+
1681
+
put_device(rdev_get_dev(rdev));
1682
+
kfree(rew);
1683
+
}
1684
+
1685
+
/**
1686
+
* regulator_event_forward_notifier - notifier callback for supply events
1687
+
* @nb: notifier block embedded in the regulator
1688
+
* @event: regulator event code
1689
+
* @data: unused
1690
+
*
1691
+
* Packages the event into a work item and schedules it in process context.
1692
+
* Takes a reference on @rdev->dev to pin the regulator until the work
1693
+
* completes (see put_device() in the worker).
1694
+
*
1695
+
* Return: NOTIFY_OK on success, NOTIFY_DONE for events that are not forwarded.
1696
+
*/
1697
+
static int regulator_event_forward_notifier(struct notifier_block *nb,
1698
+
unsigned long event,
1699
+
void __always_unused *data)
1700
+
{
1701
+
struct regulator_dev *rdev = container_of(nb, struct regulator_dev,
1702
+
supply_fwd_nb);
1703
+
struct regulator_event_work *rew;
1704
+
1705
+
switch (event) {
1706
+
case REGULATOR_EVENT_UNDER_VOLTAGE:
1707
+
break;
1708
+
default:
1709
+
/* Only forward allowed events downstream. */
1710
+
return NOTIFY_DONE;
1711
+
}
1712
+
1713
+
rew = kmalloc(sizeof(*rew), GFP_ATOMIC);
1714
+
if (!rew)
1715
+
return NOTIFY_DONE;
1716
+
1717
+
get_device(rdev_get_dev(rdev));
1718
+
rew->rdev = rdev;
1719
+
rew->event = event;
1720
+
INIT_WORK(&rew->work, regulator_event_work_fn);
1721
+
1722
+
queue_work(system_highpri_wq, &rew->work);
1723
+
1724
+
return NOTIFY_OK;
1725
+
}
1726
+
1727
+
/**
1728
+
* register_regulator_event_forwarding - enable supply event forwarding
1729
+
* @rdev: regulator device
1730
+
*
1731
+
* Registers a notifier on the regulator's supply so that supply events
1732
+
* are forwarded to the consumer regulator via the deferred work handler.
1733
+
*
1734
+
* Return: 0 on success, -EALREADY if already enabled, or a negative error code.
1735
+
*/
1736
+
static int register_regulator_event_forwarding(struct regulator_dev *rdev)
1737
+
{
1738
+
int ret;
1739
+
1740
+
if (!rdev->supply)
1741
+
return 0; /* top-level regulator: nothing to forward */
1742
+
1743
+
if (rdev->supply_fwd_nb.notifier_call)
1744
+
return -EALREADY;
1745
+
1746
+
rdev->supply_fwd_nb.notifier_call = regulator_event_forward_notifier;
1747
+
1748
+
ret = regulator_register_notifier(rdev->supply, &rdev->supply_fwd_nb);
1749
+
if (ret) {
1750
+
dev_err(&rdev->dev, "failed to register supply notifier: %pe\n",
1751
+
ERR_PTR(ret));
1752
+
rdev->supply_fwd_nb.notifier_call = NULL;
1753
+
return ret;
1754
+
}
1755
+
1676
1756
return 0;
1677
1757
}
1678
1758
···
2058
1942
{
2059
1943
struct regulator_supply_alias *map;
2060
1944
1945
+
mutex_lock(®ulator_list_mutex);
2061
1946
map = regulator_find_supply_alias(*dev, *supply);
2062
1947
if (map) {
2063
1948
dev_dbg(*dev, "Mapping supply %s to %s,%s\n",
···
2067
1950
*dev = map->alias_dev;
2068
1951
*supply = map->alias_supply;
2069
1952
}
1953
+
mutex_unlock(®ulator_list_mutex);
2070
1954
}
2071
1955
2072
1956
static int regulator_match(struct device *dev, const void *data)
···
2261
2143
put_device(&r->dev);
2262
2144
goto out;
2263
2145
}
2146
+
2147
+
/*
2148
+
* Automatically register for event forwarding from the new supply.
2149
+
* This creates the downstream propagation link for events like
2150
+
* under-voltage.
2151
+
*/
2152
+
ret = register_regulator_event_forwarding(rdev);
2153
+
if (ret < 0)
2154
+
rdev_warn(rdev, "Failed to register event forwarding: %pe\n",
2155
+
ERR_PTR(ret));
2264
2156
2265
2157
regulator_unlock_two(rdev, r, &ww_ctx);
2266
2158
···
2620
2492
const char *alias_id)
2621
2493
{
2622
2494
struct regulator_supply_alias *map;
2495
+
struct regulator_supply_alias *new_map;
2623
2496
2624
-
map = regulator_find_supply_alias(dev, id);
2625
-
if (map)
2626
-
return -EEXIST;
2627
-
2628
-
map = kzalloc(sizeof(struct regulator_supply_alias), GFP_KERNEL);
2629
-
if (!map)
2497
+
new_map = kzalloc(sizeof(struct regulator_supply_alias), GFP_KERNEL);
2498
+
if (!new_map)
2630
2499
return -ENOMEM;
2631
2500
2632
-
map->src_dev = dev;
2633
-
map->src_supply = id;
2634
-
map->alias_dev = alias_dev;
2635
-
map->alias_supply = alias_id;
2501
+
mutex_lock(®ulator_list_mutex);
2502
+
map = regulator_find_supply_alias(dev, id);
2503
+
if (map) {
2504
+
mutex_unlock(®ulator_list_mutex);
2505
+
kfree(new_map);
2506
+
return -EEXIST;
2507
+
}
2636
2508
2637
-
list_add(&map->list, ®ulator_supply_alias_list);
2638
-
2509
+
new_map->src_dev = dev;
2510
+
new_map->src_supply = id;
2511
+
new_map->alias_dev = alias_dev;
2512
+
new_map->alias_supply = alias_id;
2513
+
list_add(&new_map->list, ®ulator_supply_alias_list);
2514
+
mutex_unlock(®ulator_list_mutex);
2639
2515
pr_info("Adding alias for supply %s,%s -> %s,%s\n",
2640
2516
id, dev_name(dev), alias_id, dev_name(alias_dev));
2641
2517
···
2659
2527
{
2660
2528
struct regulator_supply_alias *map;
2661
2529
2530
+
mutex_lock(®ulator_list_mutex);
2662
2531
map = regulator_find_supply_alias(dev, id);
2663
2532
if (map) {
2664
2533
list_del(&map->list);
2665
2534
kfree(map);
2666
2535
}
2536
+
mutex_unlock(®ulator_list_mutex);
2667
2537
}
2668
2538
EXPORT_SYMBOL_GPL(regulator_unregister_supply_alias);
2669
2539
···
2750
2616
2751
2617
mutex_lock(®ulator_list_mutex);
2752
2618
2619
+
if (gpiod_is_shared(gpiod))
2620
+
/*
2621
+
* The sharing of this GPIO pin is managed internally by
2622
+
* GPIOLIB. We don't need to keep track of its enable count.
2623
+
*/
2624
+
goto skip_compare;
2625
+
2753
2626
list_for_each_entry(pin, ®ulator_ena_gpio_list, list) {
2754
2627
if (gpiod_is_equal(pin->gpiod, gpiod)) {
2755
2628
rdev_dbg(rdev, "GPIO is already used\n");
···
2769
2628
return -ENOMEM;
2770
2629
}
2771
2630
2631
+
skip_compare:
2772
2632
pin = new_pin;
2773
2633
new_pin = NULL;
2774
2634
···
6173
6031
return;
6174
6032
6175
6033
if (rdev->supply) {
6034
+
regulator_unregister_notifier(rdev->supply,
6035
+
&rdev->supply_fwd_nb);
6036
+
6176
6037
while (rdev->use_count--)
6177
6038
regulator_disable(rdev->supply);
6178
6039
regulator_put(rdev->supply);
+551
drivers/regulator/fp9931.c
+551
drivers/regulator/fp9931.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
// Copyright (C) 2025 Andreas Kemnade
3
+
4
+
/* Datasheet: https://www.fitipower.com/dl/file/flXa6hIchVeu0W3K */
5
+
6
+
#include <linux/cleanup.h>
7
+
#include <linux/completion.h>
8
+
#include <linux/gpio/consumer.h>
9
+
#include <linux/i2c.h>
10
+
#include <linux/module.h>
11
+
#include <linux/mutex.h>
12
+
#include <linux/hwmon.h>
13
+
#include <linux/pm_runtime.h>
14
+
#include <linux/property.h>
15
+
#include <linux/regulator/consumer.h>
16
+
#include <linux/regulator/driver.h>
17
+
#include <linux/regulator/machine.h>
18
+
#include <linux/regmap.h>
19
+
20
+
#define FP9931_REG_TMST_VALUE 0
21
+
#define FP9931_REG_VCOM_SETTING 1
22
+
#define FP9931_REG_VPOSNEG_SETTING 2
23
+
#define FP9931_REG_PWRON_DELAY 3
24
+
#define FP9931_REG_CONTROL_REG1 11
25
+
26
+
#define PGOOD_TIMEOUT_MSECS 200
27
+
28
+
struct fp9931_data {
29
+
struct device *dev;
30
+
struct regmap *regmap;
31
+
struct regulator *vin_reg;
32
+
struct gpio_desc *pgood_gpio;
33
+
struct gpio_desc *en_gpio;
34
+
struct gpio_desc *en_ts_gpio;
35
+
struct completion pgood_completion;
36
+
int pgood_irq;
37
+
};
38
+
39
+
static const unsigned int VPOSNEG_table[] = {
40
+
7040000,
41
+
7040000,
42
+
7040000,
43
+
7040000,
44
+
7040000,
45
+
7040000,
46
+
7260000,
47
+
7490000,
48
+
7710000,
49
+
7930000,
50
+
8150000,
51
+
8380000,
52
+
8600000,
53
+
8820000,
54
+
9040000,
55
+
9270000,
56
+
9490000,
57
+
9710000,
58
+
9940000,
59
+
10160000,
60
+
10380000,
61
+
10600000,
62
+
10830000,
63
+
11050000,
64
+
11270000,
65
+
11490000,
66
+
11720000,
67
+
11940000,
68
+
12160000,
69
+
12380000,
70
+
12610000,
71
+
12830000,
72
+
13050000,
73
+
13280000,
74
+
13500000,
75
+
13720000,
76
+
13940000,
77
+
14170000,
78
+
14390000,
79
+
14610000,
80
+
14830000,
81
+
15060000,
82
+
};
83
+
84
+
static const struct hwmon_channel_info *fp9931_info[] = {
85
+
HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ),
86
+
HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
87
+
NULL
88
+
};
89
+
90
+
static int setup_timings(struct fp9931_data *data)
91
+
{
92
+
u32 tdly[4];
93
+
u8 tdlys = 0;
94
+
int i;
95
+
int ret;
96
+
97
+
ret = device_property_count_u32(data->dev, "fitipower,tdly-ms");
98
+
if (ret == -EINVAL) /* property is optional */
99
+
return 0;
100
+
101
+
if (ret < 0)
102
+
return ret;
103
+
104
+
if (ret != ARRAY_SIZE(tdly)) {
105
+
dev_err(data->dev, "invalid delay specification");
106
+
return -EINVAL;
107
+
}
108
+
109
+
ret = device_property_read_u32_array(data->dev, "fitipower,tdly-ms",
110
+
tdly, ARRAY_SIZE(tdly));
111
+
if (ret)
112
+
return ret;
113
+
114
+
for (i = ARRAY_SIZE(tdly) - 1; i >= 0; i--) {
115
+
if (tdly[i] > 4 || tdly[i] == 3)
116
+
return -EINVAL;
117
+
118
+
if (tdly[i] == 4) /* convert from ms */
119
+
tdly[i] = 3;
120
+
121
+
tdlys <<= 2;
122
+
tdlys |= tdly[i];
123
+
}
124
+
125
+
ret = pm_runtime_resume_and_get(data->dev);
126
+
if (ret < 0)
127
+
return ret;
128
+
129
+
ret = regmap_write(data->regmap, FP9931_REG_PWRON_DELAY, tdlys);
130
+
pm_runtime_put_autosuspend(data->dev);
131
+
132
+
return ret;
133
+
}
134
+
135
+
static int fp9931_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
136
+
u32 attr, int channel, long *temp)
137
+
{
138
+
struct fp9931_data *data = dev_get_drvdata(dev);
139
+
unsigned int val;
140
+
int ret;
141
+
142
+
ret = pm_runtime_resume_and_get(data->dev);
143
+
if (ret < 0)
144
+
return ret;
145
+
146
+
ret = regmap_read(data->regmap, FP9931_REG_TMST_VALUE, &val);
147
+
if (ret)
148
+
return ret;
149
+
150
+
pm_runtime_put_autosuspend(data->dev);
151
+
*temp = (s8)val * 1000;
152
+
153
+
return 0;
154
+
}
155
+
156
+
static umode_t fp9931_hwmon_is_visible(const void *data,
157
+
enum hwmon_sensor_types type,
158
+
u32 attr, int channel)
159
+
{
160
+
return 0444;
161
+
}
162
+
163
+
static const struct hwmon_ops fp9931_hwmon_ops = {
164
+
.is_visible = fp9931_hwmon_is_visible,
165
+
.read = fp9931_hwmon_read,
166
+
};
167
+
168
+
static const struct hwmon_chip_info fp9931_chip_info = {
169
+
.ops = &fp9931_hwmon_ops,
170
+
.info = fp9931_info,
171
+
};
172
+
173
+
static int fp9931_runtime_suspend(struct device *dev)
174
+
{
175
+
int ret = 0;
176
+
struct fp9931_data *data = dev_get_drvdata(dev);
177
+
178
+
if (data->en_ts_gpio)
179
+
gpiod_set_value_cansleep(data->en_ts_gpio, 0);
180
+
181
+
if (data->vin_reg) {
182
+
ret = regulator_disable(data->vin_reg);
183
+
regcache_mark_dirty(data->regmap);
184
+
}
185
+
186
+
return ret;
187
+
}
188
+
189
+
static int fp9931_runtime_resume(struct device *dev)
190
+
{
191
+
int ret = 0;
192
+
struct fp9931_data *data = dev_get_drvdata(dev);
193
+
194
+
if (data->vin_reg)
195
+
ret = regulator_enable(data->vin_reg);
196
+
197
+
if (ret)
198
+
return ret;
199
+
200
+
if (data->en_ts_gpio) {
201
+
gpiod_set_value_cansleep(data->en_ts_gpio, 1);
202
+
/* wait for one ADC conversion to have sane temperature */
203
+
usleep_range(10000, 15000);
204
+
}
205
+
206
+
ret = regcache_sync(data->regmap);
207
+
208
+
return ret;
209
+
}
210
+
211
+
static bool fp9931_volatile_reg(struct device *dev, unsigned int reg)
212
+
{
213
+
return reg == FP9931_REG_TMST_VALUE;
214
+
}
215
+
216
+
static const struct reg_default fp9931_reg_default = {
217
+
.reg = FP9931_REG_VCOM_SETTING,
218
+
.def = 0x80,
219
+
};
220
+
221
+
static const struct regmap_config regmap_config = {
222
+
.reg_bits = 8,
223
+
.val_bits = 8,
224
+
.max_register = 12,
225
+
.cache_type = REGCACHE_FLAT,
226
+
.volatile_reg = fp9931_volatile_reg,
227
+
.reg_defaults = &fp9931_reg_default,
228
+
.num_reg_defaults = 1,
229
+
};
230
+
231
+
static void disable_nopm(void *d)
232
+
{
233
+
struct fp9931_data *data = d;
234
+
235
+
fp9931_runtime_suspend(data->dev);
236
+
}
237
+
238
+
static int fp9931_v3p3_enable(struct regulator_dev *rdev)
239
+
{
240
+
struct fp9931_data *data = rdev_get_drvdata(rdev);
241
+
int ret;
242
+
243
+
ret = pm_runtime_resume_and_get(data->dev);
244
+
if (ret < 0)
245
+
return ret;
246
+
247
+
ret = regulator_enable_regmap(rdev);
248
+
if (ret < 0)
249
+
pm_runtime_put_autosuspend(data->dev);
250
+
251
+
return ret;
252
+
}
253
+
254
+
static int fp9931_v3p3_disable(struct regulator_dev *rdev)
255
+
{
256
+
struct fp9931_data *data = rdev_get_drvdata(rdev);
257
+
int ret;
258
+
259
+
ret = regulator_disable_regmap(rdev);
260
+
pm_runtime_put_autosuspend(data->dev);
261
+
262
+
return ret;
263
+
}
264
+
265
+
static int fp9931_v3p3_is_enabled(struct regulator_dev *rdev)
266
+
{
267
+
struct fp9931_data *data = rdev_get_drvdata(rdev);
268
+
int ret;
269
+
270
+
if (pm_runtime_status_suspended(data->dev))
271
+
return 0;
272
+
273
+
ret = pm_runtime_resume_and_get(data->dev);
274
+
if (ret < 0)
275
+
return 0;
276
+
277
+
ret = regulator_is_enabled_regmap(rdev);
278
+
279
+
pm_runtime_put_autosuspend(data->dev);
280
+
return ret;
281
+
}
282
+
283
+
static const struct regulator_ops fp9931_v3p3ops = {
284
+
.list_voltage = regulator_list_voltage_linear,
285
+
.enable = fp9931_v3p3_enable,
286
+
.disable = fp9931_v3p3_disable,
287
+
.is_enabled = fp9931_v3p3_is_enabled,
288
+
};
289
+
290
+
static int fp9931_check_powergood(struct regulator_dev *rdev)
291
+
{
292
+
struct fp9931_data *data = rdev_get_drvdata(rdev);
293
+
294
+
if (pm_runtime_status_suspended(data->dev))
295
+
return 0;
296
+
297
+
return gpiod_get_value_cansleep(data->pgood_gpio);
298
+
}
299
+
300
+
static int fp9931_get_voltage_sel(struct regulator_dev *rdev)
301
+
{
302
+
struct fp9931_data *data = rdev_get_drvdata(rdev);
303
+
int ret;
304
+
305
+
ret = pm_runtime_resume_and_get(data->dev);
306
+
if (ret < 0)
307
+
return ret;
308
+
309
+
ret = regulator_get_voltage_sel_regmap(rdev);
310
+
pm_runtime_put_autosuspend(data->dev);
311
+
312
+
return ret;
313
+
}
314
+
315
+
static int fp9931_set_voltage_sel(struct regulator_dev *rdev, unsigned int selector)
316
+
{
317
+
struct fp9931_data *data = rdev_get_drvdata(rdev);
318
+
int ret;
319
+
320
+
ret = pm_runtime_resume_and_get(data->dev);
321
+
if (ret < 0)
322
+
return ret;
323
+
324
+
ret = regulator_set_voltage_sel_regmap(rdev, selector);
325
+
pm_runtime_put_autosuspend(data->dev);
326
+
327
+
return ret;
328
+
}
329
+
330
+
static irqreturn_t pgood_handler(int irq, void *dev_id)
331
+
{
332
+
struct fp9931_data *data = dev_id;
333
+
334
+
complete(&data->pgood_completion);
335
+
336
+
return IRQ_HANDLED;
337
+
}
338
+
339
+
static int fp9931_set_enable(struct regulator_dev *rdev)
340
+
{
341
+
struct fp9931_data *data = rdev_get_drvdata(rdev);
342
+
int ret;
343
+
344
+
ret = pm_runtime_resume_and_get(data->dev);
345
+
if (ret < 0)
346
+
return ret;
347
+
348
+
reinit_completion(&data->pgood_completion);
349
+
gpiod_set_value_cansleep(data->en_gpio, 1);
350
+
dev_dbg(data->dev, "turning on...");
351
+
wait_for_completion_timeout(&data->pgood_completion,
352
+
msecs_to_jiffies(PGOOD_TIMEOUT_MSECS));
353
+
dev_dbg(data->dev, "turned on");
354
+
if (gpiod_get_value_cansleep(data->pgood_gpio) != 1) {
355
+
pm_runtime_put_autosuspend(data->dev);
356
+
return -ETIMEDOUT;
357
+
}
358
+
359
+
return 0;
360
+
}
361
+
362
+
static int fp9931_clear_enable(struct regulator_dev *rdev)
363
+
{
364
+
struct fp9931_data *data = rdev_get_drvdata(rdev);
365
+
366
+
gpiod_set_value_cansleep(data->en_gpio, 0);
367
+
pm_runtime_put_autosuspend(data->dev);
368
+
return 0;
369
+
}
370
+
371
+
static const struct regulator_ops fp9931_vcom_ops = {
372
+
.list_voltage = regulator_list_voltage_linear,
373
+
.map_voltage = regulator_map_voltage_linear,
374
+
.enable = fp9931_set_enable,
375
+
.disable = fp9931_clear_enable,
376
+
.is_enabled = fp9931_check_powergood,
377
+
.set_voltage_sel = fp9931_set_voltage_sel,
378
+
.get_voltage_sel = fp9931_get_voltage_sel,
379
+
};
380
+
381
+
static const struct regulator_ops fp9931_vposneg_ops = {
382
+
.list_voltage = regulator_list_voltage_table,
383
+
.map_voltage = regulator_map_voltage_ascend,
384
+
/* gets enabled by enabling vcom, too */
385
+
.is_enabled = fp9931_check_powergood,
386
+
.set_voltage_sel = fp9931_set_voltage_sel,
387
+
.get_voltage_sel = fp9931_get_voltage_sel,
388
+
};
389
+
390
+
static const struct regulator_desc regulators[] = {
391
+
{
392
+
.name = "v3p3",
393
+
.of_match = of_match_ptr("v3p3"),
394
+
.id = 0,
395
+
.ops = &fp9931_v3p3ops,
396
+
.type = REGULATOR_VOLTAGE,
397
+
.owner = THIS_MODULE,
398
+
.enable_reg = FP9931_REG_CONTROL_REG1,
399
+
.enable_mask = BIT(1),
400
+
.n_voltages = 1,
401
+
.min_uV = 3300000
402
+
},
403
+
{
404
+
.name = "vposneg",
405
+
.of_match = of_match_ptr("vposneg"),
406
+
.id = 1,
407
+
.ops = &fp9931_vposneg_ops,
408
+
.type = REGULATOR_VOLTAGE,
409
+
.owner = THIS_MODULE,
410
+
.n_voltages = ARRAY_SIZE(VPOSNEG_table),
411
+
.vsel_reg = FP9931_REG_VPOSNEG_SETTING,
412
+
.vsel_mask = 0x3F,
413
+
.volt_table = VPOSNEG_table,
414
+
},
415
+
{
416
+
.name = "vcom",
417
+
.of_match = of_match_ptr("vcom"),
418
+
.id = 2,
419
+
.ops = &fp9931_vcom_ops,
420
+
.type = REGULATOR_VOLTAGE,
421
+
.owner = THIS_MODULE,
422
+
.n_voltages = 255,
423
+
.min_uV = 0,
424
+
.uV_step = 5000000 / 255,
425
+
.vsel_reg = FP9931_REG_VCOM_SETTING,
426
+
.vsel_mask = 0xFF
427
+
},
428
+
};
429
+
430
+
static int fp9931_probe(struct i2c_client *client)
431
+
{
432
+
struct fp9931_data *data;
433
+
struct regulator_config config = { };
434
+
struct regulator_dev *rdev;
435
+
int ret = 0;
436
+
int i;
437
+
438
+
data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
439
+
data->regmap = devm_regmap_init_i2c(client, ®map_config);
440
+
if (IS_ERR(data->regmap))
441
+
return dev_err_probe(&client->dev, PTR_ERR(data->regmap),
442
+
"failed to allocate regmap!\n");
443
+
444
+
data->vin_reg = devm_regulator_get_optional(&client->dev, "vin");
445
+
if (IS_ERR(data->vin_reg))
446
+
return dev_err_probe(&client->dev, PTR_ERR(data->vin_reg),
447
+
"failed to get vin regulator\n");
448
+
449
+
data->pgood_gpio = devm_gpiod_get(&client->dev, "pg", GPIOD_IN);
450
+
if (IS_ERR(data->pgood_gpio))
451
+
return dev_err_probe(&client->dev,
452
+
PTR_ERR(data->pgood_gpio),
453
+
"failed to get power good gpio\n");
454
+
455
+
data->pgood_irq = gpiod_to_irq(data->pgood_gpio);
456
+
if (data->pgood_irq < 0)
457
+
return data->pgood_irq;
458
+
459
+
data->en_gpio = devm_gpiod_get(&client->dev, "enable", GPIOD_OUT_LOW);
460
+
if (IS_ERR(data->en_gpio))
461
+
return dev_err_probe(&client->dev, PTR_ERR(data->en_gpio),
462
+
"failed to get en gpio\n");
463
+
464
+
data->en_ts_gpio = devm_gpiod_get_optional(&client->dev, "en-ts", GPIOD_OUT_LOW);
465
+
if (IS_ERR(data->en_ts_gpio))
466
+
return dev_err_probe(&client->dev,
467
+
PTR_ERR(data->en_ts_gpio),
468
+
"failed to get en gpio\n");
469
+
470
+
data->dev = &client->dev;
471
+
i2c_set_clientdata(client, data);
472
+
473
+
init_completion(&data->pgood_completion);
474
+
475
+
ret = devm_request_threaded_irq(&client->dev, data->pgood_irq, NULL,
476
+
pgood_handler,
477
+
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
478
+
"PGOOD", data);
479
+
if (ret)
480
+
return dev_err_probe(&client->dev, ret,
481
+
"failed to request irq\n");
482
+
483
+
if (IS_ENABLED(CONFIG_PM)) {
484
+
devm_pm_runtime_enable(&client->dev);
485
+
pm_runtime_set_autosuspend_delay(&client->dev, 4000);
486
+
pm_runtime_use_autosuspend(&client->dev);
487
+
} else {
488
+
ret = fp9931_runtime_resume(&client->dev);
489
+
if (ret < 0)
490
+
return ret;
491
+
492
+
devm_add_action_or_reset(&client->dev, disable_nopm, data);
493
+
}
494
+
495
+
ret = setup_timings(data);
496
+
if (ret)
497
+
return dev_err_probe(&client->dev, ret, "failed to setup timings\n");
498
+
499
+
config.driver_data = data;
500
+
config.dev = &client->dev;
501
+
config.regmap = data->regmap;
502
+
503
+
for (i = 0; i < ARRAY_SIZE(regulators); i++) {
504
+
rdev = devm_regulator_register(&client->dev, ®ulators[i],
505
+
&config);
506
+
if (IS_ERR(rdev))
507
+
return dev_err_probe(&client->dev, PTR_ERR(rdev),
508
+
"failed to register %s regulator\n",
509
+
regulators[i].name);
510
+
}
511
+
512
+
if (IS_REACHABLE(CONFIG_HWMON)) {
513
+
struct device *hwmon_dev;
514
+
515
+
hwmon_dev = devm_hwmon_device_register_with_info(&client->dev, "fp9931", data,
516
+
&fp9931_chip_info, NULL);
517
+
if (IS_ERR(hwmon_dev))
518
+
dev_notice(&client->dev, "failed to register hwmon\n");
519
+
}
520
+
521
+
return 0;
522
+
}
523
+
524
+
static const struct dev_pm_ops fp9931_pm_ops = {
525
+
SET_RUNTIME_PM_OPS(fp9931_runtime_suspend, fp9931_runtime_resume, NULL)
526
+
};
527
+
528
+
static const struct of_device_id fp9931_dt_ids[] = {
529
+
{
530
+
.compatible = "fitipower,fp9931",
531
+
}, {
532
+
/* sentinel */
533
+
}
534
+
};
535
+
MODULE_DEVICE_TABLE(of, fp9931_dt_ids);
536
+
537
+
static struct i2c_driver fp9931_i2c_driver = {
538
+
.driver = {
539
+
.name = "fp9931",
540
+
.of_match_table = fp9931_dt_ids,
541
+
.pm = &fp9931_pm_ops,
542
+
},
543
+
.probe = fp9931_probe,
544
+
};
545
+
546
+
module_i2c_driver(fp9931_i2c_driver);
547
+
548
+
/* Module information */
549
+
MODULE_DESCRIPTION("FP9931 regulator driver");
550
+
MODULE_LICENSE("GPL");
551
+
+5
-5
drivers/regulator/hi6421-regulator.c
+5
-5
drivers/regulator/hi6421-regulator.c
···
387
387
const struct hi6421_regulator_info *info;
388
388
unsigned int reg_val;
389
389
390
-
info = container_of(rdev->desc, struct hi6421_regulator_info, desc);
390
+
info = container_of_const(rdev->desc, struct hi6421_regulator_info, desc);
391
391
regmap_read(rdev->regmap, rdev->desc->enable_reg, ®_val);
392
392
if (reg_val & info->mode_mask)
393
393
return REGULATOR_MODE_IDLE;
···
400
400
const struct hi6421_regulator_info *info;
401
401
unsigned int reg_val;
402
402
403
-
info = container_of(rdev->desc, struct hi6421_regulator_info, desc);
403
+
info = container_of_const(rdev->desc, struct hi6421_regulator_info, desc);
404
404
regmap_read(rdev->regmap, rdev->desc->enable_reg, ®_val);
405
405
if (reg_val & info->mode_mask)
406
406
return REGULATOR_MODE_STANDBY;
···
414
414
const struct hi6421_regulator_info *info;
415
415
unsigned int new_mode;
416
416
417
-
info = container_of(rdev->desc, struct hi6421_regulator_info, desc);
417
+
info = container_of_const(rdev->desc, struct hi6421_regulator_info, desc);
418
418
switch (mode) {
419
419
case REGULATOR_MODE_NORMAL:
420
420
new_mode = 0;
···
439
439
const struct hi6421_regulator_info *info;
440
440
unsigned int new_mode;
441
441
442
-
info = container_of(rdev->desc, struct hi6421_regulator_info, desc);
442
+
info = container_of_const(rdev->desc, struct hi6421_regulator_info, desc);
443
443
switch (mode) {
444
444
case REGULATOR_MODE_NORMAL:
445
445
new_mode = 0;
···
464
464
{
465
465
const struct hi6421_regulator_info *info;
466
466
467
-
info = container_of(rdev->desc, struct hi6421_regulator_info, desc);
467
+
info = container_of_const(rdev->desc, struct hi6421_regulator_info, desc);
468
468
469
469
if (load_uA > info->eco_microamp)
470
470
return REGULATOR_MODE_NORMAL;
+2
-2
drivers/regulator/hi6421v530-regulator.c
+2
-2
drivers/regulator/hi6421v530-regulator.c
···
110
110
const struct hi6421v530_regulator_info *info;
111
111
unsigned int reg_val;
112
112
113
-
info = container_of(rdev->desc, struct hi6421v530_regulator_info, rdesc);
113
+
info = container_of_const(rdev->desc, struct hi6421v530_regulator_info, rdesc);
114
114
regmap_read(rdev->regmap, rdev->desc->enable_reg, ®_val);
115
115
116
116
if (reg_val & (info->mode_mask))
···
125
125
const struct hi6421v530_regulator_info *info;
126
126
unsigned int new_mode;
127
127
128
-
info = container_of(rdev->desc, struct hi6421v530_regulator_info, rdesc);
128
+
info = container_of_const(rdev->desc, struct hi6421v530_regulator_info, rdesc);
129
129
switch (mode) {
130
130
case REGULATOR_MODE_NORMAL:
131
131
new_mode = 0;
+3
-3
drivers/regulator/hi6421v600-regulator.c
+3
-3
drivers/regulator/hi6421v600-regulator.c
···
121
121
const struct hi6421_spmi_reg_info *sreg;
122
122
unsigned int reg_val;
123
123
124
-
sreg = container_of(rdev->desc, struct hi6421_spmi_reg_info, desc);
124
+
sreg = container_of_const(rdev->desc, struct hi6421_spmi_reg_info, desc);
125
125
regmap_read(rdev->regmap, rdev->desc->enable_reg, ®_val);
126
126
127
127
if (reg_val & sreg->eco_mode_mask)
···
136
136
const struct hi6421_spmi_reg_info *sreg;
137
137
unsigned int val;
138
138
139
-
sreg = container_of(rdev->desc, struct hi6421_spmi_reg_info, desc);
139
+
sreg = container_of_const(rdev->desc, struct hi6421_spmi_reg_info, desc);
140
140
switch (mode) {
141
141
case REGULATOR_MODE_NORMAL:
142
142
val = 0;
···
162
162
{
163
163
const struct hi6421_spmi_reg_info *sreg;
164
164
165
-
sreg = container_of(rdev->desc, struct hi6421_spmi_reg_info, desc);
165
+
sreg = container_of_const(rdev->desc, struct hi6421_spmi_reg_info, desc);
166
166
167
167
if (!sreg->eco_uA || ((unsigned int)load_uA > sreg->eco_uA))
168
168
return REGULATOR_MODE_NORMAL;
+1
-1
drivers/regulator/irq_helpers.c
+1
-1
drivers/regulator/irq_helpers.c
+3
-3
drivers/regulator/max77650-regulator.c
+3
-3
drivers/regulator/max77650-regulator.c
···
68
68
struct regmap *map;
69
69
int val, rv, en;
70
70
71
-
rdesc = container_of(rdev->desc, struct max77650_regulator_desc, desc);
71
+
rdesc = container_of_const(rdev->desc, struct max77650_regulator_desc, desc);
72
72
map = rdev_get_regmap(rdev);
73
73
74
74
rv = regmap_read(map, rdesc->regB, &val);
···
85
85
const struct max77650_regulator_desc *rdesc;
86
86
struct regmap *map;
87
87
88
-
rdesc = container_of(rdev->desc, struct max77650_regulator_desc, desc);
88
+
rdesc = container_of_const(rdev->desc, struct max77650_regulator_desc, desc);
89
89
map = rdev_get_regmap(rdev);
90
90
91
91
return regmap_update_bits(map, rdesc->regB,
···
98
98
const struct max77650_regulator_desc *rdesc;
99
99
struct regmap *map;
100
100
101
-
rdesc = container_of(rdev->desc, struct max77650_regulator_desc, desc);
101
+
rdesc = container_of_const(rdev->desc, struct max77650_regulator_desc, desc);
102
102
map = rdev_get_regmap(rdev);
103
103
104
104
return regmap_update_bits(map, rdesc->regB,
+3
-3
drivers/regulator/mt6315-regulator.c
+3
-3
drivers/regulator/mt6315-regulator.c
···
80
80
int ret, regval;
81
81
u32 modeset_mask;
82
82
83
-
info = container_of(rdev->desc, struct mt6315_regulator_info, desc);
83
+
info = container_of_const(rdev->desc, struct mt6315_regulator_info, desc);
84
84
modeset_mask = init->modeset_mask[rdev_get_id(rdev)];
85
85
ret = regmap_read(rdev->regmap, MT6315_BUCK_TOP_4PHASE_ANA_CON42, ®val);
86
86
if (ret != 0) {
···
111
111
int ret, val, curr_mode;
112
112
u32 modeset_mask;
113
113
114
-
info = container_of(rdev->desc, struct mt6315_regulator_info, desc);
114
+
info = container_of_const(rdev->desc, struct mt6315_regulator_info, desc);
115
115
modeset_mask = init->modeset_mask[rdev_get_id(rdev)];
116
116
curr_mode = mt6315_regulator_get_mode(rdev);
117
117
switch (mode) {
···
165
165
int ret;
166
166
u32 regval;
167
167
168
-
info = container_of(rdev->desc, struct mt6315_regulator_info, desc);
168
+
info = container_of_const(rdev->desc, struct mt6315_regulator_info, desc);
169
169
ret = regmap_read(rdev->regmap, info->status_reg, ®val);
170
170
if (ret < 0) {
171
171
dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret);
+345
drivers/regulator/mt6316-regulator.c
+345
drivers/regulator/mt6316-regulator.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
//
3
+
// Copyright (c) 2024 MediaTek Inc.
4
+
// Copyright (c) 2025 Collabora Ltd
5
+
// AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
6
+
7
+
#include <linux/module.h>
8
+
#include <linux/of.h>
9
+
#include <linux/regmap.h>
10
+
#include <linux/spmi.h>
11
+
12
+
#include <linux/regulator/driver.h>
13
+
#include <linux/regulator/machine.h>
14
+
#include <linux/regulator/of_regulator.h>
15
+
16
+
#define MT6316_BUCK_MODE_AUTO 0
17
+
#define MT6316_BUCK_MODE_FORCE_PWM 1
18
+
#define MT6316_BUCK_MODE_LP 2
19
+
20
+
#define MT6316_CHIP_ID 0x20b
21
+
#define MT6316_BUCK_TOP_CON0 0x1440
22
+
#define EN_SET_OFFSET 0x1
23
+
#define EN_CLR_OFFSET 0x2
24
+
25
+
#define MT6316_BUCK_TOP_CON1 0x1443
26
+
27
+
#define MT6316_BUCK_TOP_ELR0 0x1448
28
+
#define MT6316_BUCK_TOP_ELR2 0x144a
29
+
#define MT6316_BUCK_TOP_ELR4 0x144c
30
+
#define MT6316_BUCK_TOP_ELR6 0x144e
31
+
#define MT6316_VSEL_MASK GENMASK(8, 0)
32
+
33
+
#define MT6316_VBUCK1_DBG 0x14a8
34
+
#define MT6316_VBUCK2_DBG 0x1528
35
+
#define MT6316_VBUCK3_DBG 0x15a8
36
+
#define MT6316_VBUCK4_DBG 0x1628
37
+
#define MT6316_BUCK_QI BIT(0)
38
+
39
+
#define MT6316_BUCK_TOP_4PHASE_TOP_ANA_CON0 0x1688
40
+
#define MT6316_BUCK_TOP_4PHASE_TOP_ELR_0 0x1690
41
+
42
+
enum mt6316_type {
43
+
MT6316_TYPE_2PHASE,
44
+
MT6316_TYPE_3PHASE,
45
+
MT6316_TYPE_4PHASE
46
+
};
47
+
48
+
/**
49
+
* struct mt6316_regulator_info - MT6316 regulators information
50
+
* @desc: Regulator description structure
51
+
* @debug_reg: Debug register for regulator status
52
+
* @lp_mode_reg: Low Power mode register (normal/idle)
53
+
* @lp_mode_mask: Low Power mode regulator mask
54
+
* @modeset_reg: AUTO/PWM mode register
55
+
* @modeset_mask: AUTO/PWM regulator mask
56
+
*/
57
+
struct mt6316_regulator_info {
58
+
struct regulator_desc desc;
59
+
u16 debug_reg;
60
+
u16 lp_mode_reg;
61
+
u16 lp_mode_mask;
62
+
u16 modeset_reg;
63
+
u16 modeset_mask;
64
+
};
65
+
66
+
#define MT6316_BUCK(match, vreg_id, min, max, step, vs_reg) \
67
+
{ \
68
+
.desc = { \
69
+
.name = match, \
70
+
.of_match = of_match_ptr(match), \
71
+
.ops = &mt6316_vreg_setclr_ops, \
72
+
.type = REGULATOR_VOLTAGE, \
73
+
.owner = THIS_MODULE, \
74
+
.n_voltages = (max - min) / step + 1, \
75
+
.min_uV = min, \
76
+
.uV_step = step, \
77
+
.enable_reg = MT6316_BUCK_TOP_CON0, \
78
+
.enable_mask = BIT(vreg_id - 1), \
79
+
.vsel_reg = vs_reg, \
80
+
.vsel_mask = MT6316_VSEL_MASK, \
81
+
.of_map_mode = mt6316_map_mode, \
82
+
}, \
83
+
.lp_mode_reg = MT6316_BUCK_TOP_CON1, \
84
+
.lp_mode_mask = BIT(vreg_id - 1), \
85
+
.modeset_reg = MT6316_BUCK_TOP_4PHASE_TOP_ANA_CON0, \
86
+
.modeset_mask = BIT(vreg_id - 1), \
87
+
.debug_reg = MT6316_VBUCK##vreg_id##_DBG, \
88
+
}
89
+
90
+
/* Values in some MT6316 registers are big endian, 9 bits long... */
91
+
static inline u16 mt6316_be9_to_cpu(u16 val)
92
+
{
93
+
return ((val >> 8) & BIT(0)) | ((val & GENMASK(7, 0)) << 1);
94
+
}
95
+
96
+
static inline u16 mt6316_cpu_to_be9(u16 val)
97
+
{
98
+
return ((val & BIT(0)) << 8) | (val >> 1);
99
+
}
100
+
101
+
static unsigned int mt6316_map_mode(u32 mode)
102
+
{
103
+
switch (mode) {
104
+
case MT6316_BUCK_MODE_AUTO:
105
+
return REGULATOR_MODE_NORMAL;
106
+
case MT6316_BUCK_MODE_FORCE_PWM:
107
+
return REGULATOR_MODE_FAST;
108
+
case MT6316_BUCK_MODE_LP:
109
+
return REGULATOR_MODE_IDLE;
110
+
default:
111
+
return REGULATOR_MODE_INVALID;
112
+
}
113
+
}
114
+
115
+
static int mt6316_vreg_enable_setclr(struct regulator_dev *rdev)
116
+
{
117
+
return regmap_write(rdev->regmap, rdev->desc->enable_reg + EN_SET_OFFSET,
118
+
rdev->desc->enable_mask);
119
+
}
120
+
121
+
static int mt6316_vreg_disable_setclr(struct regulator_dev *rdev)
122
+
{
123
+
return regmap_write(rdev->regmap, rdev->desc->enable_reg + EN_CLR_OFFSET,
124
+
rdev->desc->enable_mask);
125
+
}
126
+
127
+
static int mt6316_regulator_set_voltage_sel(struct regulator_dev *rdev, unsigned int selector)
128
+
{
129
+
u16 val = mt6316_cpu_to_be9(selector);
130
+
131
+
return regmap_bulk_write(rdev->regmap, rdev->desc->vsel_reg, &val, sizeof(val));
132
+
}
133
+
134
+
static int mt6316_regulator_get_voltage_sel(struct regulator_dev *rdev)
135
+
{
136
+
u16 val;
137
+
int ret;
138
+
139
+
ret = regmap_bulk_read(rdev->regmap, rdev->desc->vsel_reg, &val, sizeof(val));
140
+
if (ret)
141
+
return ret;
142
+
143
+
return mt6316_be9_to_cpu(val & rdev->desc->vsel_mask);
144
+
}
145
+
146
+
static int mt6316_regulator_get_status(struct regulator_dev *rdev)
147
+
{
148
+
struct mt6316_regulator_info *info = rdev_get_drvdata(rdev);
149
+
u32 val;
150
+
int ret;
151
+
152
+
ret = regmap_read(rdev->regmap, info->debug_reg, &val);
153
+
if (ret)
154
+
return ret;
155
+
156
+
return val & MT6316_BUCK_QI ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;
157
+
}
158
+
159
+
static unsigned int mt6316_regulator_get_mode(struct regulator_dev *rdev)
160
+
{
161
+
struct mt6316_regulator_info *info = rdev_get_drvdata(rdev);
162
+
unsigned int val;
163
+
int ret;
164
+
165
+
ret = regmap_read(rdev->regmap, info->modeset_reg, &val);
166
+
if (ret) {
167
+
dev_err(&rdev->dev, "Failed to get mode: %d\n", ret);
168
+
return ret;
169
+
}
170
+
171
+
if ((val & info->modeset_mask) == info->modeset_mask)
172
+
return REGULATOR_MODE_FAST;
173
+
174
+
ret = regmap_read(rdev->regmap, info->lp_mode_reg, &val);
175
+
val &= info->lp_mode_mask;
176
+
if (ret) {
177
+
dev_err(&rdev->dev, "Failed to get lp mode: %d\n", ret);
178
+
return ret;
179
+
}
180
+
181
+
return val ? REGULATOR_MODE_IDLE : REGULATOR_MODE_NORMAL;
182
+
}
183
+
184
+
static int mt6316_regulator_set_mode(struct regulator_dev *rdev,
185
+
unsigned int mode)
186
+
{
187
+
struct mt6316_regulator_info *info = rdev_get_drvdata(rdev);
188
+
struct regmap *regmap = rdev->regmap;
189
+
int cur_mode, ret;
190
+
191
+
switch (mode) {
192
+
case REGULATOR_MODE_FAST:
193
+
ret = regmap_set_bits(regmap, info->modeset_reg, info->modeset_mask);
194
+
break;
195
+
case REGULATOR_MODE_NORMAL:
196
+
cur_mode = mt6316_regulator_get_mode(rdev);
197
+
if (cur_mode < 0) {
198
+
ret = cur_mode;
199
+
break;
200
+
}
201
+
202
+
if (cur_mode == REGULATOR_MODE_FAST) {
203
+
ret = regmap_clear_bits(regmap, info->modeset_reg, info->modeset_mask);
204
+
break;
205
+
} else if (cur_mode == REGULATOR_MODE_IDLE) {
206
+
ret = regmap_clear_bits(regmap, info->lp_mode_reg, info->lp_mode_mask);
207
+
if (ret == 0)
208
+
usleep_range(100, 200);
209
+
} else {
210
+
ret = 0;
211
+
}
212
+
break;
213
+
case REGULATOR_MODE_IDLE:
214
+
ret = regmap_set_bits(regmap, info->lp_mode_reg, info->lp_mode_mask);
215
+
break;
216
+
default:
217
+
ret = -EINVAL;
218
+
}
219
+
220
+
if (ret) {
221
+
dev_err(&rdev->dev, "Failed to set mode %u: %d\n", mode, ret);
222
+
return ret;
223
+
}
224
+
225
+
return 0;
226
+
}
227
+
228
+
static const struct regulator_ops mt6316_vreg_setclr_ops = {
229
+
.list_voltage = regulator_list_voltage_linear,
230
+
.map_voltage = regulator_map_voltage_linear,
231
+
.set_voltage_sel = mt6316_regulator_set_voltage_sel,
232
+
.get_voltage_sel = mt6316_regulator_get_voltage_sel,
233
+
.set_voltage_time_sel = regulator_set_voltage_time_sel,
234
+
.enable = mt6316_vreg_enable_setclr,
235
+
.disable = mt6316_vreg_disable_setclr,
236
+
.is_enabled = regulator_is_enabled_regmap,
237
+
.get_status = mt6316_regulator_get_status,
238
+
.set_mode = mt6316_regulator_set_mode,
239
+
.get_mode = mt6316_regulator_get_mode,
240
+
};
241
+
242
+
/* MT6316BP/VP - 2+2 phase buck */
243
+
static struct mt6316_regulator_info mt6316bv_regulators[] = {
244
+
MT6316_BUCK("vbuck12", 1, 0, 1277500, 2500, MT6316_BUCK_TOP_ELR0),
245
+
MT6316_BUCK("vbuck34", 3, 0, 1277500, 2500, MT6316_BUCK_TOP_ELR4),
246
+
};
247
+
248
+
/* MT6316CP/HP/KP - 3+1 phase buck */
249
+
static struct mt6316_regulator_info mt6316chk_regulators[] = {
250
+
MT6316_BUCK("vbuck124", 1, 0, 1277500, 2500, MT6316_BUCK_TOP_ELR0),
251
+
MT6316_BUCK("vbuck3", 3, 0, 1277500, 2500, MT6316_BUCK_TOP_ELR4),
252
+
};
253
+
254
+
/* MT6316DP/TP - 4 phase buck */
255
+
static struct mt6316_regulator_info mt6316dt_regulators[] = {
256
+
MT6316_BUCK("vbuck1234", 1, 0, 1277500, 2500, MT6316_BUCK_TOP_ELR0),
257
+
};
258
+
259
+
static const struct regmap_config mt6316_spmi_regmap_config = {
260
+
.reg_bits = 16,
261
+
.val_bits = 8,
262
+
.max_register = 0x1700,
263
+
.fast_io = true,
264
+
};
265
+
266
+
static int mt6316_regulator_probe(struct spmi_device *sdev)
267
+
{
268
+
struct regulator_config config = {};
269
+
struct mt6316_regulator_info *info;
270
+
struct regulator_dev *rdev;
271
+
enum mt6316_type type;
272
+
int num_vregs, ret;
273
+
unsigned int i;
274
+
u32 chip_id;
275
+
276
+
config.regmap = devm_regmap_init_spmi_ext(sdev, &mt6316_spmi_regmap_config);
277
+
if (IS_ERR(config.regmap))
278
+
return PTR_ERR(config.regmap);
279
+
280
+
/*
281
+
* The first read is expected to fail: this PMIC needs to be woken up
282
+
* and that can be done with any activity over the SPMI bus.
283
+
*/
284
+
regmap_read(config.regmap, MT6316_CHIP_ID, &chip_id);
285
+
286
+
/* The second read, instead, shall not fail! */
287
+
ret = regmap_read(config.regmap, MT6316_CHIP_ID, &chip_id);
288
+
if (ret) {
289
+
dev_err(&sdev->dev, "Cannot read Chip ID!\n");
290
+
return ret;
291
+
}
292
+
dev_dbg(&sdev->dev, "Chip ID: 0x%x\n", chip_id);
293
+
294
+
config.dev = &sdev->dev;
295
+
296
+
type = (uintptr_t)device_get_match_data(&sdev->dev);
297
+
switch (type) {
298
+
case MT6316_TYPE_2PHASE:
299
+
info = mt6316bv_regulators;
300
+
num_vregs = ARRAY_SIZE(mt6316bv_regulators);
301
+
break;
302
+
case MT6316_TYPE_3PHASE:
303
+
info = mt6316chk_regulators;
304
+
num_vregs = ARRAY_SIZE(mt6316chk_regulators);
305
+
break;
306
+
case MT6316_TYPE_4PHASE:
307
+
info = mt6316dt_regulators;
308
+
num_vregs = ARRAY_SIZE(mt6316dt_regulators);
309
+
break;
310
+
default:
311
+
return -EINVAL;
312
+
}
313
+
314
+
for (i = 0; i < num_vregs; i++) {
315
+
config.driver_data = &info[i];
316
+
317
+
rdev = devm_regulator_register(&sdev->dev, &info[i].desc, &config);
318
+
if (IS_ERR(rdev))
319
+
return dev_err_probe(&sdev->dev, PTR_ERR(rdev),
320
+
"failed to register %s\n", info[i].desc.name);
321
+
}
322
+
323
+
return 0;
324
+
}
325
+
326
+
static const struct of_device_id mt6316_regulator_match[] = {
327
+
{ .compatible = "mediatek,mt6316b-regulator", .data = (void *)MT6316_TYPE_2PHASE },
328
+
{ .compatible = "mediatek,mt6316c-regulator", .data = (void *)MT6316_TYPE_3PHASE },
329
+
{ .compatible = "mediatek,mt6316d-regulator", .data = (void *)MT6316_TYPE_4PHASE },
330
+
{ /* sentinel */ }
331
+
};
332
+
333
+
static struct spmi_driver mt6316_regulator_driver = {
334
+
.driver = {
335
+
.name = "mt6316-regulator",
336
+
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
337
+
.of_match_table = mt6316_regulator_match,
338
+
},
339
+
.probe = mt6316_regulator_probe,
340
+
};
341
+
module_spmi_driver(mt6316_regulator_driver);
342
+
343
+
MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
344
+
MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6316 PMIC");
345
+
MODULE_LICENSE("GPL");
+1
-1
drivers/regulator/mt6358-regulator.c
+1
-1
drivers/regulator/mt6358-regulator.c
···
31
31
u32 modeset_mask;
32
32
};
33
33
34
-
#define to_regulator_info(x) container_of((x), struct mt6358_regulator_info, desc)
34
+
#define to_regulator_info(x) container_of_const((x), struct mt6358_regulator_info, desc)
35
35
36
36
#define MT6358_BUCK(match, vreg, supply, min, max, step, \
37
37
vosel_mask, _da_vsel_reg, _da_vsel_mask, \
+938
drivers/regulator/mt6363-regulator.c
+938
drivers/regulator/mt6363-regulator.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
//
3
+
// Copyright (c) 2024 MediaTek Inc.
4
+
// Copyright (c) 2025 Collabora Ltd
5
+
// AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
6
+
7
+
#include <linux/bitfield.h>
8
+
#include <linux/delay.h>
9
+
#include <linux/devm-helpers.h>
10
+
#include <linux/err.h>
11
+
#include <linux/interrupt.h>
12
+
#include <linux/irq.h>
13
+
#include <linux/irqdomain.h>
14
+
#include <linux/kernel.h>
15
+
#include <linux/module.h>
16
+
#include <linux/of.h>
17
+
#include <linux/of_device.h>
18
+
#include <linux/of_irq.h>
19
+
#include <linux/platform_device.h>
20
+
#include <linux/regmap.h>
21
+
#include <linux/spmi.h>
22
+
23
+
#include <linux/regulator/driver.h>
24
+
#include <linux/regulator/machine.h>
25
+
#include <linux/regulator/mt6363-regulator.h>
26
+
#include <linux/regulator/of_regulator.h>
27
+
28
+
#define MT6363_REGULATOR_MODE_NORMAL 0
29
+
#define MT6363_REGULATOR_MODE_FCCM 1
30
+
#define MT6363_REGULATOR_MODE_LP 2
31
+
#define MT6363_REGULATOR_MODE_ULP 3
32
+
33
+
#define EN_SET_OFFSET 0x1
34
+
#define EN_CLR_OFFSET 0x2
35
+
#define OP_CFG_OFFSET 0x5
36
+
37
+
#define NORMAL_OP_CFG 0x10
38
+
#define NORMAL_OP_EN 0x800000
39
+
40
+
#define OC_IRQ_ENABLE_DELAY_MS 10
41
+
42
+
/* Unlock keys for TMA and BUCK_TOP */
43
+
#define MT6363_TMA_UNLOCK_VALUE 0x9c9c
44
+
#define MT6363_BUCK_TOP_UNLOCK_VALUE 0x5543
45
+
46
+
enum {
47
+
MT6363_ID_VBUCK1,
48
+
MT6363_ID_VBUCK2,
49
+
MT6363_ID_VBUCK3,
50
+
MT6363_ID_VBUCK4,
51
+
MT6363_ID_VBUCK5,
52
+
MT6363_ID_VBUCK6,
53
+
MT6363_ID_VBUCK7,
54
+
MT6363_ID_VS1,
55
+
MT6363_ID_VS2,
56
+
MT6363_ID_VS3,
57
+
MT6363_ID_VA12_1,
58
+
MT6363_ID_VA12_2,
59
+
MT6363_ID_VA15,
60
+
MT6363_ID_VAUX18,
61
+
MT6363_ID_VCN13,
62
+
MT6363_ID_VCN15,
63
+
MT6363_ID_VEMC,
64
+
MT6363_ID_VIO075,
65
+
MT6363_ID_VIO18,
66
+
MT6363_ID_VM18,
67
+
MT6363_ID_VSRAM_APU,
68
+
MT6363_ID_VSRAM_CPUB,
69
+
MT6363_ID_VSRAM_CPUM,
70
+
MT6363_ID_VSRAM_CPUL,
71
+
MT6363_ID_VSRAM_DIGRF,
72
+
MT6363_ID_VSRAM_MDFE,
73
+
MT6363_ID_VSRAM_MODEM,
74
+
MT6363_ID_VRF09,
75
+
MT6363_ID_VRF12,
76
+
MT6363_ID_VRF13,
77
+
MT6363_ID_VRF18,
78
+
MT6363_ID_VRFIO18,
79
+
MT6363_ID_VTREF18,
80
+
MT6363_ID_VUFS12,
81
+
MT6363_ID_VUFS18,
82
+
};
83
+
84
+
/**
85
+
* struct mt6363_regulator_info - MT6363 regulators information
86
+
* @desc: Regulator description structure
87
+
* @lp_mode_reg: Low Power mode register (normal/idle)
88
+
* @lp_mode_mask: Low Power mode regulator mask
89
+
* @hw_lp_mode_reg: Hardware voted Low Power mode register (normal/idle)
90
+
* @hw_lp_mode_mask: Hardware voted Low Power mode regulator mask
91
+
* @modeset_reg: AUTO/PWM mode register
92
+
* @modeset_mask: AUTO/PWM regulator mask
93
+
* @lp_imax_uA: Maximum load current (microamps), for Low Power mode only
94
+
* @op_en_reg: Operation mode enablement register
95
+
* @orig_op_en: Backup of a regulator's operation mode enablement register
96
+
* @orig_op_cfg: Backup of a regulator's operation mode configuration register
97
+
* @oc_work: Delayed work for enabling overcurrent IRQ
98
+
* @hwirq: PMIC-Internal HW Interrupt for overcurrent event
99
+
* @virq: Mapped Interrupt for overcurrent event
100
+
*/
101
+
struct mt6363_regulator_info {
102
+
struct regulator_desc desc;
103
+
u16 lp_mode_reg;
104
+
u16 lp_mode_mask;
105
+
u16 hw_lp_mode_reg;
106
+
u16 hw_lp_mode_mask;
107
+
u16 modeset_reg;
108
+
u16 modeset_mask;
109
+
int lp_imax_uA;
110
+
u16 op_en_reg;
111
+
u32 orig_op_en;
112
+
u8 orig_op_cfg;
113
+
struct delayed_work oc_work;
114
+
u8 hwirq;
115
+
int virq;
116
+
};
117
+
118
+
#define MT6363_BUCK(match, vreg, min, max, step, en_reg, lp_reg, \
119
+
mset_reg, ocp_intn) \
120
+
[MT6363_ID_##vreg] = { \
121
+
.desc = { \
122
+
.name = match, \
123
+
.supply_name = "vsys-"match, \
124
+
.of_match = of_match_ptr(match), \
125
+
.ops = &mt6363_vreg_setclr_ops, \
126
+
.type = REGULATOR_VOLTAGE, \
127
+
.id = MT6363_ID_##vreg, \
128
+
.owner = THIS_MODULE, \
129
+
.n_voltages = (max - min) / step + 1, \
130
+
.min_uV = min, \
131
+
.uV_step = step, \
132
+
.enable_reg = en_reg, \
133
+
.enable_mask = BIT(MT6363_RG_BUCK_##vreg##_EN_BIT), \
134
+
.vsel_reg = MT6363_RG_BUCK_##vreg##_VOSEL_ADDR, \
135
+
.vsel_mask = MT6363_RG_BUCK_##vreg##_VOSEL_MASK, \
136
+
.of_map_mode = mt6363_map_mode, \
137
+
}, \
138
+
.lp_mode_reg = lp_reg, \
139
+
.lp_mode_mask = BIT(MT6363_RG_BUCK_##vreg##_LP_BIT), \
140
+
.hw_lp_mode_reg = MT6363_BUCK_##vreg##_HW_LP_MODE, \
141
+
.hw_lp_mode_mask = 0xc, \
142
+
.modeset_reg = mset_reg, \
143
+
.modeset_mask = BIT(MT6363_RG_##vreg##_FCCM_BIT), \
144
+
.lp_imax_uA = 100000, \
145
+
.op_en_reg = MT6363_BUCK_##vreg##_OP_EN_0, \
146
+
.hwirq = ocp_intn, \
147
+
}
148
+
149
+
#define MT6363_LDO_LINEAR_OPS(match, vreg, in_sup, vops, min, max, \
150
+
step, buck_reg, ocp_intn) \
151
+
[MT6363_ID_##vreg] = { \
152
+
.desc = { \
153
+
.name = match, \
154
+
.supply_name = in_sup, \
155
+
.of_match = of_match_ptr(match), \
156
+
.ops = &vops, \
157
+
.type = REGULATOR_VOLTAGE, \
158
+
.id = MT6363_ID_##vreg, \
159
+
.owner = THIS_MODULE, \
160
+
.n_voltages = (max - min) / step + 1, \
161
+
.min_uV = min, \
162
+
.uV_step = step, \
163
+
.enable_reg = MT6363_RG_##buck_reg##_EN_ADDR, \
164
+
.enable_mask = BIT(MT6363_RG_LDO_##vreg##_EN_BIT), \
165
+
.vsel_reg = MT6363_RG_LDO_##vreg##_VOSEL_ADDR, \
166
+
.vsel_mask = MT6363_RG_LDO_##vreg##_VOSEL_MASK, \
167
+
.of_map_mode = mt6363_map_mode, \
168
+
}, \
169
+
.lp_mode_reg = MT6363_RG_##buck_reg##_LP_ADDR, \
170
+
.lp_mode_mask = BIT(MT6363_RG_LDO_##vreg##_LP_BIT), \
171
+
.hw_lp_mode_reg = MT6363_LDO_##vreg##_HW_LP_MODE, \
172
+
.hw_lp_mode_mask = 0x4, \
173
+
.hwirq = ocp_intn, \
174
+
}
175
+
176
+
#define MT6363_LDO_L_SC(match, vreg, inp, min, max, step, buck_reg, \
177
+
ocp_intn) \
178
+
MT6363_LDO_LINEAR_OPS(match, vreg, inp, mt6363_vreg_setclr_ops, \
179
+
min, max, step, buck_reg, ocp_intn)
180
+
181
+
#define MT6363_LDO_L(match, vreg, inp, min, max, step, buck_reg, \
182
+
ocp_intn) \
183
+
MT6363_LDO_LINEAR_OPS(match, vreg, inp, mt6363_ldo_linear_ops, \
184
+
min, max, step, buck_reg, ocp_intn)
185
+
186
+
#define MT6363_LDO_LINEAR_CAL_OPS(match, vreg, in_sup, vops, vrnum, \
187
+
ocp_intn) \
188
+
[MT6363_ID_##vreg] = { \
189
+
.desc = { \
190
+
.name = match, \
191
+
.supply_name = in_sup, \
192
+
.of_match = of_match_ptr(match), \
193
+
.ops = &vops, \
194
+
.type = REGULATOR_VOLTAGE, \
195
+
.id = MT6363_ID_##vreg, \
196
+
.owner = THIS_MODULE, \
197
+
.n_voltages = ARRAY_SIZE(ldo_volt_ranges##vrnum) * 11, \
198
+
.linear_ranges = ldo_volt_ranges##vrnum, \
199
+
.n_linear_ranges = ARRAY_SIZE(ldo_volt_ranges##vrnum), \
200
+
.linear_range_selectors_bitfield = ldos_cal_selectors, \
201
+
.enable_reg = MT6363_RG_LDO_##vreg##_ADDR, \
202
+
.enable_mask = BIT(MT6363_RG_LDO_##vreg##_EN_BIT), \
203
+
.vsel_reg = MT6363_RG_##vreg##_VOCAL_ADDR, \
204
+
.vsel_mask = MT6363_RG_##vreg##_VOCAL_MASK, \
205
+
.vsel_range_reg = MT6363_RG_##vreg##_VOSEL_ADDR, \
206
+
.vsel_range_mask = MT6363_RG_##vreg##_VOSEL_MASK, \
207
+
.of_map_mode = mt6363_map_mode, \
208
+
}, \
209
+
.lp_mode_reg = MT6363_RG_LDO_##vreg##_ADDR, \
210
+
.lp_mode_mask = BIT(MT6363_RG_LDO_##vreg##_LP_BIT), \
211
+
.hw_lp_mode_reg = MT6363_LDO_##vreg##_HW_LP_MODE, \
212
+
.hw_lp_mode_mask = 0x4, \
213
+
.lp_imax_uA = 10000, \
214
+
.op_en_reg = MT6363_LDO_##vreg##_OP_EN0, \
215
+
.hwirq = ocp_intn, \
216
+
}
217
+
218
+
#define MT6363_LDO_VT(match, vreg, inp, vranges_num, ocp_intn) \
219
+
MT6363_LDO_LINEAR_CAL_OPS(match, vreg, inp, mt6363_ldo_vtable_ops,\
220
+
vranges_num, ocp_intn)
221
+
222
+
static const unsigned int ldos_cal_selectors[] = {
223
+
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
224
+
};
225
+
226
+
static const struct linear_range ldo_volt_ranges0[] = {
227
+
REGULATOR_LINEAR_RANGE(1200000, 0, 10, 10000),
228
+
REGULATOR_LINEAR_RANGE(1300000, 0, 10, 10000),
229
+
REGULATOR_LINEAR_RANGE(1500000, 0, 10, 10000),
230
+
REGULATOR_LINEAR_RANGE(1700000, 0, 10, 10000),
231
+
REGULATOR_LINEAR_RANGE(1800000, 0, 10, 10000),
232
+
REGULATOR_LINEAR_RANGE(2000000, 0, 10, 10000),
233
+
REGULATOR_LINEAR_RANGE(2500000, 0, 10, 10000),
234
+
REGULATOR_LINEAR_RANGE(2600000, 0, 10, 10000),
235
+
REGULATOR_LINEAR_RANGE(2700000, 0, 10, 10000),
236
+
REGULATOR_LINEAR_RANGE(2800000, 0, 10, 10000),
237
+
REGULATOR_LINEAR_RANGE(2900000, 0, 10, 10000),
238
+
REGULATOR_LINEAR_RANGE(3000000, 0, 10, 10000),
239
+
REGULATOR_LINEAR_RANGE(3100000, 0, 10, 10000),
240
+
REGULATOR_LINEAR_RANGE(3300000, 0, 10, 10000),
241
+
REGULATOR_LINEAR_RANGE(3400000, 0, 10, 10000),
242
+
REGULATOR_LINEAR_RANGE(3500000, 0, 10, 10000)
243
+
};
244
+
245
+
static const struct linear_range ldo_volt_ranges1[] = {
246
+
REGULATOR_LINEAR_RANGE(900000, 0, 10, 10000),
247
+
REGULATOR_LINEAR_RANGE(1000000, 0, 10, 10000),
248
+
REGULATOR_LINEAR_RANGE(1100000, 0, 10, 10000),
249
+
REGULATOR_LINEAR_RANGE(1200000, 0, 10, 10000),
250
+
REGULATOR_LINEAR_RANGE(1300000, 0, 10, 10000),
251
+
REGULATOR_LINEAR_RANGE(1700000, 0, 10, 10000),
252
+
REGULATOR_LINEAR_RANGE(1800000, 0, 10, 10000),
253
+
REGULATOR_LINEAR_RANGE(1810000, 0, 10, 10000)
254
+
};
255
+
256
+
static const struct linear_range ldo_volt_ranges2[] = {
257
+
REGULATOR_LINEAR_RANGE(1800000, 0, 10, 10000),
258
+
REGULATOR_LINEAR_RANGE(1900000, 0, 10, 10000),
259
+
REGULATOR_LINEAR_RANGE(2000000, 0, 10, 10000),
260
+
REGULATOR_LINEAR_RANGE(2100000, 0, 10, 10000),
261
+
REGULATOR_LINEAR_RANGE(2200000, 0, 10, 10000),
262
+
REGULATOR_LINEAR_RANGE(2300000, 0, 10, 10000),
263
+
REGULATOR_LINEAR_RANGE(2400000, 0, 10, 10000),
264
+
REGULATOR_LINEAR_RANGE(2500000, 0, 10, 10000),
265
+
REGULATOR_LINEAR_RANGE(2600000, 0, 10, 10000),
266
+
REGULATOR_LINEAR_RANGE(2700000, 0, 10, 10000),
267
+
REGULATOR_LINEAR_RANGE(2800000, 0, 10, 10000),
268
+
REGULATOR_LINEAR_RANGE(2900000, 0, 10, 10000),
269
+
REGULATOR_LINEAR_RANGE(3000000, 0, 10, 10000),
270
+
REGULATOR_LINEAR_RANGE(3100000, 0, 10, 10000),
271
+
REGULATOR_LINEAR_RANGE(3200000, 0, 10, 10000),
272
+
REGULATOR_LINEAR_RANGE(3300000, 0, 10, 10000)
273
+
};
274
+
275
+
static const struct linear_range ldo_volt_ranges3[] = {
276
+
REGULATOR_LINEAR_RANGE(600000, 0, 10, 10000),
277
+
REGULATOR_LINEAR_RANGE(700000, 0, 10, 10000),
278
+
REGULATOR_LINEAR_RANGE(800000, 0, 10, 10000),
279
+
REGULATOR_LINEAR_RANGE(900000, 0, 10, 10000),
280
+
REGULATOR_LINEAR_RANGE(1000000, 0, 10, 10000),
281
+
REGULATOR_LINEAR_RANGE(1100000, 0, 10, 10000),
282
+
REGULATOR_LINEAR_RANGE(1200000, 0, 10, 10000),
283
+
REGULATOR_LINEAR_RANGE(1300000, 0, 10, 10000),
284
+
REGULATOR_LINEAR_RANGE(1400000, 0, 10, 10000),
285
+
REGULATOR_LINEAR_RANGE(1500000, 0, 10, 10000),
286
+
REGULATOR_LINEAR_RANGE(1600000, 0, 10, 10000),
287
+
REGULATOR_LINEAR_RANGE(1700000, 0, 10, 10000),
288
+
REGULATOR_LINEAR_RANGE(1800000, 0, 10, 10000),
289
+
REGULATOR_LINEAR_RANGE(1900000, 0, 10, 10000),
290
+
REGULATOR_LINEAR_RANGE(2000000, 0, 10, 10000),
291
+
REGULATOR_LINEAR_RANGE(2100000, 0, 10, 10000)
292
+
};
293
+
294
+
static const struct linear_range ldo_volt_ranges4[] = {
295
+
REGULATOR_LINEAR_RANGE(550000, 0, 10, 5000),
296
+
REGULATOR_LINEAR_RANGE(600000, 0, 10, 5000),
297
+
REGULATOR_LINEAR_RANGE(650000, 0, 10, 5000),
298
+
REGULATOR_LINEAR_RANGE(700000, 0, 10, 5000),
299
+
REGULATOR_LINEAR_RANGE(750000, 0, 10, 5000),
300
+
REGULATOR_LINEAR_RANGE(800000, 0, 10, 5000),
301
+
REGULATOR_LINEAR_RANGE(900000, 0, 10, 5000),
302
+
REGULATOR_LINEAR_RANGE(950000, 0, 10, 5000),
303
+
REGULATOR_LINEAR_RANGE(1000000, 0, 10, 5000),
304
+
REGULATOR_LINEAR_RANGE(1050000, 0, 10, 5000),
305
+
REGULATOR_LINEAR_RANGE(1100000, 0, 10, 5000),
306
+
REGULATOR_LINEAR_RANGE(1150000, 0, 10, 5000),
307
+
REGULATOR_LINEAR_RANGE(1700000, 0, 10, 5000),
308
+
REGULATOR_LINEAR_RANGE(1750000, 0, 10, 5000),
309
+
REGULATOR_LINEAR_RANGE(1800000, 0, 10, 5000),
310
+
REGULATOR_LINEAR_RANGE(1850000, 0, 10, 5000)
311
+
};
312
+
313
+
static const struct linear_range ldo_volt_ranges5[] = {
314
+
REGULATOR_LINEAR_RANGE(600000, 0, 10, 5000),
315
+
REGULATOR_LINEAR_RANGE(650000, 0, 10, 5000),
316
+
REGULATOR_LINEAR_RANGE(700000, 0, 10, 5000),
317
+
REGULATOR_LINEAR_RANGE(750000, 0, 10, 5000),
318
+
REGULATOR_LINEAR_RANGE(800000, 0, 10, 5000)
319
+
};
320
+
321
+
static int mt6363_vreg_enable_setclr(struct regulator_dev *rdev)
322
+
{
323
+
return regmap_write(rdev->regmap, rdev->desc->enable_reg + EN_SET_OFFSET,
324
+
rdev->desc->enable_mask);
325
+
}
326
+
327
+
static int mt6363_vreg_disable_setclr(struct regulator_dev *rdev)
328
+
{
329
+
return regmap_write(rdev->regmap, rdev->desc->enable_reg + EN_CLR_OFFSET,
330
+
rdev->desc->enable_mask);
331
+
}
332
+
333
+
static inline unsigned int mt6363_map_mode(unsigned int mode)
334
+
{
335
+
switch (mode) {
336
+
case MT6363_REGULATOR_MODE_NORMAL:
337
+
return REGULATOR_MODE_NORMAL;
338
+
case MT6363_REGULATOR_MODE_FCCM:
339
+
return REGULATOR_MODE_FAST;
340
+
case MT6363_REGULATOR_MODE_LP:
341
+
return REGULATOR_MODE_IDLE;
342
+
case MT6363_REGULATOR_MODE_ULP:
343
+
return REGULATOR_MODE_STANDBY;
344
+
default:
345
+
return REGULATOR_MODE_INVALID;
346
+
}
347
+
}
348
+
349
+
static unsigned int mt6363_regulator_get_mode(struct regulator_dev *rdev)
350
+
{
351
+
struct mt6363_regulator_info *info = rdev_get_drvdata(rdev);
352
+
unsigned int val;
353
+
int ret;
354
+
355
+
if (info->modeset_reg) {
356
+
ret = regmap_read(rdev->regmap, info->modeset_reg, &val);
357
+
if (ret) {
358
+
dev_err(&rdev->dev, "Failed to get mt6363 mode: %d\n", ret);
359
+
return ret;
360
+
}
361
+
362
+
if (val & info->modeset_mask)
363
+
return REGULATOR_MODE_FAST;
364
+
} else {
365
+
val = 0;
366
+
}
367
+
368
+
ret = regmap_read(rdev->regmap, info->hw_lp_mode_reg, &val);
369
+
val &= info->hw_lp_mode_mask;
370
+
371
+
if (ret) {
372
+
dev_err(&rdev->dev, "Failed to get lp mode: %d\n", ret);
373
+
return ret;
374
+
}
375
+
376
+
if (val)
377
+
return REGULATOR_MODE_IDLE;
378
+
else
379
+
return REGULATOR_MODE_NORMAL;
380
+
}
381
+
382
+
static int mt6363_buck_unlock(struct regmap *map, bool unlock)
383
+
{
384
+
u16 buf = unlock ? MT6363_BUCK_TOP_UNLOCK_VALUE : 0;
385
+
386
+
return regmap_bulk_write(map, MT6363_BUCK_TOP_KEY_PROT_LO, &buf, sizeof(buf));
387
+
}
388
+
389
+
static int mt6363_regulator_set_mode(struct regulator_dev *rdev,
390
+
unsigned int mode)
391
+
{
392
+
struct mt6363_regulator_info *info = rdev_get_drvdata(rdev);
393
+
struct regmap *regmap = rdev->regmap;
394
+
int cur_mode, ret;
395
+
396
+
if (!info->modeset_reg && mode == REGULATOR_MODE_FAST)
397
+
return -EOPNOTSUPP;
398
+
399
+
switch (mode) {
400
+
case REGULATOR_MODE_FAST:
401
+
ret = mt6363_buck_unlock(regmap, true);
402
+
if (ret)
403
+
break;
404
+
405
+
ret = regmap_set_bits(regmap, info->modeset_reg, info->modeset_mask);
406
+
407
+
mt6363_buck_unlock(regmap, false);
408
+
break;
409
+
case REGULATOR_MODE_NORMAL:
410
+
cur_mode = mt6363_regulator_get_mode(rdev);
411
+
if (cur_mode < 0) {
412
+
ret = cur_mode;
413
+
break;
414
+
}
415
+
416
+
if (cur_mode == REGULATOR_MODE_FAST) {
417
+
ret = mt6363_buck_unlock(regmap, true);
418
+
if (ret)
419
+
break;
420
+
421
+
ret = regmap_clear_bits(regmap, info->modeset_reg, info->modeset_mask);
422
+
423
+
mt6363_buck_unlock(regmap, false);
424
+
break;
425
+
} else if (cur_mode == REGULATOR_MODE_IDLE) {
426
+
ret = regmap_clear_bits(regmap, info->lp_mode_reg, info->lp_mode_mask);
427
+
if (ret == 0)
428
+
usleep_range(100, 200);
429
+
} else {
430
+
ret = 0;
431
+
}
432
+
break;
433
+
case REGULATOR_MODE_IDLE:
434
+
ret = regmap_set_bits(regmap, info->lp_mode_reg, info->lp_mode_mask);
435
+
break;
436
+
default:
437
+
ret = -EINVAL;
438
+
}
439
+
440
+
if (ret) {
441
+
dev_err(&rdev->dev, "Failed to set mode %u: %d\n", mode, ret);
442
+
return ret;
443
+
}
444
+
445
+
return 0;
446
+
}
447
+
448
+
static int mt6363_regulator_set_load(struct regulator_dev *rdev, int load_uA)
449
+
{
450
+
struct mt6363_regulator_info *info = rdev_get_drvdata(rdev);
451
+
unsigned int opmode_cfg, opmode_en;
452
+
int i, ret;
453
+
454
+
if (!info->lp_imax_uA)
455
+
return -EINVAL;
456
+
457
+
if (load_uA >= info->lp_imax_uA) {
458
+
ret = mt6363_regulator_set_mode(rdev, REGULATOR_MODE_NORMAL);
459
+
if (ret)
460
+
return ret;
461
+
462
+
opmode_cfg = NORMAL_OP_CFG;
463
+
opmode_en = NORMAL_OP_EN;
464
+
} else {
465
+
opmode_cfg = info->orig_op_cfg;
466
+
opmode_en = info->orig_op_en;
467
+
}
468
+
469
+
ret = regmap_write(rdev->regmap, info->op_en_reg + OP_CFG_OFFSET, opmode_cfg);
470
+
if (ret)
471
+
return ret;
472
+
473
+
for (i = 0; i < 3; i++) {
474
+
ret = regmap_write(rdev->regmap, info->op_en_reg + i,
475
+
(opmode_en >> (i * 8)) & GENMASK(7, 0));
476
+
if (ret)
477
+
return ret;
478
+
}
479
+
480
+
return 0;
481
+
}
482
+
483
+
static int mt6363_vemc_set_voltage_sel(struct regulator_dev *rdev, unsigned int sel)
484
+
{
485
+
const u16 tma_unlock_key = MT6363_TMA_UNLOCK_VALUE;
486
+
const struct regulator_desc *rdesc = rdev->desc;
487
+
struct regmap *regmap = rdev->regmap;
488
+
unsigned int range, val;
489
+
int i, ret;
490
+
u16 mask;
491
+
492
+
for (i = 0; i < rdesc->n_linear_ranges; i++) {
493
+
const struct linear_range *r = &rdesc->linear_ranges[i];
494
+
unsigned int voltages_in_range = linear_range_values_in_range(r);
495
+
496
+
if (sel < voltages_in_range)
497
+
break;
498
+
sel -= voltages_in_range;
499
+
}
500
+
501
+
if (i == rdesc->n_linear_ranges)
502
+
return -EINVAL;
503
+
504
+
ret = regmap_read(rdev->regmap, MT6363_TOP_TRAP, &val);
505
+
if (ret)
506
+
return ret;
507
+
508
+
if (val > 1)
509
+
return -EINVAL;
510
+
511
+
/* Unlock TMA for writing */
512
+
ret = regmap_bulk_write(rdev->regmap, MT6363_TOP_TMA_KEY_L,
513
+
&tma_unlock_key, sizeof(tma_unlock_key));
514
+
if (ret)
515
+
return ret;
516
+
517
+
/* If HW trapping value is 1, use VEMC_VOSEL_1 instead of VEMC_VOSEL_0 */
518
+
if (val == 1) {
519
+
mask = MT6363_RG_VEMC_VOSEL_1_MASK;
520
+
sel = FIELD_PREP(MT6363_RG_VEMC_VOSEL_1_MASK, sel);
521
+
} else {
522
+
mask = rdesc->vsel_mask;
523
+
}
524
+
525
+
sel <<= ffs(rdesc->vsel_mask) - 1;
526
+
sel += rdesc->linear_ranges[i].min_sel;
527
+
528
+
range = rdesc->linear_range_selectors_bitfield[i];
529
+
range <<= ffs(rdesc->vsel_range_mask) - 1;
530
+
531
+
/* Write to the vreg calibration register for voltage finetuning */
532
+
ret = regmap_update_bits(regmap, rdesc->vsel_range_reg,
533
+
rdesc->vsel_range_mask, range);
534
+
if (ret)
535
+
goto lock_tma;
536
+
537
+
/* Function must return the result of this write operation */
538
+
ret = regmap_update_bits(regmap, rdesc->vsel_reg, mask, sel);
539
+
540
+
lock_tma:
541
+
/* Unconditionally re-lock TMA */
542
+
val = 0;
543
+
regmap_bulk_write(rdev->regmap, MT6363_TOP_TMA_KEY_L, &val, 2);
544
+
545
+
return ret;
546
+
}
547
+
548
+
static int mt6363_vemc_get_voltage_sel(struct regulator_dev *rdev)
549
+
{
550
+
const struct regulator_desc *rdesc = rdev->desc;
551
+
unsigned int vosel, trap, calsel;
552
+
int vcal, vsel, range, ret;
553
+
554
+
ret = regmap_read(rdev->regmap, rdesc->vsel_reg, &vosel);
555
+
if (ret)
556
+
return ret;
557
+
558
+
ret = regmap_read(rdev->regmap, rdesc->vsel_range_reg, &calsel);
559
+
if (ret)
560
+
return ret;
561
+
562
+
calsel &= rdesc->vsel_range_mask;
563
+
for (range = 0; range < rdesc->n_linear_ranges; range++)
564
+
if (rdesc->linear_range_selectors_bitfield[range] != calsel)
565
+
break;
566
+
567
+
if (range == rdesc->n_linear_ranges)
568
+
return -EINVAL;
569
+
570
+
ret = regmap_read(rdev->regmap, MT6363_TOP_TRAP, &trap);
571
+
if (ret)
572
+
return ret;
573
+
574
+
/* If HW trapping value is 1, use VEMC_VOSEL_1 instead of VEMC_VOSEL_0 */
575
+
if (trap > 1)
576
+
return -EINVAL;
577
+
else if (trap == 1)
578
+
vsel = FIELD_GET(MT6363_RG_VEMC_VOSEL_1_MASK, vosel);
579
+
else
580
+
vsel = vosel & rdesc->vsel_mask;
581
+
582
+
vcal = linear_range_values_in_range_array(rdesc->linear_ranges, range);
583
+
584
+
return vsel + vcal;
585
+
}
586
+
587
+
static int mt6363_va15_set_voltage_sel(struct regulator_dev *rdev, unsigned int sel)
588
+
{
589
+
struct regmap *regmap = rdev->regmap;
590
+
int ret;
591
+
592
+
ret = mt6363_buck_unlock(regmap, true);
593
+
if (ret)
594
+
return ret;
595
+
596
+
ret = regulator_set_voltage_sel_pickable_regmap(rdev, sel);
597
+
if (ret)
598
+
goto va15_unlock;
599
+
600
+
ret = regmap_update_bits(regmap, MT6363_RG_BUCK_EFUSE_RSV1,
601
+
MT6363_RG_BUCK_EFUSE_RSV1_MASK, sel);
602
+
if (ret)
603
+
goto va15_unlock;
604
+
605
+
va15_unlock:
606
+
mt6363_buck_unlock(rdev->regmap, false);
607
+
return ret;
608
+
}
609
+
610
+
static void mt6363_oc_irq_enable_work(struct work_struct *work)
611
+
{
612
+
struct delayed_work *dwork = to_delayed_work(work);
613
+
struct mt6363_regulator_info *info =
614
+
container_of(dwork, struct mt6363_regulator_info, oc_work);
615
+
616
+
enable_irq(info->virq);
617
+
}
618
+
619
+
static irqreturn_t mt6363_oc_isr(int irq, void *data)
620
+
{
621
+
struct regulator_dev *rdev = (struct regulator_dev *)data;
622
+
struct mt6363_regulator_info *info = rdev_get_drvdata(rdev);
623
+
624
+
disable_irq_nosync(info->virq);
625
+
626
+
if (regulator_is_enabled_regmap(rdev))
627
+
regulator_notifier_call_chain(rdev, REGULATOR_EVENT_OVER_CURRENT, NULL);
628
+
629
+
schedule_delayed_work(&info->oc_work, msecs_to_jiffies(OC_IRQ_ENABLE_DELAY_MS));
630
+
631
+
return IRQ_HANDLED;
632
+
}
633
+
634
+
static int mt6363_set_ocp(struct regulator_dev *rdev, int lim, int severity, bool enable)
635
+
{
636
+
struct mt6363_regulator_info *info = rdev_get_drvdata(rdev);
637
+
638
+
/* MT6363 supports only enabling protection and does not support limits */
639
+
if (lim || severity != REGULATOR_SEVERITY_PROT || !enable)
640
+
return -EOPNOTSUPP;
641
+
642
+
/* If there is no OCP interrupt, there's nothing to set */
643
+
if (info->virq <= 0)
644
+
return -EOPNOTSUPP;
645
+
646
+
return devm_request_threaded_irq(&rdev->dev, info->virq, NULL,
647
+
mt6363_oc_isr, IRQF_ONESHOT,
648
+
info->desc.name, rdev);
649
+
}
650
+
651
+
static const struct regulator_ops mt6363_vreg_setclr_ops = {
652
+
.list_voltage = regulator_list_voltage_linear,
653
+
.map_voltage = regulator_map_voltage_linear,
654
+
.set_voltage_sel = regulator_set_voltage_sel_regmap,
655
+
.get_voltage_sel = regulator_get_voltage_sel_regmap,
656
+
.set_voltage_time_sel = regulator_set_voltage_time_sel,
657
+
.enable = mt6363_vreg_enable_setclr,
658
+
.disable = mt6363_vreg_disable_setclr,
659
+
.is_enabled = regulator_is_enabled_regmap,
660
+
.set_mode = mt6363_regulator_set_mode,
661
+
.get_mode = mt6363_regulator_get_mode,
662
+
.set_load = mt6363_regulator_set_load,
663
+
.set_over_current_protection = mt6363_set_ocp,
664
+
};
665
+
666
+
static const struct regulator_ops mt6363_ldo_linear_ops = {
667
+
.list_voltage = regulator_list_voltage_linear,
668
+
.map_voltage = regulator_map_voltage_linear,
669
+
.set_voltage_sel = regulator_set_voltage_sel_regmap,
670
+
.get_voltage_sel = regulator_get_voltage_sel_regmap,
671
+
.set_voltage_time_sel = regulator_set_voltage_time_sel,
672
+
.enable = regulator_enable_regmap,
673
+
.disable = regulator_disable_regmap,
674
+
.is_enabled = regulator_is_enabled_regmap,
675
+
.set_mode = mt6363_regulator_set_mode,
676
+
.get_mode = mt6363_regulator_get_mode,
677
+
.set_over_current_protection = mt6363_set_ocp,
678
+
};
679
+
680
+
static const struct regulator_ops mt6363_ldo_vtable_ops = {
681
+
.list_voltage = regulator_list_voltage_pickable_linear_range,
682
+
.map_voltage = regulator_map_voltage_pickable_linear_range,
683
+
.set_voltage_sel = regulator_set_voltage_sel_pickable_regmap,
684
+
.get_voltage_sel = regulator_get_voltage_sel_pickable_regmap,
685
+
.set_voltage_time_sel = regulator_set_voltage_time_sel,
686
+
.enable = regulator_enable_regmap,
687
+
.disable = regulator_disable_regmap,
688
+
.is_enabled = regulator_is_enabled_regmap,
689
+
.set_mode = mt6363_regulator_set_mode,
690
+
.get_mode = mt6363_regulator_get_mode,
691
+
.set_load = mt6363_regulator_set_load,
692
+
.set_over_current_protection = mt6363_set_ocp,
693
+
};
694
+
695
+
static const struct regulator_ops mt6363_ldo_vemc_ops = {
696
+
.list_voltage = regulator_list_voltage_pickable_linear_range,
697
+
.map_voltage = regulator_map_voltage_pickable_linear_range,
698
+
.set_voltage_sel = mt6363_vemc_set_voltage_sel,
699
+
.get_voltage_sel = mt6363_vemc_get_voltage_sel,
700
+
.set_voltage_time_sel = regulator_set_voltage_time_sel,
701
+
.enable = regulator_enable_regmap,
702
+
.disable = regulator_disable_regmap,
703
+
.is_enabled = regulator_is_enabled_regmap,
704
+
.set_mode = mt6363_regulator_set_mode,
705
+
.get_mode = mt6363_regulator_get_mode,
706
+
.set_load = mt6363_regulator_set_load,
707
+
.set_over_current_protection = mt6363_set_ocp,
708
+
};
709
+
710
+
static const struct regulator_ops mt6363_ldo_va15_ops = {
711
+
.list_voltage = regulator_list_voltage_pickable_linear_range,
712
+
.map_voltage = regulator_map_voltage_pickable_linear_range,
713
+
.set_voltage_sel = mt6363_va15_set_voltage_sel,
714
+
.get_voltage_sel = regulator_get_voltage_sel_pickable_regmap,
715
+
.set_voltage_time_sel = regulator_set_voltage_time_sel,
716
+
.enable = regulator_enable_regmap,
717
+
.disable = regulator_disable_regmap,
718
+
.is_enabled = regulator_is_enabled_regmap,
719
+
.set_mode = mt6363_regulator_set_mode,
720
+
.get_mode = mt6363_regulator_get_mode,
721
+
.set_load = mt6363_regulator_set_load,
722
+
.set_over_current_protection = mt6363_set_ocp,
723
+
};
724
+
725
+
/* The array is indexed by id(MT6363_ID_XXX) */
726
+
static struct mt6363_regulator_info mt6363_regulators[] = {
727
+
MT6363_BUCK("vbuck1", VBUCK1, 0, 1193750, 6250, MT6363_RG_BUCK0_EN_ADDR,
728
+
MT6363_RG_BUCK0_LP_ADDR, MT6363_RG_BUCK0_FCCM_ADDR, 1),
729
+
MT6363_BUCK("vbuck2", VBUCK2, 0, 1193750, 6250, MT6363_RG_BUCK0_EN_ADDR,
730
+
MT6363_RG_BUCK0_LP_ADDR, MT6363_RG_BUCK0_FCCM_ADDR, 2),
731
+
MT6363_BUCK("vbuck3", VBUCK3, 0, 1193750, 6250, MT6363_RG_BUCK0_EN_ADDR,
732
+
MT6363_RG_BUCK0_LP_ADDR, MT6363_RG_BUCK0_FCCM_ADDR, 3),
733
+
MT6363_BUCK("vbuck4", VBUCK4, 0, 1193750, 6250, MT6363_RG_BUCK0_EN_ADDR,
734
+
MT6363_RG_BUCK0_LP_ADDR, MT6363_RG_BUCK0_1_FCCM_ADDR, 4),
735
+
MT6363_BUCK("vbuck5", VBUCK5, 0, 1193750, 6250, MT6363_RG_BUCK0_EN_ADDR,
736
+
MT6363_RG_BUCK0_LP_ADDR, MT6363_RG_BUCK0_1_FCCM_ADDR, 5),
737
+
MT6363_BUCK("vbuck6", VBUCK6, 0, 1193750, 6250, MT6363_RG_BUCK0_EN_ADDR,
738
+
MT6363_RG_BUCK0_LP_ADDR, MT6363_RG_BUCK0_1_FCCM_ADDR, 6),
739
+
MT6363_BUCK("vbuck7", VBUCK7, 0, 1193750, 6250, MT6363_RG_BUCK0_EN_ADDR,
740
+
MT6363_RG_BUCK0_LP_ADDR, MT6363_RG_BUCK0_1_FCCM_ADDR, 7),
741
+
MT6363_BUCK("vs1", VS1, 0, 2200000, 12500, MT6363_RG_BUCK1_EN_ADDR,
742
+
MT6363_RG_BUCK1_LP_ADDR, MT6363_RG_VS1_FCCM_ADDR, 8),
743
+
MT6363_BUCK("vs2", VS2, 0, 1600000, 12500, MT6363_RG_BUCK0_EN_ADDR,
744
+
MT6363_RG_BUCK0_LP_ADDR, MT6363_RG_BUCK0_FCCM_ADDR, 0),
745
+
MT6363_BUCK("vs3", VS3, 0, 1193750, 6250, MT6363_RG_BUCK1_EN_ADDR,
746
+
MT6363_RG_BUCK1_LP_ADDR, MT6363_RG_VS3_FCCM_ADDR, 9),
747
+
MT6363_LDO_VT("va12-1", VA12_1, "vs2-ldo2", 3, 37),
748
+
MT6363_LDO_VT("va12-2", VA12_2, "vs2-ldo2", 3, 38),
749
+
MT6363_LDO_LINEAR_CAL_OPS("va15", VA15, "vs1-ldo1", mt6363_ldo_va15_ops, 3, 39),
750
+
MT6363_LDO_VT("vaux18", VAUX18, "vsys-ldo1", 2, 31),
751
+
MT6363_LDO_VT("vcn13", VCN13, "vs2-ldo2", 1, 17),
752
+
MT6363_LDO_VT("vcn15", VCN15, "vs1-ldo2", 3, 16),
753
+
MT6363_LDO_LINEAR_CAL_OPS("vemc", VEMC, "vsys-ldo1", mt6363_ldo_vemc_ops, 0, 32),
754
+
MT6363_LDO_VT("vio0p75", VIO075, "vs1-ldo1", 5, 36),
755
+
MT6363_LDO_VT("vio18", VIO18, "vs1-ldo2", 3, 35),
756
+
MT6363_LDO_VT("vm18", VM18, "vs1-ldo1", 4, 40),
757
+
MT6363_LDO_L("vsram-apu", VSRAM_APU, "vs3-ldo1", 400000, 1193750, 6250, BUCK1, 30),
758
+
MT6363_LDO_L("vsram-cpub", VSRAM_CPUB, "vs2-ldo1", 400000, 1193750, 6250, BUCK1, 27),
759
+
MT6363_LDO_L("vsram-cpum", VSRAM_CPUM, "vs2-ldo1", 400000, 1193750, 6250, BUCK1, 28),
760
+
MT6363_LDO_L("vsram-cpul", VSRAM_CPUL, "vs2-ldo2", 400000, 1193750, 6250, BUCK1, 29),
761
+
MT6363_LDO_L_SC("vsram-digrf", VSRAM_DIGRF, "vs3-ldo1", 400000, 1193750, 6250, BUCK1, 23),
762
+
MT6363_LDO_L_SC("vsram-mdfe", VSRAM_MDFE, "vs3-ldo1", 400000, 1193750, 6250, BUCK1, 24),
763
+
MT6363_LDO_L_SC("vsram-modem", VSRAM_MODEM, "vs3-ldo2", 400000, 1193750, 6250, BUCK1, 25),
764
+
MT6363_LDO_VT("vrf0p9", VRF09, "vs3-ldo2", 1, 18),
765
+
MT6363_LDO_VT("vrf12", VRF12, "vs2-ldo1", 3, 19),
766
+
MT6363_LDO_VT("vrf13", VRF13, "vs2-ldo1", 1, 20),
767
+
MT6363_LDO_VT("vrf18", VRF18, "vs1-ldo1", 3, 21),
768
+
MT6363_LDO_VT("vrf-io18", VRFIO18, "vs1-ldo1", 3, 22),
769
+
MT6363_LDO_VT("vtref18", VTREF18, "vsys-ldo1", 2, 26),
770
+
MT6363_LDO_VT("vufs12", VUFS12, "vs2-ldo1", 4, 33),
771
+
MT6363_LDO_VT("vufs18", VUFS18, "vs1-ldo2", 3, 34),
772
+
};
773
+
774
+
static int mt6363_backup_op_setting(struct regmap *map, struct mt6363_regulator_info *info)
775
+
{
776
+
unsigned int i, val;
777
+
int ret;
778
+
779
+
ret = regmap_read(map, info->op_en_reg + OP_CFG_OFFSET, &val);
780
+
if (ret)
781
+
return ret;
782
+
783
+
info->orig_op_cfg = val;
784
+
785
+
for (i = 0; i < 3; i++) {
786
+
ret = regmap_read(map, info->op_en_reg + i, &val);
787
+
if (ret)
788
+
return ret;
789
+
790
+
info->orig_op_en |= val << (i * 8);
791
+
}
792
+
793
+
return 0;
794
+
}
795
+
796
+
static void mt6363_irq_remove(void *data)
797
+
{
798
+
int *virq = data;
799
+
800
+
irq_dispose_mapping(*virq);
801
+
}
802
+
803
+
static void mt6363_spmi_remove(void *data)
804
+
{
805
+
struct spmi_device *sdev = data;
806
+
807
+
spmi_device_remove(sdev);
808
+
};
809
+
810
+
static struct regmap *mt6363_spmi_register_regmap(struct device *dev)
811
+
{
812
+
struct regmap_config mt6363_regmap_config = {
813
+
.reg_bits = 16,
814
+
.val_bits = 16,
815
+
.max_register = 0x1f90,
816
+
.fast_io = true,
817
+
};
818
+
struct spmi_device *sdev, *sparent;
819
+
u32 base;
820
+
int ret;
821
+
822
+
if (!dev->parent)
823
+
return ERR_PTR(-ENODEV);
824
+
825
+
ret = device_property_read_u32(dev, "reg", &base);
826
+
if (ret)
827
+
return ERR_PTR(ret);
828
+
829
+
sparent = to_spmi_device(dev->parent);
830
+
if (!sparent)
831
+
return ERR_PTR(-ENODEV);
832
+
833
+
sdev = spmi_device_alloc(sparent->ctrl);
834
+
if (!sdev)
835
+
return ERR_PTR(-ENODEV);
836
+
837
+
sdev->usid = sparent->usid;
838
+
dev_set_name(&sdev->dev, "%d-%02x-regulator", sdev->ctrl->nr, sdev->usid);
839
+
ret = device_add(&sdev->dev);
840
+
if (ret) {
841
+
put_device(&sdev->dev);
842
+
return ERR_PTR(ret);
843
+
};
844
+
845
+
ret = devm_add_action_or_reset(dev, mt6363_spmi_remove, sdev);
846
+
if (ret)
847
+
return ERR_PTR(ret);
848
+
849
+
mt6363_regmap_config.reg_base = base;
850
+
851
+
return devm_regmap_init_spmi_ext(sdev, &mt6363_regmap_config);
852
+
}
853
+
854
+
static int mt6363_regulator_probe(struct platform_device *pdev)
855
+
{
856
+
struct device_node *interrupt_parent;
857
+
struct regulator_config config = {};
858
+
struct mt6363_regulator_info *info;
859
+
struct device *dev = &pdev->dev;
860
+
struct regulator_dev *rdev;
861
+
struct irq_domain *domain;
862
+
struct irq_fwspec fwspec;
863
+
struct spmi_device *sdev;
864
+
int i, ret;
865
+
866
+
config.regmap = mt6363_spmi_register_regmap(dev);
867
+
if (IS_ERR(config.regmap))
868
+
return dev_err_probe(dev, PTR_ERR(config.regmap),
869
+
"Cannot get regmap\n");
870
+
config.dev = dev;
871
+
sdev = to_spmi_device(dev->parent);
872
+
873
+
interrupt_parent = of_irq_find_parent(dev->of_node);
874
+
if (!interrupt_parent)
875
+
return dev_err_probe(dev, -EINVAL, "Cannot find IRQ parent\n");
876
+
877
+
domain = irq_find_host(interrupt_parent);
878
+
of_node_put(interrupt_parent);
879
+
fwspec.fwnode = domain->fwnode;
880
+
881
+
fwspec.param_count = 3;
882
+
fwspec.param[0] = sdev->usid;
883
+
fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
884
+
885
+
for (i = 0; i < ARRAY_SIZE(mt6363_regulators); i++) {
886
+
info = &mt6363_regulators[i];
887
+
888
+
fwspec.param[1] = info->hwirq;
889
+
info->virq = irq_create_fwspec_mapping(&fwspec);
890
+
if (!info->virq)
891
+
return dev_err_probe(dev, -EINVAL,
892
+
"Failed to map IRQ%d\n", info->hwirq);
893
+
894
+
ret = devm_add_action_or_reset(dev, mt6363_irq_remove, &info->virq);
895
+
if (ret) {
896
+
irq_dispose_mapping(info->hwirq);
897
+
return ret;
898
+
}
899
+
900
+
config.driver_data = info;
901
+
INIT_DELAYED_WORK(&info->oc_work, mt6363_oc_irq_enable_work);
902
+
903
+
rdev = devm_regulator_register(dev, &info->desc, &config);
904
+
if (IS_ERR(rdev))
905
+
return dev_err_probe(dev, PTR_ERR(rdev),
906
+
"failed to register %s\n", info->desc.name);
907
+
908
+
if (info->lp_imax_uA) {
909
+
ret = mt6363_backup_op_setting(config.regmap, info);
910
+
if (ret) {
911
+
dev_warn(dev, "Failed to backup op_setting for %s\n",
912
+
info->desc.name);
913
+
info->lp_imax_uA = 0;
914
+
}
915
+
}
916
+
}
917
+
918
+
return 0;
919
+
}
920
+
921
+
static const struct of_device_id mt6363_regulator_match[] = {
922
+
{ .compatible = "mediatek,mt6363-regulator" },
923
+
{ /* sentinel */ }
924
+
};
925
+
926
+
static struct platform_driver mt6363_regulator_driver = {
927
+
.driver = {
928
+
.name = "mt6363-regulator",
929
+
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
930
+
.of_match_table = mt6363_regulator_match,
931
+
},
932
+
.probe = mt6363_regulator_probe,
933
+
};
934
+
module_platform_driver(mt6363_regulator_driver);
935
+
936
+
MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
937
+
MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6363 PMIC");
938
+
MODULE_LICENSE("GPL");
+3
-3
drivers/regulator/of_regulator.c
+3
-3
drivers/regulator/of_regulator.c
···
79
79
80
80
static int of_get_regulation_constraints(struct device *dev,
81
81
struct device_node *np,
82
-
struct regulator_init_data **init_data,
82
+
struct regulator_init_data *init_data,
83
83
const struct regulator_desc *desc)
84
84
{
85
-
struct regulation_constraints *constraints = &(*init_data)->constraints;
85
+
struct regulation_constraints *constraints = &init_data->constraints;
86
86
struct regulator_state *suspend_state;
87
87
struct device_node *suspend_np;
88
88
unsigned int mode;
···
359
359
if (!init_data)
360
360
return NULL; /* Out of memory? */
361
361
362
-
if (of_get_regulation_constraints(dev, node, &init_data, desc))
362
+
if (of_get_regulation_constraints(dev, node, init_data, desc))
363
363
return NULL;
364
364
365
365
return init_data;
+176
-27
drivers/regulator/pca9450-regulator.c
+176
-27
drivers/regulator/pca9450-regulator.c
···
249
249
}
250
250
251
251
if (ret == 0) {
252
-
struct pca9450_regulator_desc *regulator = container_of(desc,
252
+
const struct pca9450_regulator_desc *regulator = container_of_const(desc,
253
253
struct pca9450_regulator_desc, desc);
254
254
255
255
/* Enable DVS control through PMIC_STBY_REQ for this BUCK */
···
263
263
const struct regulator_desc *desc,
264
264
struct regulator_config *cfg)
265
265
{
266
-
struct pca9450_regulator_desc *data = container_of(desc,
266
+
const struct pca9450_regulator_desc *data = container_of_const(desc,
267
267
struct pca9450_regulator_desc, desc);
268
268
const struct pc9450_dvs_config *dvs = &data->dvs;
269
269
unsigned int reg, mask;
···
308
308
309
309
static int pca9450_buck_set_mode(struct regulator_dev *rdev, unsigned int mode)
310
310
{
311
-
struct pca9450_regulator_desc *desc = container_of(rdev->desc,
311
+
const struct pca9450_regulator_desc *desc = container_of_const(rdev->desc,
312
312
struct pca9450_regulator_desc, desc);
313
313
const struct pc9450_dvs_config *dvs = &desc->dvs;
314
314
int val;
···
333
333
334
334
static unsigned int pca9450_buck_get_mode(struct regulator_dev *rdev)
335
335
{
336
-
struct pca9450_regulator_desc *desc = container_of(rdev->desc,
336
+
const struct pca9450_regulator_desc *desc = container_of_const(rdev->desc,
337
337
struct pca9450_regulator_desc, desc);
338
338
const struct pc9450_dvs_config *dvs = &desc->dvs;
339
339
int ret = 0, regval;
···
355
355
{
356
356
.desc = {
357
357
.name = "buck1",
358
+
.supply_name = "inb13",
358
359
.of_match = of_match_ptr("BUCK1"),
359
360
.regulators_node = of_match_ptr("regulators"),
360
361
.id = PCA9450_BUCK1,
···
389
388
{
390
389
.desc = {
391
390
.name = "buck2",
391
+
.supply_name = "inb26",
392
392
.of_match = of_match_ptr("BUCK2"),
393
393
.regulators_node = of_match_ptr("regulators"),
394
394
.id = PCA9450_BUCK2,
···
423
421
{
424
422
.desc = {
425
423
.name = "buck3",
424
+
.supply_name = "inb13",
426
425
.of_match = of_match_ptr("BUCK3"),
427
426
.regulators_node = of_match_ptr("regulators"),
428
427
.id = PCA9450_BUCK3,
···
457
454
{
458
455
.desc = {
459
456
.name = "buck4",
457
+
.supply_name = "inb45",
460
458
.of_match = of_match_ptr("BUCK4"),
461
459
.regulators_node = of_match_ptr("regulators"),
462
460
.id = PCA9450_BUCK4,
···
482
478
{
483
479
.desc = {
484
480
.name = "buck5",
481
+
.supply_name = "inb45",
485
482
.of_match = of_match_ptr("BUCK5"),
486
483
.regulators_node = of_match_ptr("regulators"),
487
484
.id = PCA9450_BUCK5,
···
507
502
{
508
503
.desc = {
509
504
.name = "buck6",
505
+
.supply_name = "inb26",
510
506
.of_match = of_match_ptr("BUCK6"),
511
507
.regulators_node = of_match_ptr("regulators"),
512
508
.id = PCA9450_BUCK6,
···
532
526
{
533
527
.desc = {
534
528
.name = "ldo1",
529
+
.supply_name = "inl1",
535
530
.of_match = of_match_ptr("LDO1"),
536
531
.regulators_node = of_match_ptr("regulators"),
537
532
.id = PCA9450_LDO1,
···
551
544
{
552
545
.desc = {
553
546
.name = "ldo2",
547
+
.supply_name = "inl1",
554
548
.of_match = of_match_ptr("LDO2"),
555
549
.regulators_node = of_match_ptr("regulators"),
556
550
.id = PCA9450_LDO2,
···
570
562
{
571
563
.desc = {
572
564
.name = "ldo3",
565
+
.supply_name = "inl1",
573
566
.of_match = of_match_ptr("LDO3"),
574
567
.regulators_node = of_match_ptr("regulators"),
575
568
.id = PCA9450_LDO3,
···
589
580
{
590
581
.desc = {
591
582
.name = "ldo4",
583
+
.supply_name = "inl1",
592
584
.of_match = of_match_ptr("LDO4"),
593
585
.regulators_node = of_match_ptr("regulators"),
594
586
.id = PCA9450_LDO4,
···
608
598
{
609
599
.desc = {
610
600
.name = "ldo5",
601
+
.supply_name = "inl1",
611
602
.of_match = of_match_ptr("LDO5"),
612
603
.regulators_node = of_match_ptr("regulators"),
613
604
.id = PCA9450_LDO5,
···
634
623
{
635
624
.desc = {
636
625
.name = "buck1",
626
+
.supply_name = "inb13",
637
627
.of_match = of_match_ptr("BUCK1"),
638
628
.regulators_node = of_match_ptr("regulators"),
639
629
.id = PCA9450_BUCK1,
···
668
656
{
669
657
.desc = {
670
658
.name = "buck2",
659
+
.supply_name = "inb26",
671
660
.of_match = of_match_ptr("BUCK2"),
672
661
.regulators_node = of_match_ptr("regulators"),
673
662
.id = PCA9450_BUCK2,
···
702
689
{
703
690
.desc = {
704
691
.name = "buck4",
692
+
.supply_name = "inb45",
705
693
.of_match = of_match_ptr("BUCK4"),
706
694
.regulators_node = of_match_ptr("regulators"),
707
695
.id = PCA9450_BUCK4,
···
727
713
{
728
714
.desc = {
729
715
.name = "buck5",
716
+
.supply_name = "inb45",
730
717
.of_match = of_match_ptr("BUCK5"),
731
718
.regulators_node = of_match_ptr("regulators"),
732
719
.id = PCA9450_BUCK5,
···
752
737
{
753
738
.desc = {
754
739
.name = "buck6",
740
+
.supply_name = "inb26",
755
741
.of_match = of_match_ptr("BUCK6"),
756
742
.regulators_node = of_match_ptr("regulators"),
757
743
.id = PCA9450_BUCK6,
···
777
761
{
778
762
.desc = {
779
763
.name = "ldo1",
764
+
.supply_name = "inl1",
780
765
.of_match = of_match_ptr("LDO1"),
781
766
.regulators_node = of_match_ptr("regulators"),
782
767
.id = PCA9450_LDO1,
···
796
779
{
797
780
.desc = {
798
781
.name = "ldo2",
782
+
.supply_name = "inl1",
799
783
.of_match = of_match_ptr("LDO2"),
800
784
.regulators_node = of_match_ptr("regulators"),
801
785
.id = PCA9450_LDO2,
···
815
797
{
816
798
.desc = {
817
799
.name = "ldo3",
800
+
.supply_name = "inl1",
818
801
.of_match = of_match_ptr("LDO3"),
819
802
.regulators_node = of_match_ptr("regulators"),
820
803
.id = PCA9450_LDO3,
···
834
815
{
835
816
.desc = {
836
817
.name = "ldo4",
818
+
.supply_name = "inl1",
837
819
.of_match = of_match_ptr("LDO4"),
838
820
.regulators_node = of_match_ptr("regulators"),
839
821
.id = PCA9450_LDO4,
···
853
833
{
854
834
.desc = {
855
835
.name = "ldo5",
836
+
.supply_name = "inl1",
856
837
.of_match = of_match_ptr("LDO5"),
857
838
.regulators_node = of_match_ptr("regulators"),
858
839
.id = PCA9450_LDO5,
···
875
854
{
876
855
.desc = {
877
856
.name = "buck1",
857
+
.supply_name = "inb13",
878
858
.of_match = of_match_ptr("BUCK1"),
879
859
.regulators_node = of_match_ptr("regulators"),
880
860
.id = PCA9450_BUCK1,
···
908
886
{
909
887
.desc = {
910
888
.name = "buck2",
889
+
.supply_name = "inb26",
911
890
.of_match = of_match_ptr("BUCK2"),
912
891
.regulators_node = of_match_ptr("regulators"),
913
892
.id = PCA9450_BUCK2,
···
941
918
{
942
919
.desc = {
943
920
.name = "buck4",
921
+
.supply_name = "inb45",
944
922
.of_match = of_match_ptr("BUCK4"),
945
923
.regulators_node = of_match_ptr("regulators"),
946
924
.id = PCA9450_BUCK4,
···
966
942
{
967
943
.desc = {
968
944
.name = "buck5",
945
+
.supply_name = "inb45",
969
946
.of_match = of_match_ptr("BUCK5"),
970
947
.regulators_node = of_match_ptr("regulators"),
971
948
.id = PCA9450_BUCK5,
···
991
966
{
992
967
.desc = {
993
968
.name = "buck6",
969
+
.supply_name = "inb26",
994
970
.of_match = of_match_ptr("BUCK6"),
995
971
.regulators_node = of_match_ptr("regulators"),
996
972
.id = PCA9450_BUCK6,
···
1016
990
{
1017
991
.desc = {
1018
992
.name = "ldo1",
993
+
.supply_name = "inl1",
1019
994
.of_match = of_match_ptr("LDO1"),
1020
995
.regulators_node = of_match_ptr("regulators"),
1021
996
.id = PCA9450_LDO1,
···
1035
1008
{
1036
1009
.desc = {
1037
1010
.name = "ldo3",
1011
+
.supply_name = "inl1",
1038
1012
.of_match = of_match_ptr("LDO3"),
1039
1013
.regulators_node = of_match_ptr("regulators"),
1040
1014
.id = PCA9450_LDO3,
···
1054
1026
{
1055
1027
.desc = {
1056
1028
.name = "ldo4",
1029
+
.supply_name = "inl1",
1057
1030
.of_match = of_match_ptr("LDO4"),
1058
1031
.regulators_node = of_match_ptr("regulators"),
1059
1032
.id = PCA9450_LDO4,
···
1073
1044
{
1074
1045
.desc = {
1075
1046
.name = "ldo5",
1047
+
.supply_name = "inl1",
1076
1048
.of_match = of_match_ptr("LDO5"),
1077
1049
.regulators_node = of_match_ptr("regulators"),
1078
1050
.id = PCA9450_LDO5,
···
1147
1117
return 0;
1148
1118
}
1149
1119
1120
+
static int pca9450_of_init(struct pca9450 *pca9450)
1121
+
{
1122
+
struct i2c_client *i2c = container_of(pca9450->dev, struct i2c_client, dev);
1123
+
int ret;
1124
+
unsigned int val;
1125
+
unsigned int reset_ctrl;
1126
+
unsigned int rstb_deb_ctrl;
1127
+
unsigned int t_on_deb, t_off_deb;
1128
+
unsigned int t_on_step, t_off_step;
1129
+
unsigned int t_restart;
1130
+
1131
+
if (of_property_read_bool(i2c->dev.of_node, "nxp,wdog_b-warm-reset"))
1132
+
reset_ctrl = WDOG_B_CFG_WARM;
1133
+
else
1134
+
reset_ctrl = WDOG_B_CFG_COLD_LDO12;
1135
+
1136
+
/* Set reset behavior on assertion of WDOG_B signal */
1137
+
ret = regmap_update_bits(pca9450->regmap, PCA9450_REG_RESET_CTRL,
1138
+
WDOG_B_CFG_MASK, reset_ctrl);
1139
+
if (ret)
1140
+
return dev_err_probe(&i2c->dev, ret, "Failed to set WDOG_B reset behavior\n");
1141
+
1142
+
ret = of_property_read_u32(i2c->dev.of_node, "npx,pmic-rst-b-debounce-ms", &val);
1143
+
if (ret == -EINVAL)
1144
+
rstb_deb_ctrl = T_PMIC_RST_DEB_50MS;
1145
+
else if (ret)
1146
+
return ret;
1147
+
else {
1148
+
switch (val) {
1149
+
case 10: rstb_deb_ctrl = T_PMIC_RST_DEB_10MS; break;
1150
+
case 50: rstb_deb_ctrl = T_PMIC_RST_DEB_50MS; break;
1151
+
case 100: rstb_deb_ctrl = T_PMIC_RST_DEB_100MS; break;
1152
+
case 500: rstb_deb_ctrl = T_PMIC_RST_DEB_500MS; break;
1153
+
case 1000: rstb_deb_ctrl = T_PMIC_RST_DEB_1S; break;
1154
+
case 2000: rstb_deb_ctrl = T_PMIC_RST_DEB_2S; break;
1155
+
case 4000: rstb_deb_ctrl = T_PMIC_RST_DEB_4S; break;
1156
+
case 8000: rstb_deb_ctrl = T_PMIC_RST_DEB_8S; break;
1157
+
default: return -EINVAL;
1158
+
}
1159
+
}
1160
+
ret = regmap_update_bits(pca9450->regmap, PCA9450_REG_RESET_CTRL,
1161
+
T_PMIC_RST_DEB_MASK, rstb_deb_ctrl);
1162
+
if (ret)
1163
+
return dev_err_probe(&i2c->dev, ret, "Failed to set PMIC_RST_B debounce time\n");
1164
+
1165
+
ret = of_property_read_u32(i2c->dev.of_node, "nxp,pmic-on-req-on-debounce-us", &val);
1166
+
if (ret == -EINVAL)
1167
+
t_on_deb = T_ON_DEB_20MS;
1168
+
else if (ret)
1169
+
return ret;
1170
+
else {
1171
+
switch (val) {
1172
+
case 120: t_on_deb = T_ON_DEB_120US; break;
1173
+
case 20000: t_on_deb = T_ON_DEB_20MS; break;
1174
+
case 100000: t_on_deb = T_ON_DEB_100MS; break;
1175
+
case 750000: t_on_deb = T_ON_DEB_750MS; break;
1176
+
default: return -EINVAL;
1177
+
}
1178
+
}
1179
+
1180
+
ret = of_property_read_u32(i2c->dev.of_node, "nxp,pmic-on-req-off-debounce-us", &val);
1181
+
if (ret == -EINVAL)
1182
+
t_off_deb = T_OFF_DEB_120US;
1183
+
else if (ret)
1184
+
return ret;
1185
+
else {
1186
+
switch (val) {
1187
+
case 120: t_off_deb = T_OFF_DEB_120US; break;
1188
+
case 2000: t_off_deb = T_OFF_DEB_2MS; break;
1189
+
default: return -EINVAL;
1190
+
}
1191
+
}
1192
+
1193
+
ret = of_property_read_u32(i2c->dev.of_node, "nxp,power-on-step-ms", &val);
1194
+
if (ret == -EINVAL)
1195
+
t_on_step = T_ON_STEP_2MS;
1196
+
else if (ret)
1197
+
return ret;
1198
+
else {
1199
+
switch (val) {
1200
+
case 1: t_on_step = T_ON_STEP_1MS; break;
1201
+
case 2: t_on_step = T_ON_STEP_2MS; break;
1202
+
case 4: t_on_step = T_ON_STEP_4MS; break;
1203
+
case 8: t_on_step = T_ON_STEP_8MS; break;
1204
+
default: return -EINVAL;
1205
+
}
1206
+
}
1207
+
1208
+
ret = of_property_read_u32(i2c->dev.of_node, "nxp,power-down-step-ms", &val);
1209
+
if (ret == -EINVAL)
1210
+
t_off_step = T_OFF_STEP_8MS;
1211
+
else if (ret)
1212
+
return ret;
1213
+
else {
1214
+
switch (val) {
1215
+
case 2: t_off_step = T_OFF_STEP_2MS; break;
1216
+
case 4: t_off_step = T_OFF_STEP_4MS; break;
1217
+
case 8: t_off_step = T_OFF_STEP_8MS; break;
1218
+
case 16: t_off_step = T_OFF_STEP_16MS; break;
1219
+
default: return -EINVAL;
1220
+
}
1221
+
}
1222
+
1223
+
ret = of_property_read_u32(i2c->dev.of_node, "nxp,restart-ms", &val);
1224
+
if (ret == -EINVAL)
1225
+
t_restart = T_RESTART_250MS;
1226
+
else if (ret)
1227
+
return ret;
1228
+
else {
1229
+
switch (val) {
1230
+
case 250: t_restart = T_RESTART_250MS; break;
1231
+
case 500: t_restart = T_RESTART_500MS; break;
1232
+
default: return -EINVAL;
1233
+
}
1234
+
}
1235
+
1236
+
ret = regmap_update_bits(pca9450->regmap, PCA9450_REG_PWRCTRL,
1237
+
T_ON_DEB_MASK | T_OFF_DEB_MASK | T_ON_STEP_MASK |
1238
+
T_OFF_STEP_MASK | T_RESTART_MASK,
1239
+
t_on_deb | t_off_deb | t_on_step |
1240
+
t_off_step | t_restart);
1241
+
if (ret)
1242
+
return dev_err_probe(&i2c->dev, ret,
1243
+
"Failed to set PWR_CTRL debounce configuration\n");
1244
+
1245
+
if (of_property_read_bool(i2c->dev.of_node, "nxp,i2c-lt-enable")) {
1246
+
/* Enable I2C Level Translator */
1247
+
ret = regmap_update_bits(pca9450->regmap, PCA9450_REG_CONFIG2,
1248
+
I2C_LT_MASK, I2C_LT_ON_STANDBY_RUN);
1249
+
if (ret)
1250
+
return dev_err_probe(&i2c->dev, ret,
1251
+
"Failed to enable I2C level translator\n");
1252
+
}
1253
+
1254
+
return 0;
1255
+
}
1256
+
1150
1257
static int pca9450_i2c_probe(struct i2c_client *i2c)
1151
1258
{
1152
1259
enum pca9450_chip_type type = (unsigned int)(uintptr_t)
···
1293
1126
struct regulator_dev *ldo5;
1294
1127
struct pca9450 *pca9450;
1295
1128
unsigned int device_id, i;
1296
-
unsigned int reset_ctrl;
1297
1129
int ret;
1298
1130
1299
1131
pca9450 = devm_kzalloc(&i2c->dev, sizeof(struct pca9450), GFP_KERNEL);
···
1390
1224
if (ret)
1391
1225
return dev_err_probe(&i2c->dev, ret, "Failed to clear PRESET_EN bit\n");
1392
1226
1393
-
if (of_property_read_bool(i2c->dev.of_node, "nxp,wdog_b-warm-reset"))
1394
-
reset_ctrl = WDOG_B_CFG_WARM;
1395
-
else
1396
-
reset_ctrl = WDOG_B_CFG_COLD_LDO12;
1397
-
1398
-
/* Set reset behavior on assertion of WDOG_B signal */
1399
-
ret = regmap_update_bits(pca9450->regmap, PCA9450_REG_RESET_CTRL,
1400
-
WDOG_B_CFG_MASK, reset_ctrl);
1227
+
ret = pca9450_of_init(pca9450);
1401
1228
if (ret)
1402
-
return dev_err_probe(&i2c->dev, ret, "Failed to set WDOG_B reset behavior\n");
1403
-
1404
-
if (of_property_read_bool(i2c->dev.of_node, "nxp,i2c-lt-enable")) {
1405
-
/* Enable I2C Level Translator */
1406
-
ret = regmap_update_bits(pca9450->regmap, PCA9450_REG_CONFIG2,
1407
-
I2C_LT_MASK, I2C_LT_ON_STANDBY_RUN);
1408
-
if (ret)
1409
-
return dev_err_probe(&i2c->dev, ret,
1410
-
"Failed to enable I2C level translator\n");
1411
-
}
1229
+
return dev_err_probe(&i2c->dev, ret, "Unable to parse OF data\n");
1412
1230
1413
1231
/*
1414
1232
* For LDO5 we need to be able to check the status of the SD_VSEL input in
···
1401
1251
* to this signal (if SION bit is set in IOMUX).
1402
1252
*/
1403
1253
pca9450->sd_vsel_gpio = gpiod_get_optional(&ldo5->dev, "sd-vsel", GPIOD_IN);
1404
-
if (IS_ERR(pca9450->sd_vsel_gpio)) {
1405
-
dev_err(&i2c->dev, "Failed to get SD_VSEL GPIO\n");
1406
-
return ret;
1407
-
}
1254
+
if (IS_ERR(pca9450->sd_vsel_gpio))
1255
+
return dev_err_probe(&i2c->dev, PTR_ERR(pca9450->sd_vsel_gpio),
1256
+
"Failed to get SD_VSEL GPIO\n");
1408
1257
1409
1258
pca9450->sd_vsel_fixed_low =
1410
1259
of_property_read_bool(ldo5->dev.of_node, "nxp,sd-vsel-fixed-low");
+429
drivers/regulator/pf1550-regulator.c
+429
drivers/regulator/pf1550-regulator.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
//
3
+
// regulator driver for the PF1550
4
+
//
5
+
// Copyright (C) 2016 Freescale Semiconductor, Inc.
6
+
// Robin Gong <yibin.gong@freescale.com>
7
+
//
8
+
// Portions Copyright (c) 2025 Savoir-faire Linux Inc.
9
+
// Samuel Kayode <samuel.kayode@savoirfairelinux.com>
10
+
//
11
+
12
+
#include <linux/err.h>
13
+
#include <linux/interrupt.h>
14
+
#include <linux/mfd/pf1550.h>
15
+
#include <linux/module.h>
16
+
#include <linux/platform_device.h>
17
+
#include <linux/regulator/driver.h>
18
+
#include <linux/regulator/machine.h>
19
+
20
+
#define PF1550_REGULATOR_IRQ_NR 11
21
+
#define PF1550_MAX_REGULATOR 7
22
+
23
+
struct pf1550_desc {
24
+
struct regulator_desc desc;
25
+
unsigned char stby_reg;
26
+
unsigned char stby_mask;
27
+
unsigned char stby_enable_reg;
28
+
unsigned char stby_enable_mask;
29
+
};
30
+
31
+
struct pf1550_regulator_info {
32
+
struct device *dev;
33
+
const struct pf1550_ddata *pf1550;
34
+
struct pf1550_desc regulator_descs[PF1550_MAX_REGULATOR];
35
+
struct regulator_dev *rdevs[PF1550_MAX_REGULATOR];
36
+
};
37
+
38
+
static const int pf1550_sw12_volts[] = {
39
+
1100000, 1200000, 1350000, 1500000, 1800000, 2500000, 3000000, 3300000,
40
+
};
41
+
42
+
static const int pf1550_ldo13_volts[] = {
43
+
750000, 800000, 850000, 900000, 950000, 1000000, 1050000, 1100000,
44
+
1150000, 1200000, 1250000, 1300000, 1350000, 1400000, 1450000, 1500000,
45
+
1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
46
+
2600000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000,
47
+
};
48
+
49
+
static int pf1550_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
50
+
{
51
+
int id = rdev_get_id(rdev);
52
+
unsigned int ramp_bits = 0;
53
+
int ret;
54
+
55
+
if (id > PF1550_VREFDDR)
56
+
return -EACCES;
57
+
58
+
if (ramp_delay < 0 || ramp_delay > 6250)
59
+
return -EINVAL;
60
+
61
+
ramp_delay = 6250 / ramp_delay;
62
+
ramp_bits = ramp_delay >> 1;
63
+
64
+
ret = regmap_update_bits(rdev->regmap, rdev->desc->vsel_reg + 4, 0x10,
65
+
ramp_bits << 4);
66
+
if (ret < 0)
67
+
dev_err(&rdev->dev, "ramp failed, err %d\n", ret);
68
+
69
+
return ret;
70
+
}
71
+
72
+
static int pf1550_set_suspend_enable(struct regulator_dev *rdev)
73
+
{
74
+
const struct pf1550_desc *desc = container_of_const(rdev->desc,
75
+
struct pf1550_desc,
76
+
desc);
77
+
unsigned int val = desc->stby_enable_mask;
78
+
79
+
return regmap_update_bits(rdev->regmap, desc->stby_enable_reg,
80
+
desc->stby_enable_mask, val);
81
+
}
82
+
83
+
static int pf1550_set_suspend_disable(struct regulator_dev *rdev)
84
+
{
85
+
const struct pf1550_desc *desc = container_of_const(rdev->desc,
86
+
struct pf1550_desc,
87
+
desc);
88
+
89
+
return regmap_update_bits(rdev->regmap, desc->stby_enable_reg,
90
+
desc->stby_enable_mask, 0);
91
+
}
92
+
93
+
static int pf1550_buck_set_table_suspend_voltage(struct regulator_dev *rdev,
94
+
int uV)
95
+
{
96
+
const struct pf1550_desc *desc = container_of_const(rdev->desc,
97
+
struct pf1550_desc,
98
+
desc);
99
+
int ret;
100
+
101
+
ret = regulator_map_voltage_ascend(rdev, uV, uV);
102
+
if (ret < 0) {
103
+
dev_err(rdev_get_dev(rdev), "failed to map %i uV\n", uV);
104
+
return ret;
105
+
}
106
+
107
+
return regmap_update_bits(rdev->regmap, desc->stby_reg,
108
+
desc->stby_mask, ret);
109
+
}
110
+
111
+
static int pf1550_buck_set_linear_suspend_voltage(struct regulator_dev *rdev,
112
+
int uV)
113
+
{
114
+
const struct pf1550_desc *desc = container_of_const(rdev->desc,
115
+
struct pf1550_desc,
116
+
desc);
117
+
int ret;
118
+
119
+
ret = regulator_map_voltage_linear(rdev, uV, uV);
120
+
if (ret < 0) {
121
+
dev_err(rdev_get_dev(rdev), "failed to map %i uV\n", uV);
122
+
return ret;
123
+
}
124
+
125
+
return regmap_update_bits(rdev->regmap, desc->stby_reg,
126
+
desc->stby_mask, ret);
127
+
}
128
+
129
+
static const struct regulator_ops pf1550_sw1_ops = {
130
+
.enable = regulator_enable_regmap,
131
+
.disable = regulator_disable_regmap,
132
+
.set_suspend_enable = pf1550_set_suspend_enable,
133
+
.set_suspend_disable = pf1550_set_suspend_disable,
134
+
.is_enabled = regulator_is_enabled_regmap,
135
+
.list_voltage = regulator_list_voltage_table,
136
+
.set_voltage_sel = regulator_set_voltage_sel_regmap,
137
+
.get_voltage_sel = regulator_get_voltage_sel_regmap,
138
+
.set_voltage_time_sel = regulator_set_voltage_time_sel,
139
+
.set_suspend_voltage = pf1550_buck_set_table_suspend_voltage,
140
+
.map_voltage = regulator_map_voltage_ascend,
141
+
.set_ramp_delay = pf1550_set_ramp_delay,
142
+
};
143
+
144
+
static const struct regulator_ops pf1550_sw2_ops = {
145
+
.enable = regulator_enable_regmap,
146
+
.disable = regulator_disable_regmap,
147
+
.set_suspend_enable = pf1550_set_suspend_enable,
148
+
.set_suspend_disable = pf1550_set_suspend_disable,
149
+
.is_enabled = regulator_is_enabled_regmap,
150
+
.list_voltage = regulator_list_voltage_linear,
151
+
.set_voltage_sel = regulator_set_voltage_sel_regmap,
152
+
.get_voltage_sel = regulator_get_voltage_sel_regmap,
153
+
.set_voltage_time_sel = regulator_set_voltage_time_sel,
154
+
.set_suspend_voltage = pf1550_buck_set_linear_suspend_voltage,
155
+
.map_voltage = regulator_map_voltage_linear,
156
+
.set_ramp_delay = pf1550_set_ramp_delay,
157
+
};
158
+
159
+
static const struct regulator_ops pf1550_ldo1_ops = {
160
+
.enable = regulator_enable_regmap,
161
+
.disable = regulator_disable_regmap,
162
+
.set_suspend_enable = pf1550_set_suspend_enable,
163
+
.set_suspend_disable = pf1550_set_suspend_disable,
164
+
.is_enabled = regulator_is_enabled_regmap,
165
+
.list_voltage = regulator_list_voltage_table,
166
+
.map_voltage = regulator_map_voltage_ascend,
167
+
.set_voltage_sel = regulator_set_voltage_sel_regmap,
168
+
.get_voltage_sel = regulator_get_voltage_sel_regmap,
169
+
};
170
+
171
+
static const struct regulator_ops pf1550_ldo2_ops = {
172
+
.enable = regulator_enable_regmap,
173
+
.disable = regulator_disable_regmap,
174
+
.set_suspend_enable = pf1550_set_suspend_enable,
175
+
.set_suspend_disable = pf1550_set_suspend_disable,
176
+
.is_enabled = regulator_is_enabled_regmap,
177
+
.list_voltage = regulator_list_voltage_linear,
178
+
.set_voltage_sel = regulator_set_voltage_sel_regmap,
179
+
.get_voltage_sel = regulator_get_voltage_sel_regmap,
180
+
.map_voltage = regulator_map_voltage_linear,
181
+
};
182
+
183
+
static const struct regulator_ops pf1550_fixed_ops = {
184
+
.enable = regulator_enable_regmap,
185
+
.disable = regulator_disable_regmap,
186
+
.set_suspend_enable = pf1550_set_suspend_enable,
187
+
.set_suspend_disable = pf1550_set_suspend_disable,
188
+
.is_enabled = regulator_is_enabled_regmap,
189
+
.list_voltage = regulator_list_voltage_linear,
190
+
};
191
+
192
+
#define PF_VREF(_chip, match, _name, voltage) { \
193
+
.desc = { \
194
+
.name = #_name, \
195
+
.of_match = of_match_ptr(match), \
196
+
.regulators_node = of_match_ptr("regulators"), \
197
+
.n_voltages = 1, \
198
+
.ops = &pf1550_fixed_ops, \
199
+
.type = REGULATOR_VOLTAGE, \
200
+
.id = _chip ## _ ## _name, \
201
+
.owner = THIS_MODULE, \
202
+
.min_uV = (voltage), \
203
+
.enable_reg = _chip ## _PMIC_REG_ ## _name ## _CTRL, \
204
+
.enable_mask = 0x1, \
205
+
}, \
206
+
.stby_enable_reg = _chip ## _PMIC_REG_ ## _name ## _CTRL, \
207
+
.stby_enable_mask = 0x2, \
208
+
}
209
+
210
+
#define PF_SW(_chip, match, _name, min, max, mask, step) { \
211
+
.desc = { \
212
+
.name = #_name, \
213
+
.of_match = of_match_ptr(match), \
214
+
.regulators_node = of_match_ptr("regulators"), \
215
+
.n_voltages = ((max) - (min)) / (step) + 1, \
216
+
.ops = &pf1550_sw2_ops, \
217
+
.type = REGULATOR_VOLTAGE, \
218
+
.id = _chip ## _ ## _name, \
219
+
.owner = THIS_MODULE, \
220
+
.min_uV = (min), \
221
+
.uV_step = (step), \
222
+
.linear_min_sel = 0, \
223
+
.vsel_reg = _chip ## _PMIC_REG_ ## _name ## _VOLT, \
224
+
.vsel_mask = (mask), \
225
+
.enable_reg = _chip ## _PMIC_REG_ ## _name ## _CTRL, \
226
+
.enable_mask = 0x1, \
227
+
}, \
228
+
.stby_reg = _chip ## _PMIC_REG_ ## _name ## _STBY_VOLT, \
229
+
.stby_mask = (mask), \
230
+
.stby_enable_reg = _chip ## _PMIC_REG_ ## _name ## _CTRL, \
231
+
.stby_enable_mask = 0x2, \
232
+
}
233
+
234
+
#define PF_LDO1(_chip, match, _name, mask, voltages) { \
235
+
.desc = { \
236
+
.name = #_name, \
237
+
.of_match = of_match_ptr(match), \
238
+
.regulators_node = of_match_ptr("regulators"), \
239
+
.n_voltages = ARRAY_SIZE(voltages), \
240
+
.ops = &pf1550_ldo1_ops, \
241
+
.type = REGULATOR_VOLTAGE, \
242
+
.id = _chip ## _ ## _name, \
243
+
.owner = THIS_MODULE, \
244
+
.volt_table = voltages, \
245
+
.vsel_reg = _chip ## _PMIC_REG_ ## _name ## _VOLT, \
246
+
.vsel_mask = (mask), \
247
+
.enable_reg = _chip ## _PMIC_REG_ ## _name ## _CTRL, \
248
+
.enable_mask = 0x1, \
249
+
}, \
250
+
.stby_enable_reg = _chip ## _PMIC_REG_ ## _name ## _CTRL, \
251
+
.stby_enable_mask = 0x2, \
252
+
}
253
+
254
+
#define PF_LDO2(_chip, match, _name, mask, min, max, step) { \
255
+
.desc = { \
256
+
.name = #_name, \
257
+
.of_match = of_match_ptr(match), \
258
+
.regulators_node = of_match_ptr("regulators"), \
259
+
.n_voltages = ((max) - (min)) / (step) + 1, \
260
+
.ops = &pf1550_ldo2_ops, \
261
+
.type = REGULATOR_VOLTAGE, \
262
+
.id = _chip ## _ ## _name, \
263
+
.owner = THIS_MODULE, \
264
+
.min_uV = (min), \
265
+
.uV_step = (step), \
266
+
.linear_min_sel = 0, \
267
+
.vsel_reg = _chip ## _PMIC_REG_ ## _name ## _VOLT, \
268
+
.vsel_mask = (mask), \
269
+
.enable_reg = _chip ## _PMIC_REG_ ## _name ## _CTRL, \
270
+
.enable_mask = 0x1, \
271
+
}, \
272
+
.stby_enable_reg = _chip ## _PMIC_REG_ ## _name ## _CTRL, \
273
+
.stby_enable_mask = 0x2, \
274
+
}
275
+
276
+
static struct pf1550_desc pf1550_regulators[] = {
277
+
PF_SW(PF1550, "sw1", SW1, 600000, 1387500, 0x3f, 12500),
278
+
PF_SW(PF1550, "sw2", SW2, 600000, 1387500, 0x3f, 12500),
279
+
PF_SW(PF1550, "sw3", SW3, 1800000, 3300000, 0xf, 100000),
280
+
PF_VREF(PF1550, "vrefddr", VREFDDR, 1200000),
281
+
PF_LDO1(PF1550, "ldo1", LDO1, 0x1f, pf1550_ldo13_volts),
282
+
PF_LDO2(PF1550, "ldo2", LDO2, 0xf, 1800000, 3300000, 100000),
283
+
PF_LDO1(PF1550, "ldo3", LDO3, 0x1f, pf1550_ldo13_volts),
284
+
};
285
+
286
+
static irqreturn_t pf1550_regulator_irq_handler(int irq, void *data)
287
+
{
288
+
struct pf1550_regulator_info *info = data;
289
+
struct device *dev = info->dev;
290
+
struct platform_device *pdev = to_platform_device(dev);
291
+
int i, irq_type = -1;
292
+
unsigned int event;
293
+
294
+
for (i = 0; i < PF1550_REGULATOR_IRQ_NR; i++)
295
+
if (irq == platform_get_irq(pdev, i))
296
+
irq_type = i;
297
+
298
+
switch (irq_type) {
299
+
/* The _LS interrupts indicate over-current event. The _HS interrupts
300
+
* which are more accurate and can detect catastrophic faults, issue
301
+
* an error event. The current limit FAULT interrupt is similar to the
302
+
* _HS'
303
+
*/
304
+
case PF1550_PMIC_IRQ_SW1_LS:
305
+
case PF1550_PMIC_IRQ_SW2_LS:
306
+
case PF1550_PMIC_IRQ_SW3_LS:
307
+
event = REGULATOR_EVENT_OVER_CURRENT_WARN;
308
+
for (i = 0; i < PF1550_MAX_REGULATOR; i++)
309
+
if (!strcmp(rdev_get_name(info->rdevs[i]), "SW3"))
310
+
regulator_notifier_call_chain(info->rdevs[i],
311
+
event, NULL);
312
+
break;
313
+
case PF1550_PMIC_IRQ_SW1_HS:
314
+
case PF1550_PMIC_IRQ_SW2_HS:
315
+
case PF1550_PMIC_IRQ_SW3_HS:
316
+
event = REGULATOR_EVENT_OVER_CURRENT;
317
+
for (i = 0; i < PF1550_MAX_REGULATOR; i++)
318
+
if (!strcmp(rdev_get_name(info->rdevs[i]), "SW3"))
319
+
regulator_notifier_call_chain(info->rdevs[i],
320
+
event, NULL);
321
+
break;
322
+
case PF1550_PMIC_IRQ_LDO1_FAULT:
323
+
case PF1550_PMIC_IRQ_LDO2_FAULT:
324
+
case PF1550_PMIC_IRQ_LDO3_FAULT:
325
+
event = REGULATOR_EVENT_OVER_CURRENT;
326
+
for (i = 0; i < PF1550_MAX_REGULATOR; i++)
327
+
if (!strcmp(rdev_get_name(info->rdevs[i]), "LDO3"))
328
+
regulator_notifier_call_chain(info->rdevs[i],
329
+
event, NULL);
330
+
break;
331
+
case PF1550_PMIC_IRQ_TEMP_110:
332
+
case PF1550_PMIC_IRQ_TEMP_125:
333
+
event = REGULATOR_EVENT_OVER_TEMP;
334
+
for (i = 0; i < PF1550_MAX_REGULATOR; i++)
335
+
regulator_notifier_call_chain(info->rdevs[i],
336
+
event, NULL);
337
+
break;
338
+
default:
339
+
dev_err(dev, "regulator interrupt: irq %d occurred\n",
340
+
irq_type);
341
+
}
342
+
343
+
return IRQ_HANDLED;
344
+
}
345
+
346
+
static int pf1550_regulator_probe(struct platform_device *pdev)
347
+
{
348
+
const struct pf1550_ddata *pf1550 = dev_get_drvdata(pdev->dev.parent);
349
+
struct regulator_config config = { };
350
+
struct pf1550_regulator_info *info;
351
+
int i, irq = -1, ret = 0;
352
+
353
+
info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
354
+
if (!info)
355
+
return -ENOMEM;
356
+
357
+
config.regmap = dev_get_regmap(pf1550->dev, NULL);
358
+
if (!config.regmap)
359
+
return dev_err_probe(&pdev->dev, -ENODEV,
360
+
"failed to get parent regmap\n");
361
+
362
+
config.dev = pf1550->dev;
363
+
config.regmap = pf1550->regmap;
364
+
info->dev = &pdev->dev;
365
+
info->pf1550 = pf1550;
366
+
367
+
memcpy(info->regulator_descs, pf1550_regulators,
368
+
sizeof(info->regulator_descs));
369
+
370
+
for (i = 0; i < ARRAY_SIZE(pf1550_regulators); i++) {
371
+
struct regulator_desc *desc;
372
+
373
+
desc = &info->regulator_descs[i].desc;
374
+
375
+
if ((desc->id == PF1550_SW2 && !pf1550->dvs2_enable) ||
376
+
(desc->id == PF1550_SW1 && !pf1550->dvs1_enable)) {
377
+
/* OTP_SW2_DVS_ENB == 1? or OTP_SW1_DVS_ENB == 1? */
378
+
desc->volt_table = pf1550_sw12_volts;
379
+
desc->n_voltages = ARRAY_SIZE(pf1550_sw12_volts);
380
+
desc->ops = &pf1550_sw1_ops;
381
+
}
382
+
383
+
info->rdevs[i] = devm_regulator_register(&pdev->dev, desc,
384
+
&config);
385
+
if (IS_ERR(info->rdevs[i]))
386
+
return dev_err_probe(&pdev->dev,
387
+
PTR_ERR(info->rdevs[i]),
388
+
"failed to initialize regulator-%d\n",
389
+
i);
390
+
}
391
+
392
+
platform_set_drvdata(pdev, info);
393
+
394
+
for (i = 0; i < PF1550_REGULATOR_IRQ_NR; i++) {
395
+
irq = platform_get_irq(pdev, i);
396
+
if (irq < 0)
397
+
return irq;
398
+
399
+
ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
400
+
pf1550_regulator_irq_handler,
401
+
IRQF_NO_SUSPEND,
402
+
"pf1550-regulator", info);
403
+
if (ret)
404
+
return dev_err_probe(&pdev->dev, ret,
405
+
"failed: irq request (IRQ: %d)\n",
406
+
i);
407
+
}
408
+
409
+
return 0;
410
+
}
411
+
412
+
static const struct platform_device_id pf1550_regulator_id[] = {
413
+
{ "pf1550-regulator", },
414
+
{ /* sentinel */ }
415
+
};
416
+
MODULE_DEVICE_TABLE(platform, pf1550_regulator_id);
417
+
418
+
static struct platform_driver pf1550_regulator_driver = {
419
+
.driver = {
420
+
.name = "pf1550-regulator",
421
+
},
422
+
.probe = pf1550_regulator_probe,
423
+
.id_table = pf1550_regulator_id,
424
+
};
425
+
module_platform_driver(pf1550_regulator_driver);
426
+
427
+
MODULE_DESCRIPTION("NXP PF1550 regulator driver");
428
+
MODULE_AUTHOR("Robin Gong <yibin.gong@freescale.com>");
429
+
MODULE_LICENSE("GPL");
+16
-26
drivers/regulator/pf9453-regulator.c
+16
-26
drivers/regulator/pf9453-regulator.c
···
65
65
#define PF9453_LDOSNVS_VOLTAGE_NUM 0x59
66
66
67
67
enum {
68
-
PF9453_REG_DEV_ID = 0x00,
69
-
PF9453_REG_OTP_VER = 0x01,
68
+
PF9453_REG_DEV_ID = 0x01,
70
69
PF9453_REG_INT1 = 0x02,
71
70
PF9453_REG_INT1_MASK = 0x03,
72
71
PF9453_REG_INT1_STATUS = 0x04,
···
119
120
#define LDO_ENMODE_ONREQ_STBY_DPSTBY 0x03
120
121
121
122
/* PF9453_REG_BUCK1_CTRL bits */
122
-
#define BUCK1_LPMODE 0x30
123
123
#define BUCK1_AD 0x08
124
124
#define BUCK1_FPWM 0x04
125
125
#define BUCK1_ENMODE_MASK GENMASK(1, 0)
···
129
131
#define BUCK2_RAMP_12P5MV 0x1
130
132
#define BUCK2_RAMP_6P25MV 0x2
131
133
#define BUCK2_RAMP_3P125MV 0x3
132
-
#define BUCK2_LPMODE 0x30
133
134
#define BUCK2_AD 0x08
134
135
#define BUCK2_FPWM 0x04
135
136
#define BUCK2_ENMODE_MASK GENMASK(1, 0)
136
137
137
138
/* PF9453_REG_BUCK3_CTRL bits */
138
-
#define BUCK3_LPMODE 0x30
139
139
#define BUCK3_AD 0x08
140
140
#define BUCK3_FPWM 0x04
141
141
#define BUCK3_ENMODE_MASK GENMASK(1, 0)
142
142
143
143
/* PF9453_REG_BUCK4_CTRL bits */
144
-
#define BUCK4_LPMODE 0x30
145
144
#define BUCK4_AD 0x08
146
145
#define BUCK4_FPWM 0x04
147
146
#define BUCK4_ENMODE_MASK GENMASK(1, 0)
···
186
191
#define WDOG_B_CFG_NONE 0x00
187
192
#define WDOG_B_CFG_WARM 0x40
188
193
#define WDOG_B_CFG_COLD 0x80
189
-
190
-
/* PF9453_REG_CONFIG2 bits */
191
-
#define I2C_LT_MASK GENMASK(1, 0)
192
-
#define I2C_LT_FORCE_DISABLE 0x00
193
-
#define I2C_LT_ON_STANDBY_RUN 0x01
194
-
#define I2C_LT_ON_RUN 0x02
195
-
#define I2C_LT_FORCE_ENABLE 0x03
196
194
197
195
static const struct regmap_range pf9453_status_range = {
198
196
.range_min = PF9453_REG_INT1,
···
289
301
}
290
302
291
303
/**
292
-
* pf9453_regulator_enable_regmap for regmap users
304
+
* pf9453_regulator_enable_regmap - enable regulator for regmap users
293
305
*
294
306
* @rdev: regulator to operate on
295
307
*
296
308
* Regulators that use regmap for their register I/O can set the
297
309
* enable_reg and enable_mask fields in their descriptor and then use
298
310
* this as their enable() operation, saving some code.
311
+
*
312
+
* Return: %0 on success, or negative errno.
299
313
*/
300
314
static int pf9453_regulator_enable_regmap(struct regulator_dev *rdev)
301
315
{
···
316
326
}
317
327
318
328
/**
319
-
* pf9453_regulator_disable_regmap for regmap users
329
+
* pf9453_regulator_disable_regmap - disable regulator for regmap users
320
330
*
321
331
* @rdev: regulator to operate on
322
332
*
323
333
* Regulators that use regmap for their register I/O can set the
324
334
* enable_reg and enable_mask fields in their descriptor and then use
325
335
* this as their disable() operation, saving some code.
336
+
*
337
+
* Return: %0 on success, or negative errno.
326
338
*/
327
339
static int pf9453_regulator_disable_regmap(struct regulator_dev *rdev)
328
340
{
···
343
351
}
344
352
345
353
/**
346
-
* pf9453_regulator_set_voltage_sel_regmap for regmap users
354
+
* pf9453_regulator_set_voltage_sel_regmap - set voltage for regmap users
347
355
*
348
356
* @rdev: regulator to operate on
349
357
* @sel: Selector to set
···
351
359
* Regulators that use regmap for their register I/O can set the
352
360
* vsel_reg and vsel_mask fields in their descriptor and then use this
353
361
* as their set_voltage_vsel operation, saving some code.
362
+
*
363
+
* Return: %0 on success, or negative errno.
354
364
*/
355
365
static int pf9453_regulator_set_voltage_sel_regmap(struct regulator_dev *rdev, unsigned int sel)
356
366
{
···
403
409
}
404
410
405
411
/**
406
-
* pf9453_regulator_set_ramp_delay_regmap
412
+
* pf9453_regulator_set_ramp_delay_regmap - set ramp delay for regmap users
407
413
*
408
414
* @rdev: regulator to operate on
409
415
* @ramp_delay: desired ramp delay value in microseconds
···
411
417
* Regulators that use regmap for their register I/O can set the ramp_reg
412
418
* and ramp_mask fields in their descriptor and then use this as their
413
419
* set_ramp_delay operation, saving some code.
420
+
*
421
+
* Return: %0 on success, or negative errno.
414
422
*/
415
423
static int pf9453_regulator_set_ramp_delay_regmap(struct regulator_dev *rdev, int ramp_delay)
416
424
{
···
532
536
}
533
537
}
534
538
535
-
if (ret == 0) {
536
-
struct pf9453_regulator_desc *regulator = container_of(desc,
537
-
struct pf9453_regulator_desc, desc);
538
-
539
-
/* Enable DVS control through PMIC_STBY_REQ for this BUCK */
540
-
ret = pf9453_pmic_write(pf9453, regulator->desc.enable_reg,
541
-
BUCK2_LPMODE, BUCK2_LPMODE);
542
-
}
543
539
return ret;
544
540
}
545
541
546
542
static int pf9453_set_dvs_levels(struct device_node *np, const struct regulator_desc *desc,
547
543
struct regulator_config *cfg)
548
544
{
549
-
struct pf9453_regulator_desc *data = container_of(desc, struct pf9453_regulator_desc, desc);
545
+
const struct pf9453_regulator_desc *data = container_of_const(desc,
546
+
struct pf9453_regulator_desc,
547
+
desc);
550
548
struct pf9453 *pf9453 = dev_get_drvdata(cfg->dev);
551
549
const struct pf9453_dvs_config *dvs = &data->dvs;
552
550
unsigned int reg, mask;
+2
-2
drivers/regulator/qcom-labibb-regulator.c
+2
-2
drivers/regulator/qcom-labibb-regulator.c
···
230
230
return;
231
231
232
232
reschedule:
233
-
mod_delayed_work(system_wq, &vreg->ocp_recovery_work,
233
+
mod_delayed_work(system_dfl_wq, &vreg->ocp_recovery_work,
234
234
msecs_to_jiffies(OCP_RECOVERY_INTERVAL_MS));
235
235
}
236
236
···
510
510
* taking action is not truly urgent anymore.
511
511
*/
512
512
vreg->sc_count++;
513
-
mod_delayed_work(system_wq, &vreg->sc_recovery_work,
513
+
mod_delayed_work(system_dfl_wq, &vreg->sc_recovery_work,
514
514
msecs_to_jiffies(SC_RECOVERY_INTERVAL_MS));
515
515
}
516
516
+789
-549
drivers/regulator/qcom-rpmh-regulator.c
+789
-549
drivers/regulator/qcom-rpmh-regulator.c
···
1
1
// SPDX-License-Identifier: GPL-2.0
2
2
// Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
3
-
// Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
3
+
// Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
4
5
5
#define pr_fmt(fmt) "%s: " fmt, __func__
6
6
···
30
30
enum rpmh_regulator_type {
31
31
VRM,
32
32
XOB,
33
+
};
34
+
35
+
/**
36
+
* enum regulator_hw_type - supported regulator types
37
+
* @SMPS: Switch mode power supply.
38
+
* @LDO: Linear Dropout regulator.
39
+
* @BOB: Buck/Boost type regulator.
40
+
* @VS: Simple voltage ON/OFF switch.
41
+
* @NUM_REGULATOR_TYPES: Number of regulator types.
42
+
*/
43
+
enum regulator_hw_type {
44
+
SMPS,
45
+
LDO,
46
+
BOB,
47
+
VS,
48
+
NUM_REGULATOR_TYPES,
49
+
};
50
+
51
+
struct resource_name_formats {
52
+
const char *rsc_name_fmt;
53
+
const char *rsc_name_fmt1;
54
+
};
55
+
56
+
static const struct resource_name_formats vreg_rsc_name_lookup[NUM_REGULATOR_TYPES] = {
57
+
[SMPS] = {"S%d%s", "smp%s%d"},
58
+
[LDO] = {"L%d%s", "ldo%s%d"},
59
+
[BOB] = {"B%d%s", "bob%s%d"},
60
+
[VS] = {"VS%d%s", "vs%s%d"},
33
61
};
34
62
35
63
#define RPMH_REGULATOR_REG_VRM_VOLTAGE 0x0
···
92
64
#define PMIC5_BOB_MODE_AUTO 6
93
65
#define PMIC5_BOB_MODE_PWM 7
94
66
67
+
#define PMIC530_LDO_MODE_RETENTION 3
68
+
#define PMIC530_LDO_MODE_LPM 4
69
+
#define PMIC530_LDO_MODE_OPM 5
70
+
#define PMIC530_LDO_MODE_HPM 7
71
+
72
+
#define PMIC_ID_LEN 4
95
73
/**
96
74
* struct rpmh_vreg_hw_data - RPMh regulator hardware configurations
97
75
* @regulator_type: RPMh accelerator type used to manage this
···
170
136
* struct rpmh_vreg_init_data - initialization data for an RPMh regulator
171
137
* @name: Name for the regulator which also corresponds
172
138
* to the device tree subnode name of the regulator
173
-
* @resource_name: RPMh regulator resource name format string.
174
-
* This must include exactly one field: '%s' which
175
-
* is filled at run-time with the PMIC ID provided
176
-
* by device tree property qcom,pmic-id. Example:
177
-
* "ldo%s1" for RPMh resource "ldoa1".
139
+
* @index: This is the index number of the regulator present
140
+
* on the PMIC.
141
+
* @vreg_hw_type: Regulator HW type enum, this must be BOB, SMPS,
142
+
* LDO, VS, based on the regulator HW type.
178
143
* @supply_name: Parent supply regulator name
179
144
* @hw_data: Configuration data for this PMIC regulator type
180
145
*/
181
146
struct rpmh_vreg_init_data {
182
147
const char *name;
183
-
const char *resource_name;
148
+
enum regulator_hw_type vreg_hw_type;
149
+
int index;
184
150
const char *supply_name;
185
151
const struct rpmh_vreg_hw_data *hw_data;
186
152
};
···
451
417
{
452
418
struct regulator_config reg_config = {};
453
419
char rpmh_resource_name[20] = "";
420
+
const char *rsc_name;
454
421
const struct rpmh_vreg_init_data *rpmh_data;
455
422
struct regulator_init_data *init_data;
456
423
struct regulator_dev *rdev;
···
468
433
return -EINVAL;
469
434
}
470
435
471
-
scnprintf(rpmh_resource_name, sizeof(rpmh_resource_name),
472
-
rpmh_data->resource_name, pmic_id);
436
+
if (strnlen(pmic_id, PMIC_ID_LEN) > 1 && strnstr(pmic_id, "_E", PMIC_ID_LEN)) {
437
+
rsc_name = vreg_rsc_name_lookup[rpmh_data->vreg_hw_type].rsc_name_fmt;
438
+
scnprintf(rpmh_resource_name, sizeof(rpmh_resource_name),
439
+
rsc_name, rpmh_data->index, pmic_id);
440
+
441
+
} else {
442
+
rsc_name = vreg_rsc_name_lookup[rpmh_data->vreg_hw_type].rsc_name_fmt1;
443
+
scnprintf(rpmh_resource_name, sizeof(rpmh_resource_name),
444
+
rsc_name, pmic_id, rpmh_data->index);
445
+
}
473
446
474
447
vreg->addr = cmd_db_read_addr(rpmh_resource_name);
475
448
if (!vreg->addr) {
···
562
519
[REGULATOR_MODE_FAST] = -EINVAL,
563
520
};
564
521
522
+
static const int pmic_mode_map_pmic530_ldo[REGULATOR_MODE_STANDBY + 1] = {
523
+
[REGULATOR_MODE_INVALID] = -EINVAL,
524
+
[REGULATOR_MODE_STANDBY] = PMIC530_LDO_MODE_RETENTION,
525
+
[REGULATOR_MODE_IDLE] = PMIC530_LDO_MODE_LPM,
526
+
[REGULATOR_MODE_NORMAL] = PMIC530_LDO_MODE_OPM,
527
+
[REGULATOR_MODE_FAST] = PMIC530_LDO_MODE_HPM,
528
+
};
529
+
565
530
static unsigned int rpmh_regulator_pmic4_ldo_of_map_mode(unsigned int rpmh_mode)
566
531
{
567
532
unsigned int mode;
···
589
538
break;
590
539
}
591
540
541
+
return mode;
542
+
}
543
+
544
+
static unsigned int rpmh_regulator_pmic530_ldo_of_map_mode(unsigned int rpmh_mode)
545
+
{
546
+
unsigned int mode;
547
+
548
+
switch (rpmh_mode) {
549
+
case RPMH_REGULATOR_MODE_HPM:
550
+
mode = REGULATOR_MODE_FAST;
551
+
break;
552
+
case RPMH_REGULATOR_MODE_AUTO:
553
+
mode = REGULATOR_MODE_NORMAL;
554
+
break;
555
+
case RPMH_REGULATOR_MODE_LPM:
556
+
mode = REGULATOR_MODE_IDLE;
557
+
break;
558
+
case RPMH_REGULATOR_MODE_RET:
559
+
mode = REGULATOR_MODE_STANDBY;
560
+
break;
561
+
default:
562
+
mode = REGULATOR_MODE_INVALID;
563
+
break;
564
+
}
592
565
return mode;
593
566
}
594
567
···
979
904
.of_map_mode = rpmh_regulator_pmic4_bob_of_map_mode,
980
905
};
981
906
982
-
#define RPMH_VREG(_name, _resource_name, _hw_data, _supply_name) \
907
+
static const struct rpmh_vreg_hw_data pmic5_nldo530 = {
908
+
.regulator_type = VRM,
909
+
.ops = &rpmh_regulator_vrm_drms_ops,
910
+
.voltage_ranges = (struct linear_range[]) {
911
+
REGULATOR_LINEAR_RANGE(320000, 0, 210, 8000),
912
+
},
913
+
.n_linear_ranges = 1,
914
+
.n_voltages = 211,
915
+
.hpm_min_load_uA = 30000,
916
+
.pmic_mode_map = pmic_mode_map_pmic530_ldo,
917
+
.of_map_mode = rpmh_regulator_pmic530_ldo_of_map_mode,
918
+
};
919
+
920
+
static const struct rpmh_vreg_hw_data pmic5_pldo530_mvp150 = {
921
+
.regulator_type = VRM,
922
+
.ops = &rpmh_regulator_vrm_drms_ops,
923
+
.voltage_ranges = (struct linear_range[]) {
924
+
REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000),
925
+
},
926
+
.n_linear_ranges = 1,
927
+
.n_voltages = 256,
928
+
.hpm_min_load_uA = 10000,
929
+
.pmic_mode_map = pmic_mode_map_pmic530_ldo,
930
+
.of_map_mode = rpmh_regulator_pmic530_ldo_of_map_mode,
931
+
};
932
+
933
+
static const struct rpmh_vreg_hw_data pmic5_pldo530_mvp300 = {
934
+
.regulator_type = VRM,
935
+
.ops = &rpmh_regulator_vrm_drms_ops,
936
+
.voltage_ranges = (struct linear_range[]) {
937
+
REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000),
938
+
},
939
+
.n_linear_ranges = 1,
940
+
.n_voltages = 256,
941
+
.hpm_min_load_uA = 20000,
942
+
.pmic_mode_map = pmic_mode_map_pmic530_ldo,
943
+
.of_map_mode = rpmh_regulator_pmic530_ldo_of_map_mode,
944
+
};
945
+
946
+
static const struct rpmh_vreg_hw_data pmic5_pldo530_mvp600 = {
947
+
.regulator_type = VRM,
948
+
.ops = &rpmh_regulator_vrm_drms_ops,
949
+
.voltage_ranges = (struct linear_range[]) {
950
+
REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000),
951
+
},
952
+
.n_linear_ranges = 1,
953
+
.n_voltages = 256,
954
+
.hpm_min_load_uA = 40000,
955
+
.pmic_mode_map = pmic_mode_map_pmic530_ldo,
956
+
.of_map_mode = rpmh_regulator_pmic530_ldo_of_map_mode,
957
+
};
958
+
959
+
static const struct rpmh_vreg_hw_data pmic5_ftsmps530 = {
960
+
.regulator_type = VRM,
961
+
.ops = &rpmh_regulator_vrm_ops,
962
+
.voltage_ranges = (struct linear_range[]) {
963
+
REGULATOR_LINEAR_RANGE(252000, 0, 305, 4000),
964
+
REGULATOR_LINEAR_RANGE(1480000, 306, 464, 8000),
965
+
},
966
+
.n_linear_ranges = 2,
967
+
.n_voltages = 465,
968
+
.pmic_mode_map = pmic_mode_map_pmic5_smps,
969
+
.of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode,
970
+
};
971
+
972
+
#define RPMH_VREG(_name, _vreg_hw_type, _index, _hw_data, _supply_name) \
983
973
{ \
984
974
.name = _name, \
985
-
.resource_name = _resource_name, \
975
+
.vreg_hw_type = _vreg_hw_type, \
976
+
.index = _index, \
986
977
.hw_data = _hw_data, \
987
978
.supply_name = _supply_name, \
988
979
}
989
980
990
981
static const struct rpmh_vreg_init_data pm8998_vreg_data[] = {
991
-
RPMH_VREG("smps1", "smp%s1", &pmic4_ftsmps426, "vdd-s1"),
992
-
RPMH_VREG("smps2", "smp%s2", &pmic4_ftsmps426, "vdd-s2"),
993
-
RPMH_VREG("smps3", "smp%s3", &pmic4_hfsmps3, "vdd-s3"),
994
-
RPMH_VREG("smps4", "smp%s4", &pmic4_hfsmps3, "vdd-s4"),
995
-
RPMH_VREG("smps5", "smp%s5", &pmic4_hfsmps3, "vdd-s5"),
996
-
RPMH_VREG("smps6", "smp%s6", &pmic4_ftsmps426, "vdd-s6"),
997
-
RPMH_VREG("smps7", "smp%s7", &pmic4_ftsmps426, "vdd-s7"),
998
-
RPMH_VREG("smps8", "smp%s8", &pmic4_ftsmps426, "vdd-s8"),
999
-
RPMH_VREG("smps9", "smp%s9", &pmic4_ftsmps426, "vdd-s9"),
1000
-
RPMH_VREG("smps10", "smp%s10", &pmic4_ftsmps426, "vdd-s10"),
1001
-
RPMH_VREG("smps11", "smp%s11", &pmic4_ftsmps426, "vdd-s11"),
1002
-
RPMH_VREG("smps12", "smp%s12", &pmic4_ftsmps426, "vdd-s12"),
1003
-
RPMH_VREG("smps13", "smp%s13", &pmic4_ftsmps426, "vdd-s13"),
1004
-
RPMH_VREG("ldo1", "ldo%s1", &pmic4_nldo, "vdd-l1-l27"),
1005
-
RPMH_VREG("ldo2", "ldo%s2", &pmic4_nldo, "vdd-l2-l8-l17"),
1006
-
RPMH_VREG("ldo3", "ldo%s3", &pmic4_nldo, "vdd-l3-l11"),
1007
-
RPMH_VREG("ldo4", "ldo%s4", &pmic4_nldo, "vdd-l4-l5"),
1008
-
RPMH_VREG("ldo5", "ldo%s5", &pmic4_nldo, "vdd-l4-l5"),
1009
-
RPMH_VREG("ldo6", "ldo%s6", &pmic4_pldo, "vdd-l6"),
1010
-
RPMH_VREG("ldo7", "ldo%s7", &pmic4_pldo_lv, "vdd-l7-l12-l14-l15"),
1011
-
RPMH_VREG("ldo8", "ldo%s8", &pmic4_nldo, "vdd-l2-l8-l17"),
1012
-
RPMH_VREG("ldo9", "ldo%s9", &pmic4_pldo, "vdd-l9"),
1013
-
RPMH_VREG("ldo10", "ldo%s10", &pmic4_pldo, "vdd-l10-l23-l25"),
1014
-
RPMH_VREG("ldo11", "ldo%s11", &pmic4_nldo, "vdd-l3-l11"),
1015
-
RPMH_VREG("ldo12", "ldo%s12", &pmic4_pldo_lv, "vdd-l7-l12-l14-l15"),
1016
-
RPMH_VREG("ldo13", "ldo%s13", &pmic4_pldo, "vdd-l13-l19-l21"),
1017
-
RPMH_VREG("ldo14", "ldo%s14", &pmic4_pldo_lv, "vdd-l7-l12-l14-l15"),
1018
-
RPMH_VREG("ldo15", "ldo%s15", &pmic4_pldo_lv, "vdd-l7-l12-l14-l15"),
1019
-
RPMH_VREG("ldo16", "ldo%s16", &pmic4_pldo, "vdd-l16-l28"),
1020
-
RPMH_VREG("ldo17", "ldo%s17", &pmic4_nldo, "vdd-l2-l8-l17"),
1021
-
RPMH_VREG("ldo18", "ldo%s18", &pmic4_pldo, "vdd-l18-l22"),
1022
-
RPMH_VREG("ldo19", "ldo%s19", &pmic4_pldo, "vdd-l13-l19-l21"),
1023
-
RPMH_VREG("ldo20", "ldo%s20", &pmic4_pldo, "vdd-l20-l24"),
1024
-
RPMH_VREG("ldo21", "ldo%s21", &pmic4_pldo, "vdd-l13-l19-l21"),
1025
-
RPMH_VREG("ldo22", "ldo%s22", &pmic4_pldo, "vdd-l18-l22"),
1026
-
RPMH_VREG("ldo23", "ldo%s23", &pmic4_pldo, "vdd-l10-l23-l25"),
1027
-
RPMH_VREG("ldo24", "ldo%s24", &pmic4_pldo, "vdd-l20-l24"),
1028
-
RPMH_VREG("ldo25", "ldo%s25", &pmic4_pldo, "vdd-l10-l23-l25"),
1029
-
RPMH_VREG("ldo26", "ldo%s26", &pmic4_nldo, "vdd-l26"),
1030
-
RPMH_VREG("ldo27", "ldo%s27", &pmic4_nldo, "vdd-l1-l27"),
1031
-
RPMH_VREG("ldo28", "ldo%s28", &pmic4_pldo, "vdd-l16-l28"),
1032
-
RPMH_VREG("lvs1", "vs%s1", &pmic4_lvs, "vin-lvs-1-2"),
1033
-
RPMH_VREG("lvs2", "vs%s2", &pmic4_lvs, "vin-lvs-1-2"),
982
+
RPMH_VREG("smps1", SMPS, 1, &pmic4_ftsmps426, "vdd-s1"),
983
+
RPMH_VREG("smps2", SMPS, 2, &pmic4_ftsmps426, "vdd-s2"),
984
+
RPMH_VREG("smps3", SMPS, 3, &pmic4_hfsmps3, "vdd-s3"),
985
+
RPMH_VREG("smps4", SMPS, 4, &pmic4_hfsmps3, "vdd-s4"),
986
+
RPMH_VREG("smps5", SMPS, 5, &pmic4_hfsmps3, "vdd-s5"),
987
+
RPMH_VREG("smps6", SMPS, 6, &pmic4_ftsmps426, "vdd-s6"),
988
+
RPMH_VREG("smps7", SMPS, 7, &pmic4_ftsmps426, "vdd-s7"),
989
+
RPMH_VREG("smps8", SMPS, 8, &pmic4_ftsmps426, "vdd-s8"),
990
+
RPMH_VREG("smps9", SMPS, 9, &pmic4_ftsmps426, "vdd-s9"),
991
+
RPMH_VREG("smps10", SMPS, 10, &pmic4_ftsmps426, "vdd-s10"),
992
+
RPMH_VREG("smps11", SMPS, 11, &pmic4_ftsmps426, "vdd-s11"),
993
+
RPMH_VREG("smps12", SMPS, 12, &pmic4_ftsmps426, "vdd-s12"),
994
+
RPMH_VREG("smps13", SMPS, 13, &pmic4_ftsmps426, "vdd-s13"),
995
+
RPMH_VREG("ldo1", LDO, 1, &pmic4_nldo, "vdd-l1-l27"),
996
+
RPMH_VREG("ldo2", LDO, 2, &pmic4_nldo, "vdd-l2-l8-l17"),
997
+
RPMH_VREG("ldo3", LDO, 3, &pmic4_nldo, "vdd-l3-l11"),
998
+
RPMH_VREG("ldo4", LDO, 4, &pmic4_nldo, "vdd-l4-l5"),
999
+
RPMH_VREG("ldo5", LDO, 5, &pmic4_nldo, "vdd-l4-l5"),
1000
+
RPMH_VREG("ldo6", LDO, 6, &pmic4_pldo, "vdd-l6"),
1001
+
RPMH_VREG("ldo7", LDO, 7, &pmic4_pldo_lv, "vdd-l7-l12-l14-l15"),
1002
+
RPMH_VREG("ldo8", LDO, 8, &pmic4_nldo, "vdd-l2-l8-l17"),
1003
+
RPMH_VREG("ldo9", LDO, 9, &pmic4_pldo, "vdd-l9"),
1004
+
RPMH_VREG("ldo10", LDO, 10, &pmic4_pldo, "vdd-l10-l23-l25"),
1005
+
RPMH_VREG("ldo11", LDO, 11, &pmic4_nldo, "vdd-l3-l11"),
1006
+
RPMH_VREG("ldo12", LDO, 12, &pmic4_pldo_lv, "vdd-l7-l12-l14-l15"),
1007
+
RPMH_VREG("ldo13", LDO, 13, &pmic4_pldo, "vdd-l13-l19-l21"),
1008
+
RPMH_VREG("ldo14", LDO, 14, &pmic4_pldo_lv, "vdd-l7-l12-l14-l15"),
1009
+
RPMH_VREG("ldo15", LDO, 15, &pmic4_pldo_lv, "vdd-l7-l12-l14-l15"),
1010
+
RPMH_VREG("ldo16", LDO, 16, &pmic4_pldo, "vdd-l16-l28"),
1011
+
RPMH_VREG("ldo17", LDO, 17, &pmic4_nldo, "vdd-l2-l8-l17"),
1012
+
RPMH_VREG("ldo18", LDO, 18, &pmic4_pldo, "vdd-l18-l22"),
1013
+
RPMH_VREG("ldo19", LDO, 19, &pmic4_pldo, "vdd-l13-l19-l21"),
1014
+
RPMH_VREG("ldo20", LDO, 20, &pmic4_pldo, "vdd-l20-l24"),
1015
+
RPMH_VREG("ldo21", LDO, 21, &pmic4_pldo, "vdd-l13-l19-l21"),
1016
+
RPMH_VREG("ldo22", LDO, 22, &pmic4_pldo, "vdd-l18-l22"),
1017
+
RPMH_VREG("ldo23", LDO, 23, &pmic4_pldo, "vdd-l10-l23-l25"),
1018
+
RPMH_VREG("ldo24", LDO, 24, &pmic4_pldo, "vdd-l20-l24"),
1019
+
RPMH_VREG("ldo25", LDO, 25, &pmic4_pldo, "vdd-l10-l23-l25"),
1020
+
RPMH_VREG("ldo26", LDO, 26, &pmic4_nldo, "vdd-l26"),
1021
+
RPMH_VREG("ldo27", LDO, 27, &pmic4_nldo, "vdd-l1-l27"),
1022
+
RPMH_VREG("ldo28", LDO, 28, &pmic4_pldo, "vdd-l16-l28"),
1023
+
RPMH_VREG("lvs1", VS, 1, &pmic4_lvs, "vin-lvs-1-2"),
1024
+
RPMH_VREG("lvs2", VS, 2, &pmic4_lvs, "vin-lvs-1-2"),
1034
1025
{}
1035
1026
};
1036
1027
1037
1028
static const struct rpmh_vreg_init_data pmg1110_vreg_data[] = {
1038
-
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
1029
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"),
1039
1030
{}
1040
1031
};
1041
1032
1042
1033
static const struct rpmh_vreg_init_data pmi8998_vreg_data[] = {
1043
-
RPMH_VREG("bob", "bob%s1", &pmic4_bob, "vdd-bob"),
1034
+
RPMH_VREG("bob", BOB, 1, &pmic4_bob, "vdd-bob"),
1044
1035
{}
1045
1036
};
1046
1037
1047
1038
static const struct rpmh_vreg_init_data pm8005_vreg_data[] = {
1048
-
RPMH_VREG("smps1", "smp%s1", &pmic4_ftsmps426, "vdd-s1"),
1049
-
RPMH_VREG("smps2", "smp%s2", &pmic4_ftsmps426, "vdd-s2"),
1050
-
RPMH_VREG("smps3", "smp%s3", &pmic4_ftsmps426, "vdd-s3"),
1051
-
RPMH_VREG("smps4", "smp%s4", &pmic4_ftsmps426, "vdd-s4"),
1039
+
RPMH_VREG("smps1", SMPS, 1, &pmic4_ftsmps426, "vdd-s1"),
1040
+
RPMH_VREG("smps2", SMPS, 2, &pmic4_ftsmps426, "vdd-s2"),
1041
+
RPMH_VREG("smps3", SMPS, 3, &pmic4_ftsmps426, "vdd-s3"),
1042
+
RPMH_VREG("smps4", SMPS, 4, &pmic4_ftsmps426, "vdd-s4"),
1052
1043
{}
1053
1044
};
1054
1045
1055
1046
static const struct rpmh_vreg_init_data pm8150_vreg_data[] = {
1056
-
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
1057
-
RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps510, "vdd-s2"),
1058
-
RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps510, "vdd-s3"),
1059
-
RPMH_VREG("smps4", "smp%s4", &pmic5_hfsmps510, "vdd-s4"),
1060
-
RPMH_VREG("smps5", "smp%s5", &pmic5_hfsmps510, "vdd-s5"),
1061
-
RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps510, "vdd-s6"),
1062
-
RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps510, "vdd-s7"),
1063
-
RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps510, "vdd-s8"),
1064
-
RPMH_VREG("smps9", "smp%s9", &pmic5_ftsmps510, "vdd-s9"),
1065
-
RPMH_VREG("smps10", "smp%s10", &pmic5_ftsmps510, "vdd-s10"),
1066
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1-l8-l11"),
1067
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo, "vdd-l2-l10"),
1068
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3-l4-l5-l18"),
1069
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l3-l4-l5-l18"),
1070
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo, "vdd-l3-l4-l5-l18"),
1071
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo, "vdd-l6-l9"),
1072
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l7-l12-l14-l15"),
1073
-
RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo, "vdd-l1-l8-l11"),
1074
-
RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo, "vdd-l6-l9"),
1075
-
RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo, "vdd-l2-l10"),
1076
-
RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo, "vdd-l1-l8-l11"),
1077
-
RPMH_VREG("ldo12", "ldo%s12", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
1078
-
RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l13-l16-l17"),
1079
-
RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
1080
-
RPMH_VREG("ldo15", "ldo%s15", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
1081
-
RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l13-l16-l17"),
1082
-
RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo, "vdd-l13-l16-l17"),
1083
-
RPMH_VREG("ldo18", "ldo%s18", &pmic5_nldo, "vdd-l3-l4-l5-l18"),
1047
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"),
1048
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps510, "vdd-s2"),
1049
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps510, "vdd-s3"),
1050
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_hfsmps510, "vdd-s4"),
1051
+
RPMH_VREG("smps5", SMPS, 5, &pmic5_hfsmps510, "vdd-s5"),
1052
+
RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"),
1053
+
RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps510, "vdd-s7"),
1054
+
RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps510, "vdd-s8"),
1055
+
RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps510, "vdd-s9"),
1056
+
RPMH_VREG("smps10", SMPS, 10, &pmic5_ftsmps510, "vdd-s10"),
1057
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l8-l11"),
1058
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_pldo, "vdd-l2-l10"),
1059
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3-l4-l5-l18"),
1060
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l3-l4-l5-l18"),
1061
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo, "vdd-l3-l4-l5-l18"),
1062
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l6-l9"),
1063
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l7-l12-l14-l15"),
1064
+
RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l1-l8-l11"),
1065
+
RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l6-l9"),
1066
+
RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l2-l10"),
1067
+
RPMH_VREG("ldo11", LDO, 11, &pmic5_nldo, "vdd-l1-l8-l11"),
1068
+
RPMH_VREG("ldo12", LDO, 12, &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
1069
+
RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l13-l16-l17"),
1070
+
RPMH_VREG("ldo14", LDO, 14, &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
1071
+
RPMH_VREG("ldo15", LDO, 15, &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
1072
+
RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l13-l16-l17"),
1073
+
RPMH_VREG("ldo17", LDO, 17, &pmic5_pldo, "vdd-l13-l16-l17"),
1074
+
RPMH_VREG("ldo18", LDO, 18, &pmic5_nldo, "vdd-l3-l4-l5-l18"),
1084
1075
{}
1085
1076
};
1086
1077
1087
1078
static const struct rpmh_vreg_init_data pm8150l_vreg_data[] = {
1088
-
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
1089
-
RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps510, "vdd-s2"),
1090
-
RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps510, "vdd-s3"),
1091
-
RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps510, "vdd-s4"),
1092
-
RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps510, "vdd-s5"),
1093
-
RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps510, "vdd-s6"),
1094
-
RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps510, "vdd-s7"),
1095
-
RPMH_VREG("smps8", "smp%s8", &pmic5_hfsmps510, "vdd-s8"),
1096
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_pldo_lv, "vdd-l1-l8"),
1097
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l2-l3"),
1098
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l2-l3"),
1099
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_pldo, "vdd-l4-l5-l6"),
1100
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l4-l5-l6"),
1101
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l4-l5-l6"),
1102
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l7-l11"),
1103
-
RPMH_VREG("ldo8", "ldo%s8", &pmic5_pldo_lv, "vdd-l1-l8"),
1104
-
RPMH_VREG("ldo9", "ldo%s9", &pmic5_pldo, "vdd-l9-l10"),
1105
-
RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo, "vdd-l9-l10"),
1106
-
RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo, "vdd-l7-l11"),
1107
-
RPMH_VREG("bob", "bob%s1", &pmic5_bob, "vdd-bob"),
1079
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"),
1080
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps510, "vdd-s2"),
1081
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps510, "vdd-s3"),
1082
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps510, "vdd-s4"),
1083
+
RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps510, "vdd-s5"),
1084
+
RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"),
1085
+
RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps510, "vdd-s7"),
1086
+
RPMH_VREG("smps8", SMPS, 8, &pmic5_hfsmps510, "vdd-s8"),
1087
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_pldo_lv, "vdd-l1-l8"),
1088
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l2-l3"),
1089
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l2-l3"),
1090
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_pldo, "vdd-l4-l5-l6"),
1091
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l4-l5-l6"),
1092
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l4-l5-l6"),
1093
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l7-l11"),
1094
+
RPMH_VREG("ldo8", LDO, 8, &pmic5_pldo_lv, "vdd-l1-l8"),
1095
+
RPMH_VREG("ldo9", LDO, 9, &pmic5_pldo, "vdd-l9-l10"),
1096
+
RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l9-l10"),
1097
+
RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, "vdd-l7-l11"),
1098
+
RPMH_VREG("bob", BOB, 1, &pmic5_bob, "vdd-bob"),
1108
1099
{}
1109
1100
};
1110
1101
1111
1102
static const struct rpmh_vreg_init_data pmm8155au_vreg_data[] = {
1112
-
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
1113
-
RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps510, "vdd-s2"),
1114
-
RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps510, "vdd-s3"),
1115
-
RPMH_VREG("smps4", "smp%s4", &pmic5_hfsmps510, "vdd-s4"),
1116
-
RPMH_VREG("smps5", "smp%s5", &pmic5_hfsmps510, "vdd-s5"),
1117
-
RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps510, "vdd-s6"),
1118
-
RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps510, "vdd-s7"),
1119
-
RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps510, "vdd-s8"),
1120
-
RPMH_VREG("smps9", "smp%s9", &pmic5_ftsmps510, "vdd-s9"),
1121
-
RPMH_VREG("smps10", "smp%s10", &pmic5_ftsmps510, "vdd-s10"),
1122
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1-l8-l11"),
1123
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo, "vdd-l2-l10"),
1124
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3-l4-l5-l18"),
1125
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l3-l4-l5-l18"),
1126
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo, "vdd-l3-l4-l5-l18"),
1127
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo, "vdd-l6-l9"),
1128
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
1129
-
RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo, "vdd-l1-l8-l11"),
1130
-
RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo, "vdd-l6-l9"),
1131
-
RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo, "vdd-l2-l10"),
1132
-
RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo, "vdd-l1-l8-l11"),
1133
-
RPMH_VREG("ldo12", "ldo%s12", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
1134
-
RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l13-l16-l17"),
1135
-
RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
1136
-
RPMH_VREG("ldo15", "ldo%s15", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
1137
-
RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l13-l16-l17"),
1138
-
RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo, "vdd-l13-l16-l17"),
1139
-
RPMH_VREG("ldo18", "ldo%s18", &pmic5_nldo, "vdd-l3-l4-l5-l18"),
1103
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"),
1104
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps510, "vdd-s2"),
1105
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps510, "vdd-s3"),
1106
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_hfsmps510, "vdd-s4"),
1107
+
RPMH_VREG("smps5", SMPS, 5, &pmic5_hfsmps510, "vdd-s5"),
1108
+
RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"),
1109
+
RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps510, "vdd-s7"),
1110
+
RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps510, "vdd-s8"),
1111
+
RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps510, "vdd-s9"),
1112
+
RPMH_VREG("smps10", SMPS, 10, &pmic5_ftsmps510, "vdd-s10"),
1113
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l8-l11"),
1114
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_pldo, "vdd-l2-l10"),
1115
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3-l4-l5-l18"),
1116
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l3-l4-l5-l18"),
1117
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo, "vdd-l3-l4-l5-l18"),
1118
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l6-l9"),
1119
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
1120
+
RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l1-l8-l11"),
1121
+
RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l6-l9"),
1122
+
RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l2-l10"),
1123
+
RPMH_VREG("ldo11", LDO, 11, &pmic5_nldo, "vdd-l1-l8-l11"),
1124
+
RPMH_VREG("ldo12", LDO, 12, &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
1125
+
RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l13-l16-l17"),
1126
+
RPMH_VREG("ldo14", LDO, 14, &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
1127
+
RPMH_VREG("ldo15", LDO, 15, &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"),
1128
+
RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l13-l16-l17"),
1129
+
RPMH_VREG("ldo17", LDO, 17, &pmic5_pldo, "vdd-l13-l16-l17"),
1130
+
RPMH_VREG("ldo18", LDO, 18, &pmic5_nldo, "vdd-l3-l4-l5-l18"),
1140
1131
{}
1141
1132
};
1142
1133
1143
1134
static const struct rpmh_vreg_init_data pmm8654au_vreg_data[] = {
1144
-
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps527, "vdd-s1"),
1145
-
RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps527, "vdd-s2"),
1146
-
RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps527, "vdd-s3"),
1147
-
RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps527, "vdd-s4"),
1148
-
RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps527, "vdd-s5"),
1149
-
RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps527, "vdd-s6"),
1150
-
RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps527, "vdd-s7"),
1151
-
RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps527, "vdd-s8"),
1152
-
RPMH_VREG("smps9", "smp%s9", &pmic5_ftsmps527, "vdd-s9"),
1153
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-s9"),
1154
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2-l3"),
1155
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l2-l3"),
1156
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo515, "vdd-s9"),
1157
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo515, "vdd-s9"),
1158
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo515, "vdd-l6-l7"),
1159
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_nldo515, "vdd-l6-l7"),
1160
-
RPMH_VREG("ldo8", "ldo%s8", &pmic5_pldo515_mv, "vdd-l8-l9"),
1161
-
RPMH_VREG("ldo9", "ldo%s9", &pmic5_pldo, "vdd-l8-l9"),
1135
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps527, "vdd-s1"),
1136
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps527, "vdd-s2"),
1137
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps527, "vdd-s3"),
1138
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps527, "vdd-s4"),
1139
+
RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps527, "vdd-s5"),
1140
+
RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps527, "vdd-s6"),
1141
+
RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps527, "vdd-s7"),
1142
+
RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps527, "vdd-s8"),
1143
+
RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps527, "vdd-s9"),
1144
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-s9"),
1145
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, "vdd-l2-l3"),
1146
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l2-l3"),
1147
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo515, "vdd-s9"),
1148
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo515, "vdd-s9"),
1149
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo515, "vdd-l6-l7"),
1150
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo515, "vdd-l6-l7"),
1151
+
RPMH_VREG("ldo8", LDO, 8, &pmic5_pldo515_mv, "vdd-l8-l9"),
1152
+
RPMH_VREG("ldo9", LDO, 9, &pmic5_pldo, "vdd-l8-l9"),
1162
1153
{}
1163
1154
};
1164
1155
1165
1156
static const struct rpmh_vreg_init_data pm8350_vreg_data[] = {
1166
-
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
1167
-
RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps510, "vdd-s2"),
1168
-
RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps510, "vdd-s3"),
1169
-
RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps510, "vdd-s4"),
1170
-
RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps510, "vdd-s5"),
1171
-
RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps510, "vdd-s6"),
1172
-
RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps510, "vdd-s7"),
1173
-
RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps510, "vdd-s8"),
1174
-
RPMH_VREG("smps9", "smp%s9", &pmic5_ftsmps510, "vdd-s9"),
1175
-
RPMH_VREG("smps10", "smp%s10", &pmic5_hfsmps510, "vdd-s10"),
1176
-
RPMH_VREG("smps11", "smp%s11", &pmic5_hfsmps510, "vdd-s11"),
1177
-
RPMH_VREG("smps12", "smp%s12", &pmic5_hfsmps510, "vdd-s12"),
1178
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1-l4"),
1179
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo, "vdd-l2-l7"),
1180
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3-l5"),
1181
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l1-l4"),
1182
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo, "vdd-l3-l5"),
1183
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo, "vdd-l6-l9-l10"),
1184
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l2-l7"),
1185
-
RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo, "vdd-l8"),
1186
-
RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo, "vdd-l6-l9-l10"),
1187
-
RPMH_VREG("ldo10", "ldo%s10", &pmic5_nldo, "vdd-l6-l9-l10"),
1157
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"),
1158
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps510, "vdd-s2"),
1159
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps510, "vdd-s3"),
1160
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps510, "vdd-s4"),
1161
+
RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps510, "vdd-s5"),
1162
+
RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"),
1163
+
RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps510, "vdd-s7"),
1164
+
RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps510, "vdd-s8"),
1165
+
RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps510, "vdd-s9"),
1166
+
RPMH_VREG("smps10", SMPS, 10, &pmic5_hfsmps510, "vdd-s10"),
1167
+
RPMH_VREG("smps11", SMPS, 11, &pmic5_hfsmps510, "vdd-s11"),
1168
+
RPMH_VREG("smps12", SMPS, 12, &pmic5_hfsmps510, "vdd-s12"),
1169
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l4"),
1170
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_pldo, "vdd-l2-l7"),
1171
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3-l5"),
1172
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l1-l4"),
1173
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo, "vdd-l3-l5"),
1174
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l6-l9-l10"),
1175
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l2-l7"),
1176
+
RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l8"),
1177
+
RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l6-l9-l10"),
1178
+
RPMH_VREG("ldo10", LDO, 10, &pmic5_nldo, "vdd-l6-l9-l10"),
1188
1179
{}
1189
1180
};
1190
1181
1191
1182
static const struct rpmh_vreg_init_data pm8350c_vreg_data[] = {
1192
-
RPMH_VREG("smps1", "smp%s1", &pmic5_hfsmps515, "vdd-s1"),
1193
-
RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps510, "vdd-s2"),
1194
-
RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps510, "vdd-s3"),
1195
-
RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps510, "vdd-s4"),
1196
-
RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps510, "vdd-s5"),
1197
-
RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps510, "vdd-s6"),
1198
-
RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps510, "vdd-s7"),
1199
-
RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps510, "vdd-s8"),
1200
-
RPMH_VREG("smps9", "smp%s9", &pmic5_ftsmps510, "vdd-s9"),
1201
-
RPMH_VREG("smps10", "smp%s10", &pmic5_ftsmps510, "vdd-s10"),
1202
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_pldo_lv, "vdd-l1-l12"),
1203
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo_lv, "vdd-l2-l8"),
1204
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
1205
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
1206
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
1207
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l6-l9-l11"),
1208
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
1209
-
RPMH_VREG("ldo8", "ldo%s8", &pmic5_pldo_lv, "vdd-l2-l8"),
1210
-
RPMH_VREG("ldo9", "ldo%s9", &pmic5_pldo, "vdd-l6-l9-l11"),
1211
-
RPMH_VREG("ldo10", "ldo%s10", &pmic5_nldo, "vdd-l10"),
1212
-
RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo, "vdd-l6-l9-l11"),
1213
-
RPMH_VREG("ldo12", "ldo%s12", &pmic5_pldo_lv, "vdd-l1-l12"),
1214
-
RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
1215
-
RPMH_VREG("bob", "bob%s1", &pmic5_bob, "vdd-bob"),
1183
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_hfsmps515, "vdd-s1"),
1184
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps510, "vdd-s2"),
1185
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps510, "vdd-s3"),
1186
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps510, "vdd-s4"),
1187
+
RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps510, "vdd-s5"),
1188
+
RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"),
1189
+
RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps510, "vdd-s7"),
1190
+
RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps510, "vdd-s8"),
1191
+
RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps510, "vdd-s9"),
1192
+
RPMH_VREG("smps10", SMPS, 10, &pmic5_ftsmps510, "vdd-s10"),
1193
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_pldo_lv, "vdd-l1-l12"),
1194
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_pldo_lv, "vdd-l2-l8"),
1195
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
1196
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
1197
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
1198
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l6-l9-l11"),
1199
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
1200
+
RPMH_VREG("ldo8", LDO, 8, &pmic5_pldo_lv, "vdd-l2-l8"),
1201
+
RPMH_VREG("ldo9", LDO, 9, &pmic5_pldo, "vdd-l6-l9-l11"),
1202
+
RPMH_VREG("ldo10", LDO, 10, &pmic5_nldo, "vdd-l10"),
1203
+
RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, "vdd-l6-l9-l11"),
1204
+
RPMH_VREG("ldo12", LDO, 12, &pmic5_pldo_lv, "vdd-l1-l12"),
1205
+
RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l3-l4-l5-l7-l13"),
1206
+
RPMH_VREG("bob", BOB, 1, &pmic5_bob, "vdd-bob"),
1216
1207
{}
1217
1208
};
1218
1209
1219
1210
static const struct rpmh_vreg_init_data pm8450_vreg_data[] = {
1220
-
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps520, "vdd-s1"),
1221
-
RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps520, "vdd-s2"),
1222
-
RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps520, "vdd-s3"),
1223
-
RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps520, "vdd-s4"),
1224
-
RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps520, "vdd-s5"),
1225
-
RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps520, "vdd-s6"),
1226
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1"),
1227
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l2"),
1228
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3"),
1229
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_pldo_lv, "vdd-l4"),
1211
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps520, "vdd-s1"),
1212
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps520, "vdd-s2"),
1213
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps520, "vdd-s3"),
1214
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps520, "vdd-s4"),
1215
+
RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps520, "vdd-s5"),
1216
+
RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps520, "vdd-s6"),
1217
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1"),
1218
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l2"),
1219
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"),
1220
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_pldo_lv, "vdd-l4"),
1230
1221
{}
1231
1222
};
1232
1223
1233
1224
static const struct rpmh_vreg_init_data pm8550_vreg_data[] = {
1234
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1-l4-l10"),
1235
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo, "vdd-l2-l13-l14"),
1236
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"),
1237
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo515, "vdd-l1-l4-l10"),
1238
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l5-l16"),
1239
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l6-l7"),
1240
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l6-l7"),
1241
-
RPMH_VREG("ldo8", "ldo%s8", &pmic5_pldo, "vdd-l8-l9"),
1242
-
RPMH_VREG("ldo9", "ldo%s9", &pmic5_pldo, "vdd-l8-l9"),
1243
-
RPMH_VREG("ldo10", "ldo%s10", &pmic5_nldo515, "vdd-l1-l4-l10"),
1244
-
RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo515, "vdd-l11"),
1245
-
RPMH_VREG("ldo12", "ldo%s12", &pmic5_nldo515, "vdd-l12"),
1246
-
RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l2-l13-l14"),
1247
-
RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo, "vdd-l2-l13-l14"),
1248
-
RPMH_VREG("ldo15", "ldo%s15", &pmic5_nldo515, "vdd-l15"),
1249
-
RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l5-l16"),
1250
-
RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo, "vdd-l17"),
1251
-
RPMH_VREG("bob1", "bob%s1", &pmic5_bob, "vdd-bob1"),
1252
-
RPMH_VREG("bob2", "bob%s2", &pmic5_bob, "vdd-bob2"),
1225
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-l1-l4-l10"),
1226
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_pldo, "vdd-l2-l13-l14"),
1227
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l3"),
1228
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo515, "vdd-l1-l4-l10"),
1229
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l5-l16"),
1230
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l6-l7"),
1231
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l6-l7"),
1232
+
RPMH_VREG("ldo8", LDO, 8, &pmic5_pldo, "vdd-l8-l9"),
1233
+
RPMH_VREG("ldo9", LDO, 9, &pmic5_pldo, "vdd-l8-l9"),
1234
+
RPMH_VREG("ldo10", LDO, 10, &pmic5_nldo515, "vdd-l1-l4-l10"),
1235
+
RPMH_VREG("ldo11", LDO, 11, &pmic5_nldo515, "vdd-l11"),
1236
+
RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo515, "vdd-l12"),
1237
+
RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l2-l13-l14"),
1238
+
RPMH_VREG("ldo14", LDO, 14, &pmic5_pldo, "vdd-l2-l13-l14"),
1239
+
RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo515, "vdd-l15"),
1240
+
RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l5-l16"),
1241
+
RPMH_VREG("ldo17", LDO, 17, &pmic5_pldo, "vdd-l17"),
1242
+
RPMH_VREG("bob1", BOB, 1, &pmic5_bob, "vdd-bob1"),
1243
+
RPMH_VREG("bob2", BOB, 2, &pmic5_bob, "vdd-bob2"),
1253
1244
{}
1254
1245
};
1255
1246
1256
1247
static const struct rpmh_vreg_init_data pm8550vs_vreg_data[] = {
1257
-
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525, "vdd-s1"),
1258
-
RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525, "vdd-s2"),
1259
-
RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525, "vdd-s3"),
1260
-
RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525, "vdd-s4"),
1261
-
RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525, "vdd-s5"),
1262
-
RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525, "vdd-s6"),
1263
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"),
1264
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2"),
1265
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"),
1248
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps525, "vdd-s1"),
1249
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps525, "vdd-s2"),
1250
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps525, "vdd-s3"),
1251
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps525, "vdd-s4"),
1252
+
RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps525, "vdd-s5"),
1253
+
RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps525, "vdd-s6"),
1254
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-l1"),
1255
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, "vdd-l2"),
1256
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l3"),
1266
1257
{}
1267
1258
};
1268
1259
1269
1260
static const struct rpmh_vreg_init_data pm8550ve_vreg_data[] = {
1270
-
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525, "vdd-s1"),
1271
-
RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525, "vdd-s2"),
1272
-
RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525, "vdd-s3"),
1273
-
RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525, "vdd-s4"),
1274
-
RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525, "vdd-s5"),
1275
-
RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525, "vdd-s6"),
1276
-
RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps525, "vdd-s7"),
1277
-
RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps525, "vdd-s8"),
1278
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"),
1279
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2"),
1280
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"),
1261
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps525, "vdd-s1"),
1262
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps525, "vdd-s2"),
1263
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps525, "vdd-s3"),
1264
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps525, "vdd-s4"),
1265
+
RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps525, "vdd-s5"),
1266
+
RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps525, "vdd-s6"),
1267
+
RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps525, "vdd-s7"),
1268
+
RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps525, "vdd-s8"),
1269
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-l1"),
1270
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, "vdd-l2"),
1271
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l3"),
1281
1272
{}
1282
1273
};
1283
1274
1284
1275
static const struct rpmh_vreg_init_data pmc8380_vreg_data[] = {
1285
-
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525, "vdd-s1"),
1286
-
RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525, "vdd-s2"),
1287
-
RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525, "vdd-s3"),
1288
-
RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525, "vdd-s4"),
1289
-
RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525, "vdd-s5"),
1290
-
RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525, "vdd-s6"),
1291
-
RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps525, "vdd-s7"),
1292
-
RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps525, "vdd-s8"),
1293
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"),
1294
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2"),
1295
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"),
1276
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps525, "vdd-s1"),
1277
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps525, "vdd-s2"),
1278
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps525, "vdd-s3"),
1279
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps525, "vdd-s4"),
1280
+
RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps525, "vdd-s5"),
1281
+
RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps525, "vdd-s6"),
1282
+
RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps525, "vdd-s7"),
1283
+
RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps525, "vdd-s8"),
1284
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-l1"),
1285
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, "vdd-l2"),
1286
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l3"),
1296
1287
{}
1297
1288
};
1298
1289
1299
1290
static const struct rpmh_vreg_init_data pm8009_vreg_data[] = {
1300
-
RPMH_VREG("smps1", "smp%s1", &pmic5_hfsmps510, "vdd-s1"),
1301
-
RPMH_VREG("smps2", "smp%s2", &pmic5_hfsmps515, "vdd-s2"),
1302
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1"),
1303
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l2"),
1304
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3"),
1305
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l4"),
1306
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l5-l6"),
1307
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l5-l6"),
1308
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo_lv, "vdd-l7"),
1291
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_hfsmps510, "vdd-s1"),
1292
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_hfsmps515, "vdd-s2"),
1293
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1"),
1294
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l2"),
1295
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"),
1296
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l4"),
1297
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l5-l6"),
1298
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l5-l6"),
1299
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo_lv, "vdd-l7"),
1309
1300
{}
1310
1301
};
1311
1302
1312
1303
static const struct rpmh_vreg_init_data pm8009_1_vreg_data[] = {
1313
-
RPMH_VREG("smps1", "smp%s1", &pmic5_hfsmps510, "vdd-s1"),
1314
-
RPMH_VREG("smps2", "smp%s2", &pmic5_hfsmps515_1, "vdd-s2"),
1315
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1"),
1316
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l2"),
1317
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3"),
1318
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l4"),
1319
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l5-l6"),
1320
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l5-l6"),
1321
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo_lv, "vdd-l7"),
1304
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_hfsmps510, "vdd-s1"),
1305
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_hfsmps515_1, "vdd-s2"),
1306
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1"),
1307
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l2"),
1308
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"),
1309
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l4"),
1310
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l5-l6"),
1311
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l5-l6"),
1312
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo_lv, "vdd-l7"),
1322
1313
{}
1323
1314
};
1324
1315
1325
1316
static const struct rpmh_vreg_init_data pm8010_vreg_data[] = {
1326
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo502, "vdd-l1-l2"),
1327
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo502, "vdd-l1-l2"),
1328
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_pldo502ln, "vdd-l3-l4"),
1329
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_pldo502ln, "vdd-l3-l4"),
1330
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo502, "vdd-l5"),
1331
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo502ln, "vdd-l6"),
1332
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo502, "vdd-l7"),
1317
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo502, "vdd-l1-l2"),
1318
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo502, "vdd-l1-l2"),
1319
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_pldo502ln, "vdd-l3-l4"),
1320
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_pldo502ln, "vdd-l3-l4"),
1321
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo502, "vdd-l5"),
1322
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo502ln, "vdd-l6"),
1323
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo502, "vdd-l7"),
1333
1324
};
1334
1325
1335
1326
static const struct rpmh_vreg_init_data pm6150_vreg_data[] = {
1336
-
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
1337
-
RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps510, "vdd-s2"),
1338
-
RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps510, "vdd-s3"),
1339
-
RPMH_VREG("smps4", "smp%s4", &pmic5_hfsmps510, "vdd-s4"),
1340
-
RPMH_VREG("smps5", "smp%s5", &pmic5_hfsmps510, "vdd-s5"),
1341
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1"),
1342
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l2-l3"),
1343
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l2-l3"),
1344
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l4-l7-l8"),
1345
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
1346
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo, "vdd-l6"),
1347
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_nldo, "vdd-l4-l7-l8"),
1348
-
RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo, "vdd-l4-l7-l8"),
1349
-
RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo, "vdd-l9"),
1350
-
RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo_lv, "vdd-l10-l14-l15"),
1351
-
RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo_lv, "vdd-l11-l12-l13"),
1352
-
RPMH_VREG("ldo12", "ldo%s12", &pmic5_pldo_lv, "vdd-l11-l12-l13"),
1353
-
RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo_lv, "vdd-l11-l12-l13"),
1354
-
RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo_lv, "vdd-l10-l14-l15"),
1355
-
RPMH_VREG("ldo15", "ldo%s15", &pmic5_pldo_lv, "vdd-l10-l14-l15"),
1356
-
RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
1357
-
RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
1358
-
RPMH_VREG("ldo18", "ldo%s18", &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
1359
-
RPMH_VREG("ldo19", "ldo%s19", &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
1327
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"),
1328
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps510, "vdd-s2"),
1329
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps510, "vdd-s3"),
1330
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_hfsmps510, "vdd-s4"),
1331
+
RPMH_VREG("smps5", SMPS, 5, &pmic5_hfsmps510, "vdd-s5"),
1332
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1"),
1333
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l2-l3"),
1334
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l2-l3"),
1335
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l4-l7-l8"),
1336
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
1337
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l6"),
1338
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo, "vdd-l4-l7-l8"),
1339
+
RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l4-l7-l8"),
1340
+
RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l9"),
1341
+
RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo_lv, "vdd-l10-l14-l15"),
1342
+
RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo_lv, "vdd-l11-l12-l13"),
1343
+
RPMH_VREG("ldo12", LDO, 12, &pmic5_pldo_lv, "vdd-l11-l12-l13"),
1344
+
RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo_lv, "vdd-l11-l12-l13"),
1345
+
RPMH_VREG("ldo14", LDO, 14, &pmic5_pldo_lv, "vdd-l10-l14-l15"),
1346
+
RPMH_VREG("ldo15", LDO, 15, &pmic5_pldo_lv, "vdd-l10-l14-l15"),
1347
+
RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
1348
+
RPMH_VREG("ldo17", LDO, 17, &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
1349
+
RPMH_VREG("ldo18", LDO, 18, &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
1350
+
RPMH_VREG("ldo19", LDO, 19, &pmic5_pldo, "vdd-l5-l16-l17-l18-l19"),
1360
1351
{}
1361
1352
};
1362
1353
1363
1354
static const struct rpmh_vreg_init_data pm6150l_vreg_data[] = {
1364
-
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
1365
-
RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps510, "vdd-s2"),
1366
-
RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps510, "vdd-s3"),
1367
-
RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps510, "vdd-s4"),
1368
-
RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps510, "vdd-s5"),
1369
-
RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps510, "vdd-s6"),
1370
-
RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps510, "vdd-s7"),
1371
-
RPMH_VREG("smps8", "smp%s8", &pmic5_hfsmps510, "vdd-s8"),
1372
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_pldo_lv, "vdd-l1-l8"),
1373
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l2-l3"),
1374
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l2-l3"),
1375
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_pldo, "vdd-l4-l5-l6"),
1376
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l4-l5-l6"),
1377
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l4-l5-l6"),
1378
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l7-l11"),
1379
-
RPMH_VREG("ldo8", "ldo%s8", &pmic5_pldo, "vdd-l1-l8"),
1380
-
RPMH_VREG("ldo9", "ldo%s9", &pmic5_pldo, "vdd-l9-l10"),
1381
-
RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo, "vdd-l9-l10"),
1382
-
RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo, "vdd-l7-l11"),
1383
-
RPMH_VREG("bob", "bob%s1", &pmic5_bob, "vdd-bob"),
1355
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"),
1356
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps510, "vdd-s2"),
1357
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps510, "vdd-s3"),
1358
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps510, "vdd-s4"),
1359
+
RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps510, "vdd-s5"),
1360
+
RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"),
1361
+
RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps510, "vdd-s7"),
1362
+
RPMH_VREG("smps8", SMPS, 8, &pmic5_hfsmps510, "vdd-s8"),
1363
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_pldo_lv, "vdd-l1-l8"),
1364
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l2-l3"),
1365
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l2-l3"),
1366
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_pldo, "vdd-l4-l5-l6"),
1367
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l4-l5-l6"),
1368
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l4-l5-l6"),
1369
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l7-l11"),
1370
+
RPMH_VREG("ldo8", LDO, 8, &pmic5_pldo, "vdd-l1-l8"),
1371
+
RPMH_VREG("ldo9", LDO, 9, &pmic5_pldo, "vdd-l9-l10"),
1372
+
RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l9-l10"),
1373
+
RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, "vdd-l7-l11"),
1374
+
RPMH_VREG("bob", BOB, 1, &pmic5_bob, "vdd-bob"),
1384
1375
{}
1385
1376
};
1386
1377
1387
1378
static const struct rpmh_vreg_init_data pm6350_vreg_data[] = {
1388
-
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, NULL),
1389
-
RPMH_VREG("smps2", "smp%s2", &pmic5_hfsmps510, NULL),
1379
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, NULL),
1380
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_hfsmps510, NULL),
1390
1381
/* smps3 - smps5 not configured */
1391
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, NULL),
1392
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo, NULL),
1393
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_pldo, NULL),
1394
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, NULL),
1395
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, NULL),
1396
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, NULL),
1397
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, NULL),
1398
-
RPMH_VREG("ldo8", "ldo%s8", &pmic5_pldo, NULL),
1399
-
RPMH_VREG("ldo9", "ldo%s9", &pmic5_pldo, NULL),
1400
-
RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo, NULL),
1401
-
RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo, NULL),
1402
-
RPMH_VREG("ldo12", "ldo%s12", &pmic5_pldo, NULL),
1403
-
RPMH_VREG("ldo13", "ldo%s13", &pmic5_nldo, NULL),
1404
-
RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo, NULL),
1405
-
RPMH_VREG("ldo15", "ldo%s15", &pmic5_nldo, NULL),
1406
-
RPMH_VREG("ldo16", "ldo%s16", &pmic5_nldo, NULL),
1382
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, NULL),
1383
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_pldo, NULL),
1384
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_pldo, NULL),
1385
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, NULL),
1386
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, NULL),
1387
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, NULL),
1388
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, NULL),
1389
+
RPMH_VREG("ldo8", LDO, 8, &pmic5_pldo, NULL),
1390
+
RPMH_VREG("ldo9", LDO, 9, &pmic5_pldo, NULL),
1391
+
RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, NULL),
1392
+
RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, NULL),
1393
+
RPMH_VREG("ldo12", LDO, 12, &pmic5_pldo, NULL),
1394
+
RPMH_VREG("ldo13", LDO, 13, &pmic5_nldo, NULL),
1395
+
RPMH_VREG("ldo14", LDO, 14, &pmic5_pldo, NULL),
1396
+
RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo, NULL),
1397
+
RPMH_VREG("ldo16", LDO, 16, &pmic5_nldo, NULL),
1407
1398
/* ldo17 not configured */
1408
-
RPMH_VREG("ldo18", "ldo%s18", &pmic5_nldo, NULL),
1409
-
RPMH_VREG("ldo19", "ldo%s19", &pmic5_nldo, NULL),
1410
-
RPMH_VREG("ldo20", "ldo%s20", &pmic5_nldo, NULL),
1411
-
RPMH_VREG("ldo21", "ldo%s21", &pmic5_nldo, NULL),
1412
-
RPMH_VREG("ldo22", "ldo%s22", &pmic5_nldo, NULL),
1399
+
RPMH_VREG("ldo18", LDO, 18, &pmic5_nldo, NULL),
1400
+
RPMH_VREG("ldo19", LDO, 19, &pmic5_nldo, NULL),
1401
+
RPMH_VREG("ldo20", LDO, 20, &pmic5_nldo, NULL),
1402
+
RPMH_VREG("ldo21", LDO, 21, &pmic5_nldo, NULL),
1403
+
RPMH_VREG("ldo22", LDO, 22, &pmic5_nldo, NULL),
1404
+
};
1405
+
1406
+
static const struct rpmh_vreg_init_data pmcx0102_vreg_data[] = {
1407
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps530, "vdd-s1"),
1408
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps530, "vdd-s2"),
1409
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps530, "vdd-s3"),
1410
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps530, "vdd-s4"),
1411
+
RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps530, "vdd-s5"),
1412
+
RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps530, "vdd-s6"),
1413
+
RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps530, "vdd-s7"),
1414
+
RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps530, "vdd-s8"),
1415
+
RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps530, "vdd-s9"),
1416
+
RPMH_VREG("smps10", SMPS, 10, &pmic5_ftsmps530, "vdd-s10"),
1417
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo530, "vdd-l1"),
1418
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo530, "vdd-l2"),
1419
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo530, "vdd-l3"),
1420
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo530, "vdd-l4"),
1421
+
{}
1422
+
};
1423
+
1424
+
static const struct rpmh_vreg_init_data pmh0101_vreg_data[] = {
1425
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo530, "vdd-l1-l4-l10"),
1426
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_pldo530_mvp300, "vdd-l2-l13-l14"),
1427
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo530, "vdd-l3-l11"),
1428
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo530, "vdd-l1-l4-l10"),
1429
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo530_mvp150, "vdd-l5-l16"),
1430
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo530_mvp300, "vdd-l6-l7"),
1431
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo530_mvp300, "vdd-l6-l7"),
1432
+
RPMH_VREG("ldo8", LDO, 8, &pmic5_pldo530_mvp150, "vdd-l8-l9"),
1433
+
RPMH_VREG("ldo9", LDO, 9, &pmic5_pldo515_mv, "vdd-l8-l9"),
1434
+
RPMH_VREG("ldo10", LDO, 10, &pmic5_nldo530, "vdd-l1-l4-l10"),
1435
+
RPMH_VREG("ldo11", LDO, 11, &pmic5_nldo530, "vdd-l3-l11"),
1436
+
RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo530, "vdd-l12"),
1437
+
RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo530_mvp150, "vdd-l2-l13-l14"),
1438
+
RPMH_VREG("ldo14", LDO, 14, &pmic5_pldo530_mvp150, "vdd-l2-l13-l14"),
1439
+
RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo530, "vdd-l15"),
1440
+
RPMH_VREG("ldo16", LDO, 15, &pmic5_pldo530_mvp600, "vdd-l5-l16"),
1441
+
RPMH_VREG("ldo17", LDO, 17, &pmic5_pldo515_mv, "vdd-l17"),
1442
+
RPMH_VREG("ldo18", LDO, 18, &pmic5_nldo530, "vdd-l18"),
1443
+
RPMH_VREG("bob1", BOB, 1, &pmic5_bob, "vdd-bob1"),
1444
+
RPMH_VREG("bob2", BOB, 2, &pmic5_bob, "vdd-bob2"),
1445
+
{}
1446
+
};
1447
+
1448
+
static const struct rpmh_vreg_init_data pmh0104_vreg_data[] = {
1449
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps530, "vdd-s1"),
1450
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps530, "vdd-s2"),
1451
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps530, "vdd-s3"),
1452
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps530, "vdd-s4"),
1453
+
{}
1454
+
};
1455
+
1456
+
static const struct rpmh_vreg_init_data pmh0110_vreg_data[] = {
1457
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps530, "vdd-s1"),
1458
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps530, "vdd-s2"),
1459
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps530, "vdd-s3"),
1460
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps530, "vdd-s4"),
1461
+
RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps530, "vdd-s5"),
1462
+
RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps530, "vdd-s6"),
1463
+
RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps530, "vdd-s7"),
1464
+
RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps530, "vdd-s8"),
1465
+
RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps530, "vdd-s9"),
1466
+
RPMH_VREG("smps10", SMPS, 10, &pmic5_ftsmps530, "vdd-s10"),
1467
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo530, "vdd-l1"),
1468
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo530, "vdd-l2"),
1469
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo530, "vdd-l3"),
1470
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo530, "vdd-l4"),
1471
+
{}
1413
1472
};
1414
1473
1415
1474
static const struct rpmh_vreg_init_data pmx55_vreg_data[] = {
1416
-
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
1417
-
RPMH_VREG("smps2", "smp%s2", &pmic5_hfsmps510, "vdd-s2"),
1418
-
RPMH_VREG("smps3", "smp%s3", &pmic5_hfsmps510, "vdd-s3"),
1419
-
RPMH_VREG("smps4", "smp%s4", &pmic5_hfsmps510, "vdd-s4"),
1420
-
RPMH_VREG("smps5", "smp%s5", &pmic5_hfsmps510, "vdd-s5"),
1421
-
RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps510, "vdd-s6"),
1422
-
RPMH_VREG("smps7", "smp%s7", &pmic5_hfsmps510, "vdd-s7"),
1423
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1-l2"),
1424
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l1-l2"),
1425
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3-l9"),
1426
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l4-l12"),
1427
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l5-l6"),
1428
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l5-l6"),
1429
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_nldo, "vdd-l7-l8"),
1430
-
RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo, "vdd-l7-l8"),
1431
-
RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo, "vdd-l3-l9"),
1432
-
RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo, "vdd-l10-l11-l13"),
1433
-
RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo, "vdd-l10-l11-l13"),
1434
-
RPMH_VREG("ldo12", "ldo%s12", &pmic5_nldo, "vdd-l4-l12"),
1435
-
RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l10-l11-l13"),
1436
-
RPMH_VREG("ldo14", "ldo%s14", &pmic5_nldo, "vdd-l14"),
1437
-
RPMH_VREG("ldo15", "ldo%s15", &pmic5_nldo, "vdd-l15"),
1438
-
RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l16"),
1475
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"),
1476
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_hfsmps510, "vdd-s2"),
1477
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_hfsmps510, "vdd-s3"),
1478
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_hfsmps510, "vdd-s4"),
1479
+
RPMH_VREG("smps5", SMPS, 5, &pmic5_hfsmps510, "vdd-s5"),
1480
+
RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"),
1481
+
RPMH_VREG("smps7", SMPS, 7, &pmic5_hfsmps510, "vdd-s7"),
1482
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l2"),
1483
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l1-l2"),
1484
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3-l9"),
1485
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l4-l12"),
1486
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l5-l6"),
1487
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l5-l6"),
1488
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo, "vdd-l7-l8"),
1489
+
RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l7-l8"),
1490
+
RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l3-l9"),
1491
+
RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l10-l11-l13"),
1492
+
RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, "vdd-l10-l11-l13"),
1493
+
RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo, "vdd-l4-l12"),
1494
+
RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l10-l11-l13"),
1495
+
RPMH_VREG("ldo14", LDO, 14, &pmic5_nldo, "vdd-l14"),
1496
+
RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo, "vdd-l15"),
1497
+
RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l16"),
1439
1498
{}
1440
1499
};
1441
1500
1442
1501
static const struct rpmh_vreg_init_data pmx65_vreg_data[] = {
1443
-
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"),
1444
-
RPMH_VREG("smps2", "smp%s2", &pmic5_hfsmps510, "vdd-s2"),
1445
-
RPMH_VREG("smps3", "smp%s3", &pmic5_hfsmps510, "vdd-s3"),
1446
-
RPMH_VREG("smps4", "smp%s4", &pmic5_hfsmps510, "vdd-s4"),
1447
-
RPMH_VREG("smps5", "smp%s5", &pmic5_hfsmps510, "vdd-s5"),
1448
-
RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps510, "vdd-s6"),
1449
-
RPMH_VREG("smps7", "smp%s7", &pmic5_hfsmps510, "vdd-s7"),
1450
-
RPMH_VREG("smps8", "smp%s8", &pmic5_hfsmps510, "vdd-s8"),
1451
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1"),
1452
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l2-l18"),
1453
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3"),
1454
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l4"),
1455
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l5-l6-l16"),
1456
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l5-l6-l16"),
1457
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_nldo, "vdd-l7"),
1458
-
RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo, "vdd-l8-l9"),
1459
-
RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo, "vdd-l8-l9"),
1460
-
RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo, "vdd-l10"),
1461
-
RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo, "vdd-l11-l13"),
1462
-
RPMH_VREG("ldo12", "ldo%s12", &pmic5_nldo, "vdd-l12"),
1463
-
RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l11-l13"),
1464
-
RPMH_VREG("ldo14", "ldo%s14", &pmic5_nldo, "vdd-l14"),
1465
-
RPMH_VREG("ldo15", "ldo%s15", &pmic5_nldo, "vdd-l15"),
1466
-
RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l5-l6-l16"),
1467
-
RPMH_VREG("ldo17", "ldo%s17", &pmic5_nldo, "vdd-l17"),
1502
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"),
1503
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_hfsmps510, "vdd-s2"),
1504
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_hfsmps510, "vdd-s3"),
1505
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_hfsmps510, "vdd-s4"),
1506
+
RPMH_VREG("smps5", SMPS, 5, &pmic5_hfsmps510, "vdd-s5"),
1507
+
RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps510, "vdd-s6"),
1508
+
RPMH_VREG("smps7", SMPS, 7, &pmic5_hfsmps510, "vdd-s7"),
1509
+
RPMH_VREG("smps8", SMPS, 8, &pmic5_hfsmps510, "vdd-s8"),
1510
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1"),
1511
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l2-l18"),
1512
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"),
1513
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l4"),
1514
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo, "vdd-l5-l6-l16"),
1515
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo, "vdd-l5-l6-l16"),
1516
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo, "vdd-l7"),
1517
+
RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l8-l9"),
1518
+
RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l8-l9"),
1519
+
RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l10"),
1520
+
RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, "vdd-l11-l13"),
1521
+
RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo, "vdd-l12"),
1522
+
RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l11-l13"),
1523
+
RPMH_VREG("ldo14", LDO, 14, &pmic5_nldo, "vdd-l14"),
1524
+
RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo, "vdd-l15"),
1525
+
RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l5-l6-l16"),
1526
+
RPMH_VREG("ldo17", LDO, 17, &pmic5_nldo, "vdd-l17"),
1468
1527
/* ldo18 not configured */
1469
-
RPMH_VREG("ldo19", "ldo%s19", &pmic5_nldo, "vdd-l19"),
1470
-
RPMH_VREG("ldo20", "ldo%s20", &pmic5_nldo, "vdd-l20"),
1471
-
RPMH_VREG("ldo21", "ldo%s21", &pmic5_nldo, "vdd-l21"),
1528
+
RPMH_VREG("ldo19", LDO, 19, &pmic5_nldo, "vdd-l19"),
1529
+
RPMH_VREG("ldo20", LDO, 20, &pmic5_nldo, "vdd-l20"),
1530
+
RPMH_VREG("ldo21", LDO, 21, &pmic5_nldo, "vdd-l21"),
1472
1531
{}
1473
1532
};
1474
1533
1475
1534
static const struct rpmh_vreg_init_data pmx75_vreg_data[] = {
1476
-
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525, "vdd-s1"),
1477
-
RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525, "vdd-s2"),
1478
-
RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525, "vdd-s3"),
1479
-
RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525, "vdd-s4"),
1480
-
RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525, "vdd-s5"),
1481
-
RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525, "vdd-s6"),
1482
-
RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps525, "vdd-s7"),
1483
-
RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps525, "vdd-s8"),
1484
-
RPMH_VREG("smps9", "smp%s9", &pmic5_ftsmps525, "vdd-s9"),
1485
-
RPMH_VREG("smps10", "smp%s10", &pmic5_ftsmps525, "vdd-s10"),
1486
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"),
1487
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2-18"),
1488
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"),
1489
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo515, "vdd-l4-l16"),
1490
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo_lv, "vdd-l5-l6"),
1491
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo_lv, "vdd-l5-l6"),
1492
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_nldo515, "vdd-l7"),
1493
-
RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo515, "vdd-l8-l9"),
1494
-
RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo515, "vdd-l8-l9"),
1495
-
RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo, "vdd-l10"),
1496
-
RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo, "vdd-l11-l13"),
1497
-
RPMH_VREG("ldo12", "ldo%s12", &pmic5_nldo515, "vdd-l12"),
1498
-
RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l11-l13"),
1499
-
RPMH_VREG("ldo14", "ldo%s14", &pmic5_nldo515, "vdd-l14"),
1500
-
RPMH_VREG("ldo15", "ldo%s15", &pmic5_nldo515, "vdd-l15"),
1501
-
RPMH_VREG("ldo16", "ldo%s16", &pmic5_nldo515, "vdd-l4-l16"),
1502
-
RPMH_VREG("ldo17", "ldo%s17", &pmic5_nldo515, "vdd-l17"),
1535
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps525, "vdd-s1"),
1536
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps525, "vdd-s2"),
1537
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps525, "vdd-s3"),
1538
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps525, "vdd-s4"),
1539
+
RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps525, "vdd-s5"),
1540
+
RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps525, "vdd-s6"),
1541
+
RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps525, "vdd-s7"),
1542
+
RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps525, "vdd-s8"),
1543
+
RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps525, "vdd-s9"),
1544
+
RPMH_VREG("smps10", SMPS, 10, &pmic5_ftsmps525, "vdd-s10"),
1545
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-l1"),
1546
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, "vdd-l2-18"),
1547
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l3"),
1548
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo515, "vdd-l4-l16"),
1549
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo_lv, "vdd-l5-l6"),
1550
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo_lv, "vdd-l5-l6"),
1551
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo515, "vdd-l7"),
1552
+
RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo515, "vdd-l8-l9"),
1553
+
RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo515, "vdd-l8-l9"),
1554
+
RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo, "vdd-l10"),
1555
+
RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo, "vdd-l11-l13"),
1556
+
RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo515, "vdd-l12"),
1557
+
RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo, "vdd-l11-l13"),
1558
+
RPMH_VREG("ldo14", LDO, 14, &pmic5_nldo515, "vdd-l14"),
1559
+
RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo515, "vdd-l15"),
1560
+
RPMH_VREG("ldo16", LDO, 16, &pmic5_nldo515, "vdd-l4-l16"),
1561
+
RPMH_VREG("ldo17", LDO, 17, &pmic5_nldo515, "vdd-l17"),
1503
1562
/* ldo18 not configured */
1504
-
RPMH_VREG("ldo19", "ldo%s19", &pmic5_nldo515, "vdd-l19"),
1505
-
RPMH_VREG("ldo20", "ldo%s20", &pmic5_nldo515, "vdd-l20-l21"),
1506
-
RPMH_VREG("ldo21", "ldo%s21", &pmic5_nldo515, "vdd-l20-l21"),
1563
+
RPMH_VREG("ldo19", LDO, 19, &pmic5_nldo515, "vdd-l19"),
1564
+
RPMH_VREG("ldo20", LDO, 20, &pmic5_nldo515, "vdd-l20-l21"),
1565
+
RPMH_VREG("ldo21", LDO, 21, &pmic5_nldo515, "vdd-l20-l21"),
1507
1566
};
1508
1567
1509
1568
static const struct rpmh_vreg_init_data pm7325_vreg_data[] = {
1510
-
RPMH_VREG("smps1", "smp%s1", &pmic5_hfsmps510, "vdd-s1"),
1511
-
RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps520, "vdd-s2"),
1512
-
RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps520, "vdd-s3"),
1513
-
RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps520, "vdd-s4"),
1514
-
RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps520, "vdd-s5"),
1515
-
RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps520, "vdd-s6"),
1516
-
RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps520, "vdd-s7"),
1517
-
RPMH_VREG("smps8", "smp%s8", &pmic5_hfsmps510, "vdd-s8"),
1518
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1-l4-l12-l15"),
1519
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo, "vdd-l2-l7"),
1520
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3"),
1521
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l1-l4-l12-l15"),
1522
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo, "vdd-l5"),
1523
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo, "vdd-l6-l9-l10"),
1524
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l2-l7"),
1525
-
RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo, "vdd-l8"),
1526
-
RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo, "vdd-l6-l9-l10"),
1527
-
RPMH_VREG("ldo10", "ldo%s10", &pmic5_nldo, "vdd-l6-l9-l10"),
1528
-
RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"),
1529
-
RPMH_VREG("ldo12", "ldo%s12", &pmic5_nldo, "vdd-l1-l4-l12-l15"),
1530
-
RPMH_VREG("ldo13", "ldo%s13", &pmic5_nldo, "vdd-l13"),
1531
-
RPMH_VREG("ldo14", "ldo%s14", &pmic5_nldo, "vdd-l14-l16"),
1532
-
RPMH_VREG("ldo15", "ldo%s15", &pmic5_nldo, "vdd-l1-l4-l12-l15"),
1533
-
RPMH_VREG("ldo16", "ldo%s16", &pmic5_nldo, "vdd-l14-l16"),
1534
-
RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"),
1535
-
RPMH_VREG("ldo18", "ldo%s18", &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"),
1536
-
RPMH_VREG("ldo19", "ldo%s19", &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"),
1569
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_hfsmps510, "vdd-s1"),
1570
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps520, "vdd-s2"),
1571
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps520, "vdd-s3"),
1572
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps520, "vdd-s4"),
1573
+
RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps520, "vdd-s5"),
1574
+
RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps520, "vdd-s6"),
1575
+
RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps520, "vdd-s7"),
1576
+
RPMH_VREG("smps8", SMPS, 8, &pmic5_hfsmps510, "vdd-s8"),
1577
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l4-l12-l15"),
1578
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_pldo, "vdd-l2-l7"),
1579
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"),
1580
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo, "vdd-l1-l4-l12-l15"),
1581
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo, "vdd-l5"),
1582
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l6-l9-l10"),
1583
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l2-l7"),
1584
+
RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l8"),
1585
+
RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l6-l9-l10"),
1586
+
RPMH_VREG("ldo10", LDO, 10, &pmic5_nldo, "vdd-l6-l9-l10"),
1587
+
RPMH_VREG("ldo11", LDO, 11, &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"),
1588
+
RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo, "vdd-l1-l4-l12-l15"),
1589
+
RPMH_VREG("ldo13", LDO, 13, &pmic5_nldo, "vdd-l13"),
1590
+
RPMH_VREG("ldo14", LDO, 14, &pmic5_nldo, "vdd-l14-l16"),
1591
+
RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo, "vdd-l1-l4-l12-l15"),
1592
+
RPMH_VREG("ldo16", LDO, 16, &pmic5_nldo, "vdd-l14-l16"),
1593
+
RPMH_VREG("ldo17", LDO, 17, &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"),
1594
+
RPMH_VREG("ldo18", LDO, 18, &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"),
1595
+
RPMH_VREG("ldo19", LDO, 19, &pmic5_pldo_lv, "vdd-l11-l17-l18-l19"),
1537
1596
{}
1538
1597
};
1539
1598
1540
1599
static const struct rpmh_vreg_init_data pm7550_vreg_data[] = {
1541
-
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525, "vdd-s1"),
1542
-
RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525, "vdd-s2"),
1543
-
RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525, "vdd-s3"),
1544
-
RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525, "vdd-s4"),
1545
-
RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525, "vdd-s5"),
1546
-
RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525, "vdd-s6"),
1547
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"),
1548
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2-l3"),
1549
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l2-l3"),
1550
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo515, "vdd-l4-l5"),
1551
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo515, "vdd-l4-l5"),
1552
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo515, "vdd-l6"),
1553
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_nldo515, "vdd-l7"),
1554
-
RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo515, "vdd-l8"),
1555
-
RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo515, "vdd-l9-l10"),
1556
-
RPMH_VREG("ldo10", "ldo%s10", &pmic5_nldo515, "vdd-l9-l10"),
1557
-
RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo515, "vdd-l11"),
1558
-
RPMH_VREG("ldo12", "ldo%s12", &pmic5_pldo515_mv, "vdd-l12-l14"),
1559
-
RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo515_mv, "vdd-l13-l16"),
1560
-
RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo, "vdd-l12-l14"),
1561
-
RPMH_VREG("ldo15", "ldo%s15", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
1562
-
RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l13-l16"),
1563
-
RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
1564
-
RPMH_VREG("ldo18", "ldo%s18", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
1565
-
RPMH_VREG("ldo19", "ldo%s19", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
1566
-
RPMH_VREG("ldo20", "ldo%s20", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
1567
-
RPMH_VREG("ldo21", "ldo%s21", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
1568
-
RPMH_VREG("ldo22", "ldo%s22", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
1569
-
RPMH_VREG("ldo23", "ldo%s23", &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
1570
-
RPMH_VREG("bob", "bob%s1", &pmic5_bob, "vdd-bob"),
1600
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps525, "vdd-s1"),
1601
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps525, "vdd-s2"),
1602
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps525, "vdd-s3"),
1603
+
RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps525, "vdd-s4"),
1604
+
RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps525, "vdd-s5"),
1605
+
RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps525, "vdd-s6"),
1606
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-l1"),
1607
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, "vdd-l2-l3"),
1608
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l2-l3"),
1609
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo515, "vdd-l4-l5"),
1610
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo515, "vdd-l4-l5"),
1611
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo515, "vdd-l6"),
1612
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo515, "vdd-l7"),
1613
+
RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo515, "vdd-l8"),
1614
+
RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo515, "vdd-l9-l10"),
1615
+
RPMH_VREG("ldo10", LDO, 10, &pmic5_nldo515, "vdd-l9-l10"),
1616
+
RPMH_VREG("ldo11", LDO, 11, &pmic5_nldo515, "vdd-l11"),
1617
+
RPMH_VREG("ldo12", LDO, 12, &pmic5_pldo515_mv, "vdd-l12-l14"),
1618
+
RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo515_mv, "vdd-l13-l16"),
1619
+
RPMH_VREG("ldo14", LDO, 14, &pmic5_pldo, "vdd-l12-l14"),
1620
+
RPMH_VREG("ldo15", LDO, 15, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
1621
+
RPMH_VREG("ldo16", LDO, 16, &pmic5_pldo, "vdd-l13-l16"),
1622
+
RPMH_VREG("ldo17", LDO, 17, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
1623
+
RPMH_VREG("ldo18", LDO, 18, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
1624
+
RPMH_VREG("ldo19", LDO, 19, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
1625
+
RPMH_VREG("ldo20", LDO, 20, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
1626
+
RPMH_VREG("ldo21", LDO, 21, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
1627
+
RPMH_VREG("ldo22", LDO, 22, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
1628
+
RPMH_VREG("ldo23", LDO, 23, &pmic5_pldo, "vdd-l15-l17-l18-l19-l20-l21-l22-l23"),
1629
+
RPMH_VREG("bob", BOB, 1, &pmic5_bob, "vdd-bob"),
1571
1630
{}
1572
1631
};
1573
1632
1574
1633
static const struct rpmh_vreg_init_data pmr735a_vreg_data[] = {
1575
-
RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps520, "vdd-s1"),
1576
-
RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps520, "vdd-s2"),
1577
-
RPMH_VREG("smps3", "smp%s3", &pmic5_hfsmps515, "vdd-s3"),
1578
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1-l2"),
1579
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l1-l2"),
1580
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3"),
1581
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_pldo_lv, "vdd-l4"),
1582
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo, "vdd-l5-l6"),
1583
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo, "vdd-l5-l6"),
1584
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l7-bob"),
1634
+
RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps520, "vdd-s1"),
1635
+
RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps520, "vdd-s2"),
1636
+
RPMH_VREG("smps3", SMPS, 3, &pmic5_hfsmps515, "vdd-s3"),
1637
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l2"),
1638
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l1-l2"),
1639
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"),
1640
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_pldo_lv, "vdd-l4"),
1641
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo, "vdd-l5-l6"),
1642
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l5-l6"),
1643
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo, "vdd-l7-bob"),
1585
1644
{}
1586
1645
};
1587
1646
1588
1647
static const struct rpmh_vreg_init_data pmr735b_vreg_data[] = {
1589
-
RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1-l2"),
1590
-
RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo, "vdd-l1-l2"),
1591
-
RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3"),
1592
-
RPMH_VREG("ldo4", "ldo%s4", &pmic5_pldo_lv, "vdd-l4"),
1593
-
RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo, "vdd-l5"),
1594
-
RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo, "vdd-l6"),
1595
-
RPMH_VREG("ldo7", "ldo%s7", &pmic5_nldo, "vdd-l7-l8"),
1596
-
RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo, "vdd-l7-l8"),
1597
-
RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo, "vdd-l9"),
1598
-
RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo_lv, "vdd-l10"),
1599
-
RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo, "vdd-l11"),
1600
-
RPMH_VREG("ldo12", "ldo%s12", &pmic5_nldo, "vdd-l12"),
1648
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo, "vdd-l1-l2"),
1649
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo, "vdd-l1-l2"),
1650
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo, "vdd-l3"),
1651
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_pldo_lv, "vdd-l4"),
1652
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo, "vdd-l5"),
1653
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo, "vdd-l6"),
1654
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo, "vdd-l7-l8"),
1655
+
RPMH_VREG("ldo8", LDO, 8, &pmic5_nldo, "vdd-l7-l8"),
1656
+
RPMH_VREG("ldo9", LDO, 9, &pmic5_nldo, "vdd-l9"),
1657
+
RPMH_VREG("ldo10", LDO, 10, &pmic5_pldo_lv, "vdd-l10"),
1658
+
RPMH_VREG("ldo11", LDO, 11, &pmic5_nldo, "vdd-l11"),
1659
+
RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo, "vdd-l12"),
1660
+
{}
1661
+
};
1662
+
1663
+
static const struct rpmh_vreg_init_data pmr735d_vreg_data[] = {
1664
+
RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, "vdd-l1-l2-l5"),
1665
+
RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, "vdd-l1-l2-l5"),
1666
+
RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo515, "vdd-l3-l4"),
1667
+
RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo515, "vdd-l3-l4"),
1668
+
RPMH_VREG("ldo5", LDO, 5, &pmic5_nldo515, "vdd-l1-l2-l5"),
1669
+
RPMH_VREG("ldo6", LDO, 6, &pmic5_nldo515, "vdd-l6"),
1670
+
RPMH_VREG("ldo7", LDO, 7, &pmic5_nldo515, "vdd-l7"),
1601
1671
{}
1602
1672
};
1603
1673
1604
1674
static const struct rpmh_vreg_init_data pm660_vreg_data[] = {
1605
-
RPMH_VREG("smps1", "smp%s1", &pmic4_ftsmps426, "vdd-s1"),
1606
-
RPMH_VREG("smps2", "smp%s2", &pmic4_ftsmps426, "vdd-s2"),
1607
-
RPMH_VREG("smps3", "smp%s3", &pmic4_ftsmps426, "vdd-s3"),
1608
-
RPMH_VREG("smps4", "smp%s4", &pmic4_hfsmps3, "vdd-s4"),
1609
-
RPMH_VREG("smps5", "smp%s5", &pmic4_hfsmps3, "vdd-s5"),
1610
-
RPMH_VREG("smps6", "smp%s6", &pmic4_hfsmps3, "vdd-s6"),
1611
-
RPMH_VREG("ldo1", "ldo%s1", &pmic4_nldo, "vdd-l1-l6-l7"),
1612
-
RPMH_VREG("ldo2", "ldo%s2", &pmic4_nldo, "vdd-l2-l3"),
1613
-
RPMH_VREG("ldo3", "ldo%s3", &pmic4_nldo, "vdd-l2-l3"),
1675
+
RPMH_VREG("smps1", SMPS, 1, &pmic4_ftsmps426, "vdd-s1"),
1676
+
RPMH_VREG("smps2", SMPS, 2, &pmic4_ftsmps426, "vdd-s2"),
1677
+
RPMH_VREG("smps3", SMPS, 3, &pmic4_ftsmps426, "vdd-s3"),
1678
+
RPMH_VREG("smps4", SMPS, 4, &pmic4_hfsmps3, "vdd-s4"),
1679
+
RPMH_VREG("smps5", SMPS, 5, &pmic4_hfsmps3, "vdd-s5"),
1680
+
RPMH_VREG("smps6", SMPS, 6, &pmic4_hfsmps3, "vdd-s6"),
1681
+
RPMH_VREG("ldo1", LDO, 1, &pmic4_nldo, "vdd-l1-l6-l7"),
1682
+
RPMH_VREG("ldo2", LDO, 2, &pmic4_nldo, "vdd-l2-l3"),
1683
+
RPMH_VREG("ldo3", LDO, 3, &pmic4_nldo, "vdd-l2-l3"),
1614
1684
/* ldo4 is inaccessible on PM660 */
1615
-
RPMH_VREG("ldo5", "ldo%s5", &pmic4_nldo, "vdd-l5"),
1616
-
RPMH_VREG("ldo6", "ldo%s6", &pmic4_nldo, "vdd-l1-l6-l7"),
1617
-
RPMH_VREG("ldo7", "ldo%s7", &pmic4_nldo, "vdd-l1-l6-l7"),
1618
-
RPMH_VREG("ldo8", "ldo%s8", &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
1619
-
RPMH_VREG("ldo9", "ldo%s9", &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
1620
-
RPMH_VREG("ldo10", "ldo%s10", &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
1621
-
RPMH_VREG("ldo11", "ldo%s11", &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
1622
-
RPMH_VREG("ldo12", "ldo%s12", &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
1623
-
RPMH_VREG("ldo13", "ldo%s13", &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
1624
-
RPMH_VREG("ldo14", "ldo%s14", &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
1625
-
RPMH_VREG("ldo15", "ldo%s15", &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
1626
-
RPMH_VREG("ldo16", "ldo%s16", &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
1627
-
RPMH_VREG("ldo17", "ldo%s17", &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
1628
-
RPMH_VREG("ldo18", "ldo%s18", &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
1629
-
RPMH_VREG("ldo19", "ldo%s19", &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
1685
+
RPMH_VREG("ldo5", LDO, 5, &pmic4_nldo, "vdd-l5"),
1686
+
RPMH_VREG("ldo6", LDO, 6, &pmic4_nldo, "vdd-l1-l6-l7"),
1687
+
RPMH_VREG("ldo7", LDO, 7, &pmic4_nldo, "vdd-l1-l6-l7"),
1688
+
RPMH_VREG("ldo8", LDO, 8, &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
1689
+
RPMH_VREG("ldo9", LDO, 9, &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
1690
+
RPMH_VREG("ldo10", LDO, 10, &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
1691
+
RPMH_VREG("ldo11", LDO, 11, &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
1692
+
RPMH_VREG("ldo12", LDO, 12, &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
1693
+
RPMH_VREG("ldo13", LDO, 13, &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
1694
+
RPMH_VREG("ldo14", LDO, 14, &pmic4_pldo_lv, "vdd-l8-l9-l10-l11-l12-l13-l14"),
1695
+
RPMH_VREG("ldo15", LDO, 15, &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
1696
+
RPMH_VREG("ldo16", LDO, 16, &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
1697
+
RPMH_VREG("ldo17", LDO, 17, &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
1698
+
RPMH_VREG("ldo18", LDO, 18, &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
1699
+
RPMH_VREG("ldo19", LDO, 19, &pmic4_pldo, "vdd-l15-l16-l17-l18-l19"),
1630
1700
{}
1631
1701
};
1632
1702
1633
1703
static const struct rpmh_vreg_init_data pm660l_vreg_data[] = {
1634
-
RPMH_VREG("smps1", "smp%s1", &pmic4_ftsmps426, "vdd-s1"),
1635
-
RPMH_VREG("smps2", "smp%s2", &pmic4_ftsmps426, "vdd-s2"),
1636
-
RPMH_VREG("smps3", "smp%s3", &pmic4_ftsmps426, "vdd-s3-s4"),
1637
-
RPMH_VREG("smps5", "smp%s5", &pmic4_ftsmps426, "vdd-s5"),
1638
-
RPMH_VREG("ldo1", "ldo%s1", &pmic4_nldo, "vdd-l1-l9-l10"),
1639
-
RPMH_VREG("ldo2", "ldo%s2", &pmic4_pldo, "vdd-l2"),
1640
-
RPMH_VREG("ldo3", "ldo%s3", &pmic4_pldo, "vdd-l3-l5-l7-l8"),
1641
-
RPMH_VREG("ldo4", "ldo%s4", &pmic4_pldo, "vdd-l4-l6"),
1642
-
RPMH_VREG("ldo5", "ldo%s5", &pmic4_pldo, "vdd-l3-l5-l7-l8"),
1643
-
RPMH_VREG("ldo6", "ldo%s6", &pmic4_pldo, "vdd-l4-l6"),
1644
-
RPMH_VREG("ldo7", "ldo%s7", &pmic4_pldo, "vdd-l3-l5-l7-l8"),
1645
-
RPMH_VREG("ldo8", "ldo%s8", &pmic4_pldo, "vdd-l3-l5-l7-l8"),
1646
-
RPMH_VREG("bob", "bob%s1", &pmic4_bob, "vdd-bob"),
1704
+
RPMH_VREG("smps1", SMPS, 1, &pmic4_ftsmps426, "vdd-s1"),
1705
+
RPMH_VREG("smps2", SMPS, 2, &pmic4_ftsmps426, "vdd-s2"),
1706
+
RPMH_VREG("smps3", SMPS, 3, &pmic4_ftsmps426, "vdd-s3-s4"),
1707
+
RPMH_VREG("smps5", SMPS, 5, &pmic4_ftsmps426, "vdd-s5"),
1708
+
RPMH_VREG("ldo1", LDO, 1, &pmic4_nldo, "vdd-l1-l9-l10"),
1709
+
RPMH_VREG("ldo2", LDO, 2, &pmic4_pldo, "vdd-l2"),
1710
+
RPMH_VREG("ldo3", LDO, 3, &pmic4_pldo, "vdd-l3-l5-l7-l8"),
1711
+
RPMH_VREG("ldo4", LDO, 4, &pmic4_pldo, "vdd-l4-l6"),
1712
+
RPMH_VREG("ldo5", LDO, 5, &pmic4_pldo, "vdd-l3-l5-l7-l8"),
1713
+
RPMH_VREG("ldo6", LDO, 6, &pmic4_pldo, "vdd-l4-l6"),
1714
+
RPMH_VREG("ldo7", LDO, 7, &pmic4_pldo, "vdd-l3-l5-l7-l8"),
1715
+
RPMH_VREG("ldo8", LDO, 8, &pmic4_pldo, "vdd-l3-l5-l7-l8"),
1716
+
RPMH_VREG("bob", BOB, 1, &pmic4_bob, "vdd-bob"),
1647
1717
{}
1648
1718
};
1649
1719
···
1910
1690
.data = pmc8380_vreg_data,
1911
1691
},
1912
1692
{
1693
+
.compatible = "qcom,pmcx0102-rpmh-regulators",
1694
+
.data = pmcx0102_vreg_data,
1695
+
},
1696
+
{
1697
+
.compatible = "qcom,pmh0101-rpmh-regulators",
1698
+
.data = pmh0101_vreg_data,
1699
+
},
1700
+
{
1701
+
.compatible = "qcom,pmh0104-rpmh-regulators",
1702
+
.data = pmh0104_vreg_data,
1703
+
},
1704
+
{
1705
+
.compatible = "qcom,pmh0110-rpmh-regulators",
1706
+
.data = pmh0110_vreg_data,
1707
+
},
1708
+
{
1913
1709
.compatible = "qcom,pmm8155au-rpmh-regulators",
1914
1710
.data = pmm8155au_vreg_data,
1915
1711
},
···
1960
1724
{
1961
1725
.compatible = "qcom,pmr735b-rpmh-regulators",
1962
1726
.data = pmr735b_vreg_data,
1727
+
},
1728
+
{
1729
+
.compatible = "qcom,pmr735d-rpmh-regulators",
1730
+
.data = pmr735d_vreg_data,
1963
1731
},
1964
1732
{
1965
1733
.compatible = "qcom,pm660-rpmh-regulators",
-2
drivers/regulator/renesas-usb-vbus-regulator.c
-2
drivers/regulator/renesas-usb-vbus-regulator.c
···
7
7
8
8
#include <linux/module.h>
9
9
#include <linux/err.h>
10
-
#include <linux/kernel.h>
11
10
#include <linux/of.h>
12
11
#include <linux/platform_device.h>
13
12
#include <linux/regmap.h>
14
13
#include <linux/regulator/driver.h>
15
-
#include <linux/regulator/of_regulator.h>
16
14
17
15
static const struct regulator_ops rzg2l_usb_vbus_reg_ops = {
18
16
.enable = regulator_enable_regmap,
+27
drivers/regulator/sy7636a-regulator.c
+27
drivers/regulator/sy7636a-regulator.c
···
12
12
#include <linux/mfd/sy7636a.h>
13
13
#include <linux/module.h>
14
14
#include <linux/platform_device.h>
15
+
#include <linux/regulator/consumer.h>
15
16
#include <linux/regulator/driver.h>
16
17
#include <linux/regulator/machine.h>
17
18
#include <linux/regmap.h>
···
20
19
struct sy7636a_data {
21
20
struct regmap *regmap;
22
21
struct gpio_desc *pgood_gpio;
22
+
struct gpio_desc *en_gpio;
23
+
struct gpio_desc *vcom_en_gpio;
23
24
};
24
25
25
26
static int sy7636a_get_vcom_voltage_op(struct regulator_dev *rdev)
···
100
97
101
98
data->regmap = regmap;
102
99
data->pgood_gpio = gdp;
100
+
101
+
ret = devm_regulator_get_enable_optional(&pdev->dev, "vin");
102
+
if (ret)
103
+
return dev_err_probe(&pdev->dev, ret,
104
+
"failed to get vin regulator\n");
105
+
106
+
data->en_gpio = devm_gpiod_get_optional(&pdev->dev, "enable",
107
+
GPIOD_OUT_HIGH);
108
+
if (IS_ERR(data->en_gpio))
109
+
return dev_err_probe(&pdev->dev,
110
+
PTR_ERR(data->en_gpio),
111
+
"failed to get en gpio\n");
112
+
113
+
/* Let VCOM just follow the default power on sequence */
114
+
data->vcom_en_gpio = devm_gpiod_get_optional(&pdev->dev,
115
+
"vcom-en", GPIOD_OUT_LOW);
116
+
if (IS_ERR(data->vcom_en_gpio))
117
+
return dev_err_probe(&pdev->dev,
118
+
PTR_ERR(data->vcom_en_gpio),
119
+
"failed to get vcom-en gpio\n");
120
+
121
+
/* if chip was not enabled, give it time to wake up */
122
+
if (data->en_gpio)
123
+
usleep_range(2500, 4000);
103
124
104
125
platform_set_drvdata(pdev, data);
105
126
+273
include/linux/mfd/pf1550.h
+273
include/linux/mfd/pf1550.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0
2
+
*
3
+
* Declarations for the PF1550 PMIC
4
+
*
5
+
* Copyright (C) 2016 Freescale Semiconductor, Inc.
6
+
* Robin Gong <yibin.gong@freescale.com>
7
+
*
8
+
* Portions Copyright (c) 2025 Savoir-faire Linux Inc.
9
+
* Samuel Kayode <samuel.kayode@savoirfairelinux.com>
10
+
*/
11
+
12
+
#ifndef __LINUX_MFD_PF1550_H
13
+
#define __LINUX_MFD_PF1550_H
14
+
15
+
#include <linux/i2c.h>
16
+
#include <linux/regmap.h>
17
+
18
+
enum pf1550_pmic_reg {
19
+
/* PMIC regulator part */
20
+
PF1550_PMIC_REG_DEVICE_ID = 0x00,
21
+
PF1550_PMIC_REG_OTP_FLAVOR = 0x01,
22
+
PF1550_PMIC_REG_SILICON_REV = 0x02,
23
+
24
+
PF1550_PMIC_REG_INT_CATEGORY = 0x06,
25
+
PF1550_PMIC_REG_SW_INT_STAT0 = 0x08,
26
+
PF1550_PMIC_REG_SW_INT_MASK0 = 0x09,
27
+
PF1550_PMIC_REG_SW_INT_SENSE0 = 0x0a,
28
+
PF1550_PMIC_REG_SW_INT_STAT1 = 0x0b,
29
+
PF1550_PMIC_REG_SW_INT_MASK1 = 0x0c,
30
+
PF1550_PMIC_REG_SW_INT_SENSE1 = 0x0d,
31
+
PF1550_PMIC_REG_SW_INT_STAT2 = 0x0e,
32
+
PF1550_PMIC_REG_SW_INT_MASK2 = 0x0f,
33
+
PF1550_PMIC_REG_SW_INT_SENSE2 = 0x10,
34
+
PF1550_PMIC_REG_LDO_INT_STAT0 = 0x18,
35
+
PF1550_PMIC_REG_LDO_INT_MASK0 = 0x19,
36
+
PF1550_PMIC_REG_LDO_INT_SENSE0 = 0x1a,
37
+
PF1550_PMIC_REG_TEMP_INT_STAT0 = 0x20,
38
+
PF1550_PMIC_REG_TEMP_INT_MASK0 = 0x21,
39
+
PF1550_PMIC_REG_TEMP_INT_SENSE0 = 0x22,
40
+
PF1550_PMIC_REG_ONKEY_INT_STAT0 = 0x24,
41
+
PF1550_PMIC_REG_ONKEY_INT_MASK0 = 0x25,
42
+
PF1550_PMIC_REG_ONKEY_INT_SENSE0 = 0x26,
43
+
PF1550_PMIC_REG_MISC_INT_STAT0 = 0x28,
44
+
PF1550_PMIC_REG_MISC_INT_MASK0 = 0x29,
45
+
PF1550_PMIC_REG_MISC_INT_SENSE0 = 0x2a,
46
+
47
+
PF1550_PMIC_REG_COINCELL_CONTROL = 0x30,
48
+
49
+
PF1550_PMIC_REG_SW1_VOLT = 0x32,
50
+
PF1550_PMIC_REG_SW1_STBY_VOLT = 0x33,
51
+
PF1550_PMIC_REG_SW1_SLP_VOLT = 0x34,
52
+
PF1550_PMIC_REG_SW1_CTRL = 0x35,
53
+
PF1550_PMIC_REG_SW1_CTRL1 = 0x36,
54
+
PF1550_PMIC_REG_SW2_VOLT = 0x38,
55
+
PF1550_PMIC_REG_SW2_STBY_VOLT = 0x39,
56
+
PF1550_PMIC_REG_SW2_SLP_VOLT = 0x3a,
57
+
PF1550_PMIC_REG_SW2_CTRL = 0x3b,
58
+
PF1550_PMIC_REG_SW2_CTRL1 = 0x3c,
59
+
PF1550_PMIC_REG_SW3_VOLT = 0x3e,
60
+
PF1550_PMIC_REG_SW3_STBY_VOLT = 0x3f,
61
+
PF1550_PMIC_REG_SW3_SLP_VOLT = 0x40,
62
+
PF1550_PMIC_REG_SW3_CTRL = 0x41,
63
+
PF1550_PMIC_REG_SW3_CTRL1 = 0x42,
64
+
PF1550_PMIC_REG_VSNVS_CTRL = 0x48,
65
+
PF1550_PMIC_REG_VREFDDR_CTRL = 0x4a,
66
+
PF1550_PMIC_REG_LDO1_VOLT = 0x4c,
67
+
PF1550_PMIC_REG_LDO1_CTRL = 0x4d,
68
+
PF1550_PMIC_REG_LDO2_VOLT = 0x4f,
69
+
PF1550_PMIC_REG_LDO2_CTRL = 0x50,
70
+
PF1550_PMIC_REG_LDO3_VOLT = 0x52,
71
+
PF1550_PMIC_REG_LDO3_CTRL = 0x53,
72
+
PF1550_PMIC_REG_PWRCTRL0 = 0x58,
73
+
PF1550_PMIC_REG_PWRCTRL1 = 0x59,
74
+
PF1550_PMIC_REG_PWRCTRL2 = 0x5a,
75
+
PF1550_PMIC_REG_PWRCTRL3 = 0x5b,
76
+
PF1550_PMIC_REG_SW1_PWRDN_SEQ = 0x5f,
77
+
PF1550_PMIC_REG_SW2_PWRDN_SEQ = 0x60,
78
+
PF1550_PMIC_REG_SW3_PWRDN_SEQ = 0x61,
79
+
PF1550_PMIC_REG_LDO1_PWRDN_SEQ = 0x62,
80
+
PF1550_PMIC_REG_LDO2_PWRDN_SEQ = 0x63,
81
+
PF1550_PMIC_REG_LDO3_PWRDN_SEQ = 0x64,
82
+
PF1550_PMIC_REG_VREFDDR_PWRDN_SEQ = 0x65,
83
+
84
+
PF1550_PMIC_REG_STATE_INFO = 0x67,
85
+
PF1550_PMIC_REG_I2C_ADDR = 0x68,
86
+
PF1550_PMIC_REG_IO_DRV0 = 0x69,
87
+
PF1550_PMIC_REG_IO_DRV1 = 0x6a,
88
+
PF1550_PMIC_REG_RC_16MHZ = 0x6b,
89
+
PF1550_PMIC_REG_KEY = 0x6f,
90
+
91
+
/* Charger part */
92
+
PF1550_CHARG_REG_CHG_INT = 0x80,
93
+
PF1550_CHARG_REG_CHG_INT_MASK = 0x82,
94
+
PF1550_CHARG_REG_CHG_INT_OK = 0x84,
95
+
PF1550_CHARG_REG_VBUS_SNS = 0x86,
96
+
PF1550_CHARG_REG_CHG_SNS = 0x87,
97
+
PF1550_CHARG_REG_BATT_SNS = 0x88,
98
+
PF1550_CHARG_REG_CHG_OPER = 0x89,
99
+
PF1550_CHARG_REG_CHG_TMR = 0x8a,
100
+
PF1550_CHARG_REG_CHG_EOC_CNFG = 0x8d,
101
+
PF1550_CHARG_REG_CHG_CURR_CNFG = 0x8e,
102
+
PF1550_CHARG_REG_BATT_REG = 0x8f,
103
+
PF1550_CHARG_REG_BATFET_CNFG = 0x91,
104
+
PF1550_CHARG_REG_THM_REG_CNFG = 0x92,
105
+
PF1550_CHARG_REG_VBUS_INLIM_CNFG = 0x94,
106
+
PF1550_CHARG_REG_VBUS_LIN_DPM = 0x95,
107
+
PF1550_CHARG_REG_USB_PHY_LDO_CNFG = 0x96,
108
+
PF1550_CHARG_REG_DBNC_DELAY_TIME = 0x98,
109
+
PF1550_CHARG_REG_CHG_INT_CNFG = 0x99,
110
+
PF1550_CHARG_REG_THM_ADJ_SETTING = 0x9a,
111
+
PF1550_CHARG_REG_VBUS2SYS_CNFG = 0x9b,
112
+
PF1550_CHARG_REG_LED_PWM = 0x9c,
113
+
PF1550_CHARG_REG_FAULT_BATFET_CNFG = 0x9d,
114
+
PF1550_CHARG_REG_LED_CNFG = 0x9e,
115
+
PF1550_CHARG_REG_CHGR_KEY2 = 0x9f,
116
+
117
+
PF1550_TEST_REG_FMRADDR = 0xc4,
118
+
PF1550_TEST_REG_FMRDATA = 0xc5,
119
+
PF1550_TEST_REG_KEY3 = 0xdf,
120
+
121
+
PF1550_PMIC_REG_END = 0xff,
122
+
};
123
+
124
+
/* One-Time Programmable(OTP) memory */
125
+
enum pf1550_otp_reg {
126
+
PF1550_OTP_SW1_SW2 = 0x1e,
127
+
PF1550_OTP_SW2_SW3 = 0x1f,
128
+
};
129
+
130
+
#define PF1550_DEVICE_ID 0x7c
131
+
132
+
/* Keys for reading OTP */
133
+
#define PF1550_OTP_PMIC_KEY 0x15
134
+
#define PF1550_OTP_CHGR_KEY 0x50
135
+
#define PF1550_OTP_TEST_KEY 0xab
136
+
137
+
/* Supported charger modes */
138
+
#define PF1550_CHG_BAT_OFF 1
139
+
#define PF1550_CHG_BAT_ON 2
140
+
141
+
#define PF1550_CHG_PRECHARGE 0
142
+
#define PF1550_CHG_CONSTANT_CURRENT 1
143
+
#define PF1550_CHG_CONSTANT_VOL 2
144
+
#define PF1550_CHG_EOC 3
145
+
#define PF1550_CHG_DONE 4
146
+
#define PF1550_CHG_TIMER_FAULT 6
147
+
#define PF1550_CHG_SUSPEND 7
148
+
#define PF1550_CHG_OFF_INV 8
149
+
#define PF1550_CHG_BAT_OVER 9
150
+
#define PF1550_CHG_OFF_TEMP 10
151
+
#define PF1550_CHG_LINEAR_ONLY 12
152
+
#define PF1550_CHG_SNS_MASK 0xf
153
+
#define PF1550_CHG_INT_MASK 0x51
154
+
155
+
#define PF1550_BAT_NO_VBUS 0
156
+
#define PF1550_BAT_LOW_THAN_PRECHARG 1
157
+
#define PF1550_BAT_CHARG_FAIL 2
158
+
#define PF1550_BAT_HIGH_THAN_PRECHARG 4
159
+
#define PF1550_BAT_OVER_VOL 5
160
+
#define PF1550_BAT_NO_DETECT 6
161
+
#define PF1550_BAT_SNS_MASK 0x7
162
+
163
+
#define PF1550_VBUS_UVLO BIT(2)
164
+
#define PF1550_VBUS_IN2SYS BIT(3)
165
+
#define PF1550_VBUS_OVLO BIT(4)
166
+
#define PF1550_VBUS_VALID BIT(5)
167
+
168
+
#define PF1550_CHARG_REG_BATT_REG_CHGCV_MASK 0x3f
169
+
#define PF1550_CHARG_REG_BATT_REG_VMINSYS_SHIFT 6
170
+
#define PF1550_CHARG_REG_BATT_REG_VMINSYS_MASK GENMASK(7, 6)
171
+
#define PF1550_CHARG_REG_THM_REG_CNFG_REGTEMP_SHIFT 2
172
+
#define PF1550_CHARG_REG_THM_REG_CNFG_REGTEMP_MASK GENMASK(3, 2)
173
+
174
+
#define PF1550_ONKEY_RST_EN BIT(7)
175
+
176
+
/* DVS enable masks */
177
+
#define OTP_SW1_DVS_ENB BIT(1)
178
+
#define OTP_SW2_DVS_ENB BIT(3)
179
+
180
+
/* Top level interrupt masks */
181
+
#define IRQ_REGULATOR (BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(6))
182
+
#define IRQ_ONKEY BIT(5)
183
+
#define IRQ_CHG BIT(0)
184
+
185
+
/* Regulator interrupt masks */
186
+
#define PMIC_IRQ_SW1_LS BIT(0)
187
+
#define PMIC_IRQ_SW2_LS BIT(1)
188
+
#define PMIC_IRQ_SW3_LS BIT(2)
189
+
#define PMIC_IRQ_SW1_HS BIT(0)
190
+
#define PMIC_IRQ_SW2_HS BIT(1)
191
+
#define PMIC_IRQ_SW3_HS BIT(2)
192
+
#define PMIC_IRQ_LDO1_FAULT BIT(0)
193
+
#define PMIC_IRQ_LDO2_FAULT BIT(1)
194
+
#define PMIC_IRQ_LDO3_FAULT BIT(2)
195
+
#define PMIC_IRQ_TEMP_110 BIT(0)
196
+
#define PMIC_IRQ_TEMP_125 BIT(1)
197
+
198
+
/* Onkey interrupt masks */
199
+
#define ONKEY_IRQ_PUSHI BIT(0)
200
+
#define ONKEY_IRQ_1SI BIT(1)
201
+
#define ONKEY_IRQ_2SI BIT(2)
202
+
#define ONKEY_IRQ_3SI BIT(3)
203
+
#define ONKEY_IRQ_4SI BIT(4)
204
+
#define ONKEY_IRQ_8SI BIT(5)
205
+
206
+
/* Charger interrupt masks */
207
+
#define CHARG_IRQ_BAT2SOCI BIT(1)
208
+
#define CHARG_IRQ_BATI BIT(2)
209
+
#define CHARG_IRQ_CHGI BIT(3)
210
+
#define CHARG_IRQ_VBUSI BIT(5)
211
+
#define CHARG_IRQ_DPMI BIT(6)
212
+
#define CHARG_IRQ_THMI BIT(7)
213
+
214
+
enum pf1550_irq {
215
+
PF1550_IRQ_CHG,
216
+
PF1550_IRQ_REGULATOR,
217
+
PF1550_IRQ_ONKEY,
218
+
};
219
+
220
+
enum pf1550_pmic_irq {
221
+
PF1550_PMIC_IRQ_SW1_LS,
222
+
PF1550_PMIC_IRQ_SW2_LS,
223
+
PF1550_PMIC_IRQ_SW3_LS,
224
+
PF1550_PMIC_IRQ_SW1_HS,
225
+
PF1550_PMIC_IRQ_SW2_HS,
226
+
PF1550_PMIC_IRQ_SW3_HS,
227
+
PF1550_PMIC_IRQ_LDO1_FAULT,
228
+
PF1550_PMIC_IRQ_LDO2_FAULT,
229
+
PF1550_PMIC_IRQ_LDO3_FAULT,
230
+
PF1550_PMIC_IRQ_TEMP_110,
231
+
PF1550_PMIC_IRQ_TEMP_125,
232
+
};
233
+
234
+
enum pf1550_onkey_irq {
235
+
PF1550_ONKEY_IRQ_PUSHI,
236
+
PF1550_ONKEY_IRQ_1SI,
237
+
PF1550_ONKEY_IRQ_2SI,
238
+
PF1550_ONKEY_IRQ_3SI,
239
+
PF1550_ONKEY_IRQ_4SI,
240
+
PF1550_ONKEY_IRQ_8SI,
241
+
};
242
+
243
+
enum pf1550_charg_irq {
244
+
PF1550_CHARG_IRQ_BAT2SOCI,
245
+
PF1550_CHARG_IRQ_BATI,
246
+
PF1550_CHARG_IRQ_CHGI,
247
+
PF1550_CHARG_IRQ_VBUSI,
248
+
PF1550_CHARG_IRQ_THMI,
249
+
};
250
+
251
+
enum pf1550_regulators {
252
+
PF1550_SW1,
253
+
PF1550_SW2,
254
+
PF1550_SW3,
255
+
PF1550_VREFDDR,
256
+
PF1550_LDO1,
257
+
PF1550_LDO2,
258
+
PF1550_LDO3,
259
+
};
260
+
261
+
struct pf1550_ddata {
262
+
struct regmap_irq_chip_data *irq_data_regulator;
263
+
struct regmap_irq_chip_data *irq_data_charger;
264
+
struct regmap_irq_chip_data *irq_data_onkey;
265
+
struct regmap_irq_chip_data *irq_data;
266
+
struct regmap *regmap;
267
+
struct device *dev;
268
+
bool dvs1_enable;
269
+
bool dvs2_enable;
270
+
int irq;
271
+
};
272
+
273
+
#endif /* __LINUX_MFD_PF1550_H */
+3
include/linux/regulator/driver.h
+3
include/linux/regulator/driver.h
+330
include/linux/regulator/mt6363-regulator.h
+330
include/linux/regulator/mt6363-regulator.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2024 MediaTek Inc.
4
+
* Copyright (c) 2025 Collabora Ltd
5
+
*/
6
+
7
+
#include <linux/bits.h>
8
+
9
+
#ifndef __LINUX_REGULATOR_MT6363_H
10
+
#define __LINUX_REGULATOR_MT6363_H
11
+
12
+
/* Register */
13
+
#define MT6363_TOP_TRAP 0x6
14
+
#define MT6363_TOP_TMA_KEY_L 0x36e
15
+
#define MT6363_RG_BUCK0_EN_ADDR 0x210
16
+
#define MT6363_RG_BUCK_VS2_EN_BIT 0
17
+
#define MT6363_RG_BUCK_VBUCK1_EN_BIT 1
18
+
#define MT6363_RG_BUCK_VBUCK2_EN_BIT 2
19
+
#define MT6363_RG_BUCK_VBUCK3_EN_BIT 3
20
+
#define MT6363_RG_BUCK_VBUCK4_EN_BIT 4
21
+
#define MT6363_RG_BUCK_VBUCK5_EN_BIT 5
22
+
#define MT6363_RG_BUCK_VBUCK6_EN_BIT 6
23
+
#define MT6363_RG_BUCK_VBUCK7_EN_BIT 7
24
+
#define MT6363_RG_BUCK1_EN_ADDR 0x213
25
+
#define MT6363_RG_BUCK_VS1_EN_BIT 0
26
+
#define MT6363_RG_BUCK_VS3_EN_BIT 1
27
+
#define MT6363_RG_LDO_VSRAM_DIGRF_EN_BIT 4
28
+
#define MT6363_RG_LDO_VSRAM_MDFE_EN_BIT 5
29
+
#define MT6363_RG_LDO_VSRAM_MODEM_EN_BIT 6
30
+
#define MT6363_RG_BUCK0_LP_ADDR 0x216
31
+
#define MT6363_RG_BUCK_VS2_LP_BIT 0
32
+
#define MT6363_RG_BUCK_VBUCK1_LP_BIT 1
33
+
#define MT6363_RG_BUCK_VBUCK2_LP_BIT 2
34
+
#define MT6363_RG_BUCK_VBUCK3_LP_BIT 3
35
+
#define MT6363_RG_BUCK_VBUCK4_LP_BIT 4
36
+
#define MT6363_RG_BUCK_VBUCK5_LP_BIT 5
37
+
#define MT6363_RG_BUCK_VBUCK6_LP_BIT 6
38
+
#define MT6363_RG_BUCK_VBUCK7_LP_BIT 7
39
+
#define MT6363_RG_BUCK1_LP_ADDR 0x219
40
+
#define MT6363_RG_BUCK_VS1_LP_BIT 0
41
+
#define MT6363_RG_BUCK_VS3_LP_BIT 1
42
+
#define MT6363_RG_LDO_VSRAM_DIGRF_LP_BIT 4
43
+
#define MT6363_RG_LDO_VSRAM_MDFE_LP_BIT 5
44
+
#define MT6363_RG_LDO_VSRAM_MODEM_LP_BIT 6
45
+
#define MT6363_RG_BUCK_VS2_VOSEL_ADDR 0x21c
46
+
#define MT6363_RG_BUCK_VS2_VOSEL_MASK GENMASK(7, 0)
47
+
#define MT6363_RG_BUCK_VBUCK1_VOSEL_ADDR 0x21d
48
+
#define MT6363_RG_BUCK_VBUCK1_VOSEL_MASK GENMASK(7, 0)
49
+
#define MT6363_RG_BUCK_VBUCK2_VOSEL_ADDR 0x21e
50
+
#define MT6363_RG_BUCK_VBUCK2_VOSEL_MASK GENMASK(7, 0)
51
+
#define MT6363_RG_BUCK_VBUCK3_VOSEL_ADDR 0x21f
52
+
#define MT6363_RG_BUCK_VBUCK3_VOSEL_MASK GENMASK(7, 0)
53
+
#define MT6363_RG_BUCK_VBUCK4_VOSEL_ADDR 0x220
54
+
#define MT6363_RG_BUCK_VBUCK4_VOSEL_MASK GENMASK(7, 0)
55
+
#define MT6363_RG_BUCK_VBUCK5_VOSEL_ADDR 0x221
56
+
#define MT6363_RG_BUCK_VBUCK5_VOSEL_MASK GENMASK(7, 0)
57
+
#define MT6363_RG_BUCK_VBUCK6_VOSEL_ADDR 0x222
58
+
#define MT6363_RG_BUCK_VBUCK6_VOSEL_MASK GENMASK(7, 0)
59
+
#define MT6363_RG_BUCK_VBUCK7_VOSEL_ADDR 0x223
60
+
#define MT6363_RG_BUCK_VBUCK7_VOSEL_MASK GENMASK(7, 0)
61
+
#define MT6363_RG_BUCK_VS1_VOSEL_ADDR 0x224
62
+
#define MT6363_RG_BUCK_VS1_VOSEL_MASK GENMASK(7, 0)
63
+
#define MT6363_RG_BUCK_VS3_VOSEL_ADDR 0x225
64
+
#define MT6363_RG_BUCK_VS3_VOSEL_MASK GENMASK(7, 0)
65
+
#define MT6363_RG_LDO_VSRAM_DIGRF_VOSEL_ADDR 0x228
66
+
#define MT6363_RG_LDO_VSRAM_DIGRF_VOSEL_MASK GENMASK(6, 0)
67
+
#define MT6363_RG_LDO_VSRAM_MDFE_VOSEL_ADDR 0x229
68
+
#define MT6363_RG_LDO_VSRAM_MDFE_VOSEL_MASK GENMASK(6, 0)
69
+
#define MT6363_RG_LDO_VSRAM_MODEM_VOSEL_ADDR 0x22a
70
+
#define MT6363_RG_LDO_VSRAM_MODEM_VOSEL_MASK GENMASK(6, 0)
71
+
#define MT6363_BUCK_TOP_KEY_PROT_LO 0x13fa
72
+
#define MT6363_BUCK_VS2_WDTDBG_VOSEL_ADDR 0x13fc
73
+
#define MT6363_BUCK_VBUCK1_WDTDBG_VOSEL_ADDR 0x13fd
74
+
#define MT6363_BUCK_VBUCK2_WDTDBG_VOSEL_ADDR 0x13fe
75
+
#define MT6363_BUCK_VBUCK3_WDTDBG_VOSEL_ADDR 0x13ff
76
+
#define MT6363_BUCK_VBUCK4_WDTDBG_VOSEL_ADDR 0x1400
77
+
#define MT6363_BUCK_VBUCK5_WDTDBG_VOSEL_ADDR 0x1401
78
+
#define MT6363_BUCK_VBUCK6_WDTDBG_VOSEL_ADDR 0x1402
79
+
#define MT6363_BUCK_VBUCK7_WDTDBG_VOSEL_ADDR 0x1403
80
+
#define MT6363_BUCK_VS1_WDTDBG_VOSEL_ADDR 0x1404
81
+
#define MT6363_BUCK_VS3_WDTDBG_VOSEL_ADDR 0x1405
82
+
#define MT6363_RG_BUCK_EFUSE_RSV1 0x1417
83
+
#define MT6363_RG_BUCK_EFUSE_RSV1_MASK GENMASK(7, 4)
84
+
#define MT6363_BUCK_VS2_OP_EN_0 0x145d
85
+
#define MT6363_BUCK_VS2_HW_LP_MODE 0x1468
86
+
#define MT6363_BUCK_VBUCK1_OP_EN_0 0x14dd
87
+
#define MT6363_BUCK_VBUCK1_HW_LP_MODE 0x14e8
88
+
#define MT6363_RG_BUCK_VBUCK1_SSHUB_EN_ADDR 0x14ea
89
+
#define MT6363_RG_BUCK_VBUCK1_SSHUB_VOSEL_ADDR 0x14eb
90
+
#define MT6363_RG_BUCK_VBUCK1_SSHUB_VOSEL_MASK GENMASK(7, 0)
91
+
#define MT6363_BUCK_VBUCK2_OP_EN_0 0x155d
92
+
#define MT6363_BUCK_VBUCK2_HW_LP_MODE 0x1568
93
+
#define MT6363_RG_BUCK_VBUCK2_SSHUB_EN_ADDR 0x156a
94
+
#define MT6363_RG_BUCK_VBUCK2_SSHUB_VOSEL_ADDR 0x156b
95
+
#define MT6363_RG_BUCK_VBUCK2_SSHUB_VOSEL_MASK GENMASK(7, 0)
96
+
#define MT6363_BUCK_VBUCK3_OP_EN_0 0x15dd
97
+
#define MT6363_BUCK_VBUCK3_HW_LP_MODE 0x15e8
98
+
#define MT6363_BUCK_VBUCK4_OP_EN_0 0x165d
99
+
#define MT6363_BUCK_VBUCK4_HW_LP_MODE 0x1668
100
+
#define MT6363_RG_BUCK_VBUCK4_SSHUB_EN_ADDR 0x166a
101
+
#define MT6363_RG_BUCK_VBUCK4_SSHUB_VOSEL_ADDR 0x166b
102
+
#define MT6363_RG_BUCK_VBUCK4_SSHUB_VOSEL_MASK GENMASK(7, 0)
103
+
#define MT6363_BUCK_VBUCK5_OP_EN_0 0x16dd
104
+
#define MT6363_BUCK_VBUCK5_HW_LP_MODE 0x16e8
105
+
#define MT6363_BUCK_VBUCK6_OP_EN_0 0x175d
106
+
#define MT6363_BUCK_VBUCK6_HW_LP_MODE 0x1768
107
+
#define MT6363_BUCK_VBUCK7_OP_EN_0 0x17dd
108
+
#define MT6363_BUCK_VBUCK7_HW_LP_MODE 0x17e8
109
+
#define MT6363_BUCK_VS1_OP_EN_0 0x185d
110
+
#define MT6363_BUCK_VS1_HW_LP_MODE 0x1868
111
+
#define MT6363_BUCK_VS3_OP_EN_0 0x18dd
112
+
#define MT6363_BUCK_VS3_HW_LP_MODE 0x18e8
113
+
#define MT6363_RG_VS1_FCCM_ADDR 0x1964
114
+
#define MT6363_RG_VS1_FCCM_BIT 0
115
+
#define MT6363_RG_VS3_FCCM_ADDR 0x1973
116
+
#define MT6363_RG_VS3_FCCM_BIT 0
117
+
#define MT6363_RG_BUCK0_FCCM_ADDR 0x1a02
118
+
#define MT6363_RG_VBUCK1_FCCM_BIT 0
119
+
#define MT6363_RG_VBUCK2_FCCM_BIT 1
120
+
#define MT6363_RG_VBUCK3_FCCM_BIT 2
121
+
#define MT6363_RG_VS2_FCCM_BIT 3
122
+
#define MT6363_RG_BUCK0_1_FCCM_ADDR 0x1a82
123
+
#define MT6363_RG_VBUCK4_FCCM_BIT 0
124
+
#define MT6363_RG_VBUCK5_FCCM_BIT 1
125
+
#define MT6363_RG_VBUCK6_FCCM_BIT 2
126
+
#define MT6363_RG_VBUCK7_FCCM_BIT 3
127
+
#define MT6363_RG_VCN13_VOSEL_ADDR 0x1b0f
128
+
#define MT6363_RG_VCN13_VOSEL_MASK GENMASK(3, 0)
129
+
#define MT6363_RG_VEMC_VOSEL_ADDR 0x1b10
130
+
#define MT6363_RG_VEMC_VOSEL_MASK GENMASK(3, 0)
131
+
#define MT6363_RG_VEMC_VOSEL_1_MASK GENMASK(7, 4)
132
+
#define MT6363_RG_LDO_VSRAM_CPUB_VOSEL_ADDR 0x1b14
133
+
#define MT6363_RG_LDO_VSRAM_CPUB_VOSEL_MASK GENMASK(6, 0)
134
+
#define MT6363_RG_LDO_VSRAM_CPUM_VOSEL_ADDR 0x1b15
135
+
#define MT6363_RG_LDO_VSRAM_CPUM_VOSEL_MASK GENMASK(6, 0)
136
+
#define MT6363_RG_LDO_VSRAM_CPUL_VOSEL_ADDR 0x1b16
137
+
#define MT6363_RG_LDO_VSRAM_CPUL_VOSEL_MASK GENMASK(6, 0)
138
+
#define MT6363_RG_LDO_VSRAM_APU_VOSEL_ADDR 0x1b17
139
+
#define MT6363_RG_LDO_VSRAM_APU_VOSEL_MASK GENMASK(6, 0)
140
+
#define MT6363_RG_VEMC_VOCAL_ADDR 0x1b1b
141
+
#define MT6363_RG_VEMC_VOCAL_MASK GENMASK(3, 0)
142
+
#define MT6363_RG_LDO_VCN15_ADDR 0x1b57
143
+
#define MT6363_RG_LDO_VCN15_EN_BIT 0
144
+
#define MT6363_RG_LDO_VCN15_LP_BIT 1
145
+
#define MT6363_LDO_VCN15_HW_LP_MODE 0x1b5b
146
+
#define MT6363_LDO_VCN15_OP_EN0 0x1b5c
147
+
#define MT6363_RG_LDO_VRF09_ADDR 0x1b65
148
+
#define MT6363_RG_LDO_VRF09_EN_BIT 0
149
+
#define MT6363_RG_LDO_VRF09_LP_BIT 1
150
+
#define MT6363_LDO_VRF09_HW_LP_MODE 0x1b69
151
+
#define MT6363_LDO_VRF09_OP_EN0 0x1b6a
152
+
#define MT6363_RG_LDO_VRF12_ADDR 0x1b73
153
+
#define MT6363_RG_LDO_VRF12_EN_BIT 0
154
+
#define MT6363_RG_LDO_VRF12_LP_BIT 1
155
+
#define MT6363_LDO_VRF12_HW_LP_MODE 0x1b77
156
+
#define MT6363_LDO_VRF12_OP_EN0 0x1b78
157
+
#define MT6363_RG_LDO_VRF13_ADDR 0x1b81
158
+
#define MT6363_RG_LDO_VRF13_EN_BIT 0
159
+
#define MT6363_RG_LDO_VRF13_LP_BIT 1
160
+
#define MT6363_LDO_VRF13_HW_LP_MODE 0x1b85
161
+
#define MT6363_LDO_VRF13_OP_EN0 0x1b86
162
+
#define MT6363_RG_LDO_VRF18_ADDR 0x1b8f
163
+
#define MT6363_RG_LDO_VRF18_EN_BIT 0
164
+
#define MT6363_RG_LDO_VRF18_LP_BIT 1
165
+
#define MT6363_LDO_VRF18_HW_LP_MODE 0x1b93
166
+
#define MT6363_LDO_VRF18_OP_EN0 0x1b94
167
+
#define MT6363_RG_LDO_VRFIO18_ADDR 0x1b9d
168
+
#define MT6363_RG_LDO_VRFIO18_EN_BIT 0
169
+
#define MT6363_RG_LDO_VRFIO18_LP_BIT 1
170
+
#define MT6363_LDO_VRFIO18_HW_LP_MODE 0x1ba1
171
+
#define MT6363_LDO_VRFIO18_OP_EN0 0x1ba2
172
+
#define MT6363_RG_LDO_VTREF18_ADDR 0x1bd7
173
+
#define MT6363_RG_LDO_VTREF18_EN_BIT 0
174
+
#define MT6363_RG_LDO_VTREF18_LP_BIT 1
175
+
#define MT6363_LDO_VTREF18_HW_LP_MODE 0x1bdb
176
+
#define MT6363_LDO_VTREF18_OP_EN0 0x1bdc
177
+
#define MT6363_RG_LDO_VAUX18_ADDR 0x1be5
178
+
#define MT6363_RG_LDO_VAUX18_EN_BIT 0
179
+
#define MT6363_RG_LDO_VAUX18_LP_BIT 1
180
+
#define MT6363_LDO_VAUX18_HW_LP_MODE 0x1be9
181
+
#define MT6363_LDO_VAUX18_OP_EN0 0x1bea
182
+
#define MT6363_RG_LDO_VEMC_ADDR 0x1bf3
183
+
#define MT6363_RG_LDO_VEMC_EN_BIT 0
184
+
#define MT6363_RG_LDO_VEMC_LP_BIT 1
185
+
#define MT6363_LDO_VEMC_HW_LP_MODE 0x1bf7
186
+
#define MT6363_LDO_VEMC_OP_EN0 0x1bf8
187
+
#define MT6363_RG_LDO_VUFS12_ADDR 0x1c01
188
+
#define MT6363_RG_LDO_VUFS12_EN_BIT 0
189
+
#define MT6363_RG_LDO_VUFS12_LP_BIT 1
190
+
#define MT6363_LDO_VUFS12_HW_LP_MODE 0x1c05
191
+
#define MT6363_LDO_VUFS12_OP_EN0 0x1c06
192
+
#define MT6363_RG_LDO_VUFS18_ADDR 0x1c0f
193
+
#define MT6363_RG_LDO_VUFS18_EN_BIT 0
194
+
#define MT6363_RG_LDO_VUFS18_LP_BIT 1
195
+
#define MT6363_LDO_VUFS18_HW_LP_MODE 0x1c13
196
+
#define MT6363_LDO_VUFS18_OP_EN0 0x1c14
197
+
#define MT6363_RG_LDO_VIO18_ADDR 0x1c1d
198
+
#define MT6363_RG_LDO_VIO18_EN_BIT 0
199
+
#define MT6363_RG_LDO_VIO18_LP_BIT 1
200
+
#define MT6363_LDO_VIO18_HW_LP_MODE 0x1c21
201
+
#define MT6363_LDO_VIO18_OP_EN0 0x1c22
202
+
#define MT6363_RG_LDO_VIO075_ADDR 0x1c57
203
+
#define MT6363_RG_LDO_VIO075_EN_BIT 0
204
+
#define MT6363_RG_LDO_VIO075_LP_BIT 1
205
+
#define MT6363_LDO_VIO075_HW_LP_MODE 0x1c5b
206
+
#define MT6363_LDO_VIO075_OP_EN0 0x1c5c
207
+
#define MT6363_RG_LDO_VA12_1_ADDR 0x1c65
208
+
#define MT6363_RG_LDO_VA12_1_EN_BIT 0
209
+
#define MT6363_RG_LDO_VA12_1_LP_BIT 1
210
+
#define MT6363_LDO_VA12_1_HW_LP_MODE 0x1c69
211
+
#define MT6363_LDO_VA12_1_OP_EN0 0x1c6a
212
+
#define MT6363_RG_LDO_VA12_2_ADDR 0x1c73
213
+
#define MT6363_RG_LDO_VA12_2_EN_BIT 0
214
+
#define MT6363_RG_LDO_VA12_2_LP_BIT 1
215
+
#define MT6363_LDO_VA12_2_HW_LP_MODE 0x1c77
216
+
#define MT6363_LDO_VA12_2_OP_EN0 0x1c78
217
+
#define MT6363_RG_LDO_VA15_ADDR 0x1c81
218
+
#define MT6363_RG_LDO_VA15_EN_BIT 0
219
+
#define MT6363_RG_LDO_VA15_LP_BIT 1
220
+
#define MT6363_LDO_VA15_HW_LP_MODE 0x1c85
221
+
#define MT6363_LDO_VA15_OP_EN0 0x1c86
222
+
#define MT6363_RG_LDO_VM18_ADDR 0x1c8f
223
+
#define MT6363_RG_LDO_VM18_EN_BIT 0
224
+
#define MT6363_RG_LDO_VM18_LP_BIT 1
225
+
#define MT6363_LDO_VM18_HW_LP_MODE 0x1c93
226
+
#define MT6363_LDO_VM18_OP_EN0 0x1c94
227
+
#define MT6363_RG_LDO_VCN13_ADDR 0x1cd7
228
+
#define MT6363_RG_LDO_VCN13_EN_BIT 0
229
+
#define MT6363_RG_LDO_VCN13_LP_BIT 1
230
+
#define MT6363_LDO_VCN13_HW_LP_MODE 0x1cdb
231
+
#define MT6363_LDO_VCN13_OP_EN0 0x1ce4
232
+
#define MT6363_LDO_VSRAM_DIGRF_HW_LP_MODE 0x1cf1
233
+
#define MT6363_LDO_VSRAM_DIGRF_OP_EN0 0x1cfa
234
+
#define MT6363_LDO_VSRAM_MDFE_HW_LP_MODE 0x1d5b
235
+
#define MT6363_LDO_VSRAM_MDFE_OP_EN0 0x1d64
236
+
#define MT6363_LDO_VSRAM_MODEM_HW_LP_MODE 0x1d76
237
+
#define MT6363_LDO_VSRAM_MODEM_OP_EN0 0x1d7f
238
+
#define MT6363_RG_LDO_VSRAM_CPUB_ADDR 0x1dd7
239
+
#define MT6363_RG_LDO_VSRAM_CPUB_EN_BIT 0
240
+
#define MT6363_RG_LDO_VSRAM_CPUB_LP_BIT 1
241
+
#define MT6363_LDO_VSRAM_CPUB_HW_LP_MODE 0x1ddb
242
+
#define MT6363_LDO_VSRAM_CPUB_OP_EN0 0x1de4
243
+
#define MT6363_RG_LDO_VSRAM_CPUM_ADDR 0x1ded
244
+
#define MT6363_RG_LDO_VSRAM_CPUM_EN_BIT 0
245
+
#define MT6363_RG_LDO_VSRAM_CPUM_LP_BIT 1
246
+
#define MT6363_LDO_VSRAM_CPUM_HW_LP_MODE 0x1df1
247
+
#define MT6363_LDO_VSRAM_CPUM_OP_EN0 0x1dfa
248
+
#define MT6363_RG_LDO_VSRAM_CPUL_ADDR 0x1e57
249
+
#define MT6363_RG_LDO_VSRAM_CPUL_EN_BIT 0
250
+
#define MT6363_RG_LDO_VSRAM_CPUL_LP_BIT 1
251
+
#define MT6363_LDO_VSRAM_CPUL_HW_LP_MODE 0x1e5b
252
+
#define MT6363_LDO_VSRAM_CPUL_OP_EN0 0x1e64
253
+
#define MT6363_RG_LDO_VSRAM_APU_ADDR 0x1e6d
254
+
#define MT6363_RG_LDO_VSRAM_APU_EN_BIT 0
255
+
#define MT6363_RG_LDO_VSRAM_APU_LP_BIT 1
256
+
#define MT6363_LDO_VSRAM_APU_HW_LP_MODE 0x1e71
257
+
#define MT6363_LDO_VSRAM_APU_OP_EN0 0x1e7a
258
+
#define MT6363_RG_VTREF18_VOCAL_ADDR 0x1ed8
259
+
#define MT6363_RG_VTREF18_VOCAL_MASK GENMASK(3, 0)
260
+
#define MT6363_RG_VTREF18_VOSEL_ADDR 0x1ed9
261
+
#define MT6363_RG_VTREF18_VOSEL_MASK GENMASK(3, 0)
262
+
#define MT6363_RG_VAUX18_VOCAL_ADDR 0x1edc
263
+
#define MT6363_RG_VAUX18_VOCAL_MASK GENMASK(3, 0)
264
+
#define MT6363_RG_VAUX18_VOSEL_ADDR 0x1edd
265
+
#define MT6363_RG_VAUX18_VOSEL_MASK GENMASK(3, 0)
266
+
#define MT6363_RG_VCN15_VOCAL_ADDR 0x1ee3
267
+
#define MT6363_RG_VCN15_VOCAL_MASK GENMASK(3, 0)
268
+
#define MT6363_RG_VCN15_VOSEL_ADDR 0x1ee4
269
+
#define MT6363_RG_VCN15_VOSEL_MASK GENMASK(3, 0)
270
+
#define MT6363_RG_VUFS18_VOCAL_ADDR 0x1ee7
271
+
#define MT6363_RG_VUFS18_VOCAL_MASK GENMASK(3, 0)
272
+
#define MT6363_RG_VUFS18_VOSEL_ADDR 0x1ee8
273
+
#define MT6363_RG_VUFS18_VOSEL_MASK GENMASK(3, 0)
274
+
#define MT6363_RG_VIO18_VOCAL_ADDR 0x1eeb
275
+
#define MT6363_RG_VIO18_VOCAL_MASK GENMASK(3, 0)
276
+
#define MT6363_RG_VIO18_VOSEL_ADDR 0x1eec
277
+
#define MT6363_RG_VIO18_VOSEL_MASK GENMASK(3, 0)
278
+
#define MT6363_RG_VM18_VOCAL_ADDR 0x1eef
279
+
#define MT6363_RG_VM18_VOCAL_MASK GENMASK(3, 0)
280
+
#define MT6363_RG_VM18_VOSEL_ADDR 0x1ef0
281
+
#define MT6363_RG_VM18_VOSEL_MASK GENMASK(3, 0)
282
+
#define MT6363_RG_VA15_VOCAL_ADDR 0x1ef3
283
+
#define MT6363_RG_VA15_VOCAL_MASK GENMASK(3, 0)
284
+
#define MT6363_RG_VA15_VOSEL_ADDR 0x1ef4
285
+
#define MT6363_RG_VA15_VOSEL_MASK GENMASK(3, 0)
286
+
#define MT6363_RG_VRF18_VOCAL_ADDR 0x1ef7
287
+
#define MT6363_RG_VRF18_VOCAL_MASK GENMASK(3, 0)
288
+
#define MT6363_RG_VRF18_VOSEL_ADDR 0x1ef8
289
+
#define MT6363_RG_VRF18_VOSEL_MASK GENMASK(3, 0)
290
+
#define MT6363_RG_VRFIO18_VOCAL_ADDR 0x1efb
291
+
#define MT6363_RG_VRFIO18_VOCAL_MASK GENMASK(3, 0)
292
+
#define MT6363_RG_VRFIO18_VOSEL_ADDR 0x1efc
293
+
#define MT6363_RG_VRFIO18_VOSEL_MASK GENMASK(3, 0)
294
+
#define MT6363_RG_VIO075_VOCFG_ADDR 0x1f01
295
+
#define MT6363_RG_VIO075_VOCAL_ADDR MT6363_RG_VIO075_VOCFG_ADDR
296
+
#define MT6363_RG_VIO075_VOCAL_MASK GENMASK(3, 0)
297
+
#define MT6363_RG_VIO075_VOSEL_ADDR MT6363_RG_VIO075_VOCFG_ADDR
298
+
#define MT6363_RG_VIO075_VOSEL_MASK GENMASK(6, 4)
299
+
#define MT6363_RG_VCN13_VOCAL_ADDR 0x1f58
300
+
#define MT6363_RG_VCN13_VOCAL_MASK GENMASK(3, 0)
301
+
#define MT6363_RG_VUFS12_VOCAL_ADDR 0x1f61
302
+
#define MT6363_RG_VUFS12_VOCAL_MASK GENMASK(3, 0)
303
+
#define MT6363_RG_VUFS12_VOSEL_ADDR 0x1f62
304
+
#define MT6363_RG_VUFS12_VOSEL_MASK GENMASK(3, 0)
305
+
#define MT6363_RG_VA12_1_VOCAL_ADDR 0x1f65
306
+
#define MT6363_RG_VA12_1_VOCAL_MASK GENMASK(3, 0)
307
+
#define MT6363_RG_VA12_1_VOSEL_ADDR 0x1f66
308
+
#define MT6363_RG_VA12_1_VOSEL_MASK GENMASK(3, 0)
309
+
#define MT6363_RG_VA12_2_VOCAL_ADDR 0x1f69
310
+
#define MT6363_RG_VA12_2_VOCAL_MASK GENMASK(3, 0)
311
+
#define MT6363_RG_VA12_2_VOSEL_ADDR 0x1f6a
312
+
#define MT6363_RG_VA12_2_VOSEL_MASK GENMASK(3, 0)
313
+
#define MT6363_RG_VRF12_VOCAL_ADDR 0x1f6d
314
+
#define MT6363_RG_VRF12_VOCAL_MASK GENMASK(3, 0)
315
+
#define MT6363_RG_VRF12_VOSEL_ADDR 0x1f6e
316
+
#define MT6363_RG_VRF12_VOSEL_MASK GENMASK(3, 0)
317
+
#define MT6363_RG_VRF13_VOCAL_ADDR 0x1f71
318
+
#define MT6363_RG_VRF13_VOCAL_MASK GENMASK(3, 0)
319
+
#define MT6363_RG_VRF13_VOSEL_ADDR 0x1f72
320
+
#define MT6363_RG_VRF13_VOSEL_MASK GENMASK(3, 0)
321
+
#define MT6363_RG_VRF09_VOCAL_ADDR 0x1f78
322
+
#define MT6363_RG_VRF09_VOCAL_MASK GENMASK(3, 0)
323
+
#define MT6363_RG_VRF09_VOSEL_ADDR 0x1f79
324
+
#define MT6363_RG_VRF09_VOSEL_MASK GENMASK(3, 0)
325
+
#define MT6363_ISINK_EN_CTRL0 0x21db
326
+
#define MT6363_ISINK_CTRL0_MASK GENMASK(7, 0)
327
+
#define MT6363_ISINK_EN_CTRL1 0x21dc
328
+
#define MT6363_ISINK_CTRL1_MASK GENMASK(7, 4)
329
+
330
+
#endif /* __LINUX_REGULATOR_MT6363_H */
+32
include/linux/regulator/pca9450.h
+32
include/linux/regulator/pca9450.h
···
223
223
#define IRQ_THERM_105 0x02
224
224
#define IRQ_THERM_125 0x01
225
225
226
+
/* PCA9450_REG_PWRCTRL bits */
227
+
#define T_ON_DEB_MASK 0xC0
228
+
#define T_ON_DEB_120US (0 << 6)
229
+
#define T_ON_DEB_20MS (1 << 6)
230
+
#define T_ON_DEB_100MS (2 << 6)
231
+
#define T_ON_DEB_750MS (3 << 6)
232
+
#define T_OFF_DEB_MASK 0x20
233
+
#define T_OFF_DEB_120US (0 << 5)
234
+
#define T_OFF_DEB_2MS (1 << 5)
235
+
#define T_ON_STEP_MASK 0x18
236
+
#define T_ON_STEP_1MS (0 << 3)
237
+
#define T_ON_STEP_2MS (1 << 3)
238
+
#define T_ON_STEP_4MS (2 << 3)
239
+
#define T_ON_STEP_8MS (3 << 3)
240
+
#define T_OFF_STEP_MASK 0x06
241
+
#define T_OFF_STEP_2MS (0 << 1)
242
+
#define T_OFF_STEP_4MS (1 << 1)
243
+
#define T_OFF_STEP_8MS (2 << 1)
244
+
#define T_OFF_STEP_16MS (3 << 1)
245
+
#define T_RESTART_MASK 0x01
246
+
#define T_RESTART_250MS 0
247
+
#define T_RESTART_500MS 1
248
+
226
249
/* PCA9450_REG_RESET_CTRL bits */
227
250
#define WDOG_B_CFG_MASK 0xC0
228
251
#define WDOG_B_CFG_NONE 0x00
229
252
#define WDOG_B_CFG_WARM 0x40
230
253
#define WDOG_B_CFG_COLD_LDO12 0x80
231
254
#define WDOG_B_CFG_COLD 0xC0
255
+
#define T_PMIC_RST_DEB_MASK 0x07
256
+
#define T_PMIC_RST_DEB_10MS 0x00
257
+
#define T_PMIC_RST_DEB_50MS 0x01
258
+
#define T_PMIC_RST_DEB_100MS 0x02
259
+
#define T_PMIC_RST_DEB_500MS 0x03
260
+
#define T_PMIC_RST_DEB_1S 0x04
261
+
#define T_PMIC_RST_DEB_2S 0x05
262
+
#define T_PMIC_RST_DEB_4S 0x06
263
+
#define T_PMIC_RST_DEB_8S 0x07
232
264
233
265
/* PCA9450_REG_CONFIG2 bits */
234
266
#define I2C_LT_MASK 0x03