Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'rtw-next-2026-01-15' of https://github.com/pkshih/rtw
Ping-Ke Shih says:
==================
rtw-next patches for -next release.
Main changes are to prepare to support RTL8922DE, including refactor/add
register settings in common flow, and add newly firmware command/event
handlers.
Others are some random fixes and improvements across all drivers.
==================
Link: https://patch.msgid.link/006be16d-61ba-4af8-b76a-bc94100c3555@RTKEXHMBS03.realtek.com.tw
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
+3685
-401
+1
drivers/net/wireless/realtek/rtl8xxxu/core.c
+1
drivers/net/wireless/realtek/rtl8xxxu/core.c
+1
-1
drivers/net/wireless/realtek/rtlwifi/regd.c
+1
-1
drivers/net/wireless/realtek/rtlwifi/regd.c
···
206
206
}
207
207
208
208
/*
209
-
*If a country IE has been recieved check its rule for this
209
+
*If a country IE has been received check its rule for this
210
210
*channel first before enabling active scan. The passive scan
211
211
*would have been enforced by the initial processing of our
212
212
*custom regulatory domain.
+37
-17
drivers/net/wireless/realtek/rtw88/main.c
+37
-17
drivers/net/wireless/realtek/rtw88/main.c
···
730
730
}
731
731
EXPORT_SYMBOL(rtw_set_rx_freq_band);
732
732
733
-
void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period)
733
+
void rtw_set_dtim_period(struct rtw_dev *rtwdev, u8 dtim_period)
734
734
{
735
735
rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_TIMIE);
736
-
rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period - 1);
736
+
rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period ? dtim_period - 1 : 0);
737
737
}
738
738
739
739
void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel,
···
1483
1483
1484
1484
set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
1485
1485
set_bit(RTW_FLAG_SCANNING, rtwdev->flags);
1486
+
1487
+
rtw_phy_dig_set_max_coverage(rtwdev);
1486
1488
}
1487
1489
1488
1490
void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
···
1496
1494
if (!rtwvif)
1497
1495
return;
1498
1496
1497
+
rtw_phy_dig_reset(rtwdev);
1499
1498
clear_bit(RTW_FLAG_SCANNING, rtwdev->flags);
1500
1499
clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
1501
1500
···
1661
1658
return len;
1662
1659
}
1663
1660
1661
+
static struct ieee80211_supported_band *
1662
+
rtw_sband_dup(struct rtw_dev *rtwdev,
1663
+
const struct ieee80211_supported_band *sband)
1664
+
{
1665
+
struct ieee80211_supported_band *dup;
1666
+
1667
+
dup = devm_kmemdup(rtwdev->dev, sband, sizeof(*sband), GFP_KERNEL);
1668
+
if (!dup)
1669
+
return NULL;
1670
+
1671
+
dup->channels = devm_kmemdup_array(rtwdev->dev, sband->channels,
1672
+
sband->n_channels,
1673
+
sizeof(*sband->channels),
1674
+
GFP_KERNEL);
1675
+
if (!dup->channels)
1676
+
return NULL;
1677
+
1678
+
dup->bitrates = devm_kmemdup_array(rtwdev->dev, sband->bitrates,
1679
+
sband->n_bitrates,
1680
+
sizeof(*sband->bitrates),
1681
+
GFP_KERNEL);
1682
+
if (!dup->bitrates)
1683
+
return NULL;
1684
+
1685
+
return dup;
1686
+
}
1687
+
1664
1688
static void rtw_set_supported_band(struct ieee80211_hw *hw,
1665
1689
const struct rtw_chip_info *chip)
1666
1690
{
1667
-
struct rtw_dev *rtwdev = hw->priv;
1668
1691
struct ieee80211_supported_band *sband;
1692
+
struct rtw_dev *rtwdev = hw->priv;
1669
1693
1670
1694
if (chip->band & RTW_BAND_2G) {
1671
-
sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL);
1695
+
sband = rtw_sband_dup(rtwdev, &rtw_band_2ghz);
1672
1696
if (!sband)
1673
1697
goto err_out;
1674
1698
if (chip->ht_supported)
···
1704
1674
}
1705
1675
1706
1676
if (chip->band & RTW_BAND_5G) {
1707
-
sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL);
1677
+
sband = rtw_sband_dup(rtwdev, &rtw_band_5ghz);
1708
1678
if (!sband)
1709
1679
goto err_out;
1710
1680
if (chip->ht_supported)
···
1718
1688
1719
1689
err_out:
1720
1690
rtw_err(rtwdev, "failed to set supported band\n");
1721
-
}
1722
-
1723
-
static void rtw_unset_supported_band(struct ieee80211_hw *hw,
1724
-
const struct rtw_chip_info *chip)
1725
-
{
1726
-
kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
1727
-
kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]);
1728
1691
}
1729
1692
1730
1693
static void rtw_vif_smps_iter(void *data, u8 *mac,
···
2343
2320
2344
2321
void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
2345
2322
{
2346
-
const struct rtw_chip_info *chip = rtwdev->chip;
2347
-
2348
2323
ieee80211_unregister_hw(hw);
2349
-
rtw_unset_supported_band(hw, chip);
2350
2324
rtw_debugfs_deinit(rtwdev);
2351
2325
rtw_led_deinit(rtwdev);
2352
2326
}
···
2464
2444
2465
2445
if (enable) {
2466
2446
rtw_write32_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
2467
-
rtw_write32_clr(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE);
2447
+
rtw_write8_clr(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE);
2468
2448
} else {
2469
2449
rtw_write32_clr(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
2470
-
rtw_write32_set(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE);
2450
+
rtw_write8_set(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE);
2471
2451
}
2472
2452
}
2473
2453
+1
-1
drivers/net/wireless/realtek/rtw88/main.h
+1
-1
drivers/net/wireless/realtek/rtw88/main.h
···
2226
2226
}
2227
2227
2228
2228
void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel);
2229
-
void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period);
2229
+
void rtw_set_dtim_period(struct rtw_dev *rtwdev, u8 dtim_period);
2230
2230
void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
2231
2231
struct rtw_channel_params *ch_param);
2232
2232
bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
+20
drivers/net/wireless/realtek/rtw88/phy.c
+20
drivers/net/wireless/realtek/rtw88/phy.c
···
370
370
#define DIG_CVRG_MIN 0x1c
371
371
#define DIG_RSSI_GAIN_OFFSET 15
372
372
373
+
void rtw_phy_dig_set_max_coverage(struct rtw_dev *rtwdev)
374
+
{
375
+
/* Lower values result in greater coverage. */
376
+
rtw_dbg(rtwdev, RTW_DBG_PHY, "Setting IGI=%#x for max coverage\n",
377
+
DIG_CVRG_MIN);
378
+
379
+
rtw_phy_dig_write(rtwdev, DIG_CVRG_MIN);
380
+
}
381
+
382
+
void rtw_phy_dig_reset(struct rtw_dev *rtwdev)
383
+
{
384
+
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
385
+
u8 last_igi;
386
+
387
+
last_igi = dm_info->igi_history[0];
388
+
rtw_dbg(rtwdev, RTW_DBG_PHY, "Resetting IGI=%#x\n", last_igi);
389
+
390
+
rtw_phy_dig_write(rtwdev, last_igi);
391
+
}
392
+
373
393
static bool
374
394
rtw_phy_dig_check_damping(struct rtw_dm_info *dm_info)
375
395
{
+2
drivers/net/wireless/realtek/rtw88/phy.h
+2
drivers/net/wireless/realtek/rtw88/phy.h
+2
drivers/net/wireless/realtek/rtw88/rtw8821cu.c
+2
drivers/net/wireless/realtek/rtw88/rtw8821cu.c
···
37
37
.driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, /* Edimax */
38
38
{ USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xd811, 0xff, 0xff, 0xff),
39
39
.driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, /* Edimax */
40
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0105, 0xff, 0xff, 0xff),
41
+
.driver_info = (kernel_ulong_t)&(rtw8821c_hw_spec) }, /* Mercusys */
40
42
{},
41
43
};
42
44
MODULE_DEVICE_TABLE(usb, rtw_8821cu_id_table);
+2
-1
drivers/net/wireless/realtek/rtw88/rtw8822b.c
+2
-1
drivers/net/wireless/realtek/rtw88/rtw8822b.c
···
1005
1005
hal->antenna_tx = antenna_tx;
1006
1006
hal->antenna_rx = antenna_rx;
1007
1007
1008
-
rtw8822b_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false);
1008
+
if (test_bit(RTW_FLAG_POWERON, rtwdev->flags))
1009
+
rtw8822b_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false);
1009
1010
1010
1011
return 0;
1011
1012
}
+134
drivers/net/wireless/realtek/rtw89/cam.c
+134
drivers/net/wireless/realtek/rtw89/cam.c
···
1140
1140
le32_encode_bits(mld_bssid[5], DCTLINFO_V2_W12_MLD_BSSID_5);
1141
1141
h2c->m12 = cpu_to_le32(DCTLINFO_V2_W12_ALL);
1142
1142
}
1143
+
1144
+
void rtw89_cam_fill_dctl_sec_cam_info_v3(struct rtw89_dev *rtwdev,
1145
+
struct rtw89_vif_link *rtwvif_link,
1146
+
struct rtw89_sta_link *rtwsta_link,
1147
+
struct rtw89_h2c_dctlinfo_ud_v3 *h2c)
1148
+
{
1149
+
struct ieee80211_sta *sta = rtwsta_link_to_sta_safe(rtwsta_link);
1150
+
struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif_link->rtwvif);
1151
+
struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
1152
+
struct rtw89_addr_cam_entry *addr_cam =
1153
+
rtw89_get_addr_cam_of(rtwvif_link, rtwsta_link);
1154
+
bool is_mld = sta ? sta->mlo : ieee80211_vif_is_mld(vif);
1155
+
struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
1156
+
u8 *ptk_tx_iv = rtw_wow->key_info.ptk_tx_iv;
1157
+
u8 *mld_sma, *mld_tma, *mld_bssid;
1158
+
1159
+
h2c->c0 = le32_encode_bits(rtwsta_link ? rtwsta_link->mac_id :
1160
+
rtwvif_link->mac_id,
1161
+
DCTLINFO_V3_C0_MACID) |
1162
+
le32_encode_bits(1, DCTLINFO_V3_C0_OP);
1163
+
1164
+
h2c->w2 = le32_encode_bits(is_mld, DCTLINFO_V3_W2_IS_MLD);
1165
+
h2c->m2 = cpu_to_le32(DCTLINFO_V3_W2_IS_MLD);
1166
+
1167
+
h2c->w4 = le32_encode_bits(addr_cam->sec_ent_keyid[0],
1168
+
DCTLINFO_V3_W4_SEC_ENT0_KEYID) |
1169
+
le32_encode_bits(addr_cam->sec_ent_keyid[1],
1170
+
DCTLINFO_V3_W4_SEC_ENT1_KEYID) |
1171
+
le32_encode_bits(addr_cam->sec_ent_keyid[2],
1172
+
DCTLINFO_V3_W4_SEC_ENT2_KEYID) |
1173
+
le32_encode_bits(addr_cam->sec_ent_keyid[3],
1174
+
DCTLINFO_V3_W4_SEC_ENT3_KEYID) |
1175
+
le32_encode_bits(addr_cam->sec_ent_keyid[4],
1176
+
DCTLINFO_V3_W4_SEC_ENT4_KEYID) |
1177
+
le32_encode_bits(addr_cam->sec_ent_keyid[5],
1178
+
DCTLINFO_V3_W4_SEC_ENT5_KEYID) |
1179
+
le32_encode_bits(addr_cam->sec_ent_keyid[6],
1180
+
DCTLINFO_V3_W4_SEC_ENT6_KEYID);
1181
+
h2c->m4 = cpu_to_le32(DCTLINFO_V3_W4_SEC_ENT0_KEYID |
1182
+
DCTLINFO_V3_W4_SEC_ENT1_KEYID |
1183
+
DCTLINFO_V3_W4_SEC_ENT2_KEYID |
1184
+
DCTLINFO_V3_W4_SEC_ENT3_KEYID |
1185
+
DCTLINFO_V3_W4_SEC_ENT4_KEYID |
1186
+
DCTLINFO_V3_W4_SEC_ENT5_KEYID |
1187
+
DCTLINFO_V3_W4_SEC_ENT6_KEYID);
1188
+
1189
+
h2c->w5 = le32_encode_bits(addr_cam->sec_cam_map[0],
1190
+
DCTLINFO_V3_W5_SEC_ENT_VALID_V1);
1191
+
h2c->m5 = cpu_to_le32(DCTLINFO_V3_W5_SEC_ENT_VALID_V1);
1192
+
1193
+
h2c->w6 = le32_encode_bits(addr_cam->sec_ent[0],
1194
+
DCTLINFO_V3_W6_SEC_ENT0_V2) |
1195
+
le32_encode_bits(addr_cam->sec_ent[1],
1196
+
DCTLINFO_V3_W6_SEC_ENT1_V2) |
1197
+
le32_encode_bits(addr_cam->sec_ent[2],
1198
+
DCTLINFO_V3_W6_SEC_ENT2_V2);
1199
+
h2c->m6 = cpu_to_le32(DCTLINFO_V3_W6_SEC_ENT0_V2 |
1200
+
DCTLINFO_V3_W6_SEC_ENT1_V2 |
1201
+
DCTLINFO_V3_W6_SEC_ENT2_V2);
1202
+
1203
+
h2c->w7 = le32_encode_bits(addr_cam->sec_ent[3],
1204
+
DCTLINFO_V3_W7_SEC_ENT3_V2) |
1205
+
le32_encode_bits(addr_cam->sec_ent[4],
1206
+
DCTLINFO_V3_W7_SEC_ENT4_V2) |
1207
+
le32_encode_bits(addr_cam->sec_ent[5],
1208
+
DCTLINFO_V3_W7_SEC_ENT5_V2);
1209
+
h2c->m7 = cpu_to_le32(DCTLINFO_V3_W7_SEC_ENT3_V2 |
1210
+
DCTLINFO_V3_W7_SEC_ENT4_V2 |
1211
+
DCTLINFO_V3_W7_SEC_ENT5_V2);
1212
+
1213
+
h2c->w8 = le32_encode_bits(addr_cam->sec_ent[6],
1214
+
DCTLINFO_V3_W8_SEC_ENT6_V2);
1215
+
h2c->m8 = cpu_to_le32(DCTLINFO_V3_W8_SEC_ENT6_V2);
1216
+
1217
+
if (rtw_wow->ptk_alg) {
1218
+
h2c->w0 = le32_encode_bits(ptk_tx_iv[0] | ptk_tx_iv[1] << 8,
1219
+
DCTLINFO_V3_W0_AES_IV_L);
1220
+
h2c->m0 = cpu_to_le32(DCTLINFO_V3_W0_AES_IV_L);
1221
+
1222
+
h2c->w1 = le32_encode_bits(ptk_tx_iv[4] |
1223
+
ptk_tx_iv[5] << 8 |
1224
+
ptk_tx_iv[6] << 16 |
1225
+
ptk_tx_iv[7] << 24,
1226
+
DCTLINFO_V3_W1_AES_IV_H);
1227
+
h2c->m1 = cpu_to_le32(DCTLINFO_V3_W1_AES_IV_H);
1228
+
1229
+
h2c->w4 |= le32_encode_bits(rtw_wow->ptk_keyidx,
1230
+
DCTLINFO_V3_W4_SEC_KEY_ID);
1231
+
h2c->m4 |= cpu_to_le32(DCTLINFO_V3_W4_SEC_KEY_ID);
1232
+
}
1233
+
1234
+
if (!is_mld)
1235
+
return;
1236
+
1237
+
if (rtwvif_link->net_type == RTW89_NET_TYPE_INFRA) {
1238
+
mld_sma = rtwvif->mac_addr;
1239
+
mld_tma = vif->cfg.ap_addr;
1240
+
mld_bssid = vif->cfg.ap_addr;
1241
+
} else if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE && sta) {
1242
+
mld_sma = rtwvif->mac_addr;
1243
+
mld_tma = sta->addr;
1244
+
mld_bssid = rtwvif->mac_addr;
1245
+
} else {
1246
+
return;
1247
+
}
1248
+
1249
+
h2c->w9 = le32_encode_bits(mld_sma[0], DCTLINFO_V3_W9_MLD_SMA_0_V2) |
1250
+
le32_encode_bits(mld_sma[1], DCTLINFO_V3_W9_MLD_SMA_1_V2) |
1251
+
le32_encode_bits(mld_sma[2], DCTLINFO_V3_W9_MLD_SMA_2_V2) |
1252
+
le32_encode_bits(mld_sma[3], DCTLINFO_V3_W9_MLD_SMA_3_V2);
1253
+
h2c->m9 = cpu_to_le32(DCTLINFO_V3_W9_ALL);
1254
+
1255
+
h2c->w10 = le32_encode_bits(mld_sma[4], DCTLINFO_V3_W10_MLD_SMA_4_V2) |
1256
+
le32_encode_bits(mld_sma[5], DCTLINFO_V3_W10_MLD_SMA_5_V2) |
1257
+
le32_encode_bits(mld_tma[0], DCTLINFO_V3_W10_MLD_TMA_0_V2) |
1258
+
le32_encode_bits(mld_tma[1], DCTLINFO_V3_W10_MLD_TMA_1_V2);
1259
+
h2c->m10 = cpu_to_le32(DCTLINFO_V3_W10_ALL);
1260
+
1261
+
h2c->w11 = le32_encode_bits(mld_tma[2], DCTLINFO_V3_W11_MLD_TMA_2_V2) |
1262
+
le32_encode_bits(mld_tma[3], DCTLINFO_V3_W11_MLD_TMA_3_V2) |
1263
+
le32_encode_bits(mld_tma[4], DCTLINFO_V3_W11_MLD_TMA_4_V2) |
1264
+
le32_encode_bits(mld_tma[5], DCTLINFO_V3_W11_MLD_TMA_5_V2);
1265
+
h2c->m11 = cpu_to_le32(DCTLINFO_V3_W11_ALL);
1266
+
1267
+
h2c->w12 = le32_encode_bits(mld_bssid[0], DCTLINFO_V3_W12_MLD_TA_BSSID_0_V2) |
1268
+
le32_encode_bits(mld_bssid[1], DCTLINFO_V3_W12_MLD_TA_BSSID_1_V2) |
1269
+
le32_encode_bits(mld_bssid[2], DCTLINFO_V3_W12_MLD_TA_BSSID_2_V2) |
1270
+
le32_encode_bits(mld_bssid[3], DCTLINFO_V3_W12_MLD_TA_BSSID_3_V2);
1271
+
h2c->m12 = cpu_to_le32(DCTLINFO_V3_W12_ALL);
1272
+
1273
+
h2c->w13 = le32_encode_bits(mld_bssid[4], DCTLINFO_V3_W13_MLD_TA_BSSID_4_V2) |
1274
+
le32_encode_bits(mld_bssid[5], DCTLINFO_V3_W13_MLD_TA_BSSID_5_V2);
1275
+
h2c->m13 = cpu_to_le32(DCTLINFO_V3_W13_ALL);
1276
+
}
+129
drivers/net/wireless/realtek/rtw89/cam.h
+129
drivers/net/wireless/realtek/rtw89/cam.h
···
302
302
#define DCTLINFO_V2_W12_MLD_BSSID_5 GENMASK(15, 8)
303
303
#define DCTLINFO_V2_W12_ALL GENMASK(15, 0)
304
304
305
+
struct rtw89_h2c_dctlinfo_ud_v3 {
306
+
__le32 c0;
307
+
__le32 w0;
308
+
__le32 w1;
309
+
__le32 w2;
310
+
__le32 w3;
311
+
__le32 w4;
312
+
__le32 w5;
313
+
__le32 w6;
314
+
__le32 w7;
315
+
__le32 w8;
316
+
__le32 w9;
317
+
__le32 w10;
318
+
__le32 w11;
319
+
__le32 w12;
320
+
__le32 w13;
321
+
__le32 w14;
322
+
__le32 w15;
323
+
__le32 m0;
324
+
__le32 m1;
325
+
__le32 m2;
326
+
__le32 m3;
327
+
__le32 m4;
328
+
__le32 m5;
329
+
__le32 m6;
330
+
__le32 m7;
331
+
__le32 m8;
332
+
__le32 m9;
333
+
__le32 m10;
334
+
__le32 m11;
335
+
__le32 m12;
336
+
__le32 m13;
337
+
__le32 m14;
338
+
__le32 m15;
339
+
} __packed;
340
+
341
+
#define DCTLINFO_V3_C0_MACID GENMASK(15, 0)
342
+
#define DCTLINFO_V3_C0_OP BIT(16)
343
+
344
+
#define DCTLINFO_V3_W0_QOS_FIELD_H GENMASK(7, 0)
345
+
#define DCTLINFO_V3_W0_HW_EXSEQ_MACID GENMASK(14, 8)
346
+
#define DCTLINFO_V3_W0_QOS_DATA BIT(15)
347
+
#define DCTLINFO_V3_W0_AES_IV_L GENMASK(31, 16)
348
+
#define DCTLINFO_V3_W0_ALL GENMASK(31, 0)
349
+
#define DCTLINFO_V3_W1_AES_IV_H GENMASK(31, 0)
350
+
#define DCTLINFO_V3_W1_ALL GENMASK(31, 0)
351
+
#define DCTLINFO_V3_W2_SEQ0 GENMASK(11, 0)
352
+
#define DCTLINFO_V3_W2_SEQ1 GENMASK(23, 12)
353
+
#define DCTLINFO_V3_W2_AMSDU_MAX_LEN GENMASK(26, 24)
354
+
#define DCTLINFO_V3_W2_STA_AMSDU_EN BIT(27)
355
+
#define DCTLINFO_V3_W2_CHKSUM_OFLD_EN BIT(28)
356
+
#define DCTLINFO_V3_W2_WITH_LLC BIT(29)
357
+
#define DCTLINFO_V3_W2_NAT25_EN BIT(30)
358
+
#define DCTLINFO_V3_W2_IS_MLD BIT(31)
359
+
#define DCTLINFO_V3_W2_ALL GENMASK(31, 0)
360
+
#define DCTLINFO_V3_W3_SEQ2 GENMASK(11, 0)
361
+
#define DCTLINFO_V3_W3_SEQ3 GENMASK(23, 12)
362
+
#define DCTLINFO_V3_W3_TGT_IND GENMASK(27, 24)
363
+
#define DCTLINFO_V3_W3_TGT_IND_EN BIT(28)
364
+
#define DCTLINFO_V3_W3_HTC_LB GENMASK(31, 29)
365
+
#define DCTLINFO_V3_W3_ALL GENMASK(31, 0)
366
+
#define DCTLINFO_V3_W4_VLAN_TAG_SEL GENMASK(7, 5)
367
+
#define DCTLINFO_V3_W4_HTC_ORDER BIT(8)
368
+
#define DCTLINFO_V3_W4_SEC_KEY_ID GENMASK(10, 9)
369
+
#define DCTLINFO_V3_W4_VLAN_RX_DYNAMIC_PCP_EN BIT(11)
370
+
#define DCTLINFO_V3_W4_VLAN_RX_PKT_DROP BIT(12)
371
+
#define DCTLINFO_V3_W4_VLAN_RX_VALID BIT(13)
372
+
#define DCTLINFO_V3_W4_VLAN_TX_VALID BIT(14)
373
+
#define DCTLINFO_V3_W4_WAPI BIT(15)
374
+
#define DCTLINFO_V3_W4_SEC_ENT_MODE GENMASK(17, 16)
375
+
#define DCTLINFO_V3_W4_SEC_ENT0_KEYID GENMASK(19, 18)
376
+
#define DCTLINFO_V3_W4_SEC_ENT1_KEYID GENMASK(21, 20)
377
+
#define DCTLINFO_V3_W4_SEC_ENT2_KEYID GENMASK(23, 22)
378
+
#define DCTLINFO_V3_W4_SEC_ENT3_KEYID GENMASK(25, 24)
379
+
#define DCTLINFO_V3_W4_SEC_ENT4_KEYID GENMASK(27, 26)
380
+
#define DCTLINFO_V3_W4_SEC_ENT5_KEYID GENMASK(29, 28)
381
+
#define DCTLINFO_V3_W4_SEC_ENT6_KEYID GENMASK(31, 30)
382
+
#define DCTLINFO_V3_W4_ALL GENMASK(31, 5)
383
+
#define DCTLINFO_V3_W5_SEC_ENT7_KEYID GENMASK(1, 0)
384
+
#define DCTLINFO_V3_W5_SEC_ENT8_KEYID GENMASK(3, 2)
385
+
#define DCTLINFO_V3_W5_SEC_ENT_VALID_V1 GENMASK(23, 8)
386
+
#define DCTLINFO_V3_W5_ALL (GENMASK(23, 8) | GENMASK(3, 0))
387
+
#define DCTLINFO_V3_W6_SEC_ENT0_V2 GENMASK(8, 0)
388
+
#define DCTLINFO_V3_W6_SEC_ENT1_V2 GENMASK(18, 10)
389
+
#define DCTLINFO_V3_W6_SEC_ENT2_V2 GENMASK(28, 20)
390
+
#define DCTLINFO_V3_W6_ALL GENMASK(28, 0)
391
+
#define DCTLINFO_V3_W7_SEC_ENT3_V2 GENMASK(8, 0)
392
+
#define DCTLINFO_V3_W7_SEC_ENT4_V2 GENMASK(18, 10)
393
+
#define DCTLINFO_V3_W7_SEC_ENT5_V2 GENMASK(28, 20)
394
+
#define DCTLINFO_V3_W7_ALL GENMASK(28, 0)
395
+
#define DCTLINFO_V3_W8_SEC_ENT6_V2 GENMASK(8, 0)
396
+
#define DCTLINFO_V3_W8_SEC_ENT7_V1 GENMASK(18, 10)
397
+
#define DCTLINFO_V3_W8_SEC_ENT8_V1 GENMASK(28, 20)
398
+
#define DCTLINFO_V3_W8_ALL GENMASK(28, 0)
399
+
#define DCTLINFO_V3_W9_MLD_SMA_0_V2 GENMASK(7, 0)
400
+
#define DCTLINFO_V3_W9_MLD_SMA_1_V2 GENMASK(15, 8)
401
+
#define DCTLINFO_V3_W9_MLD_SMA_2_V2 GENMASK(23, 16)
402
+
#define DCTLINFO_V3_W9_MLD_SMA_3_V2 GENMASK(31, 24)
403
+
#define DCTLINFO_V3_W9_MLD_SMA_L_V2 GENMASK(31, 0)
404
+
#define DCTLINFO_V3_W9_ALL GENMASK(31, 0)
405
+
#define DCTLINFO_V3_W10_MLD_SMA_4_V2 GENMASK(7, 0)
406
+
#define DCTLINFO_V3_W10_MLD_SMA_5_V2 GENMASK(15, 8)
407
+
#define DCTLINFO_V3_W10_MLD_SMA_H_V2 GENMASK(15, 0)
408
+
#define DCTLINFO_V3_W10_MLD_TMA_0_V2 GENMASK(23, 16)
409
+
#define DCTLINFO_V3_W10_MLD_TMA_1_V2 GENMASK(31, 24)
410
+
#define DCTLINFO_V3_W10_MLD_TMA_L_V2 GENMASK(31, 16)
411
+
#define DCTLINFO_V3_W10_ALL GENMASK(31, 0)
412
+
#define DCTLINFO_V3_W11_MLD_TMA_2_V2 GENMASK(7, 0)
413
+
#define DCTLINFO_V3_W11_MLD_TMA_3_V2 GENMASK(15, 8)
414
+
#define DCTLINFO_V3_W11_MLD_TMA_4_V2 GENMASK(23, 16)
415
+
#define DCTLINFO_V3_W11_MLD_TMA_5_V2 GENMASK(31, 24)
416
+
#define DCTLINFO_V3_W11_MLD_TMA_H_V2 GENMASK(31, 0)
417
+
#define DCTLINFO_V3_W11_ALL GENMASK(31, 0)
418
+
#define DCTLINFO_V3_W12_MLD_TA_BSSID_0_V2 GENMASK(7, 0)
419
+
#define DCTLINFO_V3_W12_MLD_TA_BSSID_1_V2 GENMASK(15, 8)
420
+
#define DCTLINFO_V3_W12_MLD_TA_BSSID_2_V2 GENMASK(23, 16)
421
+
#define DCTLINFO_V3_W12_MLD_TA_BSSID_3_V2 GENMASK(31, 24)
422
+
#define DCTLINFO_V3_W12_MLD_TA_BSSID_L_V2 GENMASK(31, 0)
423
+
#define DCTLINFO_V3_W12_ALL GENMASK(31, 0)
424
+
#define DCTLINFO_V3_W13_MLD_TA_BSSID_4_V2 GENMASK(7, 0)
425
+
#define DCTLINFO_V3_W13_MLD_TA_BSSID_5_V2 GENMASK(15, 8)
426
+
#define DCTLINFO_V3_W13_MLD_TA_BSSID_H_V2 GENMASK(15, 0)
427
+
#define DCTLINFO_V3_W13_HW_EXSEQ_MACID_V1 GENMASK(24, 16)
428
+
#define DCTLINFO_V3_W13_ALL GENMASK(24, 0)
429
+
305
430
int rtw89_cam_init(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif);
306
431
void rtw89_cam_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif);
307
432
int rtw89_cam_init_addr_cam(struct rtw89_dev *rtwdev,
···
453
328
struct rtw89_vif_link *rtwvif_link,
454
329
struct rtw89_sta_link *rtwsta_link,
455
330
struct rtw89_h2c_dctlinfo_ud_v2 *h2c);
331
+
void rtw89_cam_fill_dctl_sec_cam_info_v3(struct rtw89_dev *rtwdev,
332
+
struct rtw89_vif_link *rtwvif_link,
333
+
struct rtw89_sta_link *rtwsta_link,
334
+
struct rtw89_h2c_dctlinfo_ud_v3 *h2c);
456
335
int rtw89_cam_fill_bssid_cam_info(struct rtw89_dev *rtwdev,
457
336
struct rtw89_vif_link *rtwvif_link,
458
337
struct rtw89_sta_link *rtwsta_link,
+37
-1
drivers/net/wireless/realtek/rtw89/chan.c
+37
-1
drivers/net/wireless/realtek/rtw89/chan.c
···
295
295
mgnt->chanctx_tbl[i][j] = RTW89_CHANCTX_IDLE;
296
296
}
297
297
298
+
hal->entity_force_hw = RTW89_PHY_NUM;
299
+
298
300
rtw89_config_default_chandef(rtwdev);
299
301
}
300
302
···
419
417
}
420
418
EXPORT_SYMBOL(__rtw89_mgnt_chan_get);
421
419
420
+
bool rtw89_entity_check_hw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
421
+
{
422
+
switch (rtwdev->mlo_dbcc_mode) {
423
+
case MLO_2_PLUS_0_1RF:
424
+
return phy_idx == RTW89_PHY_0;
425
+
case MLO_0_PLUS_2_1RF:
426
+
return phy_idx == RTW89_PHY_1;
427
+
default:
428
+
return false;
429
+
}
430
+
}
431
+
432
+
void rtw89_entity_force_hw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
433
+
{
434
+
rtwdev->hal.entity_force_hw = phy_idx;
435
+
436
+
if (phy_idx != RTW89_PHY_NUM)
437
+
rtw89_debug(rtwdev, RTW89_DBG_CHAN, "%s: %d\n", __func__, phy_idx);
438
+
else
439
+
rtw89_debug(rtwdev, RTW89_DBG_CHAN, "%s: (none)\n", __func__);
440
+
}
441
+
422
442
static enum rtw89_mlo_dbcc_mode
423
443
rtw89_entity_sel_mlo_dbcc_mode(struct rtw89_dev *rtwdev, u8 active_hws)
424
444
{
425
445
if (rtwdev->chip->chip_gen != RTW89_CHIP_BE)
426
446
return MLO_DBCC_NOT_SUPPORT;
447
+
448
+
switch (rtwdev->hal.entity_force_hw) {
449
+
case RTW89_PHY_0:
450
+
return MLO_2_PLUS_0_1RF;
451
+
case RTW89_PHY_1:
452
+
return MLO_0_PLUS_2_1RF;
453
+
default:
454
+
break;
455
+
}
427
456
428
457
switch (active_hws) {
429
458
case BIT(0):
···
2641
2608
static void rtw89_mcc_detect_connection(struct rtw89_dev *rtwdev,
2642
2609
struct rtw89_mcc_role *role)
2643
2610
{
2611
+
struct rtw89_vif_link *rtwvif_link = role->rtwvif_link;
2644
2612
struct ieee80211_vif *vif;
2645
2613
bool start_detect;
2646
2614
int ret;
2647
2615
2648
2616
ret = rtw89_core_send_nullfunc(rtwdev, role->rtwvif_link, true, false,
2649
2617
RTW89_MCC_PROBE_TIMEOUT);
2650
-
if (ret)
2618
+
if (ret &&
2619
+
READ_ONCE(rtwvif_link->sync_bcn_tsf) == rtwvif_link->last_sync_bcn_tsf)
2651
2620
role->probe_count++;
2652
2621
else
2653
2622
role->probe_count = 0;
2654
2623
2624
+
rtwvif_link->last_sync_bcn_tsf = READ_ONCE(rtwvif_link->sync_bcn_tsf);
2655
2625
if (role->probe_count < RTW89_MCC_PROBE_MAX_TRIES)
2656
2626
return;
2657
2627
+2
drivers/net/wireless/realtek/rtw89/chan.h
+2
drivers/net/wireless/realtek/rtw89/chan.h
···
166
166
const struct cfg80211_chan_def *chandef);
167
167
void rtw89_entity_init(struct rtw89_dev *rtwdev);
168
168
enum rtw89_entity_mode rtw89_entity_recalc(struct rtw89_dev *rtwdev);
169
+
bool rtw89_entity_check_hw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
170
+
void rtw89_entity_force_hw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
169
171
void rtw89_chanctx_work(struct wiphy *wiphy, struct wiphy_work *work);
170
172
void rtw89_queue_chanctx_work(struct rtw89_dev *rtwdev);
171
173
void rtw89_queue_chanctx_change(struct rtw89_dev *rtwdev,
+212
-25
drivers/net/wireless/realtek/rtw89/core.c
+212
-25
drivers/net/wireless/realtek/rtw89/core.c
···
470
470
__rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_1);
471
471
}
472
472
473
+
void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev,
474
+
struct rtw89_vif_link *rtwvif_link)
475
+
{
476
+
const struct rtw89_chip_info *chip = rtwdev->chip;
477
+
bool mon = !!rtwdev->pure_monitor_mode_vif;
478
+
bool prehdl_link = false;
479
+
480
+
if (chip->chip_gen != RTW89_CHIP_AX &&
481
+
!RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, &rtwdev->fw) &&
482
+
!mon && !rtw89_entity_check_hw(rtwdev, rtwvif_link->phy_idx))
483
+
prehdl_link = true;
484
+
485
+
if (prehdl_link) {
486
+
rtw89_entity_force_hw(rtwdev, rtwvif_link->phy_idx);
487
+
rtw89_set_channel(rtwdev);
488
+
}
489
+
490
+
if (chip->ops->rfk_channel)
491
+
chip->ops->rfk_channel(rtwdev, rtwvif_link);
492
+
493
+
if (prehdl_link) {
494
+
rtw89_entity_force_hw(rtwdev, RTW89_PHY_NUM);
495
+
rtw89_set_channel(rtwdev);
496
+
}
497
+
}
498
+
473
499
static void rtw89_chip_rfk_channel_for_pure_mon_vif(struct rtw89_dev *rtwdev,
474
500
enum rtw89_phy_idx phy_idx)
475
501
{
···
574
548
struct ieee80211_hdr *hdr = (void *)skb->data;
575
549
__le16 fc = hdr->frame_control;
576
550
577
-
if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc))
551
+
if (ieee80211_is_mgmt(fc) || ieee80211_is_any_nullfunc(fc))
578
552
return RTW89_CORE_TX_TYPE_MGMT;
579
553
580
554
return RTW89_CORE_TX_TYPE_DATA;
···
859
833
860
834
desc_info->qsel = qsel;
861
835
desc_info->ch_dma = ch_dma;
836
+
desc_info->sw_mld = true;
862
837
desc_info->port = desc_info->hiq ? rtwvif_link->port : 0;
863
838
desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
864
839
desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL;
···
1078
1051
desc_info->ch_dma = ch_dma;
1079
1052
desc_info->tid_indicate = tid_indicate;
1080
1053
desc_info->qsel = qsel;
1054
+
desc_info->sw_mld = false;
1081
1055
desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
1082
1056
desc_info->port = desc_info->hiq ? rtwvif_link->port : 0;
1083
1057
desc_info->er_cap = rtwsta_link ? rtwsta_link->er_cap : false;
···
1235
1207
if (addr_cam->valid && desc_info->mlo)
1236
1208
upd_wlan_hdr = true;
1237
1209
1238
-
if (rtw89_is_tx_rpt_skb(rtwdev, tx_req->skb))
1210
+
if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS || tx_req->with_wait)
1239
1211
rtw89_tx_rpt_init(rtwdev, tx_req);
1240
1212
1241
1213
is_bmc = (is_broadcast_ether_addr(hdr->addr1) ||
···
1354
1326
static int rtw89_core_tx_write_link(struct rtw89_dev *rtwdev,
1355
1327
struct rtw89_vif_link *rtwvif_link,
1356
1328
struct rtw89_sta_link *rtwsta_link,
1357
-
struct sk_buff *skb, int *qsel, bool sw_mld,
1329
+
struct sk_buff *skb, int *qsel,
1358
1330
struct rtw89_tx_wait_info *wait)
1359
1331
{
1360
1332
struct ieee80211_sta *sta = rtwsta_link_to_sta_safe(rtwsta_link);
···
1369
1341
tx_req.sta = sta;
1370
1342
tx_req.rtwvif_link = rtwvif_link;
1371
1343
tx_req.rtwsta_link = rtwsta_link;
1372
-
tx_req.desc_info.sw_mld = sw_mld;
1373
-
rcu_assign_pointer(skb_data->wait, wait);
1344
+
tx_req.with_wait = !!wait;
1374
1345
1375
1346
rtw89_traffic_stats_accu(rtwdev, rtwvif, skb, true, true);
1376
1347
rtw89_wow_parse_akm(rtwdev, skb);
1377
1348
rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
1378
1349
rtw89_core_tx_wake(rtwdev, &tx_req);
1350
+
1351
+
rcu_assign_pointer(skb_data->wait, wait);
1379
1352
1380
1353
ret = rtw89_hci_tx_write(rtwdev, &tx_req);
1381
1354
if (ret) {
···
1414
1385
}
1415
1386
}
1416
1387
1417
-
return rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, qsel, false,
1418
-
NULL);
1388
+
return rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, qsel, NULL);
1419
1389
}
1420
1390
1421
1391
static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info)
···
1659
1631
return cpu_to_le32(dword);
1660
1632
}
1661
1633
1634
+
static __le32 rtw89_build_txwd_body2_v3(struct rtw89_tx_desc_info *desc_info)
1635
+
{
1636
+
u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND_V1, desc_info->tid_indicate) |
1637
+
FIELD_PREP(BE_TXD_BODY2_QSEL_V1, desc_info->qsel) |
1638
+
FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) |
1639
+
FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) |
1640
+
FIELD_PREP(BE_TXD_BODY2_MACID_V1, desc_info->mac_id);
1641
+
1642
+
return cpu_to_le32(dword);
1643
+
}
1644
+
1662
1645
static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info)
1663
1646
{
1664
1647
u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq) |
1665
1648
FIELD_PREP(BE_TXD_BODY3_MLO_FLAG, desc_info->mlo) |
1666
1649
FIELD_PREP(BE_TXD_BODY3_IS_MLD_SW_EN, desc_info->sw_mld);
1650
+
1651
+
return cpu_to_le32(dword);
1652
+
}
1653
+
1654
+
static __le32 rtw89_build_txwd_body3_v3(struct rtw89_tx_desc_info *desc_info)
1655
+
{
1656
+
u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq) |
1657
+
FIELD_PREP(BE_TXD_BODY3_MLO_FLAG, desc_info->mlo) |
1658
+
FIELD_PREP(BE_TXD_BODY3_IS_MLD_SW_EN, desc_info->sw_mld) |
1659
+
FIELD_PREP(BE_TXD_BODY3_BK_V1, desc_info->bk);
1667
1660
1668
1661
return cpu_to_le32(dword);
1669
1662
}
···
1760
1711
return cpu_to_le32(dword);
1761
1712
}
1762
1713
1714
+
static __le32 rtw89_build_txwd_info2_v3(struct rtw89_tx_desc_info *desc_info)
1715
+
{
1716
+
u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1717
+
FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN_V1, desc_info->sec_en) |
1718
+
FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX_V1, desc_info->sec_cam_idx);
1719
+
1720
+
return cpu_to_le32(dword);
1721
+
}
1722
+
1763
1723
static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info)
1764
1724
{
1765
1725
bool rts_en = !desc_info->is_bmc;
···
1806
1748
txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info);
1807
1749
}
1808
1750
EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2);
1751
+
1752
+
void rtw89_core_fill_txdesc_v3(struct rtw89_dev *rtwdev,
1753
+
struct rtw89_tx_desc_info *desc_info,
1754
+
void *txdesc)
1755
+
{
1756
+
struct rtw89_txwd_body_v2 *txwd_body = txdesc;
1757
+
struct rtw89_txwd_info_v2 *txwd_info;
1758
+
1759
+
txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info);
1760
+
txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info);
1761
+
txwd_body->dword2 = rtw89_build_txwd_body2_v3(desc_info);
1762
+
txwd_body->dword3 = rtw89_build_txwd_body3_v3(desc_info);
1763
+
if (desc_info->sec_en) {
1764
+
txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info);
1765
+
txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info);
1766
+
}
1767
+
txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info);
1768
+
txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info);
1769
+
1770
+
if (!desc_info->en_wd_info)
1771
+
return;
1772
+
1773
+
txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1);
1774
+
txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info);
1775
+
txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info);
1776
+
txwd_info->dword2 = rtw89_build_txwd_info2_v3(desc_info);
1777
+
txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info);
1778
+
}
1779
+
EXPORT_SYMBOL(rtw89_core_fill_txdesc_v3);
1809
1780
1810
1781
static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info)
1811
1782
{
···
2872
2785
2873
2786
rcu_read_lock();
2874
2787
bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
2875
-
beacon_int = bss_conf->beacon_int;
2788
+
beacon_int = bss_conf->beacon_int ?: 100;
2876
2789
dtim = bss_conf->dtim_period;
2877
2790
rcu_read_unlock();
2878
2791
···
2902
2815
memset(&rtwdev->bcn_track, 0, sizeof(rtwdev->bcn_track));
2903
2816
}
2904
2817
2905
-
static void rtw89_vif_rx_bcn_stat(struct rtw89_dev *rtwdev,
2906
-
struct ieee80211_bss_conf *bss_conf,
2907
-
struct sk_buff *skb)
2818
+
static void rtw89_vif_rx_bcn_stat(struct rtw89_dev *rtwdev, struct sk_buff *skb)
2908
2819
{
2909
2820
#define RTW89_APPEND_TSF_2GHZ 384
2910
2821
#define RTW89_APPEND_TSF_5GHZ 52
···
2911
2826
struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
2912
2827
struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2913
2828
struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2914
-
u32 bcn_intvl_us = ieee80211_tu_to_usec(bss_conf->beacon_int);
2829
+
u32 bcn_intvl_us = ieee80211_tu_to_usec(bcn_track->beacon_int);
2915
2830
u64 tsf = le64_to_cpu(mgmt->u.beacon.timestamp);
2916
2831
u8 wp, num = bcn_stat->num;
2917
2832
u16 append;
2918
2833
2919
2834
if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw))
2835
+
return;
2836
+
2837
+
/* Skip if not yet associated */
2838
+
if (!bcn_intvl_us)
2920
2839
return;
2921
2840
2922
2841
switch (rx_status->band) {
···
3010
2921
pkt_stat->beacon_rate = desc_info->data_rate;
3011
2922
pkt_stat->beacon_len = skb->len;
3012
2923
3013
-
rtw89_vif_rx_bcn_stat(rtwdev, bss_conf, skb);
2924
+
rtw89_vif_rx_bcn_stat(rtwdev, skb);
3014
2925
}
3015
2926
3016
2927
if (!ether_addr_equal(bss_conf->addr, hdr->addr1))
···
3496
3407
desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK);
3497
3408
}
3498
3409
EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2);
3410
+
3411
+
void rtw89_core_query_rxdesc_v3(struct rtw89_dev *rtwdev,
3412
+
struct rtw89_rx_desc_info *desc_info,
3413
+
u8 *data, u32 data_offset)
3414
+
{
3415
+
struct rtw89_rxdesc_phy_rpt_v2 *rxd_rpt;
3416
+
struct rtw89_rxdesc_short_v3 *rxd_s;
3417
+
struct rtw89_rxdesc_long_v3 *rxd_l;
3418
+
u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len;
3419
+
3420
+
rxd_s = (struct rtw89_rxdesc_short_v3 *)(data + data_offset);
3421
+
3422
+
desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK);
3423
+
desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK);
3424
+
desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK);
3425
+
desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK);
3426
+
desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK);
3427
+
desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD);
3428
+
desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK);
3429
+
desc_info->bb_sel = le32_get_bits(rxd_s->dword0, BE_RXD_BB_SEL);
3430
+
if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT)
3431
+
desc_info->mac_info_valid = true;
3432
+
3433
+
desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK);
3434
+
desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_V1);
3435
+
desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD);
3436
+
3437
+
desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR);
3438
+
desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR);
3439
+
desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC);
3440
+
desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC);
3441
+
desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH);
3442
+
3443
+
desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK);
3444
+
desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK);
3445
+
desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK);
3446
+
desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK);
3447
+
desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK);
3448
+
3449
+
desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5);
3450
+
3451
+
shift_len = desc_info->shift << 1; /* 2-byte unit */
3452
+
drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
3453
+
phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */
3454
+
hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */
3455
+
desc_info->offset = data_offset + shift_len + drv_info_len +
3456
+
phy_rtp_len + hdr_cnv_len;
3457
+
3458
+
if (desc_info->long_rxdesc)
3459
+
desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v3);
3460
+
else
3461
+
desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v3);
3462
+
desc_info->ready = true;
3463
+
3464
+
if (phy_rtp_len == sizeof(*rxd_rpt)) {
3465
+
rxd_rpt = (struct rtw89_rxdesc_phy_rpt_v2 *)(data + data_offset +
3466
+
desc_info->rxd_len);
3467
+
desc_info->rssi = le32_get_bits(rxd_rpt->dword0, BE_RXD_PHY_RSSI);
3468
+
}
3469
+
3470
+
if (!desc_info->long_rxdesc)
3471
+
return;
3472
+
3473
+
rxd_l = (struct rtw89_rxdesc_long_v3 *)(data + data_offset);
3474
+
3475
+
desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN);
3476
+
desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK);
3477
+
desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_V1);
3478
+
desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_V1);
3479
+
3480
+
desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK);
3481
+
}
3482
+
EXPORT_SYMBOL(rtw89_core_query_rxdesc_v3);
3499
3483
3500
3484
struct rtw89_core_iter_rx_status {
3501
3485
struct rtw89_dev *rtwdev;
···
4253
4091
goto out;
4254
4092
}
4255
4093
4256
-
ret = rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, &qsel, true,
4257
-
wait);
4094
+
ret = rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, &qsel, wait);
4258
4095
if (ret) {
4259
4096
rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret);
4260
4097
dev_kfree_skb_any(skb);
···
5246
5085
}
5247
5086
5248
5087
vht_cap->vht_supported = true;
5249
-
vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
5088
+
vht_cap->cap = chip->max_vht_mpdu_cap |
5250
5089
IEEE80211_VHT_CAP_SHORT_GI_80 |
5251
5090
IEEE80211_VHT_CAP_RXSTBC_1 |
5252
5091
IEEE80211_VHT_CAP_HTC_VHT |
···
5374
5213
IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
5375
5214
le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
5376
5215
IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
5377
-
le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
5216
+
le16_encode_bits(chip->max_vht_mpdu_cap,
5378
5217
IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
5379
5218
iftype_data->he_6ghz_capa.capa = capa;
5380
5219
}
···
5395
5234
u8 val, val_mcs13;
5396
5235
int sts = 8;
5397
5236
5398
-
if (chip->chip_gen == RTW89_CHIP_AX)
5237
+
if (chip->chip_gen == RTW89_CHIP_AX || hal->no_eht)
5399
5238
return;
5400
5239
5401
5240
if (hal->no_mcs_12_13)
···
5412
5251
eht_cap->has_eht = true;
5413
5252
5414
5253
eht_cap_elem->mac_cap_info[0] =
5415
-
u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991,
5254
+
u8_encode_bits(chip->max_eht_mpdu_cap,
5416
5255
IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
5417
5256
eht_cap_elem->mac_cap_info[1] = 0;
5418
5257
···
5818
5657
5819
5658
rtw89_phy_dm_init(rtwdev);
5820
5659
5660
+
rtw89_mac_set_edcca_mode_bands(rtwdev, true);
5821
5661
rtw89_mac_cfg_ppdu_status_bands(rtwdev, true);
5822
5662
rtw89_mac_cfg_phy_rpt_bands(rtwdev, true);
5823
5663
rtw89_mac_update_rts_threshold(rtwdev);
···
6085
5923
struct rtw89_btc *btc = &rtwdev->btc;
6086
5924
u8 band;
6087
5925
5926
+
bitmap_or(rtwdev->quirks, rtwdev->quirks, &rtwdev->chip->default_quirks,
5927
+
NUM_OF_RTW89_QUIRKS);
5928
+
6088
5929
INIT_LIST_HEAD(&rtwdev->ba_list);
6089
5930
INIT_LIST_HEAD(&rtwdev->forbid_ba_list);
6090
5931
INIT_LIST_HEAD(&rtwdev->rtwvifs_list);
···
6245
6080
static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev)
6246
6081
{
6247
6082
const struct rtw89_chip_info *chip = rtwdev->chip;
6083
+
struct rtw89_hal *hal = &rtwdev->hal;
6248
6084
int ret;
6085
+
u8 val2;
6249
6086
u8 val;
6250
6087
u8 cv;
6251
6088
···
6259
6092
cv = CHIP_CBV;
6260
6093
}
6261
6094
6262
-
rtwdev->hal.cv = cv;
6095
+
hal->cv = cv;
6263
6096
6264
-
if (rtw89_is_rtl885xb(rtwdev)) {
6097
+
if (rtw89_is_rtl885xb(rtwdev) || chip->chip_gen >= RTW89_CHIP_BE) {
6265
6098
ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val);
6266
6099
if (ret)
6267
6100
return;
6268
6101
6269
-
rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK);
6102
+
hal->acv = u8_get_bits(val, XTAL_SI_ACV_MASK);
6103
+
}
6104
+
6105
+
if (chip->chip_gen >= RTW89_CHIP_BE) {
6106
+
hal->cid =
6107
+
rtw89_read32_mask(rtwdev, R_BE_SYS_CHIPINFO, B_BE_HW_ID_MASK);
6108
+
6109
+
ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CHIP_ID_L, &val);
6110
+
if (ret)
6111
+
return;
6112
+
ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CHIP_ID_H, &val2);
6113
+
if (ret)
6114
+
return;
6115
+
6116
+
hal->aid = val | val2 << 8;
6270
6117
}
6271
6118
}
6272
6119
···
6379
6198
goto wake_queue;
6380
6199
}
6381
6200
6382
-
rtw89_chip_rfk_channel(rtwdev, target);
6201
+
if (RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, &rtwdev->fw))
6202
+
rtw89_chip_rfk_channel(rtwdev, target);
6383
6203
6384
6204
rtwvif->mlo_mode = RTW89_MLO_MODE_MLSR;
6385
6205
···
6491
6309
6492
6310
int rtw89_chip_info_setup(struct rtw89_dev *rtwdev)
6493
6311
{
6312
+
struct rtw89_efuse *efuse = &rtwdev->efuse;
6313
+
struct rtw89_hal *hal = &rtwdev->hal;
6494
6314
int ret;
6495
6315
6496
6316
rtw89_read_chip_ver(rtwdev);
···
6531
6347
6532
6348
rtw89_core_setup_rfe_parms(rtwdev);
6533
6349
rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev);
6350
+
6351
+
rtw89_info(rtwdev, "chip info CID: %x, CV: %x, AID: %x, ACV: %x, RFE: %d\n",
6352
+
hal->cid, hal->cv, hal->aid, hal->acv, efuse->rfe_type);
6534
6353
6535
6354
out:
6536
6355
rtw89_mac_pwr_off(rtwdev);
···
6585
6398
6586
6399
hw->extra_tx_headroom = tx_headroom;
6587
6400
hw->queues = IEEE80211_NUM_ACS;
6588
-
hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM;
6589
-
hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM;
6401
+
hw->max_rx_aggregation_subframes = chip->max_rx_agg_num;
6402
+
hw->max_tx_aggregation_subframes = chip->max_tx_agg_num;
6590
6403
hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL;
6591
6404
6592
6405
hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC |
+129
-29
drivers/net/wireless/realtek/rtw89/core.h
+129
-29
drivers/net/wireless/realtek/rtw89/core.h
···
25
25
struct rtw89_phy_rfk_log_fmt;
26
26
struct rtw89_debugfs;
27
27
struct rtw89_regd_data;
28
+
struct rtw89_wow_cam_info;
28
29
29
30
extern const struct ieee80211_ops rtw89_ops;
30
31
···
157
156
RTL8851B,
158
157
RTL8922A,
159
158
RTL8922D,
159
+
};
160
+
161
+
enum rtw89_core_chip_cid {
162
+
RTL8922D_CID7025 = 0x74,
163
+
RTL8922D_CID7090 = 0x79,
164
+
};
165
+
166
+
enum rtw89_core_chip_aid {
167
+
RTL8922D_AID1348 = 0x1348,
168
+
RTL8922D_AID7060 = 0x7060,
169
+
RTL8922D_AID7102 = 0x7102,
160
170
};
161
171
162
172
enum rtw89_chip_gen {
···
1137
1125
__le32 dword5;
1138
1126
} __packed;
1139
1127
1128
+
struct rtw89_rxdesc_short_v3 {
1129
+
__le32 dword0;
1130
+
__le32 dword1;
1131
+
__le32 dword2;
1132
+
__le32 dword3;
1133
+
__le32 dword4;
1134
+
__le32 dword5;
1135
+
} __packed;
1136
+
1140
1137
struct rtw89_rxdesc_long {
1141
1138
__le32 dword0;
1142
1139
__le32 dword1;
···
1158
1137
} __packed;
1159
1138
1160
1139
struct rtw89_rxdesc_long_v2 {
1140
+
__le32 dword0;
1141
+
__le32 dword1;
1142
+
__le32 dword2;
1143
+
__le32 dword3;
1144
+
__le32 dword4;
1145
+
__le32 dword5;
1146
+
__le32 dword6;
1147
+
__le32 dword7;
1148
+
__le32 dword8;
1149
+
__le32 dword9;
1150
+
} __packed;
1151
+
1152
+
struct rtw89_rxdesc_long_v3 {
1161
1153
__le32 dword0;
1162
1154
__le32 dword1;
1163
1155
__le32 dword2;
···
1245
1211
struct rtw89_vif_link *rtwvif_link;
1246
1212
struct rtw89_sta_link *rtwsta_link;
1247
1213
struct rtw89_tx_desc_info desc_info;
1214
+
1215
+
bool with_wait;
1248
1216
};
1249
1217
1250
1218
struct rtw89_txq {
···
3440
3404
#define RTW89_PPDU_MAC_RX_CNT_SIZE 96
3441
3405
#define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128
3442
3406
3443
-
#define RTW89_MAX_RX_AGG_NUM 64
3444
-
#define RTW89_MAX_TX_AGG_NUM 128
3445
-
3446
3407
struct rtw89_ampdu_params {
3447
3408
u16 agg_num;
3448
3409
bool amsdu;
···
3866
3833
struct rtw89_vif_link *rtwvif_link,
3867
3834
struct rtw89_sta_link *rtwsta_link,
3868
3835
bool valid, struct ieee80211_ampdu_params *params);
3836
+
int (*h2c_wow_cam_update)(struct rtw89_dev *rtwdev,
3837
+
struct rtw89_wow_cam_info *cam_info);
3869
3838
3870
3839
void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
3871
3840
void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
···
4000
3965
u8 h2c_full_cond;
4001
3966
u8 wp_ch07_full_cond;
4002
3967
u8 wp_ch811_full_cond;
3968
+
/* for WiFi 7 chips after 8922D */
3969
+
u16 ch011_full_page;
3970
+
u16 h2c_full_page;
3971
+
u16 wp_ch07_full_page;
3972
+
u16 wp_ch811_full_page;
4003
3973
};
4004
3974
4005
3975
struct rtw89_hfc_param {
···
4029
3989
u16 pge_size;
4030
3990
u16 lnk_pge_num;
4031
3991
u16 unlnk_pge_num;
4032
-
/* for WiFi 7 chips below */
3992
+
/* for WiFi 7 chips below (suffix v1) */
4033
3993
u32 srt_ofst;
4034
3994
};
4035
3995
4036
3996
struct rtw89_wde_quota {
4037
3997
u16 hif;
4038
3998
u16 wcpu;
3999
+
/* unused dcpu isn't listed */
4039
4000
u16 pkt_in;
4040
4001
u16 cpu_io;
4041
4002
};
···
4054
4013
u16 wd_rel;
4055
4014
u16 cpu_io;
4056
4015
u16 tx_rpt;
4057
-
/* for WiFi 7 chips below */
4016
+
/* for WiFi 7 chips below (suffix v1) */
4058
4017
u16 h2d;
4018
+
/* for WiFi 7 chips after 8922D (suffix v2) */
4019
+
u16 snrpt;
4059
4020
};
4060
4021
4061
4022
struct rtw89_rsvd_quota {
···
4078
4035
u32 size;
4079
4036
};
4080
4037
4038
+
struct rtw89_dle_input {
4039
+
u32 tx_ampdu_num_b0;
4040
+
u32 tx_ampdu_num_b1;
4041
+
u32 tx_amsdu_size; /* unit: KB */
4042
+
u32 h2c_max_size;
4043
+
u32 rx_amsdu_size; /* unit: KB */
4044
+
u32 c2h_max_size;
4045
+
u32 mpdu_info_tbl_b0;
4046
+
u32 mpdu_info_tbl_b1;
4047
+
};
4048
+
4081
4049
struct rtw89_dle_mem {
4082
4050
enum rtw89_qta_mode mode;
4083
4051
const struct rtw89_dle_size *wde_size;
···
4101
4047
const struct rtw89_rsvd_quota *rsvd_qt;
4102
4048
const struct rtw89_dle_rsvd_size *rsvd0_size;
4103
4049
const struct rtw89_dle_rsvd_size *rsvd1_size;
4050
+
/* for WiFi 7 chips after 8922D */
4051
+
const struct rtw89_dle_input *dle_input;
4104
4052
};
4105
4053
4106
4054
struct rtw89_reg_def {
···
4381
4325
struct rtw89_reg3_def mode;
4382
4326
};
4383
4327
4328
+
struct rtw89_sb_regs {
4329
+
struct {
4330
+
u32 cfg;
4331
+
u32 get;
4332
+
} n[2];
4333
+
};
4334
+
4384
4335
struct rtw89_dig_regs {
4385
4336
u32 seg0_pd_reg;
4386
4337
u32 pd_lower_bound_mask;
···
4487
4424
bool small_fifo_size;
4488
4425
u32 dle_scc_rsvd_size;
4489
4426
u16 max_amsdu_limit;
4427
+
u16 max_vht_mpdu_cap;
4428
+
u16 max_eht_mpdu_cap;
4429
+
u16 max_tx_agg_num;
4430
+
u16 max_rx_agg_num;
4490
4431
bool dis_2g_40m_ul_ofdma;
4491
4432
u32 rsvd_ple_ofst;
4492
4433
const struct rtw89_hfc_param_ini *hfc_param_ini[RTW89_HCI_TYPE_NUM];
···
4605
4538
u32 bss_clr_map_reg;
4606
4539
const struct rtw89_rfkill_regs *rfkill_init;
4607
4540
struct rtw89_reg_def rfkill_get;
4541
+
struct rtw89_sb_regs btc_sb;
4608
4542
u32 dma_ch_mask;
4609
4543
const struct rtw89_edcca_regs *edcca_regs;
4610
4544
const struct wiphy_wowlan_support *wowlan_stub;
4611
4545
const struct rtw89_xtal_info *xtal_info;
4546
+
unsigned long default_quirks; /* bitmap of rtw89_quirks */
4612
4547
};
4613
4548
4614
4549
struct rtw89_chip_variant {
···
4641
4572
4642
4573
struct rtw89_dle_info {
4643
4574
const struct rtw89_rsvd_quota *rsvd_qt;
4575
+
const struct rtw89_dle_input *dle_input;
4644
4576
enum rtw89_qta_mode qta_mode;
4645
4577
u16 ple_pg_size;
4646
4578
u16 ple_free_pg;
···
4734
4664
RTW89_FW_FEATURE_MACID_PAUSE_SLEEP,
4735
4665
RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0,
4736
4666
RTW89_FW_FEATURE_WOW_REASON_V1,
4737
-
RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0,
4738
-
RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1,
4667
+
RTW89_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY,
4668
+
RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0,
4669
+
RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1,
4670
+
RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V2,
4671
+
RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V3,
4672
+
),
4673
+
RTW89_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY_MCC,
4674
+
RTW89_FW_FEATURE_RFK_PRE_NOTIFY_MCC_V0,
4675
+
RTW89_FW_FEATURE_RFK_PRE_NOTIFY_MCC_V1,
4676
+
RTW89_FW_FEATURE_RFK_PRE_NOTIFY_MCC_V2,
4677
+
),
4739
4678
RTW89_FW_FEATURE_RFK_RXDCK_V0,
4740
4679
RTW89_FW_FEATURE_RFK_IQK_V0,
4741
4680
RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX,
···
4759
4680
RTW89_FW_FEATURE_LPS_DACK_BY_C2H_REG,
4760
4681
RTW89_FW_FEATURE_BEACON_TRACKING,
4761
4682
RTW89_FW_FEATURE_ADDR_CAM_V0,
4683
+
RTW89_FW_FEATURE_SER_L1_BY_EVENT,
4684
+
RTW89_FW_FEATURE_SIM_SER_L0L1_BY_HALT_H2C,
4685
+
4686
+
NUM_OF_RTW89_FW_FEATURES,
4762
4687
};
4763
4688
4764
4689
struct rtw89_fw_suit {
···
4854
4771
struct rtw89_fw_suit bbmcu0;
4855
4772
struct rtw89_fw_suit bbmcu1;
4856
4773
struct rtw89_fw_log log;
4857
-
u32 feature_map;
4858
4774
struct rtw89_fw_elm_info elm_info;
4859
4775
struct rtw89_fw_secure sec;
4776
+
4777
+
DECLARE_BITMAP(feature_map, NUM_OF_RTW89_FW_FEATURES);
4860
4778
};
4861
4779
4862
4780
#define RTW89_CHK_FW_FEATURE(_feat, _fw) \
4863
-
(!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat)))
4781
+
test_bit(RTW89_FW_FEATURE_ ## _feat, (_fw)->feature_map)
4864
4782
4865
4783
#define RTW89_CHK_FW_FEATURE_GROUP(_grp, _fw) \
4866
-
(!!((_fw)->feature_map & GENMASK(RTW89_FW_FEATURE_ ## _grp ## _MAX, \
4867
-
RTW89_FW_FEATURE_ ## _grp ## _MIN)))
4784
+
({ \
4785
+
unsigned int bit = find_next_bit((_fw)->feature_map, \
4786
+
NUM_OF_RTW89_FW_FEATURES, \
4787
+
RTW89_FW_FEATURE_ ## _grp ## _MIN); \
4788
+
bit <= RTW89_FW_FEATURE_ ## _grp ## _MAX; \
4789
+
})
4868
4790
4869
4791
#define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \
4870
-
((_fw)->feature_map |= BIT(_fw_feature))
4792
+
set_bit(_fw_feature, (_fw)->feature_map)
4793
+
4794
+
#define RTW89_CLR_FW_FEATURE(_fw_feature, _fw) \
4795
+
clear_bit(_fw_feature, (_fw)->feature_map)
4871
4796
4872
4797
struct rtw89_cam_info {
4873
4798
DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
···
5117
5026
struct rtw89_hal {
5118
5027
u32 rx_fltr;
5119
5028
u8 cv;
5029
+
u8 cid; /* enum rtw89_core_chip_cid */
5120
5030
u8 acv;
5031
+
u16 aid; /* enum rtw89_core_chip_aid */
5121
5032
u32 antenna_tx;
5122
5033
u32 antenna_rx;
5123
5034
u8 tx_nss;
···
5130
5037
bool support_cckpd;
5131
5038
bool support_igi;
5132
5039
bool no_mcs_12_13;
5040
+
bool no_eht;
5133
5041
5134
5042
atomic_t roc_chanctx_idx;
5135
5043
u8 roc_link_index;
···
5144
5050
bool entity_pause;
5145
5051
enum rtw89_entity_mode entity_mode;
5146
5052
struct rtw89_entity_mgnt entity_mgnt;
5053
+
5054
+
enum rtw89_phy_idx entity_force_hw;
5147
5055
5148
5056
u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */
5149
5057
···
5161
5065
RTW89_FLAG_DMAC_FUNC,
5162
5066
RTW89_FLAG_CMAC0_FUNC,
5163
5067
RTW89_FLAG_CMAC1_FUNC,
5068
+
RTW89_FLAG_CMAC0_PWR,
5069
+
RTW89_FLAG_CMAC1_PWR,
5164
5070
RTW89_FLAG_FW_RDY,
5165
5071
RTW89_FLAG_RUNNING,
5166
5072
RTW89_FLAG_PROBE_DONE,
···
5193
5095
};
5194
5096
5195
5097
enum rtw89_custid {
5196
-
RTW89_CUSTID_NONE,
5197
-
RTW89_CUSTID_ACER,
5198
-
RTW89_CUSTID_AMD,
5199
-
RTW89_CUSTID_ASUS,
5200
-
RTW89_CUSTID_DELL,
5201
-
RTW89_CUSTID_HP,
5202
-
RTW89_CUSTID_LENOVO,
5098
+
RTW89_CUSTID_NONE = 0,
5099
+
RTW89_CUSTID_HP = 1,
5100
+
RTW89_CUSTID_ASUS = 2,
5101
+
RTW89_CUSTID_ACER = 3,
5102
+
RTW89_CUSTID_LENOVO = 4,
5103
+
RTW89_CUSTID_NEC = 5,
5104
+
RTW89_CUSTID_AMD = 6,
5105
+
RTW89_CUSTID_FUJITSU = 7,
5106
+
RTW89_CUSTID_DELL = 8,
5203
5107
};
5204
5108
5205
5109
enum rtw89_pkt_drop_sel {
···
5316
5216
u8 ch[RTW89_RFK_CHS_NR];
5317
5217
u8 band[RTW89_RFK_CHS_NR];
5318
5218
u8 bw[RTW89_RFK_CHS_NR];
5219
+
u32 rf18[RTW89_RFK_CHS_NR];
5319
5220
u8 table_idx;
5320
5221
};
5321
5222
···
5894
5793
struct rtw89_wow_cam_info {
5895
5794
bool r_w;
5896
5795
u8 idx;
5897
-
u32 mask[RTW89_MAX_PATTERN_MASK_SIZE];
5796
+
__le32 mask[RTW89_MAX_PATTERN_MASK_SIZE];
5898
5797
u16 crc;
5899
5798
bool negative_pattern_match;
5900
5799
bool skip_mac_hdr;
···
7201
7100
chip->ops->rfk_init_late(rtwdev);
7202
7101
}
7203
7102
7204
-
static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev,
7205
-
struct rtw89_vif_link *rtwvif_link)
7206
-
{
7207
-
const struct rtw89_chip_info *chip = rtwdev->chip;
7208
-
7209
-
if (chip->ops->rfk_channel)
7210
-
chip->ops->rfk_channel(rtwdev, rtwvif_link);
7211
-
}
7212
-
7213
7103
static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev,
7214
7104
enum rtw89_phy_idx phy_idx,
7215
7105
const struct rtw89_chan *chan)
···
7650
7558
void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
7651
7559
struct rtw89_tx_desc_info *desc_info,
7652
7560
void *txdesc);
7561
+
void rtw89_core_fill_txdesc_v3(struct rtw89_dev *rtwdev,
7562
+
struct rtw89_tx_desc_info *desc_info,
7563
+
void *txdesc);
7653
7564
void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
7654
7565
struct rtw89_tx_desc_info *desc_info,
7655
7566
void *txdesc);
···
7669
7574
struct rtw89_rx_desc_info *desc_info,
7670
7575
u8 *data, u32 data_offset);
7671
7576
void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
7577
+
struct rtw89_rx_desc_info *desc_info,
7578
+
u8 *data, u32 data_offset);
7579
+
void rtw89_core_query_rxdesc_v3(struct rtw89_dev *rtwdev,
7672
7580
struct rtw89_rx_desc_info *desc_info,
7673
7581
u8 *data, u32 data_offset);
7674
7582
void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
···
7720
7622
unsigned int link_id);
7721
7623
void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id);
7722
7624
void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev);
7625
+
void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev,
7626
+
struct rtw89_vif_link *rtwvif_link);
7723
7627
const struct rtw89_6ghz_span *
7724
7628
rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq);
7725
7629
void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef);
+79
drivers/net/wireless/realtek/rtw89/debug.c
+79
drivers/net/wireless/realtek/rtw89/debug.c
···
79
79
struct rtw89_debugfs_priv send_h2c;
80
80
struct rtw89_debugfs_priv early_h2c;
81
81
struct rtw89_debugfs_priv fw_crash;
82
+
struct rtw89_debugfs_priv ser_counters;
82
83
struct rtw89_debugfs_priv btc_info;
83
84
struct rtw89_debugfs_priv btc_manual;
84
85
struct rtw89_debugfs_priv fw_log_manual;
···
3538
3537
return count;
3539
3538
}
3540
3539
3540
+
static int rtw89_dbg_trigger_ctrl_error_by_halt_h2c(struct rtw89_dev *rtwdev)
3541
+
{
3542
+
if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
3543
+
return -EBUSY;
3544
+
3545
+
return rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_RESET_FORCE);
3546
+
}
3547
+
3541
3548
static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev)
3542
3549
{
3543
3550
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3544
3551
struct rtw89_cpuio_ctrl ctrl_para = {0};
3545
3552
u16 pkt_id;
3546
3553
int ret;
3554
+
3555
+
if (RTW89_CHK_FW_FEATURE(SIM_SER_L0L1_BY_HALT_H2C, &rtwdev->fw))
3556
+
return rtw89_dbg_trigger_ctrl_error_by_halt_h2c(rtwdev);
3547
3557
3548
3558
rtw89_leave_ps_mode(rtwdev);
3549
3559
···
3612
3600
return 0;
3613
3601
}
3614
3602
3603
+
static int rtw89_dbg_trigger_mac_error_by_halt_h2c(struct rtw89_dev *rtwdev)
3604
+
{
3605
+
if (!test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
3606
+
return -EBUSY;
3607
+
3608
+
return rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L0_RESET_FORCE);
3609
+
}
3610
+
3615
3611
static int rtw89_dbg_trigger_mac_error(struct rtw89_dev *rtwdev)
3616
3612
{
3617
3613
const struct rtw89_chip_info *chip = rtwdev->chip;
3614
+
3615
+
if (RTW89_CHK_FW_FEATURE(SIM_SER_L0L1_BY_HALT_H2C, &rtwdev->fw))
3616
+
return rtw89_dbg_trigger_mac_error_by_halt_h2c(rtwdev);
3618
3617
3619
3618
rtw89_leave_ps_mode(rtwdev);
3620
3619
···
3701
3678
return ret;
3702
3679
3703
3680
return count;
3681
+
}
3682
+
3683
+
struct rtw89_dbg_ser_counters {
3684
+
unsigned int l0;
3685
+
unsigned int l1;
3686
+
unsigned int l0_to_l1;
3687
+
};
3688
+
3689
+
static void rtw89_dbg_get_ser_counters_ax(struct rtw89_dev *rtwdev,
3690
+
struct rtw89_dbg_ser_counters *cnt)
3691
+
{
3692
+
const u32 val = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO);
3693
+
3694
+
cnt->l0 = u32_get_bits(val, B_AX_SER_L0_COUNTER_MASK);
3695
+
cnt->l1 = u32_get_bits(val, B_AX_SER_L1_COUNTER_MASK);
3696
+
cnt->l0_to_l1 = u32_get_bits(val, B_AX_L0_TO_L1_EVENT_MASK);
3697
+
}
3698
+
3699
+
static void rtw89_dbg_get_ser_counters_be(struct rtw89_dev *rtwdev,
3700
+
struct rtw89_dbg_ser_counters *cnt)
3701
+
{
3702
+
const u32 val = rtw89_read32(rtwdev, R_BE_SER_DBG_INFO);
3703
+
3704
+
cnt->l0 = u32_get_bits(val, B_BE_SER_L0_COUNTER_MASK);
3705
+
cnt->l1 = u32_get_bits(val, B_BE_SER_L1_COUNTER_MASK);
3706
+
cnt->l0_to_l1 = u32_get_bits(val, B_BE_SER_L0_PROMOTE_L1_EVENT_MASK);
3707
+
}
3708
+
3709
+
static ssize_t rtw89_debug_priv_ser_counters_get(struct rtw89_dev *rtwdev,
3710
+
struct rtw89_debugfs_priv *debugfs_priv,
3711
+
char *buf, size_t bufsz)
3712
+
{
3713
+
const struct rtw89_chip_info *chip = rtwdev->chip;
3714
+
struct rtw89_dbg_ser_counters cnt = {};
3715
+
char *p = buf, *end = buf + bufsz;
3716
+
3717
+
rtw89_leave_ps_mode(rtwdev);
3718
+
3719
+
switch (chip->chip_gen) {
3720
+
case RTW89_CHIP_AX:
3721
+
rtw89_dbg_get_ser_counters_ax(rtwdev, &cnt);
3722
+
break;
3723
+
case RTW89_CHIP_BE:
3724
+
rtw89_dbg_get_ser_counters_be(rtwdev, &cnt);
3725
+
break;
3726
+
default:
3727
+
return -EOPNOTSUPP;
3728
+
}
3729
+
3730
+
p += scnprintf(p, end - p, "SER L0 Count: %d\n", cnt.l0);
3731
+
p += scnprintf(p, end - p, "SER L1 Count: %d\n", cnt.l1);
3732
+
p += scnprintf(p, end - p, "SER L0 promote event: %d\n", cnt.l0_to_l1);
3733
+
3734
+
return p - buf;
3704
3735
}
3705
3736
3706
3737
static ssize_t rtw89_debug_priv_btc_info_get(struct rtw89_dev *rtwdev,
···
4844
4767
.send_h2c = rtw89_debug_priv_set(send_h2c),
4845
4768
.early_h2c = rtw89_debug_priv_set_and_get(early_h2c, RWLOCK),
4846
4769
.fw_crash = rtw89_debug_priv_set_and_get(fw_crash, WLOCK),
4770
+
.ser_counters = rtw89_debug_priv_get(ser_counters, RLOCK),
4847
4771
.btc_info = rtw89_debug_priv_get(btc_info, RSIZE_12K),
4848
4772
.btc_manual = rtw89_debug_priv_set(btc_manual),
4849
4773
.fw_log_manual = rtw89_debug_priv_set(fw_log_manual, WLOCK),
···
4892
4814
rtw89_debugfs_add_w(send_h2c);
4893
4815
rtw89_debugfs_add_rw(early_h2c);
4894
4816
rtw89_debugfs_add_rw(fw_crash);
4817
+
rtw89_debugfs_add_r(ser_counters);
4895
4818
rtw89_debugfs_add_r(btc_info);
4896
4819
rtw89_debugfs_add_w(btc_manual);
4897
4820
rtw89_debugfs_add_w(fw_log_manual);
-4
drivers/net/wireless/realtek/rtw89/efuse.c
-4
drivers/net/wireless/realtek/rtw89/efuse.c
···
7
7
#include "mac.h"
8
8
#include "reg.h"
9
9
10
-
#define EF_FV_OFSET 0x5ea
11
-
#define EF_CV_MASK GENMASK(7, 4)
12
-
#define EF_CV_INV 15
13
-
14
10
#define EFUSE_B1_MSSDEVTYPE_MASK GENMASK(3, 0)
15
11
#define EFUSE_B1_MSSCUSTIDX0_MASK GENMASK(7, 4)
16
12
#define EFUSE_B2_MSSKEYNUM_MASK GENMASK(3, 0)
+6
drivers/net/wireless/realtek/rtw89/efuse.h
+6
drivers/net/wireless/realtek/rtw89/efuse.h
···
11
11
#define RTW89_EFUSE_BLOCK_SIZE_MASK GENMASK(15, 0)
12
12
#define RTW89_EFUSE_MAX_BLOCK_SIZE 0x10000
13
13
14
+
#define EF_FV_OFSET 0x5EA
15
+
#define EF_FV_OFSET_BE_V1 0x17CA
16
+
#define EF_CV_MASK GENMASK(7, 4)
17
+
#define EF_CV_INV 15
18
+
14
19
struct rtw89_efuse_block_cfg {
15
20
u32 offset;
16
21
u32 size;
···
31
26
int rtw89_efuse_recognize_mss_info_v1(struct rtw89_dev *rtwdev, u8 b1, u8 b2);
32
27
int rtw89_efuse_read_fw_secure_ax(struct rtw89_dev *rtwdev);
33
28
int rtw89_efuse_read_fw_secure_be(struct rtw89_dev *rtwdev);
29
+
int rtw89_efuse_read_ecv_be(struct rtw89_dev *rtwdev);
34
30
35
31
#endif
+26
drivers/net/wireless/realtek/rtw89/efuse_be.c
+26
drivers/net/wireless/realtek/rtw89/efuse_be.c
···
512
512
513
513
return 0;
514
514
}
515
+
516
+
int rtw89_efuse_read_ecv_be(struct rtw89_dev *rtwdev)
517
+
{
518
+
u32 dump_addr;
519
+
u8 buff[4]; /* efuse access must 4 bytes align */
520
+
int ret;
521
+
u8 ecv;
522
+
u8 val;
523
+
524
+
dump_addr = ALIGN_DOWN(EF_FV_OFSET_BE_V1, 4);
525
+
526
+
ret = rtw89_dump_physical_efuse_map_be(rtwdev, buff, dump_addr, 4, false);
527
+
if (ret)
528
+
return ret;
529
+
530
+
val = buff[EF_FV_OFSET_BE_V1 & 0x3];
531
+
532
+
ecv = u8_get_bits(val, EF_CV_MASK);
533
+
if (ecv == EF_CV_INV)
534
+
return -ENOENT;
535
+
536
+
rtwdev->hal.cv = ecv;
537
+
538
+
return 0;
539
+
}
540
+
EXPORT_SYMBOL(rtw89_efuse_read_ecv_be);
+797
-69
drivers/net/wireless/realtek/rtw89/fw.c
+797
-69
drivers/net/wireless/realtek/rtw89/fw.c
···
812
812
enum rtw89_fw_feature feature;
813
813
u32 ver_code;
814
814
bool (*cond)(u32 suit_ver_code, u32 comp_ver_code);
815
+
bool disable;
816
+
int size;
815
817
};
816
818
817
819
#define __CFG_FW_FEAT(_chip, _cond, _maj, _min, _sub, _idx, _feat) \
···
824
822
.cond = __fw_feat_cond_ ## _cond, \
825
823
}
826
824
825
+
#define __S_DIS_FW_FEAT(_chip, _cond, _maj, _min, _sub, _idx, _feat) \
826
+
{ \
827
+
.chip_id = _chip, \
828
+
.feature = RTW89_FW_FEATURE_ ## _feat, \
829
+
.ver_code = RTW89_FW_VER_CODE(_maj, _min, _sub, _idx), \
830
+
.cond = __fw_feat_cond_ ## _cond, \
831
+
.disable = true, \
832
+
.size = 1, \
833
+
}
834
+
835
+
#define __G_DIS_FW_FEAT(_chip, _cond, _maj, _min, _sub, _idx, _grp) \
836
+
{ \
837
+
.chip_id = _chip, \
838
+
.feature = RTW89_FW_FEATURE_ ## _grp ## _MIN, \
839
+
.ver_code = RTW89_FW_VER_CODE(_maj, _min, _sub, _idx), \
840
+
.cond = __fw_feat_cond_ ## _cond, \
841
+
.disable = true, \
842
+
.size = RTW89_FW_FEATURE_ ## _grp ## _MAX - \
843
+
RTW89_FW_FEATURE_ ## _grp ## _MIN + 1, \
844
+
}
845
+
846
+
#define __DIS_FW_FEAT(_chip, _cond, _maj, _min, _sub, _idx, _feat, _type) \
847
+
__##_type##_DIS_FW_FEAT(_chip, _cond, _maj, _min, _sub, _idx, _feat)
848
+
827
849
static const struct __fw_feat_cfg fw_feat_tbl[] = {
828
850
__CFG_FW_FEAT(RTL8851B, ge, 0, 29, 37, 1, TX_WAKE),
829
851
__CFG_FW_FEAT(RTL8851B, ge, 0, 29, 37, 1, SCAN_OFFLOAD),
830
852
__CFG_FW_FEAT(RTL8851B, ge, 0, 29, 41, 0, CRASH_TRIGGER_TYPE_0),
853
+
__CFG_FW_FEAT(RTL8851B, ge, 0, 29, 127, 0, SER_L1_BY_EVENT),
854
+
__CFG_FW_FEAT(RTL8851B, ge, 0, 29, 130, 0, SIM_SER_L0L1_BY_HALT_H2C),
831
855
__CFG_FW_FEAT(RTL8852A, le, 0, 13, 29, 0, OLD_HT_RA_FORMAT),
832
856
__CFG_FW_FEAT(RTL8852A, ge, 0, 13, 35, 0, SCAN_OFFLOAD),
833
857
__CFG_FW_FEAT(RTL8852A, ge, 0, 13, 35, 0, TX_WAKE),
···
865
837
__CFG_FW_FEAT(RTL8852B, ge, 0, 29, 29, 0, CRASH_TRIGGER_TYPE_0),
866
838
__CFG_FW_FEAT(RTL8852B, ge, 0, 29, 29, 0, SCAN_OFFLOAD),
867
839
__CFG_FW_FEAT(RTL8852B, ge, 0, 29, 29, 7, BEACON_FILTER),
840
+
__CFG_FW_FEAT(RTL8852B, ge, 0, 29, 29, 15, BEACON_LOSS_COUNT_V1),
868
841
__CFG_FW_FEAT(RTL8852B, lt, 0, 29, 30, 0, NO_WOW_CPU_IO_RX),
869
842
__CFG_FW_FEAT(RTL8852B, ge, 0, 29, 127, 0, LPS_DACK_BY_C2H_REG),
843
+
__CFG_FW_FEAT(RTL8852B, ge, 0, 29, 127, 0, SER_L1_BY_EVENT),
870
844
__CFG_FW_FEAT(RTL8852B, ge, 0, 29, 128, 0, CRASH_TRIGGER_TYPE_1),
871
845
__CFG_FW_FEAT(RTL8852B, ge, 0, 29, 128, 0, SCAN_OFFLOAD_EXTRA_OP),
872
846
__CFG_FW_FEAT(RTL8852B, ge, 0, 29, 128, 0, BEACON_TRACKING),
847
+
__CFG_FW_FEAT(RTL8852B, ge, 0, 29, 130, 0, SIM_SER_L0L1_BY_HALT_H2C),
873
848
__CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 74, 0, NO_LPS_PG),
874
849
__CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 74, 0, TX_WAKE),
875
850
__CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 90, 0, CRASH_TRIGGER_TYPE_0),
···
882
851
__CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 127, 0, SCAN_OFFLOAD_EXTRA_OP),
883
852
__CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 127, 0, LPS_DACK_BY_C2H_REG),
884
853
__CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 127, 0, CRASH_TRIGGER_TYPE_1),
885
-
__CFG_FW_FEAT(RTL8852C, le, 0, 27, 33, 0, NO_DEEP_PS),
854
+
__CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 127, 0, SER_L1_BY_EVENT),
855
+
__CFG_FW_FEAT(RTL8852BT, ge, 0, 29, 130, 0, SIM_SER_L0L1_BY_HALT_H2C),
886
856
__CFG_FW_FEAT(RTL8852C, ge, 0, 0, 0, 0, RFK_NTFY_MCC_V0),
857
+
__CFG_FW_FEAT(RTL8852C, le, 0, 27, 33, 0, NO_DEEP_PS),
887
858
__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 34, 0, TX_WAKE),
888
859
__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 36, 0, SCAN_OFFLOAD),
889
860
__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 40, 0, CRASH_TRIGGER_TYPE_0),
···
895
862
__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 128, 0, LPS_DACK_BY_C2H_REG),
896
863
__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 128, 0, CRASH_TRIGGER_TYPE_1),
897
864
__CFG_FW_FEAT(RTL8852C, ge, 0, 27, 129, 1, BEACON_TRACKING),
898
-
__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 30, 0, CRASH_TRIGGER_TYPE_0),
865
+
__CFG_FW_FEAT(RTL8852C, ge, 0, 29, 94, 0, SER_L1_BY_EVENT),
866
+
__CFG_FW_FEAT(RTL8852C, ge, 0, 29, 130, 0, SIM_SER_L0L1_BY_HALT_H2C),
867
+
__CFG_FW_FEAT(RTL8922A, ge, 0, 0, 0, 0, RFK_PRE_NOTIFY_V0),
899
868
__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 11, 0, MACID_PAUSE_SLEEP),
869
+
__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 30, 0, CRASH_TRIGGER_TYPE_0),
900
870
__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 35, 0, SCAN_OFFLOAD),
901
-
__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 21, 0, SCAN_OFFLOAD_BE_V0),
871
+
__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 35, 0, SCAN_OFFLOAD_EXTRA_OP),
902
872
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 12, 0, BEACON_FILTER),
873
+
__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 21, 0, SCAN_OFFLOAD_BE_V0),
903
874
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 22, 0, WOW_REASON_V1),
904
875
__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 28, 0, RFK_IQK_V0),
905
-
__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 31, 0, RFK_PRE_NOTIFY_V0),
876
+
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 31, 0, RFK_PRE_NOTIFY_V1),
906
877
__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 31, 0, LPS_CH_INFO),
907
878
__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 42, 0, RFK_RXDCK_V0),
908
879
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 46, 0, NOTIFY_AP_INFO),
909
880
__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 47, 0, CH_INFO_BE_V0),
910
-
__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 49, 0, RFK_PRE_NOTIFY_V1),
881
+
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 49, 0, RFK_PRE_NOTIFY_V2),
882
+
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 49, 0, RFK_PRE_NOTIFY_MCC_V0),
911
883
__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 51, 0, NO_PHYCAP_P1),
912
884
__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 64, 0, NO_POWER_DIFFERENCE),
913
885
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 71, 0, BEACON_LOSS_COUNT_V1),
914
886
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 76, 0, LPS_DACK_BY_C2H_REG),
915
887
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 79, 0, CRASH_TRIGGER_TYPE_1),
916
888
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 80, 0, BEACON_TRACKING),
889
+
__DIS_FW_FEAT(RTL8922A, ge, 0, 35, 84, 0, WITH_RFK_PRE_NOTIFY, G),
890
+
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 84, 0, RFK_PRE_NOTIFY_MCC_V1),
917
891
__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 84, 0, ADDR_CAM_V0),
918
892
};
919
893
···
936
896
if (chip->chip_id != ent->chip_id)
937
897
continue;
938
898
939
-
if (ent->cond(ver_code, ent->ver_code))
899
+
if (!ent->cond(ver_code, ent->ver_code))
900
+
continue;
901
+
902
+
if (!ent->disable) {
940
903
RTW89_SET_FW_FEATURE(ent->feature, fw);
904
+
continue;
905
+
}
906
+
907
+
for (int n = 0; n < ent->size; n++)
908
+
RTW89_CLR_FW_FEATURE(ent->feature + n, fw);
941
909
}
942
910
}
943
911
···
1061
1013
const union rtw89_fw_element_arg arg)
1062
1014
{
1063
1015
struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1064
-
struct rtw89_phy_table *tbl;
1016
+
struct rtw89_hal *hal = &rtwdev->hal;
1017
+
struct rtw89_phy_table *tbl, **pp;
1065
1018
struct rtw89_reg2_def *regs;
1066
-
enum rtw89_rf_path rf_path;
1019
+
bool radio = false;
1067
1020
u32 n_regs, i;
1021
+
u16 aid;
1068
1022
u8 idx;
1069
-
1070
-
tbl = kzalloc(sizeof(*tbl), GFP_KERNEL);
1071
-
if (!tbl)
1072
-
return -ENOMEM;
1073
1023
1074
1024
switch (le32_to_cpu(elm->id)) {
1075
1025
case RTW89_FW_ELEMENT_ID_BB_REG:
1076
-
elm_info->bb_tbl = tbl;
1026
+
pp = &elm_info->bb_tbl;
1077
1027
break;
1078
1028
case RTW89_FW_ELEMENT_ID_BB_GAIN:
1079
-
elm_info->bb_gain = tbl;
1029
+
pp = &elm_info->bb_gain;
1080
1030
break;
1081
1031
case RTW89_FW_ELEMENT_ID_RADIO_A:
1082
1032
case RTW89_FW_ELEMENT_ID_RADIO_B:
1083
1033
case RTW89_FW_ELEMENT_ID_RADIO_C:
1084
1034
case RTW89_FW_ELEMENT_ID_RADIO_D:
1085
-
rf_path = arg.rf_path;
1086
1035
idx = elm->u.reg2.idx;
1036
+
pp = &elm_info->rf_radio[idx];
1087
1037
1088
-
elm_info->rf_radio[idx] = tbl;
1089
-
tbl->rf_path = rf_path;
1090
-
tbl->config = rtw89_phy_config_rf_reg_v1;
1038
+
radio = true;
1091
1039
break;
1092
1040
case RTW89_FW_ELEMENT_ID_RF_NCTL:
1093
-
elm_info->rf_nctl = tbl;
1041
+
pp = &elm_info->rf_nctl;
1094
1042
break;
1095
1043
default:
1096
-
kfree(tbl);
1097
1044
return -ENOENT;
1098
1045
}
1046
+
1047
+
aid = le16_to_cpu(elm->aid);
1048
+
if (aid && aid != hal->aid)
1049
+
return 1; /* ignore if aid not matched */
1050
+
else if (*pp)
1051
+
return 1; /* ignore if an element is existing */
1052
+
1053
+
tbl = kzalloc(sizeof(*tbl), GFP_KERNEL);
1054
+
if (!tbl)
1055
+
return -ENOMEM;
1099
1056
1100
1057
n_regs = le32_to_cpu(elm->size) / sizeof(tbl->regs[0]);
1101
1058
regs = kcalloc(n_regs, sizeof(*regs), GFP_KERNEL);
···
1114
1061
1115
1062
tbl->n_regs = n_regs;
1116
1063
tbl->regs = regs;
1064
+
1065
+
if (radio) {
1066
+
tbl->rf_path = arg.rf_path;
1067
+
tbl->config = rtw89_phy_config_rf_reg_v1;
1068
+
}
1069
+
1070
+
*pp = tbl;
1117
1071
1118
1072
return 0;
1119
1073
···
1541
1481
u8 type, u8 cat, u8 class, u8 func,
1542
1482
bool rack, bool dack, u32 len)
1543
1483
{
1484
+
const struct rtw89_chip_info *chip = rtwdev->chip;
1544
1485
struct fwcmd_hdr *hdr;
1545
1486
1546
1487
hdr = (struct fwcmd_hdr *)skb_push(skb, 8);
1547
1488
1548
-
if (!(rtwdev->fw.h2c_seq % 4))
1489
+
if (chip->chip_gen == RTW89_CHIP_AX && !(rtwdev->fw.h2c_seq % 4))
1549
1490
rack = true;
1550
1491
hdr->hdr0 = cpu_to_le32(FIELD_PREP(H2C_HDR_DEL_TYPE, type) |
1551
1492
FIELD_PREP(H2C_HDR_CAT, cat) |
···
2328
2267
}
2329
2268
EXPORT_SYMBOL(rtw89_fw_h2c_dctl_sec_cam_v2);
2330
2269
2270
+
int rtw89_fw_h2c_dctl_sec_cam_v3(struct rtw89_dev *rtwdev,
2271
+
struct rtw89_vif_link *rtwvif_link,
2272
+
struct rtw89_sta_link *rtwsta_link)
2273
+
{
2274
+
struct rtw89_h2c_dctlinfo_ud_v3 *h2c;
2275
+
u32 len = sizeof(*h2c);
2276
+
struct sk_buff *skb;
2277
+
int ret;
2278
+
2279
+
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
2280
+
if (!skb) {
2281
+
rtw89_err(rtwdev, "failed to alloc skb for dctl sec cam\n");
2282
+
return -ENOMEM;
2283
+
}
2284
+
skb_put(skb, len);
2285
+
h2c = (struct rtw89_h2c_dctlinfo_ud_v3 *)skb->data;
2286
+
2287
+
rtw89_cam_fill_dctl_sec_cam_info_v3(rtwdev, rtwvif_link, rtwsta_link, h2c);
2288
+
2289
+
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
2290
+
H2C_CAT_MAC,
2291
+
H2C_CL_MAC_FR_EXCHG,
2292
+
H2C_FUNC_MAC_DCTLINFO_UD_V3, 0, 0,
2293
+
len);
2294
+
2295
+
ret = rtw89_h2c_tx(rtwdev, skb, false);
2296
+
if (ret) {
2297
+
rtw89_err(rtwdev, "failed to send h2c\n");
2298
+
goto fail;
2299
+
}
2300
+
2301
+
return 0;
2302
+
fail:
2303
+
dev_kfree_skb_any(skb);
2304
+
2305
+
return ret;
2306
+
}
2307
+
EXPORT_SYMBOL(rtw89_fw_h2c_dctl_sec_cam_v3);
2308
+
2331
2309
int rtw89_fw_h2c_default_dmac_tbl_v2(struct rtw89_dev *rtwdev,
2332
2310
struct rtw89_vif_link *rtwvif_link,
2333
2311
struct rtw89_sta_link *rtwsta_link)
···
2421
2321
return ret;
2422
2322
}
2423
2323
EXPORT_SYMBOL(rtw89_fw_h2c_default_dmac_tbl_v2);
2324
+
2325
+
int rtw89_fw_h2c_default_dmac_tbl_v3(struct rtw89_dev *rtwdev,
2326
+
struct rtw89_vif_link *rtwvif_link,
2327
+
struct rtw89_sta_link *rtwsta_link)
2328
+
{
2329
+
u8 mac_id = rtwsta_link ? rtwsta_link->mac_id : rtwvif_link->mac_id;
2330
+
struct rtw89_h2c_dctlinfo_ud_v3 *h2c;
2331
+
u32 len = sizeof(*h2c);
2332
+
struct sk_buff *skb;
2333
+
int ret;
2334
+
2335
+
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
2336
+
if (!skb) {
2337
+
rtw89_err(rtwdev, "failed to alloc skb for dctl v2\n");
2338
+
return -ENOMEM;
2339
+
}
2340
+
skb_put(skb, len);
2341
+
h2c = (struct rtw89_h2c_dctlinfo_ud_v3 *)skb->data;
2342
+
2343
+
h2c->c0 = le32_encode_bits(mac_id, DCTLINFO_V3_C0_MACID) |
2344
+
le32_encode_bits(1, DCTLINFO_V3_C0_OP);
2345
+
2346
+
h2c->m0 = cpu_to_le32(DCTLINFO_V3_W0_ALL);
2347
+
h2c->m1 = cpu_to_le32(DCTLINFO_V3_W1_ALL);
2348
+
h2c->m2 = cpu_to_le32(DCTLINFO_V3_W2_ALL);
2349
+
h2c->m3 = cpu_to_le32(DCTLINFO_V3_W3_ALL);
2350
+
h2c->m4 = cpu_to_le32(DCTLINFO_V3_W4_ALL);
2351
+
h2c->m5 = cpu_to_le32(DCTLINFO_V3_W5_ALL);
2352
+
h2c->m6 = cpu_to_le32(DCTLINFO_V3_W6_ALL);
2353
+
h2c->m7 = cpu_to_le32(DCTLINFO_V3_W7_ALL);
2354
+
h2c->m8 = cpu_to_le32(DCTLINFO_V3_W8_ALL);
2355
+
h2c->m9 = cpu_to_le32(DCTLINFO_V3_W9_ALL);
2356
+
h2c->m10 = cpu_to_le32(DCTLINFO_V3_W10_ALL);
2357
+
h2c->m11 = cpu_to_le32(DCTLINFO_V3_W11_ALL);
2358
+
h2c->m12 = cpu_to_le32(DCTLINFO_V3_W12_ALL);
2359
+
h2c->m13 = cpu_to_le32(DCTLINFO_V3_W13_ALL);
2360
+
2361
+
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
2362
+
H2C_CAT_MAC,
2363
+
H2C_CL_MAC_FR_EXCHG,
2364
+
H2C_FUNC_MAC_DCTLINFO_UD_V3, 0, 0,
2365
+
len);
2366
+
2367
+
ret = rtw89_h2c_tx(rtwdev, skb, false);
2368
+
if (ret) {
2369
+
rtw89_err(rtwdev, "failed to send h2c\n");
2370
+
goto fail;
2371
+
}
2372
+
2373
+
return 0;
2374
+
fail:
2375
+
dev_kfree_skb_any(skb);
2376
+
2377
+
return ret;
2378
+
}
2379
+
EXPORT_SYMBOL(rtw89_fw_h2c_default_dmac_tbl_v3);
2424
2380
2425
2381
int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev,
2426
2382
struct rtw89_vif_link *rtwvif_link,
···
3474
3318
}
3475
3319
EXPORT_SYMBOL(rtw89_fw_h2c_default_cmac_tbl_g7);
3476
3320
3321
+
int rtw89_fw_h2c_default_cmac_tbl_be(struct rtw89_dev *rtwdev,
3322
+
struct rtw89_vif_link *rtwvif_link,
3323
+
struct rtw89_sta_link *rtwsta_link)
3324
+
{
3325
+
u8 mac_id = rtwsta_link ? rtwsta_link->mac_id : rtwvif_link->mac_id;
3326
+
bool preld = rtw89_mac_chk_preload_allow(rtwdev);
3327
+
struct rtw89_h2c_cctlinfo_ud_be *h2c;
3328
+
u32 len = sizeof(*h2c);
3329
+
struct sk_buff *skb;
3330
+
int ret;
3331
+
3332
+
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
3333
+
if (!skb) {
3334
+
rtw89_err(rtwdev, "failed to alloc skb for default cmac be\n");
3335
+
return -ENOMEM;
3336
+
}
3337
+
skb_put(skb, len);
3338
+
h2c = (struct rtw89_h2c_cctlinfo_ud_be *)skb->data;
3339
+
3340
+
h2c->c0 = le32_encode_bits(mac_id, BE_CCTL_INFO_C0_V1_MACID) |
3341
+
le32_encode_bits(1, BE_CCTL_INFO_C0_V1_OP);
3342
+
3343
+
h2c->w0 = le32_encode_bits(4, BE_CCTL_INFO_W0_DATARATE);
3344
+
h2c->m0 = cpu_to_le32(BE_CCTL_INFO_W0_ALL);
3345
+
3346
+
h2c->w1 = le32_encode_bits(4, BE_CCTL_INFO_W1_DATA_RTY_LOWEST_RATE) |
3347
+
le32_encode_bits(0xa, BE_CCTL_INFO_W1_RTSRATE) |
3348
+
le32_encode_bits(4, BE_CCTL_INFO_W1_RTS_RTY_LOWEST_RATE);
3349
+
h2c->m1 = cpu_to_le32(BE_CCTL_INFO_W1_ALL);
3350
+
3351
+
h2c->w1 = le32_encode_bits(preld, BE_CCTL_INFO_W2_PRELOAD_ENABLE);
3352
+
h2c->m2 = cpu_to_le32(BE_CCTL_INFO_W2_ALL);
3353
+
3354
+
h2c->m3 = cpu_to_le32(BE_CCTL_INFO_W3_ALL);
3355
+
3356
+
h2c->w4 = le32_encode_bits(0xFFFF, BE_CCTL_INFO_W4_ACT_SUBCH_CBW);
3357
+
h2c->m4 = cpu_to_le32(BE_CCTL_INFO_W4_ALL);
3358
+
3359
+
h2c->w5 = le32_encode_bits(2, BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING0_V1) |
3360
+
le32_encode_bits(2, BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING1_V1) |
3361
+
le32_encode_bits(2, BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING2_V1) |
3362
+
le32_encode_bits(2, BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING3_V1) |
3363
+
le32_encode_bits(2, BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING4_V1);
3364
+
h2c->m5 = cpu_to_le32(BE_CCTL_INFO_W5_ALL);
3365
+
3366
+
h2c->w6 = le32_encode_bits(0xb, BE_CCTL_INFO_W6_RESP_REF_RATE);
3367
+
h2c->m6 = cpu_to_le32(BE_CCTL_INFO_W6_ALL);
3368
+
3369
+
h2c->w7 = le32_encode_bits(1, BE_CCTL_INFO_W7_NC) |
3370
+
le32_encode_bits(1, BE_CCTL_INFO_W7_NR) |
3371
+
le32_encode_bits(1, BE_CCTL_INFO_W7_CB) |
3372
+
le32_encode_bits(0x1, BE_CCTL_INFO_W7_CSI_PARA_EN) |
3373
+
le32_encode_bits(0xb, BE_CCTL_INFO_W7_CSI_FIX_RATE);
3374
+
h2c->m7 = cpu_to_le32(BE_CCTL_INFO_W7_ALL);
3375
+
3376
+
h2c->m8 = cpu_to_le32(BE_CCTL_INFO_W8_ALL);
3377
+
3378
+
h2c->w14 = le32_encode_bits(0, BE_CCTL_INFO_W14_VO_CURR_RATE) |
3379
+
le32_encode_bits(0, BE_CCTL_INFO_W14_VI_CURR_RATE) |
3380
+
le32_encode_bits(0, BE_CCTL_INFO_W14_BE_CURR_RATE_L);
3381
+
h2c->m14 = cpu_to_le32(BE_CCTL_INFO_W14_ALL);
3382
+
3383
+
h2c->w15 = le32_encode_bits(0, BE_CCTL_INFO_W15_BE_CURR_RATE_H) |
3384
+
le32_encode_bits(0, BE_CCTL_INFO_W15_BK_CURR_RATE) |
3385
+
le32_encode_bits(0, BE_CCTL_INFO_W15_MGNT_CURR_RATE);
3386
+
h2c->m15 = cpu_to_le32(BE_CCTL_INFO_W15_ALL);
3387
+
3388
+
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
3389
+
H2C_CAT_MAC, H2C_CL_MAC_FR_EXCHG,
3390
+
H2C_FUNC_MAC_CCTLINFO_UD_G7, 0, 1,
3391
+
len);
3392
+
3393
+
ret = rtw89_h2c_tx(rtwdev, skb, false);
3394
+
if (ret) {
3395
+
rtw89_err(rtwdev, "failed to send h2c\n");
3396
+
goto fail;
3397
+
}
3398
+
3399
+
return 0;
3400
+
fail:
3401
+
dev_kfree_skb_any(skb);
3402
+
3403
+
return ret;
3404
+
}
3405
+
EXPORT_SYMBOL(rtw89_fw_h2c_default_cmac_tbl_be);
3406
+
3477
3407
static void __get_sta_he_pkt_padding(struct rtw89_dev *rtwdev,
3478
3408
struct ieee80211_link_sta *link_sta,
3479
3409
u8 *pads)
···
3890
3648
}
3891
3649
EXPORT_SYMBOL(rtw89_fw_h2c_assoc_cmac_tbl_g7);
3892
3650
3651
+
int rtw89_fw_h2c_assoc_cmac_tbl_be(struct rtw89_dev *rtwdev,
3652
+
struct rtw89_vif_link *rtwvif_link,
3653
+
struct rtw89_sta_link *rtwsta_link)
3654
+
{
3655
+
struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
3656
+
const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
3657
+
u8 mac_id = rtwsta_link ? rtwsta_link->mac_id : rtwvif_link->mac_id;
3658
+
struct rtw89_h2c_cctlinfo_ud_be *h2c;
3659
+
struct ieee80211_bss_conf *bss_conf;
3660
+
struct ieee80211_link_sta *link_sta;
3661
+
u8 pads[RTW89_PPE_BW_NUM];
3662
+
u32 len = sizeof(*h2c);
3663
+
struct sk_buff *skb;
3664
+
u16 lowest_rate;
3665
+
int ret;
3666
+
3667
+
memset(pads, 0, sizeof(pads));
3668
+
3669
+
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
3670
+
if (!skb) {
3671
+
rtw89_err(rtwdev, "failed to alloc skb for assoc cmac be\n");
3672
+
return -ENOMEM;
3673
+
}
3674
+
3675
+
rcu_read_lock();
3676
+
3677
+
bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
3678
+
3679
+
if (rtwsta_link) {
3680
+
link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
3681
+
3682
+
if (link_sta->eht_cap.has_eht)
3683
+
__get_sta_eht_pkt_padding(rtwdev, link_sta, pads);
3684
+
else if (link_sta->he_cap.has_he)
3685
+
__get_sta_he_pkt_padding(rtwdev, link_sta, pads);
3686
+
}
3687
+
3688
+
if (vif->p2p)
3689
+
lowest_rate = RTW89_HW_RATE_OFDM6;
3690
+
else if (chan->band_type == RTW89_BAND_2G)
3691
+
lowest_rate = RTW89_HW_RATE_CCK1;
3692
+
else
3693
+
lowest_rate = RTW89_HW_RATE_OFDM6;
3694
+
3695
+
skb_put(skb, len);
3696
+
h2c = (struct rtw89_h2c_cctlinfo_ud_be *)skb->data;
3697
+
3698
+
h2c->c0 = le32_encode_bits(mac_id, BE_CCTL_INFO_C0_V1_MACID) |
3699
+
le32_encode_bits(1, BE_CCTL_INFO_C0_V1_OP);
3700
+
3701
+
h2c->w0 = le32_encode_bits(1, BE_CCTL_INFO_W0_DISRTSFB) |
3702
+
le32_encode_bits(1, BE_CCTL_INFO_W0_DISDATAFB);
3703
+
h2c->m0 = cpu_to_le32(BE_CCTL_INFO_W0_DISRTSFB |
3704
+
BE_CCTL_INFO_W0_DISDATAFB);
3705
+
3706
+
h2c->w1 = le32_encode_bits(lowest_rate, BE_CCTL_INFO_W1_RTS_RTY_LOWEST_RATE);
3707
+
h2c->m1 = cpu_to_le32(BE_CCTL_INFO_W1_RTS_RTY_LOWEST_RATE);
3708
+
3709
+
h2c->w2 = le32_encode_bits(0, BE_CCTL_INFO_W2_DATA_TXCNT_LMT_SEL);
3710
+
h2c->m2 = cpu_to_le32(BE_CCTL_INFO_W2_DATA_TXCNT_LMT_SEL);
3711
+
3712
+
h2c->w3 = le32_encode_bits(0, BE_CCTL_INFO_W3_RTS_TXCNT_LMT_SEL);
3713
+
h2c->m3 = cpu_to_le32(BE_CCTL_INFO_W3_RTS_TXCNT_LMT_SEL);
3714
+
3715
+
h2c->w4 = le32_encode_bits(rtwvif_link->port, BE_CCTL_INFO_W4_MULTI_PORT_ID);
3716
+
h2c->m4 = cpu_to_le32(BE_CCTL_INFO_W4_MULTI_PORT_ID);
3717
+
3718
+
if (bss_conf->eht_support) {
3719
+
u16 punct = bss_conf->chanreq.oper.punctured;
3720
+
3721
+
h2c->w4 |= le32_encode_bits(~punct,
3722
+
BE_CCTL_INFO_W4_ACT_SUBCH_CBW);
3723
+
h2c->m4 |= cpu_to_le32(BE_CCTL_INFO_W4_ACT_SUBCH_CBW);
3724
+
}
3725
+
3726
+
h2c->w5 = le32_encode_bits(pads[RTW89_CHANNEL_WIDTH_20],
3727
+
BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING0_V1) |
3728
+
le32_encode_bits(pads[RTW89_CHANNEL_WIDTH_40],
3729
+
BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING1_V1) |
3730
+
le32_encode_bits(pads[RTW89_CHANNEL_WIDTH_80],
3731
+
BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING2_V1) |
3732
+
le32_encode_bits(pads[RTW89_CHANNEL_WIDTH_160],
3733
+
BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING3_V1) |
3734
+
le32_encode_bits(pads[RTW89_CHANNEL_WIDTH_320],
3735
+
BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING4_V1);
3736
+
h2c->m5 = cpu_to_le32(BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING0_V1 |
3737
+
BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING1_V1 |
3738
+
BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING2_V1 |
3739
+
BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING3_V1 |
3740
+
BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING4_V1);
3741
+
3742
+
if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) {
3743
+
h2c->w5 |= le32_encode_bits(0, BE_CCTL_INFO_W5_DATA_DCM_V1);
3744
+
h2c->m5 |= cpu_to_le32(BE_CCTL_INFO_W5_DATA_DCM_V1);
3745
+
}
3746
+
3747
+
h2c->w6 = le32_encode_bits(vif->cfg.aid, BE_CCTL_INFO_W6_AID12_PAID) |
3748
+
le32_encode_bits(vif->type == NL80211_IFTYPE_STATION ? 1 : 0,
3749
+
BE_CCTL_INFO_W6_ULDL);
3750
+
h2c->m6 = cpu_to_le32(BE_CCTL_INFO_W6_AID12_PAID | BE_CCTL_INFO_W6_ULDL);
3751
+
3752
+
if (rtwsta_link) {
3753
+
h2c->w8 = le32_encode_bits(link_sta->he_cap.has_he,
3754
+
BE_CCTL_INFO_W8_BSR_QUEUE_SIZE_FORMAT_V1);
3755
+
h2c->m8 = cpu_to_le32(BE_CCTL_INFO_W8_BSR_QUEUE_SIZE_FORMAT_V1);
3756
+
}
3757
+
3758
+
rcu_read_unlock();
3759
+
3760
+
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
3761
+
H2C_CAT_MAC, H2C_CL_MAC_FR_EXCHG,
3762
+
H2C_FUNC_MAC_CCTLINFO_UD_G7, 0, 1,
3763
+
len);
3764
+
3765
+
ret = rtw89_h2c_tx(rtwdev, skb, false);
3766
+
if (ret) {
3767
+
rtw89_err(rtwdev, "failed to send h2c\n");
3768
+
goto fail;
3769
+
}
3770
+
3771
+
return 0;
3772
+
fail:
3773
+
dev_kfree_skb_any(skb);
3774
+
3775
+
return ret;
3776
+
}
3777
+
EXPORT_SYMBOL(rtw89_fw_h2c_assoc_cmac_tbl_be);
3778
+
3893
3779
int rtw89_fw_h2c_ampdu_cmac_tbl_g7(struct rtw89_dev *rtwdev,
3894
3780
struct rtw89_vif_link *rtwvif_link,
3895
3781
struct rtw89_sta_link *rtwsta_link)
···
4083
3713
return ret;
4084
3714
}
4085
3715
EXPORT_SYMBOL(rtw89_fw_h2c_ampdu_cmac_tbl_g7);
3716
+
3717
+
int rtw89_fw_h2c_ampdu_cmac_tbl_be(struct rtw89_dev *rtwdev,
3718
+
struct rtw89_vif_link *rtwvif_link,
3719
+
struct rtw89_sta_link *rtwsta_link)
3720
+
{
3721
+
struct rtw89_sta *rtwsta = rtwsta_link->rtwsta;
3722
+
struct rtw89_h2c_cctlinfo_ud_be *h2c;
3723
+
u32 len = sizeof(*h2c);
3724
+
struct sk_buff *skb;
3725
+
u16 agg_num = 0;
3726
+
u8 ba_bmap = 0;
3727
+
int ret;
3728
+
u8 tid;
3729
+
3730
+
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
3731
+
if (!skb) {
3732
+
rtw89_err(rtwdev, "failed to alloc skb for ampdu cmac be\n");
3733
+
return -ENOMEM;
3734
+
}
3735
+
skb_put(skb, len);
3736
+
h2c = (struct rtw89_h2c_cctlinfo_ud_be *)skb->data;
3737
+
3738
+
for_each_set_bit(tid, rtwsta->ampdu_map, IEEE80211_NUM_TIDS) {
3739
+
if (agg_num == 0)
3740
+
agg_num = rtwsta->ampdu_params[tid].agg_num;
3741
+
else
3742
+
agg_num = min(agg_num, rtwsta->ampdu_params[tid].agg_num);
3743
+
}
3744
+
3745
+
if (agg_num <= 0x20)
3746
+
ba_bmap = 3;
3747
+
else if (agg_num > 0x20 && agg_num <= 0x40)
3748
+
ba_bmap = 0;
3749
+
else if (agg_num > 0x40 && agg_num <= 0x80)
3750
+
ba_bmap = 1;
3751
+
else if (agg_num > 0x80 && agg_num <= 0x100)
3752
+
ba_bmap = 2;
3753
+
else if (agg_num > 0x100 && agg_num <= 0x200)
3754
+
ba_bmap = 4;
3755
+
else if (agg_num > 0x200 && agg_num <= 0x400)
3756
+
ba_bmap = 5;
3757
+
3758
+
h2c->c0 = le32_encode_bits(rtwsta_link->mac_id, BE_CCTL_INFO_C0_V1_MACID) |
3759
+
le32_encode_bits(1, BE_CCTL_INFO_C0_V1_OP);
3760
+
3761
+
h2c->w3 = le32_encode_bits(ba_bmap, BE_CCTL_INFO_W3_BA_BMAP);
3762
+
h2c->m3 = cpu_to_le32(BE_CCTL_INFO_W3_BA_BMAP);
3763
+
3764
+
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
3765
+
H2C_CAT_MAC, H2C_CL_MAC_FR_EXCHG,
3766
+
H2C_FUNC_MAC_CCTLINFO_UD_G7, 0, 0,
3767
+
len);
3768
+
3769
+
ret = rtw89_h2c_tx(rtwdev, skb, false);
3770
+
if (ret) {
3771
+
rtw89_err(rtwdev, "failed to send h2c\n");
3772
+
goto fail;
3773
+
}
3774
+
3775
+
return 0;
3776
+
fail:
3777
+
dev_kfree_skb_any(skb);
3778
+
3779
+
return ret;
3780
+
}
3781
+
EXPORT_SYMBOL(rtw89_fw_h2c_ampdu_cmac_tbl_be);
4086
3782
4087
3783
int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
4088
3784
struct rtw89_sta_link *rtwsta_link)
···
4247
3811
}
4248
3812
EXPORT_SYMBOL(rtw89_fw_h2c_txtime_cmac_tbl_g7);
4249
3813
3814
+
int rtw89_fw_h2c_txtime_cmac_tbl_be(struct rtw89_dev *rtwdev,
3815
+
struct rtw89_sta_link *rtwsta_link)
3816
+
{
3817
+
struct rtw89_h2c_cctlinfo_ud_be *h2c;
3818
+
u32 len = sizeof(*h2c);
3819
+
struct sk_buff *skb;
3820
+
int ret;
3821
+
3822
+
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
3823
+
if (!skb) {
3824
+
rtw89_err(rtwdev, "failed to alloc skb for txtime_cmac_be\n");
3825
+
return -ENOMEM;
3826
+
}
3827
+
skb_put(skb, len);
3828
+
h2c = (struct rtw89_h2c_cctlinfo_ud_be *)skb->data;
3829
+
3830
+
h2c->c0 = le32_encode_bits(rtwsta_link->mac_id, BE_CCTL_INFO_C0_V1_MACID) |
3831
+
le32_encode_bits(1, BE_CCTL_INFO_C0_V1_OP);
3832
+
3833
+
if (rtwsta_link->cctl_tx_time) {
3834
+
h2c->w3 |= le32_encode_bits(1, BE_CCTL_INFO_W3_AMPDU_TIME_SEL);
3835
+
h2c->m3 |= cpu_to_le32(BE_CCTL_INFO_W3_AMPDU_TIME_SEL);
3836
+
3837
+
h2c->w2 |= le32_encode_bits(rtwsta_link->ampdu_max_time,
3838
+
BE_CCTL_INFO_W2_AMPDU_MAX_TIME);
3839
+
h2c->m2 |= cpu_to_le32(BE_CCTL_INFO_W2_AMPDU_MAX_TIME);
3840
+
}
3841
+
if (rtwsta_link->cctl_tx_retry_limit) {
3842
+
h2c->w2 |= le32_encode_bits(1, BE_CCTL_INFO_W2_DATA_TXCNT_LMT_SEL) |
3843
+
le32_encode_bits(rtwsta_link->data_tx_cnt_lmt,
3844
+
BE_CCTL_INFO_W2_DATA_TX_CNT_LMT);
3845
+
h2c->m2 |= cpu_to_le32(BE_CCTL_INFO_W2_DATA_TXCNT_LMT_SEL |
3846
+
BE_CCTL_INFO_W2_DATA_TX_CNT_LMT);
3847
+
}
3848
+
3849
+
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
3850
+
H2C_CAT_MAC, H2C_CL_MAC_FR_EXCHG,
3851
+
H2C_FUNC_MAC_CCTLINFO_UD_G7, 0, 1,
3852
+
len);
3853
+
3854
+
ret = rtw89_h2c_tx(rtwdev, skb, false);
3855
+
if (ret) {
3856
+
rtw89_err(rtwdev, "failed to send h2c\n");
3857
+
goto fail;
3858
+
}
3859
+
3860
+
return 0;
3861
+
fail:
3862
+
dev_kfree_skb_any(skb);
3863
+
3864
+
return ret;
3865
+
}
3866
+
EXPORT_SYMBOL(rtw89_fw_h2c_txtime_cmac_tbl_be);
3867
+
4250
3868
int rtw89_fw_h2c_punctured_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4251
3869
struct rtw89_vif_link *rtwvif_link,
4252
3870
u16 punctured)
···
4343
3853
return ret;
4344
3854
}
4345
3855
EXPORT_SYMBOL(rtw89_fw_h2c_punctured_cmac_tbl_g7);
3856
+
3857
+
int rtw89_fw_h2c_punctured_cmac_tbl_be(struct rtw89_dev *rtwdev,
3858
+
struct rtw89_vif_link *rtwvif_link,
3859
+
u16 punctured)
3860
+
{
3861
+
struct rtw89_h2c_cctlinfo_ud_be *h2c;
3862
+
u32 len = sizeof(*h2c);
3863
+
struct sk_buff *skb;
3864
+
int ret;
3865
+
3866
+
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
3867
+
if (!skb) {
3868
+
rtw89_err(rtwdev, "failed to alloc skb for punctured cmac be\n");
3869
+
return -ENOMEM;
3870
+
}
3871
+
skb_put(skb, len);
3872
+
h2c = (struct rtw89_h2c_cctlinfo_ud_be *)skb->data;
3873
+
3874
+
h2c->c0 = le32_encode_bits(rtwvif_link->mac_id, BE_CCTL_INFO_C0_V1_MACID) |
3875
+
le32_encode_bits(1, BE_CCTL_INFO_C0_V1_OP);
3876
+
3877
+
h2c->w4 = le32_encode_bits(~punctured, BE_CCTL_INFO_W4_ACT_SUBCH_CBW);
3878
+
h2c->m4 = cpu_to_le32(BE_CCTL_INFO_W4_ACT_SUBCH_CBW);
3879
+
3880
+
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
3881
+
H2C_CAT_MAC, H2C_CL_MAC_FR_EXCHG,
3882
+
H2C_FUNC_MAC_CCTLINFO_UD_G7, 0, 1,
3883
+
len);
3884
+
3885
+
ret = rtw89_h2c_tx(rtwdev, skb, false);
3886
+
if (ret) {
3887
+
rtw89_err(rtwdev, "failed to send h2c\n");
3888
+
goto fail;
3889
+
}
3890
+
3891
+
return 0;
3892
+
fail:
3893
+
dev_kfree_skb_any(skb);
3894
+
3895
+
return ret;
3896
+
}
3897
+
EXPORT_SYMBOL(rtw89_fw_h2c_punctured_cmac_tbl_be);
4346
3898
4347
3899
int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
4348
3900
struct rtw89_sta_link *rtwsta_link)
···
6467
5935
u8 scan_offload_ver = U8_MAX;
6468
5936
u8 cfg_len = sizeof(*h2c);
6469
5937
unsigned int cond;
6470
-
u8 ap_idx = U8_MAX;
6471
5938
u8 ver = U8_MAX;
6472
5939
u8 policy_val;
6473
5940
void *ptr;
5941
+
u8 txnull;
6474
5942
u8 txbcn;
6475
5943
int ret;
6476
5944
u32 len;
6477
5945
u8 i;
6478
5946
6479
-
scan_op[0].macid = rtwvif_link->mac_id;
6480
-
scan_op[0].port = rtwvif_link->port;
6481
-
scan_op[0].chan = *op;
6482
-
vif = rtwvif_to_vif(rtwvif_link->rtwvif);
6483
-
if (vif->type == NL80211_IFTYPE_AP)
6484
-
ap_idx = 0;
6485
-
6486
-
if (ext->set) {
6487
-
scan_op[1] = *ext;
6488
-
vif = rtwvif_to_vif(ext->rtwvif_link->rtwvif);
6489
-
if (vif->type == NL80211_IFTYPE_AP)
6490
-
ap_idx = 1;
5947
+
if (option->num_opch > RTW89_MAX_OP_NUM_BE) {
5948
+
rtw89_err(rtwdev, "num of scan OP chan %d over limit\n", option->num_opch);
5949
+
return -ENOENT;
6491
5950
}
6492
5951
6493
5952
rtw89_scan_get_6g_disabled_chan(rtwdev, option);
···
6583
6060
}
6584
6061
6585
6062
for (i = 0; i < option->num_opch; i++) {
6586
-
bool is_ap_idx = i == ap_idx;
6063
+
struct rtw89_vif_link *rtwvif_link_op;
6064
+
bool is_ap;
6587
6065
6588
-
opmode = is_ap_idx ? RTW89_SCAN_OPMODE_TBTT : RTW89_SCAN_OPMODE_INTV;
6589
-
policy_val = is_ap_idx ? 2 : RTW89_OFF_CHAN_TIME / 10;
6590
-
txbcn = is_ap_idx ? 1 : 0;
6066
+
switch (i) {
6067
+
case 0:
6068
+
scan_op[0].macid = rtwvif_link->mac_id;
6069
+
scan_op[0].port = rtwvif_link->port;
6070
+
scan_op[0].chan = *op;
6071
+
rtwvif_link_op = rtwvif_link;
6072
+
break;
6073
+
case 1:
6074
+
scan_op[1] = *ext;
6075
+
rtwvif_link_op = ext->rtwvif_link;
6076
+
break;
6077
+
}
6078
+
6079
+
vif = rtwvif_to_vif(rtwvif_link_op->rtwvif);
6080
+
is_ap = vif->type == NL80211_IFTYPE_AP;
6081
+
txnull = !is_zero_ether_addr(rtwvif_link_op->bssid) &&
6082
+
vif->type != NL80211_IFTYPE_AP;
6083
+
opmode = is_ap ? RTW89_SCAN_OPMODE_TBTT : RTW89_SCAN_OPMODE_INTV;
6084
+
policy_val = is_ap ? 2 : RTW89_OFF_CHAN_TIME / 10;
6085
+
txbcn = is_ap ? 1 : 0;
6591
6086
6592
6087
opch = ptr;
6593
6088
opch->w0 = le32_encode_bits(scan_op[i].macid,
···
6616
6075
RTW89_H2C_SCANOFLD_BE_OPCH_W0_PORT) |
6617
6076
le32_encode_bits(opmode,
6618
6077
RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY) |
6619
-
le32_encode_bits(true,
6078
+
le32_encode_bits(txnull,
6620
6079
RTW89_H2C_SCANOFLD_BE_OPCH_W0_TXNULL) |
6621
6080
le32_encode_bits(policy_val,
6622
6081
RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY_VAL);
···
6890
6349
struct rtw89_fw_h2c_rfk_pre_info_common *common;
6891
6350
struct rtw89_fw_h2c_rfk_pre_info_v0 *h2c_v0;
6892
6351
struct rtw89_fw_h2c_rfk_pre_info_v1 *h2c_v1;
6352
+
struct rtw89_fw_h2c_rfk_pre_info_v2 *h2c_v2;
6893
6353
struct rtw89_fw_h2c_rfk_pre_info *h2c;
6894
6354
u8 tbl_sel[NUM_OF_RTW89_FW_RFK_PATH];
6895
6355
u32 len = sizeof(*h2c);
···
6900
6358
u32 val32;
6901
6359
int ret;
6902
6360
6903
-
if (RTW89_CHK_FW_FEATURE(RFK_PRE_NOTIFY_V1, &rtwdev->fw)) {
6361
+
if (RTW89_CHK_FW_FEATURE(RFK_PRE_NOTIFY_V3, &rtwdev->fw)) {
6362
+
} else if (RTW89_CHK_FW_FEATURE(RFK_PRE_NOTIFY_V2, &rtwdev->fw)) {
6363
+
len = sizeof(*h2c_v2);
6364
+
ver = 2;
6365
+
} else if (RTW89_CHK_FW_FEATURE(RFK_PRE_NOTIFY_V1, &rtwdev->fw)) {
6904
6366
len = sizeof(*h2c_v1);
6905
6367
ver = 1;
6906
6368
} else if (RTW89_CHK_FW_FEATURE(RFK_PRE_NOTIFY_V0, &rtwdev->fw)) {
···
6918
6372
return -ENOMEM;
6919
6373
}
6920
6374
skb_put(skb, len);
6375
+
6376
+
if (ver <= 2)
6377
+
goto old_format;
6378
+
6921
6379
h2c = (struct rtw89_fw_h2c_rfk_pre_info *)skb->data;
6922
-
common = &h2c->base_v1.common;
6380
+
6381
+
h2c->mlo_mode = cpu_to_le32(rtwdev->mlo_dbcc_mode);
6382
+
h2c->phy_idx = cpu_to_le32(phy_idx);
6383
+
h2c->mlo_1_1 = cpu_to_le32(rtw89_is_mlo_1_1(rtwdev));
6384
+
6385
+
goto done;
6386
+
6387
+
old_format:
6388
+
h2c_v2 = (struct rtw89_fw_h2c_rfk_pre_info_v2 *)skb->data;
6389
+
common = &h2c_v2->base_v1.common;
6923
6390
6924
6391
common->mlo_mode = cpu_to_le32(rtwdev->mlo_dbcc_mode);
6925
6392
···
6959
6400
if (ver <= 1)
6960
6401
continue;
6961
6402
6962
-
h2c->cur_bandwidth[path] =
6403
+
h2c_v2->cur_bandwidth[path] =
6963
6404
cpu_to_le32(rfk_mcc->data[path].bw[tbl_sel[path]]);
6964
6405
}
6965
6406
···
6990
6431
}
6991
6432
6992
6433
if (rtw89_is_mlo_1_1(rtwdev)) {
6993
-
h2c_v1 = &h2c->base_v1;
6434
+
h2c_v1 = &h2c_v2->base_v1;
6994
6435
h2c_v1->mlo_1_1 = cpu_to_le32(1);
6995
6436
}
6996
6437
done:
···
6998
6439
H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RF_FW_RFK,
6999
6440
H2C_FUNC_RFK_PRE_NOTIFY, 0, 0,
7000
6441
len);
6442
+
6443
+
ret = rtw89_h2c_tx(rtwdev, skb, false);
6444
+
if (ret) {
6445
+
rtw89_err(rtwdev, "failed to send h2c\n");
6446
+
goto fail;
6447
+
}
6448
+
6449
+
return 0;
6450
+
fail:
6451
+
dev_kfree_skb_any(skb);
6452
+
6453
+
return ret;
6454
+
}
6455
+
6456
+
int rtw89_fw_h2c_rf_pre_ntfy_mcc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
6457
+
{
6458
+
struct rtw89_rfk_mcc_info_data *rfk_mcc = rtwdev->rfk_mcc.data;
6459
+
struct rtw89_rfk_mcc_info *rfk_mcc_v0 = &rtwdev->rfk_mcc;
6460
+
struct rtw89_fw_h2c_rfk_pre_info_mcc_v0 *h2c_v0;
6461
+
struct rtw89_fw_h2c_rfk_pre_info_mcc_v1 *h2c_v1;
6462
+
struct rtw89_fw_h2c_rfk_pre_info_mcc *h2c;
6463
+
struct rtw89_hal *hal = &rtwdev->hal;
6464
+
u32 len = sizeof(*h2c);
6465
+
struct sk_buff *skb;
6466
+
u8 ver = U8_MAX;
6467
+
u8 tbl, path;
6468
+
u8 tbl_sel;
6469
+
int ret;
6470
+
6471
+
if (RTW89_CHK_FW_FEATURE(RFK_PRE_NOTIFY_MCC_V2, &rtwdev->fw)) {
6472
+
} else if (RTW89_CHK_FW_FEATURE(RFK_PRE_NOTIFY_MCC_V1, &rtwdev->fw)) {
6473
+
len = sizeof(*h2c_v1);
6474
+
ver = 1;
6475
+
} else if (RTW89_CHK_FW_FEATURE(RFK_PRE_NOTIFY_MCC_V0, &rtwdev->fw)) {
6476
+
len = sizeof(*h2c_v0);
6477
+
ver = 0;
6478
+
}
6479
+
6480
+
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
6481
+
if (!skb) {
6482
+
rtw89_err(rtwdev, "failed to alloc skb for h2c rfk_pre_ntfy_mcc\n");
6483
+
return -ENOMEM;
6484
+
}
6485
+
skb_put(skb, len);
6486
+
6487
+
if (ver != 0)
6488
+
goto v1;
6489
+
6490
+
h2c_v0 = (struct rtw89_fw_h2c_rfk_pre_info_mcc_v0 *)skb->data;
6491
+
for (tbl = 0; tbl < NUM_OF_RTW89_FW_RFK_TBL; tbl++) {
6492
+
for (path = 0; path < NUM_OF_RTW89_FW_RFK_PATH; path++) {
6493
+
h2c_v0->tbl_18[tbl][path] =
6494
+
cpu_to_le32(rfk_mcc_v0->data[path].rf18[tbl]);
6495
+
tbl_sel = rfk_mcc_v0->data[path].table_idx;
6496
+
h2c_v0->cur_18[path] =
6497
+
cpu_to_le32(rfk_mcc_v0->data[path].rf18[tbl_sel]);
6498
+
}
6499
+
}
6500
+
6501
+
h2c_v0->mlo_mode = cpu_to_le32(rtwdev->mlo_dbcc_mode);
6502
+
goto done;
6503
+
6504
+
v1:
6505
+
h2c_v1 = (struct rtw89_fw_h2c_rfk_pre_info_mcc_v1 *)skb->data;
6506
+
6507
+
BUILD_BUG_ON(NUM_OF_RTW89_FW_RFK_TBL > RTW89_RFK_CHS_NR);
6508
+
6509
+
for (tbl = 0; tbl < NUM_OF_RTW89_FW_RFK_TBL; tbl++)
6510
+
h2c_v1->tbl_18[tbl] = cpu_to_le32(rfk_mcc->rf18[tbl]);
6511
+
6512
+
BUILD_BUG_ON(ARRAY_SIZE(rtwdev->rfk_mcc.data) < NUM_OF_RTW89_FW_RFK_PATH);
6513
+
6514
+
/* shared table array, but tbl_sel can be independent by path */
6515
+
for (path = 0; path < NUM_OF_RTW89_FW_RFK_PATH; path++) {
6516
+
tbl = rfk_mcc[path].table_idx;
6517
+
h2c_v1->cur_18[path] = cpu_to_le32(rfk_mcc->rf18[tbl]);
6518
+
6519
+
if (path == phy_idx)
6520
+
h2c_v1->tbl_idx = tbl;
6521
+
}
6522
+
6523
+
h2c_v1->mlo_mode = cpu_to_le32(rtwdev->mlo_dbcc_mode);
6524
+
h2c_v1->phy_idx = phy_idx;
6525
+
6526
+
if (rtw89_is_mlo_1_1(rtwdev))
6527
+
h2c_v1->mlo_1_1 = cpu_to_le32(1);
6528
+
6529
+
if (ver == 1)
6530
+
goto done;
6531
+
6532
+
h2c = (struct rtw89_fw_h2c_rfk_pre_info_mcc *)skb->data;
6533
+
6534
+
h2c->aid = cpu_to_le32(hal->aid);
6535
+
6536
+
done:
6537
+
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
6538
+
H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RF_FW_NOTIFY,
6539
+
H2C_FUNC_OUTSRC_RF_MCC_INFO, 0, 0, len);
7001
6540
7002
6541
ret = rtw89_h2c_tx(rtwdev, skb, false);
7003
6542
if (ret) {
···
7701
7044
else
7702
7045
timeout = RTW89_C2H_TIMEOUT;
7703
7046
7047
+
if (info->timeout)
7048
+
timeout = info->timeout;
7049
+
7704
7050
ret = read_poll_timeout_atomic(rtw89_read8, val, val, 1,
7705
7051
timeout, false, rtwdev,
7706
7052
chip->c2h_ctrl_reg);
···
8044
7384
struct cfg80211_scan_request *req = rtwvif->scan_req;
8045
7385
struct rtw89_chan *op = &rtwdev->scan_info.op_chan;
8046
7386
struct rtw89_pktofld_info *info;
7387
+
struct ieee80211_vif *vif;
8047
7388
u8 band, probe_count = 0;
8048
7389
int ret;
8049
7390
···
8097
7436
ch_info->pri_ch = op->primary_channel;
8098
7437
ch_info->ch_band = op->band_type;
8099
7438
ch_info->bw = op->band_width;
8100
-
ch_info->tx_null = true;
7439
+
vif = rtwvif_link_to_vif(rtwvif_link);
7440
+
ch_info->tx_null = !is_zero_ether_addr(rtwvif_link->bssid) &&
7441
+
vif->type != NL80211_IFTYPE_AP;
8101
7442
ch_info->num_pkt = 0;
8102
7443
break;
8103
7444
case RTW89_CHAN_DFS:
···
8117
7454
ch_info->pri_ch = ext->chan.primary_channel;
8118
7455
ch_info->ch_band = ext->chan.band_type;
8119
7456
ch_info->bw = ext->chan.band_width;
8120
-
ch_info->tx_null = true;
7457
+
vif = rtwvif_link_to_vif(ext->rtwvif_link);
7458
+
ch_info->tx_null = !is_zero_ether_addr(ext->rtwvif_link->bssid) &&
7459
+
vif->type != NL80211_IFTYPE_AP;
8121
7460
ch_info->num_pkt = 0;
8122
7461
ch_info->macid_tx = true;
8123
7462
break;
···
9370
8705
return ret;
9371
8706
}
9372
8707
9373
-
#define H2C_WOW_CAM_UPD_LEN 24
9374
-
int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
9375
-
struct rtw89_wow_cam_info *cam_info)
8708
+
int rtw89_fw_h2c_wow_cam_update(struct rtw89_dev *rtwdev,
8709
+
struct rtw89_wow_cam_info *cam_info)
9376
8710
{
8711
+
struct rtw89_h2c_wow_cam_update *h2c;
8712
+
u32 len = sizeof(*h2c);
9377
8713
struct sk_buff *skb;
9378
8714
int ret;
9379
8715
9380
-
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, H2C_WOW_CAM_UPD_LEN);
8716
+
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
9381
8717
if (!skb) {
9382
-
rtw89_err(rtwdev, "failed to alloc skb for keep alive\n");
8718
+
rtw89_err(rtwdev, "failed to alloc skb for wow cam update\n");
9383
8719
return -ENOMEM;
9384
8720
}
8721
+
skb_put(skb, len);
8722
+
h2c = (struct rtw89_h2c_wow_cam_update *)skb->data;
9385
8723
9386
-
skb_put(skb, H2C_WOW_CAM_UPD_LEN);
8724
+
h2c->w0 = le32_encode_bits(cam_info->r_w, RTW89_H2C_WOW_CAM_UPD_W0_R_W) |
8725
+
le32_encode_bits(cam_info->idx, RTW89_H2C_WOW_CAM_UPD_W0_IDX);
9387
8726
9388
-
RTW89_SET_WOW_CAM_UPD_R_W(skb->data, cam_info->r_w);
9389
-
RTW89_SET_WOW_CAM_UPD_IDX(skb->data, cam_info->idx);
9390
-
if (cam_info->valid) {
9391
-
RTW89_SET_WOW_CAM_UPD_WKFM1(skb->data, cam_info->mask[0]);
9392
-
RTW89_SET_WOW_CAM_UPD_WKFM2(skb->data, cam_info->mask[1]);
9393
-
RTW89_SET_WOW_CAM_UPD_WKFM3(skb->data, cam_info->mask[2]);
9394
-
RTW89_SET_WOW_CAM_UPD_WKFM4(skb->data, cam_info->mask[3]);
9395
-
RTW89_SET_WOW_CAM_UPD_CRC(skb->data, cam_info->crc);
9396
-
RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(skb->data,
9397
-
cam_info->negative_pattern_match);
9398
-
RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(skb->data,
9399
-
cam_info->skip_mac_hdr);
9400
-
RTW89_SET_WOW_CAM_UPD_UC(skb->data, cam_info->uc);
9401
-
RTW89_SET_WOW_CAM_UPD_MC(skb->data, cam_info->mc);
9402
-
RTW89_SET_WOW_CAM_UPD_BC(skb->data, cam_info->bc);
9403
-
}
9404
-
RTW89_SET_WOW_CAM_UPD_VALID(skb->data, cam_info->valid);
8727
+
if (!cam_info->valid)
8728
+
goto fill_valid;
8729
+
8730
+
h2c->wkfm0 = cam_info->mask[0];
8731
+
h2c->wkfm1 = cam_info->mask[1];
8732
+
h2c->wkfm2 = cam_info->mask[2];
8733
+
h2c->wkfm3 = cam_info->mask[3];
8734
+
h2c->w5 = le32_encode_bits(cam_info->crc, RTW89_H2C_WOW_CAM_UPD_W5_CRC) |
8735
+
le32_encode_bits(cam_info->negative_pattern_match,
8736
+
RTW89_H2C_WOW_CAM_UPD_W5_NEGATIVE_PATTERN_MATCH) |
8737
+
le32_encode_bits(cam_info->skip_mac_hdr,
8738
+
RTW89_H2C_WOW_CAM_UPD_W5_SKIP_MAC_HDR) |
8739
+
le32_encode_bits(cam_info->uc, RTW89_H2C_WOW_CAM_UPD_W5_UC) |
8740
+
le32_encode_bits(cam_info->mc, RTW89_H2C_WOW_CAM_UPD_W5_MC) |
8741
+
le32_encode_bits(cam_info->bc, RTW89_H2C_WOW_CAM_UPD_W5_BC);
8742
+
fill_valid:
8743
+
h2c->w5 |= le32_encode_bits(cam_info->valid, RTW89_H2C_WOW_CAM_UPD_W5_VALID);
9405
8744
9406
8745
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
9407
8746
H2C_CAT_MAC,
9408
8747
H2C_CL_MAC_WOW,
9409
8748
H2C_FUNC_WOW_CAM_UPD, 0, 1,
9410
-
H2C_WOW_CAM_UPD_LEN);
8749
+
len);
9411
8750
9412
8751
ret = rtw89_h2c_tx(rtwdev, skb, false);
9413
8752
if (ret) {
···
9425
8756
9426
8757
return ret;
9427
8758
}
8759
+
EXPORT_SYMBOL(rtw89_fw_h2c_wow_cam_update);
8760
+
8761
+
int rtw89_fw_h2c_wow_cam_update_v1(struct rtw89_dev *rtwdev,
8762
+
struct rtw89_wow_cam_info *cam_info)
8763
+
{
8764
+
struct rtw89_h2c_wow_payload_cam_update *h2c;
8765
+
u32 len = sizeof(*h2c);
8766
+
struct sk_buff *skb;
8767
+
int ret;
8768
+
8769
+
skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
8770
+
if (!skb) {
8771
+
rtw89_err(rtwdev, "failed to alloc skb for wow payload cam update\n");
8772
+
return -ENOMEM;
8773
+
}
8774
+
skb_put(skb, len);
8775
+
h2c = (struct rtw89_h2c_wow_payload_cam_update *)skb->data;
8776
+
8777
+
h2c->w0 = le32_encode_bits(cam_info->r_w, RTW89_H2C_WOW_PLD_CAM_UPD_W0_R_W) |
8778
+
le32_encode_bits(cam_info->idx, RTW89_H2C_WOW_PLD_CAM_UPD_W0_IDX);
8779
+
h2c->w8 = le32_encode_bits(cam_info->valid, RTW89_H2C_WOW_PLD_CAM_UPD_W8_VALID) |
8780
+
le32_encode_bits(1, RTW89_H2C_WOW_PLD_CAM_UPD_W8_WOW_PTR);
8781
+
8782
+
if (!cam_info->valid)
8783
+
goto done;
8784
+
8785
+
h2c->wkfm0 = cam_info->mask[0];
8786
+
h2c->wkfm1 = cam_info->mask[1];
8787
+
h2c->wkfm2 = cam_info->mask[2];
8788
+
h2c->wkfm3 = cam_info->mask[3];
8789
+
h2c->w5 = le32_encode_bits(cam_info->uc, RTW89_H2C_WOW_PLD_CAM_UPD_W5_UC) |
8790
+
le32_encode_bits(cam_info->mc, RTW89_H2C_WOW_PLD_CAM_UPD_W5_MC) |
8791
+
le32_encode_bits(cam_info->bc, RTW89_H2C_WOW_PLD_CAM_UPD_W5_BC) |
8792
+
le32_encode_bits(cam_info->skip_mac_hdr,
8793
+
RTW89_H2C_WOW_PLD_CAM_UPD_W5_SKIP_MAC_HDR);
8794
+
h2c->w6 = le32_encode_bits(cam_info->crc, RTW89_H2C_WOW_PLD_CAM_UPD_W6_CRC);
8795
+
h2c->w7 = le32_encode_bits(cam_info->negative_pattern_match,
8796
+
RTW89_H2C_WOW_PLD_CAM_UPD_W7_NEGATIVE_PATTERN_MATCH);
8797
+
8798
+
done:
8799
+
rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
8800
+
H2C_CAT_MAC,
8801
+
H2C_CL_MAC_WOW,
8802
+
H2C_FUNC_WOW_PLD_CAM_UPD, 0, 1,
8803
+
len);
8804
+
8805
+
ret = rtw89_h2c_tx(rtwdev, skb, false);
8806
+
if (ret) {
8807
+
rtw89_err(rtwdev, "failed to send h2c\n");
8808
+
goto fail;
8809
+
}
8810
+
8811
+
return 0;
8812
+
fail:
8813
+
dev_kfree_skb_any(skb);
8814
+
8815
+
return ret;
8816
+
}
8817
+
EXPORT_SYMBOL(rtw89_fw_h2c_wow_cam_update_v1);
9428
8818
9429
8819
int rtw89_fw_h2c_wow_gtk_ofld(struct rtw89_dev *rtwdev,
9430
8820
struct rtw89_vif_link *rtwvif_link,
+266
-65
drivers/net/wireless/realtek/rtw89/fw.h
+266
-65
drivers/net/wireless/realtek/rtw89/fw.h
···
42
42
#define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
43
43
#define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)
44
44
#define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8)
45
+
#define RTW89_C2HREG_PHYCAP_W1_PROT_11N 1
46
+
#define RTW89_C2HREG_PHYCAP_W1_PROT_11AC 2
47
+
#define RTW89_C2HREG_PHYCAP_W1_PROT_11AX 3
48
+
#define RTW89_C2HREG_PHYCAP_W1_PROT_11BE 4
45
49
#define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16)
46
50
#define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)
47
51
#define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0)
···
124
120
struct rtw89_mac_c2h_info {
125
121
u8 id;
126
122
u8 content_len;
123
+
u32 timeout;
127
124
union {
128
125
u32 c2hreg[RTW89_C2HREG_MAX];
129
126
struct rtw89_c2hreg_hdr hdr;
···
1522
1517
#define CCTLINFO_G7_W15_MGNT_CURR_RATE GENMASK(27, 16)
1523
1518
#define CCTLINFO_G7_W15_ALL GENMASK(27, 0)
1524
1519
1520
+
struct rtw89_h2c_cctlinfo_ud_be {
1521
+
__le32 c0;
1522
+
__le32 w0;
1523
+
__le32 w1;
1524
+
__le32 w2;
1525
+
__le32 w3;
1526
+
__le32 w4;
1527
+
__le32 w5;
1528
+
__le32 w6;
1529
+
__le32 w7;
1530
+
__le32 w8;
1531
+
__le32 w9;
1532
+
__le32 w10;
1533
+
__le32 w11;
1534
+
__le32 w12;
1535
+
__le32 w13;
1536
+
__le32 w14;
1537
+
__le32 w15;
1538
+
__le32 m0;
1539
+
__le32 m1;
1540
+
__le32 m2;
1541
+
__le32 m3;
1542
+
__le32 m4;
1543
+
__le32 m5;
1544
+
__le32 m6;
1545
+
__le32 m7;
1546
+
__le32 m8;
1547
+
__le32 m9;
1548
+
__le32 m10;
1549
+
__le32 m11;
1550
+
__le32 m12;
1551
+
__le32 m13;
1552
+
__le32 m14;
1553
+
__le32 m15;
1554
+
} __packed;
1555
+
1556
+
#define BE_CCTL_INFO_C0_V1_MACID GENMASK(9, 0)
1557
+
#define BE_CCTL_INFO_C0_V1_OP BIT(10)
1558
+
1559
+
#define BE_CCTL_INFO_W0_DATARATE GENMASK(11, 0)
1560
+
#define BE_CCTL_INFO_W0_DATA_GI_LTF GENMASK(14, 12)
1561
+
#define BE_CCTL_INFO_W0_TRYRATE BIT(15)
1562
+
#define BE_CCTL_INFO_W0_ARFR_CTRL GENMASK(17, 16)
1563
+
#define BE_CCTL_INFO_W0_DIS_HE1SS_STBC BIT(18)
1564
+
#define BE_CCTL_INFO_W0_ACQ_RPT_EN BIT(20)
1565
+
#define BE_CCTL_INFO_W0_MGQ_RPT_EN BIT(21)
1566
+
#define BE_CCTL_INFO_W0_ULQ_RPT_EN BIT(22)
1567
+
#define BE_CCTL_INFO_W0_TWTQ_RPT_EN BIT(23)
1568
+
#define BE_CCTL_INFO_W0_FORCE_TXOP BIT(24)
1569
+
#define BE_CCTL_INFO_W0_DISRTSFB BIT(25)
1570
+
#define BE_CCTL_INFO_W0_DISDATAFB BIT(26)
1571
+
#define BE_CCTL_INFO_W0_NSTR_EN BIT(27)
1572
+
#define BE_CCTL_INFO_W0_AMPDU_DENSITY GENMASK(31, 28)
1573
+
#define BE_CCTL_INFO_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0))
1574
+
#define BE_CCTL_INFO_W1_DATA_RTY_LOWEST_RATE GENMASK(11, 0)
1575
+
#define BE_CCTL_INFO_W1_RTS_TXCNT_LMT GENMASK(15, 12)
1576
+
#define BE_CCTL_INFO_W1_RTSRATE GENMASK(27, 16)
1577
+
#define BE_CCTL_INFO_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28)
1578
+
#define BE_CCTL_INFO_W1_ALL GENMASK(31, 0)
1579
+
#define BE_CCTL_INFO_W2_DATA_TX_CNT_LMT GENMASK(5, 0)
1580
+
#define BE_CCTL_INFO_W2_DATA_TXCNT_LMT_SEL BIT(6)
1581
+
#define BE_CCTL_INFO_W2_MAX_AGG_NUM_SEL BIT(7)
1582
+
#define BE_CCTL_INFO_W2_RTS_EN BIT(8)
1583
+
#define BE_CCTL_INFO_W2_CTS2SELF_EN BIT(9)
1584
+
#define BE_CCTL_INFO_W2_CCA_RTS GENMASK(11, 10)
1585
+
#define BE_CCTL_INFO_W2_HW_RTS_EN BIT(12)
1586
+
#define BE_CCTL_INFO_W2_RTS_DROP_DATA_MODE GENMASK(14, 13)
1587
+
#define BE_CCTL_INFO_W2_PRELOAD_ENABLE BIT(15)
1588
+
#define BE_CCTL_INFO_W2_AMPDU_MAX_LEN GENMASK(26, 16)
1589
+
#define BE_CCTL_INFO_W2_UL_MU_DIS BIT(27)
1590
+
#define BE_CCTL_INFO_W2_AMPDU_MAX_TIME GENMASK(31, 28)
1591
+
#define BE_CCTL_INFO_W2_ALL GENMASK(31, 0)
1592
+
#define BE_CCTL_INFO_W3_MAX_AGG_NUM GENMASK(7, 0)
1593
+
#define BE_CCTL_INFO_W3_DATA_BW GENMASK(10, 8)
1594
+
#define BE_CCTL_INFO_W3_DATA_BW_ER BIT(11)
1595
+
#define BE_CCTL_INFO_W3_BA_BMAP GENMASK(14, 12)
1596
+
#define BE_CCTL_INFO_W3_VCS_STBC BIT(15)
1597
+
#define BE_CCTL_INFO_W3_VO_LFTIME_SEL GENMASK(18, 16)
1598
+
#define BE_CCTL_INFO_W3_VI_LFTIME_SEL GENMASK(21, 19)
1599
+
#define BE_CCTL_INFO_W3_BE_LFTIME_SEL GENMASK(24, 22)
1600
+
#define BE_CCTL_INFO_W3_BK_LFTIME_SEL GENMASK(27, 25)
1601
+
#define BE_CCTL_INFO_W3_AMPDU_TIME_SEL BIT(28)
1602
+
#define BE_CCTL_INFO_W3_AMPDU_LEN_SEL BIT(29)
1603
+
#define BE_CCTL_INFO_W3_RTS_TXCNT_LMT_SEL BIT(30)
1604
+
#define BE_CCTL_INFO_W3_LSIG_TXOP_EN BIT(31)
1605
+
#define BE_CCTL_INFO_W3_ALL GENMASK(31, 0)
1606
+
#define BE_CCTL_INFO_W4_MULTI_PORT_ID GENMASK(2, 0)
1607
+
#define BE_CCTL_INFO_W4_BYPASS_PUNC BIT(3)
1608
+
#define BE_CCTL_INFO_W4_MBSSID GENMASK(7, 4)
1609
+
#define BE_CCTL_INFO_W4_TID_DISABLE_V1 GENMASK(15, 8)
1610
+
#define BE_CCTL_INFO_W4_ACT_SUBCH_CBW GENMASK(31, 16)
1611
+
#define BE_CCTL_INFO_W4_ALL GENMASK(31, 0)
1612
+
#define BE_CCTL_INFO_W5_ADDR_CAM_INDEX_V1 GENMASK(9, 0)
1613
+
#define BE_CCTL_INFO_W5_SR_MCS_SU GENMASK(14, 10)
1614
+
#define BE_CCTL_INFO_W5_A_CTRL_BQR_V1 BIT(15)
1615
+
#define BE_CCTL_INFO_W5_A_CTRL_BSR_V1 BIT(16)
1616
+
#define BE_CCTL_INFO_W5_A_CTRL_CAS_V1 BIT(17)
1617
+
#define BE_CCTL_INFO_W5_DATA_ER_V1 BIT(18)
1618
+
#define BE_CCTL_INFO_W5_DATA_DCM_V1 BIT(19)
1619
+
#define BE_CCTL_INFO_W5_DATA_LDPC_V1 BIT(20)
1620
+
#define BE_CCTL_INFO_W5_DATA_STBC_V1 BIT(21)
1621
+
#define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING0_V1 GENMASK(23, 22)
1622
+
#define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING1_V1 GENMASK(25, 24)
1623
+
#define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING2_V1 GENMASK(27, 26)
1624
+
#define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING3_V1 GENMASK(29, 28)
1625
+
#define BE_CCTL_INFO_W5_NOMINAL_PKT_PADDING4_V1 GENMASK(31, 30)
1626
+
#define BE_CCTL_INFO_W5_ALL GENMASK(31, 0)
1627
+
#define BE_CCTL_INFO_W6_AID12_PAID GENMASK(11, 0)
1628
+
#define BE_CCTL_INFO_W6_RESP_REF_RATE GENMASK(23, 12)
1629
+
#define BE_CCTL_INFO_W6_ULDL BIT(31)
1630
+
#define BE_CCTL_INFO_W6_ALL (BIT(31) | GENMASK(23, 0))
1631
+
#define BE_CCTL_INFO_W7_NC GENMASK(2, 0)
1632
+
#define BE_CCTL_INFO_W7_NR GENMASK(5, 3)
1633
+
#define BE_CCTL_INFO_W7_NG GENMASK(7, 6)
1634
+
#define BE_CCTL_INFO_W7_CB GENMASK(9, 8)
1635
+
#define BE_CCTL_INFO_W7_CS GENMASK(11, 10)
1636
+
#define BE_CCTL_INFO_W7_CSI_STBC_EN BIT(13)
1637
+
#define BE_CCTL_INFO_W7_CSI_LDPC_EN BIT(14)
1638
+
#define BE_CCTL_INFO_W7_CSI_PARA_EN BIT(15)
1639
+
#define BE_CCTL_INFO_W7_CSI_FIX_RATE GENMASK(27, 16)
1640
+
#define BE_CCTL_INFO_W7_CSI_BW GENMASK(31, 29)
1641
+
#define BE_CCTL_INFO_W7_ALL GENMASK(31, 0)
1642
+
#define BE_CCTL_INFO_W8_ALL_ACK_SUPPORT_V1 BIT(0)
1643
+
#define BE_CCTL_INFO_W8_BSR_QUEUE_SIZE_FORMAT_V1 BIT(1)
1644
+
#define BE_CCTL_INFO_W8_BSR_OM_UPD_EN_V1 BIT(2)
1645
+
#define BE_CCTL_INFO_W8_MACID_FWD_IDC_V1 BIT(3)
1646
+
#define BE_CCTL_INFO_W8_AZ_SEC_EN BIT(4)
1647
+
#define BE_CCTL_INFO_W8_BF_SEC_EN BIT(5)
1648
+
#define BE_CCTL_INFO_W8_FIX_UL_ADDRCAM_IDX_V1 BIT(6)
1649
+
#define BE_CCTL_INFO_W8_CTRL_CNT_VLD_V1 BIT(7)
1650
+
#define BE_CCTL_INFO_W8_CTRL_CNT_V1 GENMASK(11, 8)
1651
+
#define BE_CCTL_INFO_W8_RESP_SEC_TYPE GENMASK(15, 12)
1652
+
#define BE_CCTL_INFO_W8_ALL GENMASK(15, 0)
1653
+
#define BE_CCTL_INFO_W9_EMLSR_TRANS_DLY GENMASK(2, 0)
1654
+
#define BE_CCTL_INFO_W9_ALL GENMASK(2, 0)
1655
+
#define BE_CCTL_INFO_W10_SW_EHT_NLTF GENMASK(1, 0)
1656
+
#define BE_CCTL_INFO_W10_TB_MLO_MODE BIT(2)
1657
+
#define BE_CCTL_INFO_W10_ALL GENMASK(2, 0)
1658
+
#define BE_CCTL_INFO_W14_VO_CURR_RATE GENMASK(11, 0)
1659
+
#define BE_CCTL_INFO_W14_VI_CURR_RATE GENMASK(23, 12)
1660
+
#define BE_CCTL_INFO_W14_BE_CURR_RATE_L GENMASK(31, 24)
1661
+
#define BE_CCTL_INFO_W14_ALL GENMASK(31, 0)
1662
+
#define BE_CCTL_INFO_W15_BE_CURR_RATE_H GENMASK(3, 0)
1663
+
#define BE_CCTL_INFO_W15_BK_CURR_RATE GENMASK(15, 4)
1664
+
#define BE_CCTL_INFO_W15_MGNT_CURR_RATE GENMASK(27, 16)
1665
+
#define BE_CCTL_INFO_W15_ALL GENMASK(27, 0)
1666
+
1525
1667
struct rtw89_h2c_bcn_upd {
1526
1668
__le32 w0;
1527
1669
__le32 w1;
···
2204
2052
le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2205
2053
}
2206
2054
2207
-
static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val)
2208
-
{
2209
-
le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2210
-
}
2055
+
struct rtw89_h2c_wow_cam_update {
2056
+
__le32 w0;
2057
+
__le32 wkfm0;
2058
+
__le32 wkfm1;
2059
+
__le32 wkfm2;
2060
+
__le32 wkfm3;
2061
+
__le32 w5;
2062
+
} __packed;
2211
2063
2212
-
static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val)
2213
-
{
2214
-
le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1));
2215
-
}
2064
+
#define RTW89_H2C_WOW_CAM_UPD_W0_R_W BIT(0)
2065
+
#define RTW89_H2C_WOW_CAM_UPD_W0_IDX GENMASK(7, 1)
2066
+
#define RTW89_H2C_WOW_CAM_UPD_WKFM0 GENMASK(31, 0)
2067
+
#define RTW89_H2C_WOW_CAM_UPD_WKFM1 GENMASK(31, 0)
2068
+
#define RTW89_H2C_WOW_CAM_UPD_WKFM2 GENMASK(31, 0)
2069
+
#define RTW89_H2C_WOW_CAM_UPD_WKFM3 GENMASK(31, 0)
2070
+
#define RTW89_H2C_WOW_CAM_UPD_W5_CRC GENMASK(15, 0)
2071
+
#define RTW89_H2C_WOW_CAM_UPD_W5_NEGATIVE_PATTERN_MATCH BIT(22)
2072
+
#define RTW89_H2C_WOW_CAM_UPD_W5_SKIP_MAC_HDR BIT(23)
2073
+
#define RTW89_H2C_WOW_CAM_UPD_W5_UC BIT(24)
2074
+
#define RTW89_H2C_WOW_CAM_UPD_W5_MC BIT(25)
2075
+
#define RTW89_H2C_WOW_CAM_UPD_W5_BC BIT(26)
2076
+
#define RTW89_H2C_WOW_CAM_UPD_W5_VALID BIT(31)
2216
2077
2217
-
static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val)
2218
-
{
2219
-
le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0));
2220
-
}
2078
+
struct rtw89_h2c_wow_payload_cam_update {
2079
+
__le32 w0;
2080
+
__le32 wkfm0;
2081
+
__le32 wkfm1;
2082
+
__le32 wkfm2;
2083
+
__le32 wkfm3;
2084
+
__le32 w5;
2085
+
__le32 w6;
2086
+
__le32 w7;
2087
+
__le32 w8;
2088
+
} __packed;
2221
2089
2222
-
static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val)
2223
-
{
2224
-
le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0));
2225
-
}
2226
-
2227
-
static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val)
2228
-
{
2229
-
le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0));
2230
-
}
2231
-
2232
-
static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val)
2233
-
{
2234
-
le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0));
2235
-
}
2236
-
2237
-
static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val)
2238
-
{
2239
-
le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0));
2240
-
}
2241
-
2242
-
static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val)
2243
-
{
2244
-
le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22));
2245
-
}
2246
-
2247
-
static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val)
2248
-
{
2249
-
le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23));
2250
-
}
2251
-
2252
-
static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val)
2253
-
{
2254
-
le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24));
2255
-
}
2256
-
2257
-
static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val)
2258
-
{
2259
-
le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25));
2260
-
}
2261
-
2262
-
static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val)
2263
-
{
2264
-
le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26));
2265
-
}
2266
-
2267
-
static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val)
2268
-
{
2269
-
le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31));
2270
-
}
2090
+
#define RTW89_H2C_WOW_PLD_CAM_UPD_W0_R_W BIT(0)
2091
+
#define RTW89_H2C_WOW_PLD_CAM_UPD_W0_IDX GENMASK(7, 1)
2092
+
#define RTW89_H2C_WOW_PLD_CAM_UPD_WKFM0 GENMASK(31, 0)
2093
+
#define RTW89_H2C_WOW_PLD_CAM_UPD_WKFM1 GENMASK(31, 0)
2094
+
#define RTW89_H2C_WOW_PLD_CAM_UPD_WKFM2 GENMASK(31, 0)
2095
+
#define RTW89_H2C_WOW_PLD_CAM_UPD_WKFM3 GENMASK(31, 0)
2096
+
#define RTW89_H2C_WOW_PLD_CAM_UPD_W5_UC BIT(0)
2097
+
#define RTW89_H2C_WOW_PLD_CAM_UPD_W5_MC BIT(1)
2098
+
#define RTW89_H2C_WOW_PLD_CAM_UPD_W5_BC BIT(2)
2099
+
#define RTW89_H2C_WOW_PLD_CAM_UPD_W5_SKIP_MAC_HDR BIT(7)
2100
+
#define RTW89_H2C_WOW_PLD_CAM_UPD_W6_CRC GENMASK(15, 0)
2101
+
#define RTW89_H2C_WOW_PLD_CAM_UPD_W7_NEGATIVE_PATTERN_MATCH BIT(0)
2102
+
#define RTW89_H2C_WOW_PLD_CAM_UPD_W8_VALID BIT(0)
2103
+
#define RTW89_H2C_WOW_PLD_CAM_UPD_W8_WOW_PTR BIT(1)
2271
2104
2272
2105
struct rtw89_h2c_wow_gtk_ofld {
2273
2106
__le32 w0;
···
2963
2826
__le32 w0;
2964
2827
} __packed;
2965
2828
2829
+
#define RTW89_MAX_OP_NUM_BE 2
2966
2830
#define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_BAND GENMASK(1, 0)
2967
2831
#define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_PORT GENMASK(4, 2)
2968
2832
#define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_MACID GENMASK(23, 8)
···
4315
4177
__le32 id; /* enum rtw89_fw_element_id */
4316
4178
__le32 size; /* exclude header size */
4317
4179
u8 ver[4];
4318
-
__le32 rsvd0;
4180
+
__le16 aid; /* should match rtw89_hal::aid */
4181
+
__le16 rsvd0;
4319
4182
__le32 rsvd1;
4320
4183
__le32 rsvd2;
4321
4184
union {
···
4446
4307
H2C_FUNC_WAKEUP_CTRL = 0x8,
4447
4308
H2C_FUNC_WOW_CAM_UPD = 0xC,
4448
4309
H2C_FUNC_AOAC_REPORT_REQ = 0xD,
4310
+
H2C_FUNC_WOW_PLD_CAM_UPD = 0x12,
4449
4311
4450
4312
NUM_OF_RTW89_WOW_H2C_FUNC,
4451
4313
};
···
4487
4347
#define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa
4488
4348
#define H2C_FUNC_MAC_DCTLINFO_UD_V2 0xc
4489
4349
#define H2C_FUNC_MAC_BCN_UPD_BE 0xd
4350
+
#define H2C_FUNC_MAC_DCTLINFO_UD_V3 0x10
4490
4351
#define H2C_FUNC_MAC_CCTLINFO_UD_G7 0x11
4491
4352
4492
4353
/* CLASS 6 - Address CAM */
···
4624
4483
#define H2C_CL_OUTSRC_RF_REG_B 0x9
4625
4484
#define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa
4626
4485
#define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2
4486
+
#define H2C_FUNC_OUTSRC_RF_MCC_INFO 0xf
4627
4487
#define H2C_FUNC_OUTSRC_RF_PS_INFO 0x10
4628
4488
#define H2C_CL_OUTSRC_RF_FW_RFK 0xb
4629
4489
···
4728
4586
__le32 mlo_1_1;
4729
4587
} __packed;
4730
4588
4731
-
struct rtw89_fw_h2c_rfk_pre_info {
4589
+
struct rtw89_fw_h2c_rfk_pre_info_v2 {
4732
4590
struct rtw89_fw_h2c_rfk_pre_info_v1 base_v1;
4733
4591
__le32 cur_bandwidth[NUM_OF_RTW89_FW_RFK_PATH];
4592
+
} __packed;
4593
+
4594
+
struct rtw89_fw_h2c_rfk_pre_info {
4595
+
__le32 mlo_mode;
4596
+
__le32 phy_idx;
4597
+
__le32 mlo_1_1;
4598
+
} __packed;
4599
+
4600
+
struct rtw89_fw_h2c_rfk_pre_info_mcc_v0 {
4601
+
__le32 tbl_18[NUM_OF_RTW89_FW_RFK_TBL][NUM_OF_RTW89_FW_RFK_PATH];
4602
+
__le32 cur_18[NUM_OF_RTW89_FW_RFK_PATH];
4603
+
__le32 mlo_mode;
4604
+
} __packed;
4605
+
4606
+
struct rtw89_fw_h2c_rfk_pre_info_mcc_v1 {
4607
+
__le32 tbl_18[NUM_OF_RTW89_FW_RFK_TBL];
4608
+
__le32 cur_18[NUM_OF_RTW89_FW_RFK_PATH];
4609
+
__le32 mlo_mode;
4610
+
__le32 mlo_1_1;
4611
+
u8 phy_idx;
4612
+
u8 tbl_idx;
4613
+
} __packed;
4614
+
4615
+
struct rtw89_fw_h2c_rfk_pre_info_mcc {
4616
+
struct rtw89_fw_h2c_rfk_pre_info_mcc_v1 base;
4617
+
u8 rsvd[2];
4618
+
__le32 aid;
4734
4619
} __packed;
4735
4620
4736
4621
struct rtw89_h2c_rf_tssi {
···
5027
4858
int rtw89_fw_h2c_default_cmac_tbl_g7(struct rtw89_dev *rtwdev,
5028
4859
struct rtw89_vif_link *rtwvif_link,
5029
4860
struct rtw89_sta_link *rtwsta_link);
4861
+
int rtw89_fw_h2c_default_cmac_tbl_be(struct rtw89_dev *rtwdev,
4862
+
struct rtw89_vif_link *rtwvif_link,
4863
+
struct rtw89_sta_link *rtwsta_link);
5030
4864
int rtw89_fw_h2c_default_dmac_tbl_v2(struct rtw89_dev *rtwdev,
4865
+
struct rtw89_vif_link *rtwvif_link,
4866
+
struct rtw89_sta_link *rtwsta_link);
4867
+
int rtw89_fw_h2c_default_dmac_tbl_v3(struct rtw89_dev *rtwdev,
5031
4868
struct rtw89_vif_link *rtwvif_link,
5032
4869
struct rtw89_sta_link *rtwsta_link);
5033
4870
int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
···
5042
4867
int rtw89_fw_h2c_assoc_cmac_tbl_g7(struct rtw89_dev *rtwdev,
5043
4868
struct rtw89_vif_link *rtwvif_link,
5044
4869
struct rtw89_sta_link *rtwsta_link);
4870
+
int rtw89_fw_h2c_assoc_cmac_tbl_be(struct rtw89_dev *rtwdev,
4871
+
struct rtw89_vif_link *rtwvif_link,
4872
+
struct rtw89_sta_link *rtwsta_link);
5045
4873
int rtw89_fw_h2c_ampdu_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4874
+
struct rtw89_vif_link *rtwvif_link,
4875
+
struct rtw89_sta_link *rtwsta_link);
4876
+
int rtw89_fw_h2c_ampdu_cmac_tbl_be(struct rtw89_dev *rtwdev,
5046
4877
struct rtw89_vif_link *rtwvif_link,
5047
4878
struct rtw89_sta_link *rtwsta_link);
5048
4879
int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
5049
4880
struct rtw89_sta_link *rtwsta_link);
5050
4881
int rtw89_fw_h2c_txtime_cmac_tbl_g7(struct rtw89_dev *rtwdev,
5051
4882
struct rtw89_sta_link *rtwsta_link);
4883
+
int rtw89_fw_h2c_txtime_cmac_tbl_be(struct rtw89_dev *rtwdev,
4884
+
struct rtw89_sta_link *rtwsta_link);
5052
4885
int rtw89_fw_h2c_punctured_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4886
+
struct rtw89_vif_link *rtwvif_link,
4887
+
u16 punctured);
4888
+
int rtw89_fw_h2c_punctured_cmac_tbl_be(struct rtw89_dev *rtwdev,
5053
4889
struct rtw89_vif_link *rtwvif_link,
5054
4890
u16 punctured);
5055
4891
int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
···
5079
4893
struct rtw89_vif_link *rtwvif_link,
5080
4894
struct rtw89_sta_link *rtwsta_link);
5081
4895
int rtw89_fw_h2c_dctl_sec_cam_v2(struct rtw89_dev *rtwdev,
4896
+
struct rtw89_vif_link *rtwvif_link,
4897
+
struct rtw89_sta_link *rtwsta_link);
4898
+
int rtw89_fw_h2c_dctl_sec_cam_v3(struct rtw89_dev *rtwdev,
5082
4899
struct rtw89_vif_link *rtwvif_link,
5083
4900
struct rtw89_sta_link *rtwsta_link);
5084
4901
void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h);
···
5137
4948
int rtw89_fw_h2c_rf_ps_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
5138
4949
int rtw89_fw_h2c_rf_pre_ntfy(struct rtw89_dev *rtwdev,
5139
4950
enum rtw89_phy_idx phy_idx);
4951
+
int rtw89_fw_h2c_rf_pre_ntfy_mcc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
5140
4952
int rtw89_fw_h2c_mcc_dig(struct rtw89_dev *rtwdev,
5141
4953
enum rtw89_chanctx_idx chanctx_idx,
5142
4954
u8 mcc_role_idx, u8 pd_val, bool en);
···
5244
5054
bool enable);
5245
5055
int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
5246
5056
struct rtw89_vif_link *rtwvif_link, bool enable);
5247
-
int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
5248
-
struct rtw89_wow_cam_info *cam_info);
5057
+
int rtw89_fw_h2c_wow_cam_update(struct rtw89_dev *rtwdev,
5058
+
struct rtw89_wow_cam_info *cam_info);
5059
+
int rtw89_fw_h2c_wow_cam_update_v1(struct rtw89_dev *rtwdev,
5060
+
struct rtw89_wow_cam_info *cam_info);
5249
5061
int rtw89_fw_h2c_wow_gtk_ofld(struct rtw89_dev *rtwdev,
5250
5062
struct rtw89_vif_link *rtwvif_link,
5251
5063
bool enable);
···
5409
5217
}
5410
5218
5411
5219
return 0;
5220
+
}
5221
+
5222
+
static inline
5223
+
int rtw89_chip_h2c_wow_cam_update(struct rtw89_dev *rtwdev,
5224
+
struct rtw89_wow_cam_info *cam_info)
5225
+
{
5226
+
const struct rtw89_chip_info *chip = rtwdev->chip;
5227
+
5228
+
return chip->ops->h2c_wow_cam_update(rtwdev, cam_info);
5412
5229
}
5413
5230
5414
5231
/* Must consider compatibility; don't insert new in the mid.
+150
-26
drivers/net/wireless/realtek/rtw89/mac.c
+150
-26
drivers/net/wireless/realtek/rtw89/mac.c
···
848
848
int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err)
849
849
{
850
850
struct rtw89_ser *ser = &rtwdev->ser;
851
+
bool ser_l1_hdl = false;
851
852
u32 halt;
852
853
int ret = 0;
853
854
···
857
856
return -EINVAL;
858
857
}
859
858
859
+
if (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN)
860
+
ser_l1_hdl = true;
861
+
862
+
if (RTW89_CHK_FW_FEATURE(SER_L1_BY_EVENT, &rtwdev->fw) && ser_l1_hdl)
863
+
goto set;
864
+
860
865
ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000,
861
866
100000, false, rtwdev, R_AX_HALT_H2C_CTRL);
862
867
if (ret) {
···
870
863
return -EFAULT;
871
864
}
872
865
866
+
set:
873
867
rtw89_write32(rtwdev, R_AX_HALT_H2C, err);
874
868
875
-
if (ser->prehandle_l1 &&
876
-
(err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN))
869
+
if (ser->prehandle_l1 && ser_l1_hdl)
877
870
return 0;
878
871
879
872
rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER);
···
1483
1476
rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST);
1484
1477
}
1485
1478
1479
+
static int rtw89_mac_pwr_off_func_for_unplugged(struct rtw89_dev *rtwdev)
1480
+
{
1481
+
/*
1482
+
* Avoid accessing IO for unplugged power-off to prevent warnings,
1483
+
* especially XTAL SI.
1484
+
*/
1485
+
return 0;
1486
+
}
1487
+
1488
+
static void rtw89_mac_update_scoreboard(struct rtw89_dev *rtwdev, u8 val)
1489
+
{
1490
+
const struct rtw89_chip_info *chip = rtwdev->chip;
1491
+
u32 reg;
1492
+
int i;
1493
+
1494
+
for (i = 0; i < ARRAY_SIZE(chip->btc_sb.n); i++) {
1495
+
reg = chip->btc_sb.n[i].cfg;
1496
+
if (!reg)
1497
+
continue;
1498
+
1499
+
rtw89_write8(rtwdev, reg + 3, val);
1500
+
}
1501
+
}
1502
+
1486
1503
static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on)
1487
1504
{
1488
-
#define PWR_ACT 1
1489
1505
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1490
1506
const struct rtw89_chip_info *chip = rtwdev->chip;
1491
1507
const struct rtw89_pwr_cfg * const *cfg_seq;
1492
1508
int (*cfg_func)(struct rtw89_dev *rtwdev);
1493
1509
int ret;
1494
-
u8 val;
1495
1510
1496
1511
rtw89_mac_power_switch_boot_mode(rtwdev);
1497
1512
···
1521
1492
cfg_seq = chip->pwr_on_seq;
1522
1493
cfg_func = chip->ops->pwr_on_func;
1523
1494
} else {
1524
-
cfg_seq = chip->pwr_off_seq;
1525
-
cfg_func = chip->ops->pwr_off_func;
1495
+
if (test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) {
1496
+
cfg_seq = NULL;
1497
+
cfg_func = rtw89_mac_pwr_off_func_for_unplugged;
1498
+
} else {
1499
+
cfg_seq = chip->pwr_off_seq;
1500
+
cfg_func = chip->ops->pwr_off_func;
1501
+
}
1526
1502
}
1527
1503
1528
1504
if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
1529
1505
__rtw89_leave_ps_mode(rtwdev);
1530
1506
1531
-
val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK);
1532
-
if (on && val == PWR_ACT) {
1533
-
rtw89_err(rtwdev, "MAC has already powered on\n");
1534
-
return -EBUSY;
1507
+
if (on) {
1508
+
ret = mac->reset_pwr_state(rtwdev);
1509
+
if (ret)
1510
+
return ret;
1535
1511
}
1536
1512
1537
1513
ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq);
···
1544
1510
return ret;
1545
1511
1546
1512
if (on) {
1547
-
if (!test_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags))
1513
+
if (!test_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags)) {
1514
+
rtw89_mac_efuse_read_ecv(rtwdev);
1548
1515
mac->efuse_read_fw_secure(rtwdev);
1516
+
}
1549
1517
1550
1518
set_bit(RTW89_FLAG_POWERON, rtwdev->flags);
1551
1519
set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags);
1552
1520
set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags);
1553
-
rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR);
1521
+
1522
+
rtw89_mac_update_scoreboard(rtwdev, MAC_AX_NOTIFY_TP_MAJOR);
1554
1523
} else {
1555
1524
clear_bit(RTW89_FLAG_POWERON, rtwdev->flags);
1556
1525
clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags);
1557
1526
clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags);
1558
1527
clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags);
1528
+
clear_bit(RTW89_FLAG_CMAC0_PWR, rtwdev->flags);
1529
+
clear_bit(RTW89_FLAG_CMAC1_PWR, rtwdev->flags);
1559
1530
clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
1560
-
rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR);
1531
+
1532
+
rtw89_mac_update_scoreboard(rtwdev, MAC_AX_NOTIFY_PWR_MAJOR);
1561
1533
rtw89_set_entity_state(rtwdev, RTW89_PHY_0, false);
1562
1534
rtw89_set_entity_state(rtwdev, RTW89_PHY_1, false);
1563
1535
}
1564
1536
1565
1537
return 0;
1566
-
#undef PWR_ACT
1567
1538
}
1568
1539
1569
1540
int rtw89_mac_pwr_on(struct rtw89_dev *rtwdev)
···
1703
1664
1704
1665
const struct rtw89_mac_size_set rtw89_mac_size = {
1705
1666
.hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0},
1706
-
.hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0},
1707
-
.hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0},
1667
+
.hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0, 2, 32, 0, 0},
1668
+
.hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0, 0, 256, 0, 0},
1708
1669
/* PCIE 64 */
1709
1670
.wde_size0 = {RTW89_WDE_PG_64, 4095, 1,},
1710
1671
.wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,},
···
1719
1680
.wde_size7 = {RTW89_WDE_PG_64, 510, 2,},
1720
1681
/* DLFW */
1721
1682
.wde_size9 = {RTW89_WDE_PG_64, 0, 1024,},
1683
+
.wde_size16_v1 = {RTW89_WDE_PG_64, 639, 1, 0,},
1722
1684
/* 8852C USB3.0 */
1723
1685
.wde_size17 = {RTW89_WDE_PG_64, 354, 30,},
1724
1686
/* 8852C DLFW */
1725
1687
.wde_size18 = {RTW89_WDE_PG_64, 0, 2048,},
1688
+
.wde_size18_v1 = {RTW89_WDE_PG_64, 0, 640, 0,},
1726
1689
/* 8852C PCIE SCC */
1727
1690
.wde_size19 = {RTW89_WDE_PG_64, 3328, 0,},
1728
1691
.wde_size23 = {RTW89_WDE_PG_64, 1022, 2,},
···
1751
1710
.ple_size18 = {RTW89_PLE_PG_128, 2544, 16,},
1752
1711
/* 8852C PCIE SCC */
1753
1712
.ple_size19 = {RTW89_PLE_PG_128, 1904, 16,},
1713
+
.ple_size20_v1 = {RTW89_PLE_PG_128, 2554, 182, 40960,},
1714
+
.ple_size22_v1 = {RTW89_PLE_PG_128, 2736, 0, 40960,},
1754
1715
/* 8852B USB2.0 SCC */
1755
1716
.ple_size32 = {RTW89_PLE_PG_128, 620, 20,},
1756
1717
/* 8852B USB3.0 SCC */
···
1764
1721
.wde_qt0_v1 = {3302, 6, 0, 20,},
1765
1722
/* 8852A USB */
1766
1723
.wde_qt1 = {512, 196, 0, 60,},
1724
+
.wde_qt3 = {0, 0, 0, 0,},
1767
1725
/* DLFW */
1768
1726
.wde_qt4 = {0, 0, 0, 0,},
1769
1727
/* PCIE 64 */
···
1777
1733
.wde_qt17 = {0, 0, 0, 0,},
1778
1734
/* 8852C PCIE SCC */
1779
1735
.wde_qt18 = {3228, 60, 0, 40,},
1736
+
.wde_qt19_v1 = {613, 6, 0, 20,},
1780
1737
.wde_qt23 = {958, 48, 0, 16,},
1781
1738
/* 8852B USB2.0/USB3.0 SCC */
1782
1739
.wde_qt25 = {152, 2, 0, 8,},
···
1789
1744
.ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,},
1790
1745
/* PCIE SCC */
1791
1746
.ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,},
1747
+
.ple_qt5_v2 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,},
1792
1748
.ple_qt9 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0,},
1793
1749
/* DLFW */
1794
1750
.ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,},
···
1800
1754
.ple_qt26 = {2654, 0, 1134, 48, 64, 13, 1478, 0, 64, 128, 120, 0,},
1801
1755
/* USB 52C USB3.0 */
1802
1756
.ple_qt42 = {1068, 0, 16, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,},
1757
+
.ple_qt42_v2 = {91, 91, 32, 16, 19, 13, 91, 91, 44, 18, 1, 4, 0, 0,},
1803
1758
/* USB 52C USB3.0 */
1804
1759
.ple_qt43 = {3068, 0, 32, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,},
1760
+
.ple_qt43_v2 = {645, 645, 32, 16, 2062, 2056, 2134, 2134, 2087, 2061, 1, 2047, 0, 0,},
1805
1761
/* DLFW 52C */
1806
1762
.ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,},
1807
1763
/* DLFW 52C */
···
1837
1789
.ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,},
1838
1790
.ple_rsvd_qt0 = {2, 107, 107, 6, 6, 6, 6, 0, 0, 0,},
1839
1791
.ple_rsvd_qt1 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,},
1792
+
.ple_rsvd_qt9 = {1, 44, 44, 6, 6, 6, 6, 69, 0, 0,},
1840
1793
.rsvd0_size0 = {212992, 0,},
1794
+
.rsvd0_size6 = {40960, 0,},
1841
1795
.rsvd1_size0 = {587776, 2048,},
1796
+
.rsvd1_size2 = {391168, 2048,},
1797
+
.dle_input3 = {0, 0, 0, 16384, 0, 2048, 0, 0,},
1798
+
.dle_input18 = {128, 128, 11454, 2048, 0, 2048, 24, 24,},
1842
1799
};
1843
1800
EXPORT_SYMBOL(rtw89_mac_size);
1844
1801
···
1864
1811
}
1865
1812
1866
1813
mac->dle_info.rsvd_qt = cfg->rsvd_qt;
1814
+
mac->dle_info.dle_input = cfg->dle_input;
1867
1815
mac->dle_info.ple_pg_size = cfg->ple_size->pge_size;
1868
1816
mac->dle_info.ple_free_pg = cfg->ple_size->lnk_pge_num;
1869
1817
mac->dle_info.qta_mode = mode;
···
2285
2231
return ret;
2286
2232
}
2287
2233
2288
-
static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
2289
-
enum rtw89_qta_mode mode)
2234
+
static int preload_init_set_ax(struct rtw89_dev *rtwdev, u8 mac_idx,
2235
+
enum rtw89_qta_mode mode)
2290
2236
{
2291
2237
u32 reg, max_preld_size, min_rsvd_size;
2292
2238
···
2314
2260
int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
2315
2261
enum rtw89_qta_mode mode)
2316
2262
{
2263
+
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
2317
2264
const struct rtw89_chip_info *chip = rtwdev->chip;
2318
2265
2319
2266
if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev) ||
2320
2267
!is_qta_poh(rtwdev))
2321
2268
return 0;
2322
2269
2323
-
return preload_init_set(rtwdev, mac_idx, mode);
2270
+
return mac->preload_init(rtwdev, mac_idx, mode);
2324
2271
}
2325
2272
2326
2273
static bool dle_is_txq_empty(struct rtw89_dev *rtwdev)
···
3116
3061
struct rtw89_efuse *efuse = &rtwdev->efuse;
3117
3062
struct rtw89_mac_c2h_info c2h_info = {};
3118
3063
struct rtw89_hal *hal = &rtwdev->hal;
3064
+
u8 protocol;
3119
3065
u8 tx_nss;
3120
3066
u8 rx_nss;
3121
3067
u8 tx_ant;
···
3163
3107
tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx);
3164
3108
rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity);
3165
3109
rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity);
3110
+
3111
+
protocol = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_PROT);
3112
+
if (protocol < RTW89_C2HREG_PHYCAP_W1_PROT_11BE)
3113
+
hal->no_eht = true;
3166
3114
3167
3115
return 0;
3168
3116
}
···
3991
3931
return 0;
3992
3932
}
3993
3933
3934
+
static int rtw89_mac_reset_pwr_state_ax(struct rtw89_dev *rtwdev)
3935
+
{
3936
+
u8 val;
3937
+
3938
+
val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK);
3939
+
if (val == MAC_AX_MAC_ON) {
3940
+
/*
3941
+
* A USB adapter might play as USB mass storage with driver and
3942
+
* then switch to WiFi adapter, causing it stays on power-on
3943
+
* state when doing WiFi USB probe. Return EAGAIN to caller to
3944
+
* power-off and power-on again to reset the state.
3945
+
*/
3946
+
if (rtwdev->hci.type == RTW89_HCI_TYPE_USB &&
3947
+
!test_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags))
3948
+
return -EAGAIN;
3949
+
3950
+
rtw89_err(rtwdev, "MAC has already powered on\n");
3951
+
return -EBUSY;
3952
+
}
3953
+
3954
+
return 0;
3955
+
}
3956
+
3994
3957
static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev)
3995
3958
{
3996
3959
u32 val32;
···
4228
4145
4229
4146
int rtw89_mac_preinit(struct rtw89_dev *rtwdev)
4230
4147
{
4148
+
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4231
4149
int ret;
4232
4150
4233
4151
ret = rtw89_mac_pwr_on(rtwdev);
4234
4152
if (ret)
4235
4153
return ret;
4154
+
4155
+
if (mac->mac_func_en) {
4156
+
ret = mac->mac_func_en(rtwdev);
4157
+
if (ret)
4158
+
return ret;
4159
+
}
4236
4160
4237
4161
return 0;
4238
4162
}
···
4431
4341
#define BCN_HOLD_DEF 200
4432
4342
#define BCN_MASK_DEF 0
4433
4343
#define TBTT_ERLY_DEF 5
4344
+
#define TBTT_AGG_DEF 1
4434
4345
#define BCN_SET_UNIT 32
4435
4346
#define BCN_ERLY_SET_DLY (10 * 2)
4436
4347
···
4735
4644
B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF);
4736
4645
}
4737
4646
4647
+
static void rtw89_mac_port_cfg_tbtt_agg(struct rtw89_dev *rtwdev,
4648
+
struct rtw89_vif_link *rtwvif_link)
4649
+
{
4650
+
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4651
+
const struct rtw89_port_reg *p = mac->port_base;
4652
+
4653
+
rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_agg,
4654
+
B_AX_TBTT_AGG_NUM_MASK, TBTT_AGG_DEF);
4655
+
}
4656
+
4738
4657
static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev,
4739
4658
struct rtw89_vif_link *rtwvif_link)
4740
4659
{
···
5005
4904
rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif_link);
5006
4905
rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif_link);
5007
4906
rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif_link);
4907
+
rtw89_mac_port_cfg_tbtt_agg(rtwdev, rtwvif_link);
5008
4908
rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif_link);
5009
4909
rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif_link);
5010
4910
rtw89_mac_port_cfg_func_en(rtwdev, rtwvif_link, true);
···
5300
5198
if (start_detect)
5301
5199
return;
5302
5200
5303
-
ieee80211_connection_loss(vif);
5304
-
} else {
5305
-
rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true);
5201
+
ieee80211_beacon_loss(vif);
5306
5202
}
5203
+
5204
+
rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true);
5307
5205
return;
5308
5206
case RTW89_BCN_FLTR_NOTIFY:
5309
5207
nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH;
···
6460
6358
6461
6359
void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val)
6462
6360
{
6361
+
const struct rtw89_chip_info *chip = rtwdev->chip;
6362
+
u32 reg = chip->btc_sb.n[0].cfg;
6463
6363
u32 fw_sb;
6464
6364
6465
-
fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD);
6365
+
fw_sb = rtw89_read32(rtwdev, reg);
6466
6366
fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb);
6467
6367
fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY;
6468
6368
if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
···
6475
6371
val = B_AX_TOGGLE |
6476
6372
FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) |
6477
6373
FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb);
6478
-
rtw89_write32(rtwdev, R_AX_SCOREBOARD, val);
6374
+
rtw89_write32(rtwdev, reg, val);
6479
6375
fsleep(1000); /* avoid BT FW loss information */
6480
6376
}
6481
6377
6482
6378
u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev)
6483
6379
{
6484
-
return rtw89_read32(rtwdev, R_AX_SCOREBOARD);
6380
+
const struct rtw89_chip_info *chip = rtwdev->chip;
6381
+
u32 reg = chip->btc_sb.n[0].get;
6382
+
6383
+
return rtw89_read32(rtwdev, reg);
6485
6384
}
6486
6385
6487
6386
int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
···
7049
6942
return ret;
7050
6943
}
7051
6944
6945
+
if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags) &&
6946
+
(u32_get_bits(val32, B_AX_WL_XTAL_SI_ADDR_MASK) != offset ||
6947
+
u32_get_bits(val32, B_AX_WL_XTAL_SI_DATA_MASK) != val))
6948
+
rtw89_warn(rtwdev, "xtal si write: offset=%x val=%x poll=%x\n",
6949
+
offset, val, val32);
6950
+
7052
6951
return 0;
7053
6952
}
7054
6953
···
7078
6965
return ret;
7079
6966
}
7080
6967
7081
-
*val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1);
6968
+
if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags) &&
6969
+
u32_get_bits(val32, B_AX_WL_XTAL_SI_ADDR_MASK) != offset)
6970
+
rtw89_warn(rtwdev, "xtal si read: offset=%x poll=%x\n",
6971
+
offset, val32);
6972
+
6973
+
*val = u32_get_bits(val32, B_AX_WL_XTAL_SI_DATA_MASK);
7082
6974
7083
6975
return 0;
7084
6976
}
···
7302
7184
.check_mac_en = rtw89_mac_check_mac_en_ax,
7303
7185
.sys_init = sys_init_ax,
7304
7186
.trx_init = trx_init_ax,
7187
+
.preload_init = preload_init_set_ax,
7188
+
.err_imr_ctrl = err_imr_ctrl_ax,
7189
+
.mac_func_en = NULL,
7305
7190
.hci_func_en = rtw89_mac_hci_func_en_ax,
7306
7191
.dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_ax,
7307
7192
.dle_func_en = dle_func_en_ax,
···
7314
7193
.typ_fltr_opt = rtw89_mac_typ_fltr_opt_ax,
7315
7194
.cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_ax,
7316
7195
.cfg_phy_rpt = NULL,
7196
+
.set_edcca_mode = NULL,
7317
7197
7318
7198
.dle_mix_cfg = dle_mix_cfg_ax,
7319
7199
.chk_dle_rdy = chk_dle_rdy_ax,
···
7328
7206
.set_cpuio = set_cpuio_ax,
7329
7207
.dle_quota_change = dle_quota_change_ax,
7330
7208
7209
+
.reset_pwr_state = rtw89_mac_reset_pwr_state_ax,
7331
7210
.disable_cpu = rtw89_mac_disable_cpu_ax,
7332
7211
.fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax,
7333
7212
.fwdl_get_status = rtw89_fw_get_rdy_ax,
···
7338
7215
.parse_phycap_map = rtw89_parse_phycap_map_ax,
7339
7216
.cnv_efuse_state = rtw89_cnv_efuse_state_ax,
7340
7217
.efuse_read_fw_secure = rtw89_efuse_read_fw_secure_ax,
7218
+
.efuse_read_ecv = NULL,
7341
7219
7342
7220
.cfg_plt = rtw89_mac_cfg_plt_ax,
7343
7221
.get_plt_cnt = rtw89_mac_get_plt_cnt_ax,
+78
-1
drivers/net/wireless/realtek/rtw89/mac.h
+78
-1
drivers/net/wireless/realtek/rtw89/mac.h
···
914
914
MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011,
915
915
MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012,
916
916
MAC_AX_ERR_L0_RCVY_EN = 0x0013,
917
+
MAC_AX_ERR_L0_RESET_FORCE = 0x0020,
918
+
MAC_AX_ERR_L0_RESET_FORCE_C1 = 0x0021,
919
+
MAC_AX_ERR_L1_RESET_FORCE = 0x0022,
917
920
MAC_AX_SET_ERR_MAX,
918
921
};
919
922
···
932
929
const struct rtw89_dle_size wde_size6;
933
930
const struct rtw89_dle_size wde_size7;
934
931
const struct rtw89_dle_size wde_size9;
932
+
const struct rtw89_dle_size wde_size16_v1;
935
933
const struct rtw89_dle_size wde_size17;
936
934
const struct rtw89_dle_size wde_size18;
935
+
const struct rtw89_dle_size wde_size18_v1;
937
936
const struct rtw89_dle_size wde_size19;
938
937
const struct rtw89_dle_size wde_size23;
939
938
const struct rtw89_dle_size wde_size25;
···
951
946
const struct rtw89_dle_size ple_size17;
952
947
const struct rtw89_dle_size ple_size18;
953
948
const struct rtw89_dle_size ple_size19;
949
+
const struct rtw89_dle_size ple_size20_v1;
950
+
const struct rtw89_dle_size ple_size22_v1;
954
951
const struct rtw89_dle_size ple_size32;
955
952
const struct rtw89_dle_size ple_size33;
956
953
const struct rtw89_dle_size ple_size34;
957
954
const struct rtw89_wde_quota wde_qt0;
958
955
const struct rtw89_wde_quota wde_qt1;
959
956
const struct rtw89_wde_quota wde_qt0_v1;
957
+
const struct rtw89_wde_quota wde_qt3;
960
958
const struct rtw89_wde_quota wde_qt4;
961
959
const struct rtw89_wde_quota wde_qt6;
962
960
const struct rtw89_wde_quota wde_qt7;
963
961
const struct rtw89_wde_quota wde_qt16;
964
962
const struct rtw89_wde_quota wde_qt17;
965
963
const struct rtw89_wde_quota wde_qt18;
964
+
const struct rtw89_wde_quota wde_qt19_v1;
966
965
const struct rtw89_wde_quota wde_qt23;
967
966
const struct rtw89_wde_quota wde_qt25;
968
967
const struct rtw89_wde_quota wde_qt31;
···
974
965
const struct rtw89_ple_quota ple_qt1;
975
966
const struct rtw89_ple_quota ple_qt4;
976
967
const struct rtw89_ple_quota ple_qt5;
968
+
const struct rtw89_ple_quota ple_qt5_v2;
977
969
const struct rtw89_ple_quota ple_qt9;
978
970
const struct rtw89_ple_quota ple_qt13;
979
971
const struct rtw89_ple_quota ple_qt18;
980
972
const struct rtw89_ple_quota ple_qt25;
981
973
const struct rtw89_ple_quota ple_qt26;
982
974
const struct rtw89_ple_quota ple_qt42;
975
+
const struct rtw89_ple_quota ple_qt42_v2;
983
976
const struct rtw89_ple_quota ple_qt43;
977
+
const struct rtw89_ple_quota ple_qt43_v2;
984
978
const struct rtw89_ple_quota ple_qt44;
985
979
const struct rtw89_ple_quota ple_qt45;
986
980
const struct rtw89_ple_quota ple_qt46;
···
1003
991
const struct rtw89_ple_quota ple_qt_51b_wow;
1004
992
const struct rtw89_rsvd_quota ple_rsvd_qt0;
1005
993
const struct rtw89_rsvd_quota ple_rsvd_qt1;
994
+
const struct rtw89_rsvd_quota ple_rsvd_qt1_v1;
995
+
const struct rtw89_rsvd_quota ple_rsvd_qt9;
1006
996
const struct rtw89_dle_rsvd_size rsvd0_size0;
997
+
const struct rtw89_dle_rsvd_size rsvd0_size6;
1007
998
const struct rtw89_dle_rsvd_size rsvd1_size0;
999
+
const struct rtw89_dle_rsvd_size rsvd1_size2;
1000
+
const struct rtw89_dle_input dle_input3;
1001
+
const struct rtw89_dle_input dle_input18;
1008
1002
};
1009
1003
1010
1004
extern const struct rtw89_mac_size_set rtw89_mac_size;
···
1037
1019
enum rtw89_mac_hwmod_sel sel);
1038
1020
int (*sys_init)(struct rtw89_dev *rtwdev);
1039
1021
int (*trx_init)(struct rtw89_dev *rtwdev);
1022
+
int (*preload_init)(struct rtw89_dev *rtwdev, u8 mac_idx,
1023
+
enum rtw89_qta_mode mode);
1024
+
void (*err_imr_ctrl)(struct rtw89_dev *rtwdev, bool en);
1025
+
int (*mac_func_en)(struct rtw89_dev *rtwdev);
1040
1026
void (*hci_func_en)(struct rtw89_dev *rtwdev);
1041
1027
void (*dmac_func_pre_en)(struct rtw89_dev *rtwdev);
1042
1028
void (*dle_func_en)(struct rtw89_dev *rtwdev, bool enable);
···
1055
1033
u8 mac_idx);
1056
1034
int (*cfg_ppdu_status)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable);
1057
1035
void (*cfg_phy_rpt)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable);
1036
+
void (*set_edcca_mode)(struct rtw89_dev *rtwdev, u8 mac_idx, bool normal);
1058
1037
1059
1038
int (*dle_mix_cfg)(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg);
1060
1039
int (*chk_dle_rdy)(struct rtw89_dev *rtwdev, bool wde_or_ple);
···
1075
1052
struct rtw89_cpuio_ctrl *ctrl_para, bool wd);
1076
1053
int (*dle_quota_change)(struct rtw89_dev *rtwdev, bool band1_en);
1077
1054
1055
+
int (*reset_pwr_state)(struct rtw89_dev *rtwdev);
1078
1056
void (*disable_cpu)(struct rtw89_dev *rtwdev);
1079
1057
int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason,
1080
1058
bool dlfw, bool include_bb);
···
1086
1062
int (*parse_phycap_map)(struct rtw89_dev *rtwdev);
1087
1063
int (*cnv_efuse_state)(struct rtw89_dev *rtwdev, bool idle);
1088
1064
int (*efuse_read_fw_secure)(struct rtw89_dev *rtwdev);
1065
+
int (*efuse_read_ecv)(struct rtw89_dev *rtwdev);
1089
1066
1090
1067
int (*cfg_plt)(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt);
1091
1068
u16 (*get_plt_cnt)(struct rtw89_dev *rtwdev, u8 band);
···
1128
1103
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1129
1104
1130
1105
return band == 0 ? reg_base : (reg_base + mac->band1_offset);
1106
+
}
1107
+
1108
+
static inline void
1109
+
rtw89_write16_idx(struct rtw89_dev *rtwdev, u32 addr, u16 data, u8 band)
1110
+
{
1111
+
addr = rtw89_mac_reg_by_idx(rtwdev, addr, band);
1112
+
1113
+
rtw89_write16(rtwdev, addr, data);
1131
1114
}
1132
1115
1133
1116
static inline
···
1373
1340
return rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_1, enable);
1374
1341
}
1375
1342
1343
+
static inline
1344
+
void rtw89_mac_set_edcca_mode(struct rtw89_dev *rtwdev, u8 mac_idx, bool normal)
1345
+
{
1346
+
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1347
+
1348
+
if (!mac->set_edcca_mode)
1349
+
return;
1350
+
1351
+
mac->set_edcca_mode(rtwdev, mac_idx, normal);
1352
+
}
1353
+
1354
+
static inline
1355
+
void rtw89_mac_set_edcca_mode_bands(struct rtw89_dev *rtwdev, bool normal)
1356
+
{
1357
+
rtw89_mac_set_edcca_mode(rtwdev, RTW89_MAC_0, normal);
1358
+
rtw89_mac_set_edcca_mode(rtwdev, RTW89_MAC_1, normal);
1359
+
}
1360
+
1376
1361
void rtw89_mac_set_rx_fltr(struct rtw89_dev *rtwdev, u8 mac_idx, u32 rx_fltr);
1377
1362
void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev);
1378
1363
void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop);
···
1402
1351
int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,
1403
1352
const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1404
1353
int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev,
1354
+
const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1355
+
int rtw89_mac_cfg_gnt_v3(struct rtw89_dev *rtwdev,
1405
1356
const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1406
1357
1407
1358
static inline
···
1620
1567
XTAL_SI_APBT = 0xD1,
1621
1568
XTAL_SI_PLL = 0xE0,
1622
1569
XTAL_SI_PLL_1 = 0xE1,
1570
+
XTAL_SI_CHIP_ID_L = 0xFD,
1571
+
XTAL_SI_CHIP_ID_H = 0xFE,
1623
1572
};
1624
1573
1625
1574
static inline
···
1652
1597
struct rtw89_mac_dle_rsvd_qt_cfg *cfg);
1653
1598
int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable);
1654
1599
1600
+
static inline int rtw89_mac_efuse_read_ecv(struct rtw89_dev *rtwdev)
1601
+
{
1602
+
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1603
+
1604
+
if (!mac->efuse_read_ecv)
1605
+
return -ENOENT;
1606
+
1607
+
return mac->efuse_read_ecv(rtwdev);
1608
+
}
1609
+
1655
1610
static inline
1656
1611
void rtw89_fwdl_secure_idmem_share_mode(struct rtw89_dev *rtwdev, u8 mode)
1657
1612
{
···
1670
1605
if (!mac->fwdl_secure_idmem_share_mode)
1671
1606
return;
1672
1607
1673
-
return mac->fwdl_secure_idmem_share_mode(rtwdev, mode);
1608
+
mac->fwdl_secure_idmem_share_mode(rtwdev, mode);
1674
1609
}
1675
1610
1676
1611
static inline
···
1784
1719
rtw89_tx_rpt_tx_status(rtwdev, skbs[i],
1785
1720
RTW89_TX_MACID_DROP);
1786
1721
}
1722
+
1723
+
static inline bool rtw89_mac_chk_preload_allow(struct rtw89_dev *rtwdev)
1724
+
{
1725
+
if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE)
1726
+
return false;
1727
+
1728
+
if (rtwdev->chip->chip_id == RTL8922D && rtwdev->hal.cid == RTL8922D_CID7090)
1729
+
return true;
1730
+
1731
+
return false;
1732
+
}
1733
+
1787
1734
#endif
+21
-19
drivers/net/wireless/realtek/rtw89/mac80211.c
+21
-19
drivers/net/wireless/realtek/rtw89/mac80211.c
···
127
127
rtwvif_link->reg_6ghz_power = RTW89_REG_6GHZ_POWER_DFLT;
128
128
rtwvif_link->rand_tsf_done = false;
129
129
rtwvif_link->detect_bcn_count = 0;
130
+
rtwvif_link->last_sync_bcn_tsf = 0;
130
131
131
132
rcu_read_lock();
132
133
···
720
719
if (changed & BSS_CHANGED_MLD_VALID_LINKS) {
721
720
struct rtw89_vif_link *cur = rtw89_get_designated_link(rtwvif);
722
721
723
-
rtw89_chip_rfk_channel(rtwdev, cur);
722
+
if (RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, &rtwdev->fw))
723
+
rtw89_chip_rfk_channel(rtwdev, cur);
724
724
725
725
if (hweight16(vif->active_links) == 1)
726
726
rtwvif->mlo_mode = RTW89_MLO_MODE_MLSR;
···
1614
1612
return 0;
1615
1613
}
1616
1614
1617
-
static void rtw89_vif_cfg_fw_links(struct rtw89_dev *rtwdev,
1618
-
struct rtw89_vif *rtwvif,
1619
-
unsigned long links, bool en)
1615
+
static void rtw89_vif_update_fw_links(struct rtw89_dev *rtwdev,
1616
+
struct rtw89_vif *rtwvif,
1617
+
u16 current_links, bool en)
1620
1618
{
1619
+
struct rtw89_vif_ml_trans *trans = &rtwvif->ml_trans;
1621
1620
struct rtw89_vif_link *rtwvif_link;
1622
1621
unsigned int link_id;
1622
+
unsigned long links;
1623
+
1624
+
/* Do follow-up when all updating links exist. */
1625
+
if (current_links != trans->mediate_links)
1626
+
return;
1627
+
1628
+
if (en)
1629
+
links = trans->links_to_add;
1630
+
else
1631
+
links = trans->links_to_del;
1623
1632
1624
1633
for_each_set_bit(link_id, &links, IEEE80211_MLD_MAX_NUM_LINKS) {
1625
1634
rtwvif_link = rtwvif->links[link_id];
···
1639
1626
1640
1627
rtw89_fw_h2c_mlo_link_cfg(rtwdev, rtwvif_link, en);
1641
1628
}
1642
-
}
1643
-
1644
-
static void rtw89_vif_update_fw_links(struct rtw89_dev *rtwdev,
1645
-
struct rtw89_vif *rtwvif,
1646
-
u16 current_links)
1647
-
{
1648
-
struct rtw89_vif_ml_trans *trans = &rtwvif->ml_trans;
1649
-
1650
-
/* Do follow-up when all updating links exist. */
1651
-
if (current_links != trans->mediate_links)
1652
-
return;
1653
-
1654
-
rtw89_vif_cfg_fw_links(rtwdev, rtwvif, trans->links_to_del, false);
1655
-
rtw89_vif_cfg_fw_links(rtwdev, rtwvif, trans->links_to_add, true);
1656
1629
}
1657
1630
1658
1631
static
···
1682
1683
if (rtwdev->scanning)
1683
1684
rtw89_hw_scan_abort(rtwdev, rtwdev->scan_info.scanning_vif);
1684
1685
1685
-
rtw89_vif_update_fw_links(rtwdev, rtwvif, old_links);
1686
+
rtw89_vif_update_fw_links(rtwdev, rtwvif, old_links, true);
1686
1687
1687
1688
if (!old_links)
1688
1689
__rtw89_ops_clr_vif_links(rtwdev, rtwvif,
···
1714
1715
__rtw89_ops_clr_vif_links(rtwdev, rtwvif,
1715
1716
BIT(RTW89_VIF_IDLE_LINK_ID));
1716
1717
}
1718
+
1719
+
if (!ret)
1720
+
rtw89_vif_update_fw_links(rtwdev, rtwvif, new_links, false);
1717
1721
1718
1722
rtw89_enter_ips_by_hwflags(rtwdev);
1719
1723
return ret;
+629
-46
drivers/net/wireless/realtek/rtw89/mac_be.c
+629
-46
drivers/net/wireless/realtek/rtw89/mac_be.c
···
89
89
struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
90
90
struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
91
91
struct rtw89_hfc_pub_info *info = ¶m->pub_info;
92
+
const struct rtw89_chip_info *chip = rtwdev->chip;
92
93
u32 val;
93
94
94
95
val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO1);
···
117
116
118
117
val = rtw89_read32(rtwdev, R_BE_CH_PAGE_CTRL);
119
118
prec_cfg->ch011_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH011_V1_MASK);
119
+
if (chip->chip_id == RTL8922D)
120
+
prec_cfg->ch011_full_page = u32_get_bits(val, B_BE_FULL_WD_PG_MASK);
120
121
prec_cfg->h2c_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH12_V1_MASK);
121
122
122
123
val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_CTRL2);
123
124
pub_cfg->pub_max = u32_get_bits(val, B_BE_PUBPG_ALL_MASK);
124
125
125
126
val = rtw89_read32(rtwdev, R_BE_WP_PAGE_CTRL1);
126
-
prec_cfg->wp_ch07_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH07_MASK);
127
-
prec_cfg->wp_ch811_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH811_MASK);
127
+
if (chip->chip_id == RTL8922D) {
128
+
prec_cfg->wp_ch07_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH07_V1_MASK);
129
+
prec_cfg->wp_ch07_full_page = u32_get_bits(val, B_BE_FULL_PAGE_WP_CH07_MASK);
130
+
prec_cfg->wp_ch811_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH811_V1_MASK);
131
+
prec_cfg->wp_ch811_full_page = u32_get_bits(val, B_BE_FULL_PAGE_WP_CH811_MASK);
132
+
} else {
133
+
prec_cfg->wp_ch07_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH07_MASK);
134
+
prec_cfg->wp_ch811_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH811_MASK);
135
+
}
128
136
129
137
val = rtw89_read32(rtwdev, R_BE_WP_PAGE_CTRL2);
130
138
pub_cfg->wp_thrd = u32_get_bits(val, B_BE_WP_THRD_MASK);
···
158
148
struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
159
149
const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
160
150
const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
151
+
const struct rtw89_chip_info *chip = rtwdev->chip;
161
152
u32 val;
162
153
163
154
val = u32_encode_bits(prec_cfg->ch011_prec, B_BE_PREC_PAGE_CH011_V1_MASK) |
164
155
u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK);
156
+
if (chip->chip_id == RTL8922D)
157
+
val = u32_replace_bits(val, prec_cfg->ch011_full_page, B_BE_FULL_WD_PG_MASK);
165
158
rtw89_write32(rtwdev, R_BE_CH_PAGE_CTRL, val);
166
159
167
160
val = u32_encode_bits(pub_cfg->pub_max, B_BE_PUBPG_ALL_MASK);
168
161
rtw89_write32(rtwdev, R_BE_PUB_PAGE_CTRL2, val);
169
162
170
-
val = u32_encode_bits(prec_cfg->wp_ch07_prec, B_BE_PREC_PAGE_WP_CH07_MASK) |
171
-
u32_encode_bits(prec_cfg->wp_ch811_prec, B_BE_PREC_PAGE_WP_CH811_MASK);
163
+
if (chip->chip_id == RTL8922D)
164
+
val = u32_encode_bits(prec_cfg->wp_ch07_prec, B_BE_PREC_PAGE_WP_CH07_V1_MASK) |
165
+
u32_encode_bits(prec_cfg->wp_ch07_full_page, B_BE_FULL_PAGE_WP_CH07_MASK) |
166
+
u32_encode_bits(prec_cfg->wp_ch811_prec, B_BE_PREC_PAGE_WP_CH811_V1_MASK) |
167
+
u32_encode_bits(prec_cfg->wp_ch811_full_page, B_BE_FULL_PAGE_WP_CH811_MASK);
168
+
else
169
+
val = u32_encode_bits(prec_cfg->wp_ch07_prec, B_BE_PREC_PAGE_WP_CH07_MASK) |
170
+
u32_encode_bits(prec_cfg->wp_ch811_prec, B_BE_PREC_PAGE_WP_CH811_MASK);
172
171
rtw89_write32(rtwdev, R_BE_WP_PAGE_CTRL1, val);
173
172
174
173
val = u32_replace_bits(rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL),
···
219
200
220
201
static void dle_clk_en_be(struct rtw89_dev *rtwdev, bool enable)
221
202
{
203
+
if (rtwdev->chip->chip_id != RTL8922A)
204
+
return;
205
+
222
206
if (enable)
223
207
rtw89_write32_set(rtwdev, R_BE_DMAC_CLK_EN,
224
208
B_BE_DLE_WDE_CLK_EN | B_BE_DLE_PLE_CLK_EN);
···
353
331
SET_QUOTA(cpu_io, PLE, 10);
354
332
SET_QUOTA(tx_rpt, PLE, 11);
355
333
SET_QUOTA(h2d, PLE, 12);
334
+
335
+
if (rtwdev->chip->chip_id == RTL8922A)
336
+
return;
337
+
338
+
SET_QUOTA(snrpt, PLE, 13);
356
339
}
357
340
358
341
static void rtw89_mac_hci_func_en_be(struct rtw89_dev *rtwdev)
···
368
341
369
342
static void rtw89_mac_dmac_func_pre_en_be(struct rtw89_dev *rtwdev)
370
343
{
344
+
const struct rtw89_chip_info *chip = rtwdev->chip;
345
+
u32 mask;
371
346
u32 val;
372
347
373
348
val = rtw89_read32(rtwdev, R_BE_HAXI_INIT_CFG1);
···
393
364
394
365
rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val);
395
366
396
-
rtw89_write32_clr(rtwdev, R_BE_HAXI_DMA_STOP1,
397
-
B_BE_STOP_CH0 | B_BE_STOP_CH1 | B_BE_STOP_CH2 |
398
-
B_BE_STOP_CH3 | B_BE_STOP_CH4 | B_BE_STOP_CH5 |
399
-
B_BE_STOP_CH6 | B_BE_STOP_CH7 | B_BE_STOP_CH8 |
400
-
B_BE_STOP_CH9 | B_BE_STOP_CH10 | B_BE_STOP_CH11 |
401
-
B_BE_STOP_CH12 | B_BE_STOP_CH13 | B_BE_STOP_CH14);
367
+
if (chip->chip_id == RTL8922A)
368
+
mask = B_BE_TX_STOP1_MASK;
369
+
else
370
+
mask = B_BE_TX_STOP1_MASK_V1;
371
+
372
+
rtw89_write32_clr(rtwdev, R_BE_HAXI_DMA_STOP1, mask);
402
373
403
374
rtw89_write32_set(rtwdev, R_BE_DMAC_TABLE_CTRL, B_BE_DMAC_ADDR_MODE);
404
375
}
···
425
396
return ret;
426
397
}
427
398
399
+
if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags) &&
400
+
(u32_get_bits(val32, B_BE_WL_XTAL_SI_ADDR_MASK) != offset ||
401
+
u32_get_bits(val32, B_BE_WL_XTAL_SI_DATA_MASK) != val))
402
+
rtw89_warn(rtwdev, "xtal si write: offset=%x val=%x poll=%x\n",
403
+
offset, val, val32);
404
+
428
405
return 0;
429
406
}
430
407
···
455
420
return ret;
456
421
}
457
422
458
-
*val = rtw89_read8(rtwdev, R_BE_WLAN_XTAL_SI_CTRL + 1);
423
+
if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags) &&
424
+
u32_get_bits(val32, B_BE_WL_XTAL_SI_ADDR_MASK) != offset)
425
+
rtw89_warn(rtwdev, "xtal si read: offset=%x poll=%x\n",
426
+
offset, val32);
427
+
428
+
*val = u32_get_bits(val32, B_BE_WL_XTAL_SI_DATA_MASK);
429
+
430
+
return 0;
431
+
}
432
+
433
+
static int rtw89_mac_reset_pwr_state_be(struct rtw89_dev *rtwdev)
434
+
{
435
+
u32 val32;
436
+
int ret;
437
+
438
+
val32 = rtw89_read32(rtwdev, R_BE_SYSON_FSM_MON);
439
+
val32 &= WLAN_FSM_MASK;
440
+
val32 |= WLAN_FSM_SET;
441
+
rtw89_write32(rtwdev, R_BE_SYSON_FSM_MON, val32);
442
+
443
+
ret = read_poll_timeout(rtw89_read32_mask, val32, val32 == WLAN_FSM_IDLE,
444
+
1000, 2000000, false,
445
+
rtwdev, R_BE_SYSON_FSM_MON, WLAN_FSM_STATE_MASK);
446
+
if (ret) {
447
+
rtw89_err(rtwdev, "[ERR]Polling WLAN PMC timeout= %X\n", val32);
448
+
return ret;
449
+
}
450
+
451
+
val32 = rtw89_read32_mask(rtwdev, R_BE_IC_PWR_STATE, B_BE_WLMAC_PWR_STE_MASK);
452
+
if (val32 == MAC_AX_MAC_OFF) {
453
+
rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
454
+
455
+
ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
456
+
1000, 2000000, false,
457
+
rtwdev, R_BE_HCI_OPT_CTRL,
458
+
B_BE_HAXIDMA_IO_ST | B_BE_HAXIDMA_BACKUP_RESTORE_ST);
459
+
if (ret) {
460
+
rtw89_err(rtwdev, "[ERR]Polling HAXI IO timeout= %X\n", val32);
461
+
return ret;
462
+
}
463
+
464
+
rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_EN);
465
+
466
+
ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
467
+
1000, 2000000, false,
468
+
rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_ST);
469
+
if (ret) {
470
+
rtw89_err(rtwdev, "[ERR]Polling WLAN IO timeout= %X\n", val32);
471
+
return ret;
472
+
}
473
+
474
+
rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
475
+
rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
476
+
} else if (val32 == MAC_AX_MAC_ON) {
477
+
rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
478
+
479
+
ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
480
+
1000, 2000000, false,
481
+
rtwdev, R_BE_HCI_OPT_CTRL,
482
+
B_BE_HAXIDMA_IO_ST | B_BE_HAXIDMA_BACKUP_RESTORE_ST);
483
+
if (ret) {
484
+
rtw89_err(rtwdev, "[ERR]Polling HAXI IO timeout= %X\n", val32);
485
+
return ret;
486
+
}
487
+
488
+
rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_EN);
489
+
490
+
ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
491
+
1000, 2000000, false,
492
+
rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_ST);
493
+
if (ret) {
494
+
rtw89_err(rtwdev, "[ERR]Polling WLAN IO timeout= %X\n", val32);
495
+
return ret;
496
+
}
497
+
498
+
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
499
+
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_OFFMAC);
500
+
501
+
ret = read_poll_timeout(rtw89_read32_mask, val32, val32 == MAC_AX_MAC_OFF,
502
+
1000, 2000000, false,
503
+
rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_OFFMAC);
504
+
if (ret) {
505
+
rtw89_err(rtwdev, "[ERR]Polling MAC state timeout= %X\n", val32);
506
+
return ret;
507
+
}
508
+
509
+
rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
510
+
rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
511
+
} else if (val32 == MAC_AX_MAC_LPS) {
512
+
rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
513
+
514
+
ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
515
+
1000, 2000000, false,
516
+
rtwdev, R_BE_HCI_OPT_CTRL,
517
+
B_BE_HAXIDMA_IO_ST | B_BE_HAXIDMA_BACKUP_RESTORE_ST);
518
+
if (ret) {
519
+
rtw89_err(rtwdev, "[ERR]Polling HAXI IO timeout= %X\n", val32);
520
+
return ret;
521
+
}
522
+
523
+
rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_EN);
524
+
525
+
ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
526
+
1000, 2000000, false,
527
+
rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_ST);
528
+
if (ret) {
529
+
rtw89_err(rtwdev, "[ERR]Polling WLAN IO timeout= %X\n", val32);
530
+
return ret;
531
+
}
532
+
533
+
rtw89_write32_set(rtwdev, R_BE_WLLPS_CTRL, B_BE_FORCE_LEAVE_LPS);
534
+
535
+
ret = read_poll_timeout(rtw89_read32_mask, val32, val32 == MAC_AX_MAC_ON,
536
+
1000, 2000000, false,
537
+
rtwdev, R_BE_IC_PWR_STATE, B_BE_WLMAC_PWR_STE_MASK);
538
+
if (ret) {
539
+
rtw89_err(rtwdev, "[ERR]Polling MAC STS timeout= %X\n", val32);
540
+
return ret;
541
+
}
542
+
543
+
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
544
+
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_OFFMAC);
545
+
546
+
ret = read_poll_timeout(rtw89_read32_mask, val32, val32 == MAC_AX_MAC_OFF,
547
+
1000, 2000000, false,
548
+
rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_OFFMAC);
549
+
if (ret) {
550
+
rtw89_err(rtwdev, "[ERR]Polling MAC state timeout= %X\n", val32);
551
+
return ret;
552
+
}
553
+
554
+
rtw89_write32_clr(rtwdev, R_BE_WLLPS_CTRL, B_BE_FORCE_LEAVE_LPS);
555
+
rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
556
+
rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
557
+
}
459
558
460
559
return 0;
461
560
}
···
608
439
val32 &= B_BE_RUN_ENV_MASK;
609
440
rtw89_write32(rtwdev, R_BE_WCPU_FW_CTRL, val32);
610
441
611
-
rtw89_write32_set(rtwdev, R_BE_DCPU_PLATFORM_ENABLE, B_BE_DCPU_PLATFORM_EN);
442
+
if (rtwdev->chip->chip_id == RTL8922A)
443
+
rtw89_write32_set(rtwdev, R_BE_DCPU_PLATFORM_ENABLE, B_BE_DCPU_PLATFORM_EN);
612
444
613
445
rtw89_write32(rtwdev, R_BE_UDM0, 0);
614
446
rtw89_write32(rtwdev, R_BE_HALT_C2H, 0);
···
755
585
756
586
static int dmac_func_en_be(struct rtw89_dev *rtwdev)
757
587
{
588
+
const struct rtw89_chip_info *chip = rtwdev->chip;
589
+
590
+
if (chip->chip_id == RTL8922A)
591
+
return 0;
592
+
593
+
rtw89_write32_set(rtwdev, R_BE_DMAC_FUNC_EN,
594
+
B_BE_MAC_FUNC_EN | B_BE_DMAC_FUNC_EN |
595
+
B_BE_MPDU_PROC_EN | B_BE_WD_RLS_EN |
596
+
B_BE_DLE_WDE_EN | B_BE_TXPKT_CTRL_EN |
597
+
B_BE_STA_SCH_EN | B_BE_DLE_PLE_EN |
598
+
B_BE_PKT_BUF_EN | B_BE_DMAC_TBL_EN |
599
+
B_BE_PKT_IN_EN | B_BE_DLE_CPUIO_EN |
600
+
B_BE_DISPATCHER_EN | B_BE_BBRPT_EN |
601
+
B_BE_MAC_SEC_EN | B_BE_H_AXIDMA_EN |
602
+
B_BE_DMAC_MLO_EN | B_BE_PLRLS_EN |
603
+
B_BE_P_AXIDMA_EN | B_BE_DLE_DATACPUIO_EN);
604
+
605
+
return 0;
606
+
}
607
+
608
+
static int cmac_share_func_en_be(struct rtw89_dev *rtwdev)
609
+
{
610
+
const struct rtw89_chip_info *chip = rtwdev->chip;
611
+
612
+
if (chip->chip_id == RTL8922A)
613
+
return 0;
614
+
615
+
rtw89_write32_set(rtwdev, R_BE_CMAC_SHARE_FUNC_EN,
616
+
B_BE_CMAC_SHARE_EN | B_BE_RESPBA_EN |
617
+
B_BE_ADDRSRCH_EN | B_BE_BTCOEX_EN);
618
+
619
+
return 0;
620
+
}
621
+
622
+
static int cmac_pwr_en_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
623
+
{
624
+
if (mac_idx > RTW89_MAC_1)
625
+
return -EINVAL;
626
+
627
+
if (mac_idx == RTW89_MAC_0) {
628
+
if (en == test_bit(RTW89_FLAG_CMAC0_PWR, rtwdev->flags))
629
+
return 0;
630
+
631
+
if (en) {
632
+
rtw89_write32_set(rtwdev, R_BE_AFE_CTRL1,
633
+
B_BE_R_SYM_WLCMAC0_ALL_EN);
634
+
rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE,
635
+
B_BE_R_SYM_ISO_CMAC02PP);
636
+
rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE,
637
+
B_BE_CMAC0_FEN);
638
+
639
+
set_bit(RTW89_FLAG_CMAC0_PWR, rtwdev->flags);
640
+
} else {
641
+
rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE,
642
+
B_BE_CMAC0_FEN);
643
+
rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE,
644
+
B_BE_R_SYM_ISO_CMAC02PP);
645
+
rtw89_write32_clr(rtwdev, R_BE_AFE_CTRL1,
646
+
B_BE_R_SYM_WLCMAC0_ALL_EN);
647
+
648
+
clear_bit(RTW89_FLAG_CMAC0_PWR, rtwdev->flags);
649
+
}
650
+
} else {
651
+
if (en == test_bit(RTW89_FLAG_CMAC1_PWR, rtwdev->flags))
652
+
return 0;
653
+
654
+
if (en) {
655
+
rtw89_write32_set(rtwdev, R_BE_AFE_CTRL1,
656
+
B_BE_R_SYM_WLCMAC1_ALL_EN);
657
+
rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE,
658
+
B_BE_R_SYM_ISO_CMAC12PP);
659
+
rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE,
660
+
B_BE_CMAC1_FEN);
661
+
662
+
set_bit(RTW89_FLAG_CMAC1_PWR, rtwdev->flags);
663
+
} else {
664
+
rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE,
665
+
B_BE_CMAC1_FEN);
666
+
rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE,
667
+
B_BE_R_SYM_ISO_CMAC12PP);
668
+
rtw89_write32_clr(rtwdev, R_BE_AFE_CTRL1,
669
+
B_BE_R_SYM_WLCMAC1_ALL_EN);
670
+
671
+
clear_bit(RTW89_FLAG_CMAC1_PWR, rtwdev->flags);
672
+
}
673
+
}
674
+
758
675
return 0;
759
676
}
760
677
761
678
static int cmac_func_en_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
762
679
{
680
+
enum rtw89_flags pwr_flag, func_flag;
763
681
u32 reg;
764
682
765
683
if (mac_idx > RTW89_MAC_1)
766
684
return -EINVAL;
767
685
768
-
if (mac_idx == RTW89_MAC_0)
686
+
if (mac_idx == RTW89_MAC_0) {
687
+
pwr_flag = RTW89_FLAG_CMAC0_PWR;
688
+
func_flag = RTW89_FLAG_CMAC0_FUNC;
689
+
} else {
690
+
pwr_flag = RTW89_FLAG_CMAC1_PWR;
691
+
func_flag = RTW89_FLAG_CMAC1_FUNC;
692
+
}
693
+
694
+
if (!test_bit(pwr_flag, rtwdev->flags)) {
695
+
rtw89_warn(rtwdev, "CMAC %u power cut did not release\n", mac_idx);
769
696
return 0;
697
+
}
770
698
771
699
if (en) {
772
-
rtw89_write32_set(rtwdev, R_BE_AFE_CTRL1, B_BE_AFE_CTRL1_SET);
773
-
rtw89_write32_clr(rtwdev, R_BE_SYS_ISO_CTRL_EXTEND, B_BE_R_SYM_ISO_CMAC12PP);
774
-
rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_CMAC1_FEN);
775
-
776
700
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CK_EN, mac_idx);
777
701
rtw89_write32_set(rtwdev, reg, B_BE_CK_EN_SET);
778
702
779
703
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CMAC_FUNC_EN, mac_idx);
780
704
rtw89_write32_set(rtwdev, reg, B_BE_CMAC_FUNC_EN_SET);
781
705
782
-
set_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags);
706
+
set_bit(func_flag, rtwdev->flags);
783
707
} else {
784
708
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CMAC_FUNC_EN, mac_idx);
785
709
rtw89_write32_clr(rtwdev, reg, B_BE_CMAC_FUNC_EN_SET);
···
881
617
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CK_EN, mac_idx);
882
618
rtw89_write32_clr(rtwdev, reg, B_BE_CK_EN_SET);
883
619
884
-
rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_CMAC1_FEN);
885
-
rtw89_write32_set(rtwdev, R_BE_SYS_ISO_CTRL_EXTEND, B_BE_R_SYM_ISO_CMAC12PP);
886
-
rtw89_write32_clr(rtwdev, R_BE_AFE_CTRL1, B_BE_AFE_CTRL1_SET);
887
-
888
-
clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags);
620
+
clear_bit(func_flag, rtwdev->flags);
889
621
}
890
622
891
623
return 0;
···
900
640
if (ret)
901
641
return ret;
902
642
643
+
ret = cmac_share_func_en_be(rtwdev);
644
+
if (ret)
645
+
return ret;
646
+
647
+
ret = cmac_pwr_en_be(rtwdev, RTW89_MAC_0, true);
648
+
if (ret)
649
+
return ret;
650
+
903
651
ret = cmac_func_en_be(rtwdev, RTW89_MAC_0, true);
904
652
if (ret)
905
653
return ret;
···
919
651
return ret;
920
652
}
921
653
654
+
static int mac_func_en_be(struct rtw89_dev *rtwdev)
655
+
{
656
+
u32 val;
657
+
int ret;
658
+
659
+
ret = dmac_func_en_be(rtwdev);
660
+
if (ret)
661
+
return ret;
662
+
663
+
ret = cmac_share_func_en_be(rtwdev);
664
+
if (ret)
665
+
return ret;
666
+
667
+
val = rtw89_read32(rtwdev, R_BE_FEN_RST_ENABLE);
668
+
if (val & B_BE_CMAC0_FEN) {
669
+
ret = cmac_pwr_en_be(rtwdev, RTW89_MAC_0, true);
670
+
if (ret)
671
+
return ret;
672
+
673
+
ret = cmac_func_en_be(rtwdev, RTW89_MAC_0, true);
674
+
if (ret)
675
+
return ret;
676
+
}
677
+
678
+
if (val & B_BE_CMAC1_FEN) {
679
+
ret = cmac_pwr_en_be(rtwdev, RTW89_MAC_1, true);
680
+
if (ret)
681
+
return ret;
682
+
683
+
ret = cmac_func_en_be(rtwdev, RTW89_MAC_1, true);
684
+
if (ret)
685
+
return ret;
686
+
}
687
+
688
+
return 0;
689
+
}
690
+
922
691
static int sta_sch_init_be(struct rtw89_dev *rtwdev)
923
692
{
924
693
u32 p_val;
925
694
int ret;
695
+
696
+
if (rtwdev->chip->chip_id == RTL8922D) {
697
+
rtw89_write32_set(rtwdev, R_BE_SS_LITE_TXL_MACID, B_BE_RPT_OTHER_BAND_EN);
698
+
return 0;
699
+
}
926
700
927
701
ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
928
702
if (ret)
···
995
685
return ret;
996
686
997
687
rtw89_write32_set(rtwdev, R_BE_MPDU_PROC, B_BE_APPEND_FCS);
998
-
rtw89_write32(rtwdev, R_BE_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL);
688
+
rtw89_write32(rtwdev, R_BE_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL |
689
+
B_BE_CA_CHK_ADDRCAM_EN);
999
690
1000
691
val32 = rtw89_read32(rtwdev, R_BE_HDR_SHCUT_SETTING);
1001
692
val32 |= (B_BE_TX_HW_SEQ_EN | B_BE_TX_HW_ACK_POLICY_EN | B_BE_TX_MAC_MPDU_PROC_EN);
1002
693
val32 &= ~B_BE_TX_ADDR_MLD_TO_LIK;
1003
694
rtw89_write32_set(rtwdev, R_BE_HDR_SHCUT_SETTING, val32);
1004
695
1005
-
rtw89_write32(rtwdev, R_BE_RX_HDRTRNS, TRXCFG_MPDU_PROC_RX_HDR_CONV);
696
+
rtw89_write32(rtwdev, R_BE_RX_HDRTRNS, TRXCFG_MPDU_PROC_RX_HDR_CONV |
697
+
B_BE_HC_ADDR_HIT_EN);
1006
698
1007
699
val32 = rtw89_read32(rtwdev, R_BE_DISP_FWD_WLAN_0);
1008
700
val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_0_DATA_MASK);
···
1040
728
1041
729
static int txpktctrl_init_be(struct rtw89_dev *rtwdev)
1042
730
{
731
+
struct rtw89_mac_info *mac = &rtwdev->mac;
1043
732
struct rtw89_mac_dle_rsvd_qt_cfg qt_cfg;
733
+
const struct rtw89_dle_input *dle_input;
734
+
u32 mpdu_info_b1_ofst;
1044
735
u32 val32;
1045
736
int ret;
1046
737
···
1054
739
return ret;
1055
740
}
1056
741
742
+
dle_input = mac->dle_info.dle_input;
743
+
if (dle_input)
744
+
mpdu_info_b1_ofst = DIV_ROUND_UP(dle_input->mpdu_info_tbl_b0,
745
+
BIT(MPDU_INFO_TBL_FACTOR));
746
+
else
747
+
mpdu_info_b1_ofst = MPDU_INFO_B1_OFST;
748
+
1057
749
val32 = rtw89_read32(rtwdev, R_BE_TXPKTCTL_MPDUINFO_CFG);
1058
750
val32 = u32_replace_bits(val32, qt_cfg.pktid, B_BE_MPDUINFO_PKTID_MASK);
1059
-
val32 = u32_replace_bits(val32, MPDU_INFO_B1_OFST, B_BE_MPDUINFO_B1_BADDR_MASK);
751
+
val32 = u32_replace_bits(val32, mpdu_info_b1_ofst, B_BE_MPDUINFO_B1_BADDR_MASK);
1060
752
val32 |= B_BE_MPDUINFO_FEN;
1061
753
rtw89_write32(rtwdev, R_BE_TXPKTCTL_MPDUINFO_CFG, val32);
1062
754
···
1072
750
1073
751
static int mlo_init_be(struct rtw89_dev *rtwdev)
1074
752
{
753
+
const struct rtw89_chip_info *chip = rtwdev->chip;
1075
754
u32 val32;
755
+
u32 reg;
1076
756
int ret;
1077
757
1078
758
val32 = rtw89_read32(rtwdev, R_BE_MLO_INIT_CTL);
···
1090
766
if (ret)
1091
767
rtw89_err(rtwdev, "[MLO]%s: MLO init polling timeout\n", __func__);
1092
768
1093
-
rtw89_write32_set(rtwdev, R_BE_SS_CTRL, B_BE_MLO_HW_CHGLINK_EN);
769
+
if (chip->chip_id == RTL8922A)
770
+
reg = R_BE_SS_CTRL;
771
+
else
772
+
reg = R_BE_SS_CTRL_V1;
773
+
774
+
rtw89_write32_set(rtwdev, reg, B_BE_MLO_HW_CHGLINK_EN);
1094
775
rtw89_write32_set(rtwdev, R_BE_CMAC_SHARE_ACQCHK_CFG_0, B_BE_R_MACID_ACQ_CHK_EN);
1095
776
1096
777
return ret;
···
1158
829
1159
830
static int scheduler_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1160
831
{
832
+
const struct rtw89_chip_info *chip = rtwdev->chip;
1161
833
u32 val32;
1162
834
u32 reg;
1163
835
int ret;
···
1166
836
ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1167
837
if (ret)
1168
838
return ret;
839
+
840
+
if (chip->chip_id == RTL8922D) {
841
+
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_SCH_EXT_CTRL, mac_idx);
842
+
rtw89_write32_set(rtwdev, reg, B_BE_CWCNT_PLUS_MODE);
843
+
}
1169
844
1170
845
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_HE_CTN_CHK_CCA_NAV, mac_idx);
1171
846
val32 = B_BE_HE_CTN_CHK_CCA_P20 | B_BE_HE_CTN_CHK_EDCCA_P20 |
···
1204
869
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_EDCA_BCNQ_PARAM, mac_idx);
1205
870
rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_CW_MASK, 0x32);
1206
871
rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_AIFS_MASK, BCN_IFS_25US);
872
+
873
+
if (chip->chip_id == RTL8922D) {
874
+
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_SCH_EDCA_RST_CFG, mac_idx);
875
+
rtw89_write32_set(rtwdev, reg, B_BE_TX_NAV_RST_EDCA_EN);
876
+
}
1207
877
1208
878
return 0;
1209
879
}
···
1325
985
1326
986
rtw89_write32(rtwdev, reg, val32);
1327
987
988
+
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_SPECIAL_TX_SETTING, mac_idx);
989
+
rtw89_write32_clr(rtwdev, reg, B_BE_BMC_NAV_PROTECT);
990
+
1328
991
return 0;
1329
992
}
1330
993
···
1351
1008
1352
1009
static int tmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1353
1010
{
1011
+
const struct rtw89_chip_info *chip = rtwdev->chip;
1354
1012
u32 reg;
1355
1013
1356
1014
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TB_PPDU_CTRL, mac_idx);
1357
1015
rtw89_write32_clr(rtwdev, reg, B_BE_QOSNULL_UPD_MUEDCA_EN);
1358
1016
1359
-
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMTX_TCR_BE_4, mac_idx);
1360
-
rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_4XLTF_ZLD_USTIMER_MASK, 0x12);
1361
-
rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_2XLTF_ZLD_USTIMER_MASK, 0xe);
1017
+
if (chip->chip_id == RTL8922A) {
1018
+
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMTX_TCR_BE_4, mac_idx);
1019
+
rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_4XLTF_ZLD_USTIMER_MASK, 0x12);
1020
+
rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_2XLTF_ZLD_USTIMER_MASK, 0xe);
1021
+
}
1022
+
1023
+
if (chip->chip_id == RTL8922D) {
1024
+
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_COMMON_PHYINTF_CTRL_0, mac_idx);
1025
+
rtw89_write32_clr(rtwdev, reg, CLEAR_DTOP_DIS);
1026
+
}
1362
1027
1363
1028
return 0;
1364
1029
}
···
1390
1039
B_BE_MACLBK_PLCP_DLY_MASK);
1391
1040
val32 &= ~B_BE_MACLBK_EN;
1392
1041
rtw89_write32(rtwdev, reg, val32);
1042
+
1043
+
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CMAC_FUNC_EN, mac_idx);
1044
+
rtw89_write32_set(rtwdev, reg, B_BE_PHYINTF_EN);
1045
+
1046
+
if (chip->chip_id == RTL8922D) {
1047
+
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_PLCP_EXT_OPTION_2, mac_idx);
1048
+
rtw89_write32_set(rtwdev, reg, B_BE_PLCP_PHASE_B_CRC_CHK_EN |
1049
+
B_BE_PLCP_PHASE_A_CRC_CHK_EN);
1050
+
}
1393
1051
1394
1052
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_0, mac_idx);
1395
1053
val32 = rtw89_read32(rtwdev, reg);
···
1469
1109
1470
1110
static int rmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1471
1111
{
1112
+
const struct rtw89_chip_info *chip = rtwdev->chip;
1472
1113
u32 rx_min_qta, rx_max_len, rx_max_pg;
1473
1114
u16 val16;
1474
1115
u32 reg;
···
1513
1152
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_PLCP_EXT_OPTION_1, mac_idx);
1514
1153
rtw89_write16_set(rtwdev, reg, B_BE_PLCP_SU_PSDU_LEN_SRC);
1515
1154
1155
+
if (chip->chip_id == RTL8922D) {
1156
+
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BSR_UPD_CTRL, mac_idx);
1157
+
rtw89_write32_set(rtwdev, reg, B_BE_QSIZE_RULE);
1158
+
1159
+
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RXGCK_CTRL, mac_idx);
1160
+
rtw89_write16_mask(rtwdev, reg, B_BE_RXGCK_GCK_RATE_LIMIT_MASK, RX_GCK_LEGACY);
1161
+
1162
+
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PLCP_HDR_FLTR, mac_idx);
1163
+
rtw89_write32_set(rtwdev, reg, B_BE_DIS_CHK_MIN_LEN);
1164
+
}
1165
+
1516
1166
return 0;
1517
1167
}
1518
1168
···
1547
1175
1548
1176
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RESP_CSI_RESERVED_PAGE, mac_idx);
1549
1177
rtw89_write32_mask(rtwdev, reg, B_BE_CSI_RESERVED_START_PAGE_MASK, qt_cfg.pktid);
1550
-
rtw89_write32_mask(rtwdev, reg, B_BE_CSI_RESERVED_PAGE_NUM_MASK, qt_cfg.pg_num);
1178
+
rtw89_write32_mask(rtwdev, reg, B_BE_CSI_RESERVED_PAGE_NUM_MASK, qt_cfg.pg_num + 1);
1551
1179
1552
1180
return 0;
1553
1181
}
···
1582
1210
1583
1211
static int ptcl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1584
1212
{
1213
+
const struct rtw89_chip_info *chip = rtwdev->chip;
1585
1214
u32 val32;
1586
1215
u8 val8;
1587
1216
u32 reg;
···
1597
1224
val32 = rtw89_read32(rtwdev, reg);
1598
1225
val32 = u32_replace_bits(val32, S_AX_CTS2S_TH_1K,
1599
1226
B_BE_HW_CTS2SELF_PKT_LEN_TH_MASK);
1600
-
val32 = u32_replace_bits(val32, S_AX_CTS2S_TH_SEC_256B,
1601
-
B_BE_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK);
1227
+
if (chip->chip_id == RTL8922A)
1228
+
val32 = u32_replace_bits(val32, S_AX_CTS2S_TH_SEC_256B,
1229
+
B_BE_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK);
1602
1230
val32 |= B_BE_HW_CTS2SELF_EN;
1603
1231
rtw89_write32(rtwdev, reg, val32);
1604
1232
···
1620
1246
rtw89_write8(rtwdev, reg, val8);
1621
1247
1622
1248
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_AMPDU_AGG_LIMIT, mac_idx);
1623
-
rtw89_write32_mask(rtwdev, reg, B_BE_AMPDU_MAX_TIME_MASK, AMPDU_MAX_TIME);
1249
+
if (chip->chip_id == RTL8922A)
1250
+
val32 = AMPDU_MAX_TIME;
1251
+
else
1252
+
val32 = AMPDU_MAX_TIME_V1;
1253
+
rtw89_write32_mask(rtwdev, reg, B_BE_AMPDU_MAX_TIME_MASK, val32);
1254
+
1255
+
if (chip->chip_id == RTL8922D) {
1256
+
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_AGG_BK_0, mac_idx);
1257
+
rtw89_write32_clr(rtwdev, reg, B_BE_WDBK_CFG | B_BE_EN_RTY_BK |
1258
+
B_BE_EN_RTY_BK_COD);
1259
+
1260
+
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_AMPDU_AGG_LIMIT, mac_idx);
1261
+
rtw89_write32_mask(rtwdev, reg, B_BE_MAX_AGG_NUM_MASK,
1262
+
MAX_TX_AMPDU_NUM_V1 - 1);
1263
+
}
1264
+
1265
+
if (rtw89_mac_chk_preload_allow(rtwdev)) {
1266
+
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_AGG_BK_0, mac_idx);
1267
+
rtw89_write32_set(rtwdev, reg, B_BE_PRELD_MGQ0_EN |
1268
+
B_BE_PRELD_HIQ_P4_EN |
1269
+
B_BE_PRELD_HIQ_P3_EN |
1270
+
B_BE_PRELD_HIQ_P2_EN |
1271
+
B_BE_PRELD_HIQ_P1_EN |
1272
+
B_BE_PRELD_HIQ_P0MB15_EN |
1273
+
B_BE_PRELD_HIQ_P0MB14_EN |
1274
+
B_BE_PRELD_HIQ_P0MB13_EN |
1275
+
B_BE_PRELD_HIQ_P0MB12_EN |
1276
+
B_BE_PRELD_HIQ_P0MB11_EN |
1277
+
B_BE_PRELD_HIQ_P0MB10_EN |
1278
+
B_BE_PRELD_HIQ_P0MB9_EN |
1279
+
B_BE_PRELD_HIQ_P0MB8_EN |
1280
+
B_BE_PRELD_HIQ_P0MB7_EN |
1281
+
B_BE_PRELD_HIQ_P0MB6_EN |
1282
+
B_BE_PRELD_HIQ_P0MB5_EN |
1283
+
B_BE_PRELD_HIQ_P0MB4_EN |
1284
+
B_BE_PRELD_HIQ_P0MB3_EN |
1285
+
B_BE_PRELD_HIQ_P0MB2_EN |
1286
+
B_BE_PRELD_HIQ_P0MB1_EN |
1287
+
B_BE_PRELD_HIQ_P0_EN);
1288
+
}
1624
1289
1625
1290
return 0;
1626
1291
}
···
1946
1533
static int preload_init_be(struct rtw89_dev *rtwdev, u8 mac_idx,
1947
1534
enum rtw89_qta_mode mode)
1948
1535
{
1536
+
const struct rtw89_chip_info *chip = rtwdev->chip;
1949
1537
u32 max_preld_size, min_rsvd_size;
1538
+
u8 preld_acq, preld_miscq;
1950
1539
u32 val32;
1951
1540
u32 reg;
1952
1541
1542
+
if (!(chip->chip_id == RTL8922A || rtw89_mac_chk_preload_allow(rtwdev)))
1543
+
return 0;
1544
+
1953
1545
max_preld_size = mac_idx == RTW89_MAC_0 ?
1954
1546
PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM;
1547
+
if (chip->chip_id == RTL8922D)
1548
+
max_preld_size = PRELD_B01_ENT_NUM_8922D;
1955
1549
max_preld_size *= PRELD_AMSDU_SIZE;
1550
+
min_rsvd_size = PRELD_NEXT_MIN_SIZE;
1956
1551
1957
-
reg = mac_idx == RTW89_MAC_0 ? R_BE_TXPKTCTL_B0_PRELD_CFG0 :
1958
-
R_BE_TXPKTCTL_B1_PRELD_CFG0;
1959
-
val32 = rtw89_read32(rtwdev, reg);
1960
-
val32 = u32_replace_bits(val32, max_preld_size, B_BE_B0_PRELD_USEMAXSZ_MASK);
1961
-
val32 |= B_BE_B0_PRELD_FEN;
1962
-
rtw89_write32(rtwdev, reg, val32);
1963
-
1964
-
min_rsvd_size = PRELD_AMSDU_SIZE;
1965
1552
reg = mac_idx == RTW89_MAC_0 ? R_BE_TXPKTCTL_B0_PRELD_CFG1 :
1966
1553
R_BE_TXPKTCTL_B1_PRELD_CFG1;
1967
1554
val32 = rtw89_read32(rtwdev, reg);
1968
1555
val32 = u32_replace_bits(val32, PRELD_NEXT_WND, B_BE_B0_PRELD_NXT_TXENDWIN_MASK);
1969
1556
val32 = u32_replace_bits(val32, min_rsvd_size, B_BE_B0_PRELD_NXT_RSVMINSZ_MASK);
1557
+
rtw89_write32(rtwdev, reg, val32);
1558
+
1559
+
reg = mac_idx == RTW89_MAC_0 ? R_BE_TXPKTCTL_B0_PRELD_CFG0 :
1560
+
R_BE_TXPKTCTL_B1_PRELD_CFG0;
1561
+
if (chip->chip_id == RTL8922D) {
1562
+
preld_acq = PRELD_ACQ_ENT_NUM_8922D;
1563
+
preld_miscq = PRELD_MISCQ_ENT_NUM_8922D;
1564
+
} else {
1565
+
preld_acq = mac_idx == RTW89_MAC_0 ? PRELD_B0_ACQ_ENT_NUM_8922A :
1566
+
PRELD_B1_ACQ_ENT_NUM_8922A;
1567
+
preld_miscq = PRELD_MISCQ_ENT_NUM_8922A;
1568
+
}
1569
+
1570
+
val32 = rtw89_read32(rtwdev, reg);
1571
+
val32 = u32_replace_bits(val32, preld_acq, B_BE_B0_PRELD_CAM_G0ENTNUM_MASK);
1572
+
val32 = u32_replace_bits(val32, preld_miscq, B_BE_B0_PRELD_CAM_G1ENTNUM_MASK);
1573
+
val32 = u32_replace_bits(val32, max_preld_size, B_BE_B0_PRELD_USEMAXSZ_MASK);
1574
+
val32 |= B_BE_B0_PRELD_FEN;
1970
1575
rtw89_write32(rtwdev, reg, val32);
1971
1576
1972
1577
return 0;
···
2018
1587
table = chip->imr_cmac_table;
2019
1588
else
2020
1589
return -EINVAL;
1590
+
1591
+
if (chip->chip_id == RTL8922D)
1592
+
rtw89_write32_mask(rtwdev, R_BE_NO_RX_ERR_CFG,
1593
+
B_BE_NO_RX_ERR_TO_MASK, 0);
2021
1594
2022
1595
for (i = 0; i < table->n_regs; i++) {
2023
1596
reg = &table->regs[i];
···
2073
1638
return ret;
2074
1639
}
2075
1640
1641
+
ret = cmac_pwr_en_be(rtwdev, RTW89_MAC_1, true);
1642
+
if (ret) {
1643
+
rtw89_err(rtwdev, "[ERR]CMAC%d pwr en %d\n", RTW89_MAC_1, ret);
1644
+
return ret;
1645
+
}
1646
+
2076
1647
ret = cmac_func_en_be(rtwdev, RTW89_MAC_1, true);
2077
1648
if (ret) {
2078
1649
rtw89_err(rtwdev, "[ERR]CMAC%d func en %d\n", RTW89_MAC_1, ret);
···
2119
1678
ret = cmac_func_en_be(rtwdev, RTW89_MAC_1, false);
2120
1679
if (ret) {
2121
1680
rtw89_err(rtwdev, "[ERR]CMAC%d func dis %d\n", RTW89_MAC_1, ret);
1681
+
return ret;
1682
+
}
1683
+
1684
+
ret = cmac_pwr_en_be(rtwdev, RTW89_MAC_1, false);
1685
+
if (ret) {
1686
+
rtw89_err(rtwdev, "[ERR]CMAC%d pwr dis %d\n", RTW89_MAC_1, ret);
2122
1687
return ret;
2123
1688
}
2124
1689
···
2178
1731
2179
1732
static int set_host_rpr_be(struct rtw89_dev *rtwdev)
2180
1733
{
1734
+
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2181
1735
u32 val32;
2182
1736
u32 mode;
2183
1737
u32 fltr;
1738
+
u32 qid;
2184
1739
bool poh;
2185
1740
2186
1741
poh = is_qta_poh(rtwdev);
2187
1742
2188
1743
if (poh) {
2189
1744
mode = RTW89_RPR_MODE_POH;
2190
-
fltr = S_BE_WDRLS_FLTR_TXOK | S_BE_WDRLS_FLTR_RTYLMT |
2191
-
S_BE_WDRLS_FLTR_LIFTIM | S_BE_WDRLS_FLTR_MACID;
1745
+
qid = WDRLS_DEST_QID_POH;
2192
1746
} else {
2193
1747
mode = RTW89_RPR_MODE_STF;
2194
1748
fltr = 0;
1749
+
qid = WDRLS_DEST_QID_STF;
1750
+
}
1751
+
1752
+
if (chip_id == RTL8922A) {
1753
+
fltr = S_BE_WDRLS_FLTR_TXOK | S_BE_WDRLS_FLTR_RTYLMT |
1754
+
S_BE_WDRLS_FLTR_LIFTIM | S_BE_WDRLS_FLTR_MACID;
1755
+
} else {
1756
+
fltr = S_BE_WDRLS_FLTR_TXOK_V1 | S_BE_WDRLS_FLTR_RTYLMT_V1 |
1757
+
S_BE_WDRLS_FLTR_LIFTIM_V1 | S_BE_WDRLS_FLTR_MACID_V1;
2195
1758
}
2196
1759
2197
1760
rtw89_write32_mask(rtwdev, R_BE_WDRLS_CFG, B_BE_WDRLS_MODE_MASK, mode);
1761
+
rtw89_write32_mask(rtwdev, R_BE_RLSRPT0_CFG0, B_BE_RLSRPT0_QID_MASK, qid);
2198
1762
2199
1763
val32 = rtw89_read32(rtwdev, R_BE_RLSRPT0_CFG1);
2200
-
val32 = u32_replace_bits(val32, fltr, B_BE_RLSRPT0_FLTR_MAP_MASK);
1764
+
if (chip_id == RTL8922A)
1765
+
val32 = u32_replace_bits(val32, fltr, B_BE_RLSRPT0_FLTR_MAP_MASK);
1766
+
else
1767
+
val32 = u32_replace_bits(val32, fltr, B_BE_RLSRPT0_FLTR_MAP_V1_MASK);
2201
1768
val32 = u32_replace_bits(val32, 30, B_BE_RLSRPT0_AGGNUM_MASK);
2202
1769
val32 = u32_replace_bits(val32, 255, B_BE_RLSRPT0_TO_MASK);
2203
1770
rtw89_write32(rtwdev, R_BE_RLSRPT0_CFG1, val32);
···
2324
1863
}
2325
1864
EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v2);
2326
1865
1866
+
int rtw89_mac_cfg_gnt_v3(struct rtw89_dev *rtwdev,
1867
+
const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
1868
+
{
1869
+
u32 val = 0;
1870
+
1871
+
if (gnt_cfg->band[0].gnt_bt)
1872
+
val |= B_BE_PTA_GNT_BT0_BB_VAL | B_BE_PTA_GNT_BT0_RX_BB0_VAL |
1873
+
B_BE_PTA_GNT_BT0_TX_BB0_VAL;
1874
+
1875
+
if (gnt_cfg->band[0].gnt_bt_sw_en)
1876
+
val |= B_BE_PTA_GNT_BT0_BB_SWCTRL | B_BE_PTA_GNT_BT0_RX_BB0_SWCTRL |
1877
+
B_BE_PTA_GNT_BT0_TX_BB0_SWCTRL;
1878
+
1879
+
if (gnt_cfg->band[0].gnt_wl)
1880
+
val |= B_BE_PTA_GNT_WL_BB0_VAL;
1881
+
1882
+
if (gnt_cfg->band[0].gnt_wl_sw_en)
1883
+
val |= B_BE_PTA_GNT_WL_BB0_SWCTRL;
1884
+
1885
+
if (gnt_cfg->band[1].gnt_bt)
1886
+
val |= B_BE_PTA_GNT_BT0_BB_VAL | B_BE_PTA_GNT_BT0_RX_BB1_VAL |
1887
+
B_BE_PTA_GNT_BT0_TX_BB1_VAL;
1888
+
1889
+
if (gnt_cfg->band[1].gnt_bt_sw_en)
1890
+
val |= B_BE_PTA_GNT_BT0_BB_SWCTRL | B_BE_PTA_GNT_BT0_RX_BB1_SWCTRL |
1891
+
B_BE_PTA_GNT_BT0_TX_BB1_SWCTRL;
1892
+
1893
+
if (gnt_cfg->band[1].gnt_wl)
1894
+
val |= B_BE_PTA_GNT_WL_BB1_VAL;
1895
+
1896
+
if (gnt_cfg->band[1].gnt_wl_sw_en)
1897
+
val |= B_BE_PTA_GNT_WL_BB1_SWCTRL;
1898
+
1899
+
if (gnt_cfg->bt[0].wlan_act_en)
1900
+
val |= B_BE_PTA_WL_ACT0_SWCTRL | B_BE_PTA_WL_ACT_RX_BT0_SWCTRL |
1901
+
B_BE_PTA_WL_ACT_TX_BT0_SWCTRL;
1902
+
if (gnt_cfg->bt[0].wlan_act)
1903
+
val |= B_BE_PTA_WL_ACT0_VAL | B_BE_PTA_WL_ACT_RX_BT0_VAL |
1904
+
B_BE_PTA_WL_ACT_TX_BT0_VAL;
1905
+
if (gnt_cfg->bt[1].wlan_act_en)
1906
+
val |= B_BE_PTA_WL_ACT1_SWCTRL | B_BE_PTA_WL_ACT_RX_BT1_SWCTRL |
1907
+
B_BE_PTA_WL_ACT_TX_BT1_SWCTRL;
1908
+
if (gnt_cfg->bt[1].wlan_act)
1909
+
val |= B_BE_PTA_WL_ACT1_VAL | B_BE_PTA_WL_ACT_RX_BT1_VAL |
1910
+
B_BE_PTA_WL_ACT_TX_BT1_VAL;
1911
+
1912
+
rtw89_write32(rtwdev, R_BE_PTA_GNT_SW_CTRL, val);
1913
+
1914
+
return 0;
1915
+
}
1916
+
EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v3);
1917
+
2327
1918
int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl)
2328
1919
{
2329
1920
struct rtw89_btc *btc = &rtwdev->btc;
2330
1921
struct rtw89_btc_dm *dm = &btc->dm;
2331
1922
struct rtw89_mac_ax_gnt *g = dm->gnt.band;
2332
1923
struct rtw89_mac_ax_wl_act *gbt = dm->gnt.bt;
1924
+
const struct rtw89_chip_info *chip = rtwdev->chip;
2333
1925
int i;
2334
1926
2335
1927
if (wl)
···
2397
1883
gbt[i].wlan_act_en = 0;
2398
1884
}
2399
1885
2400
-
return rtw89_mac_cfg_gnt_v2(rtwdev, &dm->gnt);
1886
+
if (chip->chip_id == RTL8922A)
1887
+
return rtw89_mac_cfg_gnt_v2(rtwdev, &dm->gnt);
1888
+
else
1889
+
return rtw89_mac_cfg_gnt_v3(rtwdev, &dm->gnt);
1890
+
2401
1891
}
2402
1892
EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v2);
2403
1893
···
2528
2010
rtw89_write32_mask(rtwdev, reg, B_BE_DRV_INFO_PHYRPT_EN, enable);
2529
2011
}
2530
2012
EXPORT_SYMBOL(rtw89_mac_cfg_phy_rpt_be);
2013
+
2014
+
static
2015
+
void rtw89_mac_set_edcca_mode_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool normal)
2016
+
{
2017
+
u16 resp_ack, resp_rts, resp_rts_punc, resp_normal, resp_normal_punc;
2018
+
2019
+
if (rtwdev->chip->chip_id == RTL8922A)
2020
+
return;
2021
+
2022
+
resp_ack = RESP_ACK_CFG_BE;
2023
+
resp_rts = RESP_RTS_CFG_BE;
2024
+
resp_rts_punc = RESP_RTS_PUNC_CFG_BE;
2025
+
resp_normal = RESP_NORMAL_CFG_BE;
2026
+
resp_normal_punc = RESP_NORMAL_PUNC_CFG_BE;
2027
+
2028
+
if (normal) {
2029
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_LEGACY,
2030
+
resp_ack, mac_idx);
2031
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_HE,
2032
+
resp_ack, mac_idx);
2033
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC,
2034
+
resp_ack, mac_idx);
2035
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_RTS_RESP_LEGACY,
2036
+
resp_rts, mac_idx);
2037
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_RTS_RESP_LEGACY_PUNC,
2038
+
resp_rts_punc, mac_idx);
2039
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_MURTS_RESP_LEGACY,
2040
+
resp_normal, mac_idx);
2041
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_MURTS_RESP_LEGACY_PUNC,
2042
+
resp_normal_punc, mac_idx);
2043
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_LEGACY,
2044
+
resp_normal, mac_idx);
2045
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_HE,
2046
+
resp_normal_punc, mac_idx);
2047
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_EHT_LEG_PUNC,
2048
+
resp_normal_punc, mac_idx);
2049
+
} else {
2050
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_LEGACY,
2051
+
resp_normal, mac_idx);
2052
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_HE,
2053
+
resp_normal_punc, mac_idx);
2054
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC,
2055
+
resp_normal_punc, mac_idx);
2056
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_RTS_RESP_LEGACY,
2057
+
resp_rts, mac_idx);
2058
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_RTS_RESP_LEGACY_PUNC,
2059
+
resp_rts_punc, mac_idx);
2060
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_MURTS_RESP_LEGACY,
2061
+
resp_normal, mac_idx);
2062
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_MURTS_RESP_LEGACY_PUNC,
2063
+
resp_normal_punc, mac_idx);
2064
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_LEGACY,
2065
+
resp_normal, mac_idx);
2066
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_HE,
2067
+
resp_normal_punc, mac_idx);
2068
+
rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_EHT_LEG_PUNC,
2069
+
resp_normal_punc, mac_idx);
2070
+
}
2071
+
}
2531
2072
2532
2073
static
2533
2074
int rtw89_mac_cfg_ppdu_status_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
···
3178
2601
.check_mac_en = rtw89_mac_check_mac_en_be,
3179
2602
.sys_init = sys_init_be,
3180
2603
.trx_init = trx_init_be,
2604
+
.preload_init = preload_init_be,
2605
+
.err_imr_ctrl = err_imr_ctrl_be,
2606
+
.mac_func_en = mac_func_en_be,
3181
2607
.hci_func_en = rtw89_mac_hci_func_en_be,
3182
2608
.dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_be,
3183
2609
.dle_func_en = dle_func_en_be,
···
3190
2610
.typ_fltr_opt = rtw89_mac_typ_fltr_opt_be,
3191
2611
.cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_be,
3192
2612
.cfg_phy_rpt = rtw89_mac_cfg_phy_rpt_be,
2613
+
.set_edcca_mode = rtw89_mac_set_edcca_mode_be,
3193
2614
3194
2615
.dle_mix_cfg = dle_mix_cfg_be,
3195
2616
.chk_dle_rdy = chk_dle_rdy_be,
···
3204
2623
.set_cpuio = set_cpuio_be,
3205
2624
.dle_quota_change = dle_quota_change_be,
3206
2625
2626
+
.reset_pwr_state = rtw89_mac_reset_pwr_state_be,
3207
2627
.disable_cpu = rtw89_mac_disable_cpu_be,
3208
2628
.fwdl_enable_wcpu = rtw89_mac_fwdl_enable_wcpu_be,
3209
2629
.fwdl_get_status = fwdl_get_status_be,
···
3214
2632
.parse_phycap_map = rtw89_parse_phycap_map_be,
3215
2633
.cnv_efuse_state = rtw89_cnv_efuse_state_be,
3216
2634
.efuse_read_fw_secure = rtw89_efuse_read_fw_secure_be,
2635
+
.efuse_read_ecv = rtw89_efuse_read_ecv_be,
3217
2636
3218
2637
.cfg_plt = rtw89_mac_cfg_plt_be,
3219
2638
.get_plt_cnt = rtw89_mac_get_plt_cnt_be,
+6
-1
drivers/net/wireless/realtek/rtw89/pci.c
+6
-1
drivers/net/wireless/realtek/rtw89/pci.c
···
604
604
605
605
info->parse_rpp(rtwdev, rpp, &rpp_info);
606
606
607
-
if (rpp_info.txch == RTW89_TXCH_CH12) {
607
+
if (unlikely(rpp_info.txch == RTW89_TXCH_CH12)) {
608
608
rtw89_warn(rtwdev, "should no fwcmd release report\n");
609
+
return;
610
+
}
611
+
612
+
if (unlikely(rpp_info.seq >= RTW89_PCI_TXWD_NUM_MAX)) {
613
+
rtw89_warn(rtwdev, "invalid seq %d\n", rpp_info.seq);
609
614
return;
610
615
}
611
616
+31
-25
drivers/net/wireless/realtek/rtw89/pci.h
+31
-25
drivers/net/wireless/realtek/rtw89/pci.h
···
55
55
#define B_AX_CALIB_EN BIT(13)
56
56
#define B_AX_DIV GENMASK(15, 14)
57
57
#define RAC_SET_PPR_V1 0x31
58
+
#define RAC_ANA41 0x41
59
+
#define PHY_ERR_FLAG_EN BIT(6)
58
60
59
61
#define R_AX_DBI_FLAG 0x1090
60
62
#define B_AX_DBI_RFLAG BIT(17)
···
146
144
#define R_RAC_DIRECT_OFFSET_BE_LANE1_G1 0x3880
147
145
#define R_RAC_DIRECT_OFFSET_BE_LANE0_G2 0x3900
148
146
#define R_RAC_DIRECT_OFFSET_BE_LANE1_G2 0x3980
147
+
148
+
#define RAC_DIRECT_OFFESET_L0_G1 0x3800
149
+
#define RAC_DIRECT_OFFESET_L1_G1 0x3900
150
+
#define RAC_DIRECT_OFFESET_L0_G2 0x3A00
151
+
#define RAC_DIRECT_OFFESET_L1_G2 0x3B00
149
152
150
153
#define RTW89_PCI_WR_RETRY_CNT 20
151
154
···
303
296
#define B_BE_PCIE_EN_AUX_CLK BIT(0)
304
297
305
298
#define R_BE_PCIE_PS_CTRL 0x3008
299
+
#define B_BE_ASPM_L11_EN BIT(19)
300
+
#define B_BE_ASPM_L12_EN BIT(18)
301
+
#define B_BE_PCIPM_L11_EN BIT(17)
302
+
#define B_BE_PCIPM_L12_EN BIT(16)
306
303
#define B_BE_RSM_L0S_EN BIT(8)
307
304
#define B_BE_CMAC_EXIT_L1_EN BIT(7)
308
305
#define B_BE_DMAC0_EXIT_L1_EN BIT(6)
···
778
767
#define R_AX_WP_ADDR_H_SEL8_11 0x133C
779
768
#define R_AX_WP_ADDR_H_SEL12_15 0x1340
780
769
781
-
#define R_BE_HAXI_DMA_STOP1 0xB010
782
-
#define B_BE_STOP_WPDMA BIT(31)
783
-
#define B_BE_STOP_CH14 BIT(14)
784
-
#define B_BE_STOP_CH13 BIT(13)
785
-
#define B_BE_STOP_CH12 BIT(12)
786
-
#define B_BE_STOP_CH11 BIT(11)
787
-
#define B_BE_STOP_CH10 BIT(10)
788
-
#define B_BE_STOP_CH9 BIT(9)
789
-
#define B_BE_STOP_CH8 BIT(8)
790
-
#define B_BE_STOP_CH7 BIT(7)
791
-
#define B_BE_STOP_CH6 BIT(6)
792
-
#define B_BE_STOP_CH5 BIT(5)
793
-
#define B_BE_STOP_CH4 BIT(4)
794
-
#define B_BE_STOP_CH3 BIT(3)
795
-
#define B_BE_STOP_CH2 BIT(2)
796
-
#define B_BE_STOP_CH1 BIT(1)
797
-
#define B_BE_STOP_CH0 BIT(0)
798
-
#define B_BE_TX_STOP1_MASK (B_BE_STOP_CH0 | B_BE_STOP_CH1 | \
799
-
B_BE_STOP_CH2 | B_BE_STOP_CH3 | \
800
-
B_BE_STOP_CH4 | B_BE_STOP_CH5 | \
801
-
B_BE_STOP_CH6 | B_BE_STOP_CH7 | \
802
-
B_BE_STOP_CH8 | B_BE_STOP_CH9 | \
803
-
B_BE_STOP_CH10 | B_BE_STOP_CH11 | \
804
-
B_BE_STOP_CH12)
805
-
806
770
#define R_BE_CH0_TXBD_NUM_V1 0xB030
807
771
#define R_BE_CH1_TXBD_NUM_V1 0xB032
808
772
#define R_BE_CH2_TXBD_NUM_V1 0xB034
···
960
974
#define R_BE_PCIE_CRPWM 0x30C4
961
975
962
976
#define R_BE_L1_2_CTRL_HCILDO 0x3110
977
+
#define B_BE_PM_CLKREQ_EXT_RB BIT(11)
978
+
#define B_BE_PCIE_DIS_RTK_PRST_N_L1_2 BIT(10)
979
+
#define B_BE_PCIE_PRST_IN_L1_2_RB BIT(9)
980
+
#define B_BE_PCIE_PRST_SEL_RB_V1 BIT(8)
981
+
#define B_BE_PCIE_DIS_L2_CTRL_APHY_SUSB BIT(7)
982
+
#define B_BE_PCIE_DIS_L1_2_CTRL_APHY_SUSB BIT(6)
963
983
#define B_BE_PCIE_DIS_L1_2_CTRL_HCILDO BIT(0)
964
984
965
985
#define R_BE_PL1_DBG_INFO 0x3120
···
1015
1023
#define B_BE_PL1_SER_PL1_EN BIT(31)
1016
1024
#define B_BE_PL1_IGNORE_HOT_RST BIT(30)
1017
1025
#define B_BE_PL1_TIMER_UNIT_MASK GENMASK(19, 17)
1026
+
#define PCIE_SER_TIMER_UNIT 0x2
1018
1027
#define B_BE_PL1_TIMER_CLEAR BIT(0)
1019
1028
1020
1029
#define R_BE_REG_PL1_MASK 0x34B0
1030
+
#define B_BE_SER_LTSSM_UNSTABLE_MASK BIT(6)
1021
1031
#define B_BE_SER_PCLKREQ_ACK_MASK BIT(5)
1022
1032
#define B_BE_SER_PM_CLK_MASK BIT(4)
1023
1033
#define B_BE_SER_LTSSM_IMR BIT(3)
···
1049
1055
#define B_BE_CLR_CH2_IDX BIT(2)
1050
1056
#define B_BE_CLR_CH1_IDX BIT(1)
1051
1057
#define B_BE_CLR_CH0_IDX BIT(0)
1058
+
#define B_BE_CLR_ALL_IDX_MASK (B_BE_CLR_CH0_IDX | B_BE_CLR_CH1_IDX | \
1059
+
B_BE_CLR_CH2_IDX | B_BE_CLR_CH3_IDX | \
1060
+
B_BE_CLR_CH4_IDX | B_BE_CLR_CH5_IDX | \
1061
+
B_BE_CLR_CH6_IDX | B_BE_CLR_CH7_IDX | \
1062
+
B_BE_CLR_CH8_IDX | B_BE_CLR_CH9_IDX | \
1063
+
B_BE_CLR_CH10_IDX | B_BE_CLR_CH11_IDX | \
1064
+
B_BE_CLR_CH12_IDX | B_BE_CLR_CH13_IDX | \
1065
+
B_BE_CLR_CH14_IDX)
1066
+
#define B_BE_CLR_ALL_IDX_MASK_V1 (B_BE_CLR_CH0_IDX | B_BE_CLR_CH2_IDX | \
1067
+
B_BE_CLR_CH4_IDX | B_BE_CLR_CH6_IDX | \
1068
+
B_BE_CLR_CH8_IDX | B_BE_CLR_CH10_IDX | \
1069
+
B_BE_CLR_CH12_IDX)
1052
1070
1053
1071
#define R_BE_RXBD_RWPTR_CLR1_V1 0xB018
1054
1072
#define B_BE_CLR_ROQ1_IDX_V1 BIT(5)
+115
-21
drivers/net/wireless/realtek/rtw89/pci_be.c
+115
-21
drivers/net/wireless/realtek/rtw89/pci_be.c
···
46
46
47
47
static void rtw89_pci_l1ss_set_be(struct rtw89_dev *rtwdev, bool enable)
48
48
{
49
+
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
50
+
struct rtw89_hal *hal = &rtwdev->hal;
51
+
52
+
if (enable && chip_id == RTL8922D && hal->cid == RTL8922D_CID7090)
53
+
rtw89_write32_set(rtwdev, R_BE_PCIE_PS_CTRL,
54
+
B_BE_ASPM_L11_EN | B_BE_ASPM_L12_EN |
55
+
B_BE_PCIPM_L11_EN | B_BE_PCIPM_L12_EN);
56
+
49
57
if (enable)
50
58
rtw89_write32_set(rtwdev, R_BE_PCIE_MIX_CFG,
51
59
B_BE_L1SUB_ENABLE);
···
162
154
163
155
rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val);
164
156
165
-
if (io_en == MAC_AX_PCIE_ENABLE)
157
+
if (io_en == MAC_AX_PCIE_ENABLE && rtwdev->chip->chip_id == RTL8922A)
166
158
rtw89_write32_mask(rtwdev, R_BE_HAXI_MST_WDT_TIMEOUT_SEL_V1,
167
159
B_BE_HAXI_MST_WDT_TIMEOUT_SEL_MASK, 4);
168
160
}
···
170
162
static void rtw89_pci_clr_idx_all_be(struct rtw89_dev *rtwdev)
171
163
{
172
164
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
165
+
const struct rtw89_chip_info *chip = rtwdev->chip;
173
166
struct rtw89_pci_rx_ring *rx_ring;
174
167
u32 val;
175
168
176
-
val = B_BE_CLR_CH0_IDX | B_BE_CLR_CH1_IDX | B_BE_CLR_CH2_IDX |
177
-
B_BE_CLR_CH3_IDX | B_BE_CLR_CH4_IDX | B_BE_CLR_CH5_IDX |
178
-
B_BE_CLR_CH6_IDX | B_BE_CLR_CH7_IDX | B_BE_CLR_CH8_IDX |
179
-
B_BE_CLR_CH9_IDX | B_BE_CLR_CH10_IDX | B_BE_CLR_CH11_IDX |
180
-
B_BE_CLR_CH12_IDX | B_BE_CLR_CH13_IDX | B_BE_CLR_CH14_IDX;
169
+
if (chip->chip_id == RTL8922A)
170
+
val = B_BE_CLR_ALL_IDX_MASK;
171
+
else
172
+
val = B_BE_CLR_ALL_IDX_MASK_V1;
173
+
181
174
rtw89_write32(rtwdev, R_BE_TXBD_RWPTR_CLR1, val);
182
175
183
176
rtw89_write32(rtwdev, R_BE_RXBD_RWPTR_CLR1_V1,
···
193
184
194
185
static int rtw89_pci_poll_txdma_ch_idle_be(struct rtw89_dev *rtwdev)
195
186
{
187
+
const struct rtw89_pci_info *info = rtwdev->pci_info;
188
+
u32 dma_busy1 = info->dma_busy1.addr;
189
+
u32 check = info->dma_busy1.mask;
196
190
u32 val;
197
191
198
-
return read_poll_timeout(rtw89_read32, val, (val & DMA_BUSY1_CHECK_BE) == 0,
199
-
10, 1000, false, rtwdev, R_BE_HAXI_DMA_BUSY1);
192
+
return read_poll_timeout(rtw89_read32, val, (val & check) == 0,
193
+
10, 1000, false, rtwdev, dma_busy1);
200
194
}
201
195
202
196
static int rtw89_pci_poll_rxdma_ch_idle_be(struct rtw89_dev *rtwdev)
···
235
223
static void rtw89_pci_mode_op_be(struct rtw89_dev *rtwdev)
236
224
{
237
225
const struct rtw89_pci_info *info = rtwdev->pci_info;
226
+
const struct rtw89_chip_info *chip = rtwdev->chip;
238
227
u32 val32_init1, val32_rxapp, val32_exp;
239
228
240
229
val32_init1 = rtw89_read32(rtwdev, R_BE_HAXI_INIT_CFG1);
241
-
val32_rxapp = rtw89_read32(rtwdev, R_BE_RX_APPEND_MODE);
230
+
if (chip->chip_id == RTL8922A)
231
+
val32_rxapp = rtw89_read32(rtwdev, R_BE_RX_APPEND_MODE);
242
232
val32_exp = rtw89_read32(rtwdev, R_BE_HAXI_EXP_CTRL_V1);
243
233
244
-
if (info->rxbd_mode == MAC_AX_RXBD_PKT) {
245
-
val32_init1 = u32_replace_bits(val32_init1, PCIE_RXBD_NORM,
246
-
B_BE_RXQ_RXBD_MODE_MASK);
247
-
} else if (info->rxbd_mode == MAC_AX_RXBD_SEP) {
248
-
val32_init1 = u32_replace_bits(val32_init1, PCIE_RXBD_SEP,
249
-
B_BE_RXQ_RXBD_MODE_MASK);
250
-
val32_rxapp = u32_replace_bits(val32_rxapp, 0,
251
-
B_BE_APPEND_LEN_MASK);
234
+
if (chip->chip_id == RTL8922A) {
235
+
if (info->rxbd_mode == MAC_AX_RXBD_PKT) {
236
+
val32_init1 = u32_replace_bits(val32_init1, PCIE_RXBD_NORM,
237
+
B_BE_RXQ_RXBD_MODE_MASK);
238
+
} else if (info->rxbd_mode == MAC_AX_RXBD_SEP) {
239
+
val32_init1 = u32_replace_bits(val32_init1, PCIE_RXBD_SEP,
240
+
B_BE_RXQ_RXBD_MODE_MASK);
241
+
val32_rxapp = u32_replace_bits(val32_rxapp, 0,
242
+
B_BE_APPEND_LEN_MASK);
243
+
}
252
244
}
253
245
254
246
val32_init1 = u32_replace_bits(val32_init1, info->tx_burst,
···
267
251
B_BE_CFG_WD_PERIOD_ACTIVE_MASK);
268
252
269
253
rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val32_init1);
270
-
rtw89_write32(rtwdev, R_BE_RX_APPEND_MODE, val32_rxapp);
254
+
if (chip->chip_id == RTL8922A)
255
+
rtw89_write32(rtwdev, R_BE_RX_APPEND_MODE, val32_rxapp);
271
256
rtw89_write32(rtwdev, R_BE_HAXI_EXP_CTRL_V1, val32_exp);
272
257
}
273
258
···
294
277
295
278
static void rtw89_pci_ldo_low_pwr_be(struct rtw89_dev *rtwdev)
296
279
{
280
+
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
281
+
struct rtw89_hal *hal = &rtwdev->hal;
282
+
u32 clr;
283
+
297
284
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_PSUS_OFF_CAPC_EN);
298
285
rtw89_write32_set(rtwdev, R_BE_SYS_PAGE_CLK_GATED,
299
286
B_BE_SOP_OFFPOOBS_PC | B_BE_CPHY_AUXCLK_OP |
···
305
284
rtw89_write32_clr(rtwdev, R_BE_SYS_SDIO_CTRL, B_BE_PCIE_FORCE_IBX_EN |
306
285
B_BE_PCIE_DIS_L2_RTK_PERST |
307
286
B_BE_PCIE_DIS_L2__CTRL_LDO_HCI);
308
-
rtw89_write32_clr(rtwdev, R_BE_L1_2_CTRL_HCILDO, B_BE_PCIE_DIS_L1_2_CTRL_HCILDO);
287
+
288
+
if (chip_id == RTL8922D && hal->cid == RTL8922D_CID7090)
289
+
clr = B_BE_PCIE_DIS_L1_2_CTRL_HCILDO |
290
+
B_BE_PCIE_DIS_L1_2_CTRL_APHY_SUSB |
291
+
B_BE_PCIE_DIS_RTK_PRST_N_L1_2 |
292
+
B_BE_PCIE_DIS_L2_CTRL_APHY_SUSB;
293
+
else
294
+
clr = B_BE_PCIE_DIS_L1_2_CTRL_HCILDO;
295
+
296
+
rtw89_write32_clr(rtwdev, R_BE_L1_2_CTRL_HCILDO, clr);
309
297
}
310
298
311
299
static void rtw89_pci_pcie_setting_be(struct rtw89_dev *rtwdev)
···
330
300
331
301
rtw89_write32_set(rtwdev, R_BE_EFUSE_CTRL_2_V1, B_BE_R_SYM_AUTOLOAD_WITH_PMC_SEL);
332
302
rtw89_write32_set(rtwdev, R_BE_PCIE_LAT_CTRL, B_BE_SYM_AUX_CLK_SEL);
303
+
304
+
if (chip->chip_id != RTL8922D)
305
+
return;
306
+
307
+
rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_R_SYM_PRST_CPHY_RST);
308
+
rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_USUS_OFFCAPC_EN);
333
309
}
334
310
335
311
static void rtw89_pci_ser_setting_be(struct rtw89_dev *rtwdev)
336
312
{
313
+
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
314
+
struct rtw89_hal *hal = &rtwdev->hal;
337
315
u32 val32;
316
+
int ret;
317
+
318
+
if (chip_id == RTL8922D)
319
+
goto be2_chips;
320
+
else if (chip_id != RTL8922A)
321
+
return;
338
322
339
323
rtw89_write32(rtwdev, R_BE_PL1_DBG_INFO, 0x0);
340
324
rtw89_write32_set(rtwdev, R_BE_FWS1IMR, B_BE_PCIE_SER_TIMEOUT_INDIC_EN);
···
359
315
val32 |= B_BE_SER_PMU_IMR | B_BE_SER_L1SUB_IMR | B_BE_SER_PM_MASTER_IMR |
360
316
B_BE_SER_LTSSM_IMR | B_BE_SER_PM_CLK_MASK | B_BE_SER_PCLKREQ_ACK_MASK;
361
317
rtw89_write32(rtwdev, R_BE_REG_PL1_MASK, val32);
318
+
319
+
return;
320
+
321
+
be2_chips:
322
+
rtw89_write32_clr(rtwdev, R_BE_PCIE_SER_DBG, B_BE_PCIE_SER_FLUSH_RSTB);
323
+
rtw89_write32_set(rtwdev, R_BE_PCIE_SER_DBG, B_BE_PCIE_SER_FLUSH_RSTB);
324
+
325
+
rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
326
+
RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
327
+
rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
328
+
RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
329
+
rtw89_write16_set(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
330
+
RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
331
+
rtw89_write16_set(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
332
+
RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
333
+
334
+
val32 = rtw89_read32(rtwdev, R_BE_SER_PL1_CTRL);
335
+
val32 &= ~B_BE_PL1_SER_PL1_EN;
336
+
rtw89_write32(rtwdev, R_BE_SER_PL1_CTRL, val32);
337
+
338
+
ret = read_poll_timeout_atomic(rtw89_read32, val32, !val32,
339
+
1, 1000, false, rtwdev, R_BE_REG_PL1_ISR);
340
+
if (ret)
341
+
rtw89_warn(rtwdev, "[ERR] PCIE SER clear poll fail\n");
342
+
343
+
val32 = rtw89_read32(rtwdev, R_BE_REG_PL1_MASK);
344
+
val32 |= B_BE_SER_PMU_IMR | B_BE_SER_L1SUB_IMR | B_BE_SER_PM_MASTER_IMR |
345
+
B_BE_SER_LTSSM_IMR | B_BE_SER_PM_CLK_MASK | B_BE_SER_PCLKREQ_ACK_MASK |
346
+
B_BE_SER_LTSSM_UNSTABLE_MASK;
347
+
rtw89_write32(rtwdev, R_BE_REG_PL1_MASK, val32);
348
+
349
+
rtw89_write32_mask(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_TIMER_UNIT_MASK,
350
+
PCIE_SER_TIMER_UNIT);
351
+
rtw89_write32_set(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
352
+
353
+
if (hal->cid == RTL8922D_CID7090)
354
+
rtw89_write32_set(rtwdev, R_BE_SYS_SDIO_CTRL, B_BE_SER_DETECT_EN);
362
355
}
363
356
364
357
static void rtw89_pci_ctrl_txdma_ch_be(struct rtw89_dev *rtwdev, bool enable)
365
358
{
359
+
const struct rtw89_pci_info *info = rtwdev->pci_info;
366
360
u32 mask_all;
367
361
u32 val;
368
362
···
408
326
B_BE_STOP_CH3 | B_BE_STOP_CH4 | B_BE_STOP_CH5 |
409
327
B_BE_STOP_CH6 | B_BE_STOP_CH7 | B_BE_STOP_CH8 |
410
328
B_BE_STOP_CH9 | B_BE_STOP_CH10 | B_BE_STOP_CH11;
329
+
330
+
/* mask out unsupported channels for certains chips */
331
+
mask_all &= info->dma_stop1.mask;
411
332
412
333
val = rtw89_read32(rtwdev, R_BE_HAXI_DMA_STOP1);
413
334
val |= B_BE_STOP_CH13 | B_BE_STOP_CH14;
···
494
409
int rtw89_pci_ltr_set_v2(struct rtw89_dev *rtwdev, bool en)
495
410
{
496
411
u32 ctrl0, cfg0, cfg1, dec_ctrl, idle_ltcy, act_ltcy, dis_ltcy;
412
+
u32 ltr_idle_lat_ctrl, ltr_act_lat_ctrl;
497
413
498
414
ctrl0 = rtw89_read32(rtwdev, R_BE_LTR_CTRL_0);
499
415
if (rtw89_pci_ltr_is_err_reg_val(ctrl0))
···
537
451
cfg0 = u32_replace_bits(cfg0, 3, B_BE_LTR_IDX_IDLE_MASK);
538
452
dec_ctrl = u32_replace_bits(dec_ctrl, 0, B_BE_LTR_IDX_DISABLE_V1_MASK);
539
453
540
-
rtw89_write32(rtwdev, R_BE_LTR_LATENCY_IDX3_V1, 0x90039003);
541
-
rtw89_write32(rtwdev, R_BE_LTR_LATENCY_IDX1_V1, 0x880b880b);
454
+
if (rtwdev->chip->chip_id == RTL8922A) {
455
+
ltr_idle_lat_ctrl = 0x90039003;
456
+
ltr_act_lat_ctrl = 0x880b880b;
457
+
} else {
458
+
ltr_idle_lat_ctrl = 0x90019001;
459
+
ltr_act_lat_ctrl = 0x88018801;
460
+
}
461
+
462
+
rtw89_write32(rtwdev, R_BE_LTR_LATENCY_IDX3_V1, ltr_idle_lat_ctrl);
463
+
rtw89_write32(rtwdev, R_BE_LTR_LATENCY_IDX1_V1, ltr_act_lat_ctrl);
542
464
rtw89_write32(rtwdev, R_BE_LTR_LATENCY_IDX0_V1, 0);
543
465
rtw89_write32(rtwdev, R_BE_LTR_DECISION_CTRL_V1, dec_ctrl);
544
466
rtw89_write32(rtwdev, R_BE_LTR_CFG_0, cfg0);
+37
-20
drivers/net/wireless/realtek/rtw89/phy.c
+37
-20
drivers/net/wireless/realtek/rtw89/phy.c
···
281
281
struct cfg80211_bitrate_mask *mask = &rtwsta_link->mask;
282
282
u8 band = chan->band_type;
283
283
enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
284
-
u8 he_ltf = mask->control[nl_band].he_ltf;
285
-
u8 he_gi = mask->control[nl_band].he_gi;
284
+
u8 ltf, gi;
286
285
287
286
*fix_giltf_en = true;
288
287
···
292
293
else
293
294
*fix_giltf = RTW89_GILTF_2XHE08;
294
295
295
-
if (!(rtwsta_link->use_cfg_mask && link_sta->he_cap.has_he))
296
+
if (!rtwsta_link->use_cfg_mask)
296
297
return;
297
298
298
-
if (he_ltf == 2 && he_gi == 2) {
299
-
*fix_giltf = RTW89_GILTF_LGI_4XHE32;
300
-
} else if (he_ltf == 2 && he_gi == 0) {
301
-
*fix_giltf = RTW89_GILTF_SGI_4XHE08;
302
-
} else if (he_ltf == 1 && he_gi == 1) {
303
-
*fix_giltf = RTW89_GILTF_2XHE16;
304
-
} else if (he_ltf == 1 && he_gi == 0) {
305
-
*fix_giltf = RTW89_GILTF_2XHE08;
306
-
} else if (he_ltf == 0 && he_gi == 1) {
307
-
*fix_giltf = RTW89_GILTF_1XHE16;
308
-
} else if (he_ltf == 0 && he_gi == 0) {
309
-
*fix_giltf = RTW89_GILTF_1XHE08;
299
+
if (link_sta->eht_cap.has_eht) {
300
+
ltf = mask->control[nl_band].eht_ltf;
301
+
gi = mask->control[nl_band].eht_gi;
302
+
} else if (link_sta->he_cap.has_he) {
303
+
ltf = mask->control[nl_band].he_ltf;
304
+
gi = mask->control[nl_band].he_gi;
305
+
} else {
306
+
return;
310
307
}
308
+
309
+
if (ltf == 2 && gi == 2)
310
+
*fix_giltf = RTW89_GILTF_LGI_4XHE32;
311
+
else if (ltf == 2 && gi == 0)
312
+
*fix_giltf = RTW89_GILTF_SGI_4XHE08;
313
+
else if (ltf == 1 && gi == 1)
314
+
*fix_giltf = RTW89_GILTF_2XHE16;
315
+
else if (ltf == 1 && gi == 0)
316
+
*fix_giltf = RTW89_GILTF_2XHE08;
317
+
else if (ltf == 0 && gi == 1)
318
+
*fix_giltf = RTW89_GILTF_1XHE16;
319
+
else if (ltf == 0 && gi == 0)
320
+
*fix_giltf = RTW89_GILTF_1XHE08;
311
321
}
312
322
313
323
static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev,
···
3816
3808
{
3817
3809
int ret;
3818
3810
3819
-
rtw89_phy_rfk_report_prep(rtwdev);
3811
+
if (RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, &rtwdev->fw)) {
3812
+
rtw89_phy_rfk_report_prep(rtwdev);
3813
+
rtw89_fw_h2c_rf_pre_ntfy(rtwdev, phy_idx);
3814
+
ret = rtw89_phy_rfk_report_wait(rtwdev, "PRE_NTFY", ms);
3815
+
if (ret)
3816
+
return ret;
3817
+
}
3820
3818
3821
-
ret = rtw89_fw_h2c_rf_pre_ntfy(rtwdev, phy_idx);
3822
-
if (ret)
3823
-
return ret;
3819
+
if (RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY_MCC, &rtwdev->fw)) {
3820
+
ret = rtw89_fw_h2c_rf_pre_ntfy_mcc(rtwdev, phy_idx);
3821
+
if (ret)
3822
+
return ret;
3823
+
}
3824
3824
3825
-
return rtw89_phy_rfk_report_wait(rtwdev, "PRE_NTFY", ms);
3825
+
return 0;
3826
+
3826
3827
}
3827
3828
EXPORT_SYMBOL(rtw89_phy_rfk_pre_ntfy_and_wait);
3828
3829
+1
-1
drivers/net/wireless/realtek/rtw89/ps.c
+1
-1
drivers/net/wireless/realtek/rtw89/ps.c
+560
-6
drivers/net/wireless/realtek/rtw89/reg.h
+560
-6
drivers/net/wireless/realtek/rtw89/reg.h
···
149
149
#define R_AX_WLLPS_CTRL 0x0090
150
150
#define B_AX_LPSOP_ASWRM BIT(17)
151
151
#define B_AX_LPSOP_DSWRM BIT(9)
152
+
#define B_AX_FORCE_LEAVE_LPS BIT(3)
152
153
#define B_AX_DIS_WLBT_LPSEN_LOPC BIT(1)
153
154
#define SW_LPS_OPTION 0x0001A0B2
154
155
···
314
313
#define R_AX_IC_PWR_STATE 0x03F0
315
314
#define B_AX_WHOLE_SYS_PWR_STE_MASK GENMASK(25, 16)
316
315
#define B_AX_WLMAC_PWR_STE_MASK GENMASK(9, 8)
316
+
#define MAC_AX_MAC_OFF 0
317
+
#define MAC_AX_MAC_ON 1
318
+
#define MAC_AX_MAC_LPS 2
317
319
#define B_AX_UART_HCISYS_PWR_STE_MASK GENMASK(7, 6)
318
320
#define B_AX_SDIO_HCISYS_PWR_STE_MASK GENMASK(5, 4)
319
321
#define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2)
320
322
#define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)
321
323
322
324
#define R_AX_SPS_DIG_OFF_CTRL0 0x0400
325
+
#define B_AX_R1_L1_MASK GENMASK(7, 6)
323
326
#define B_AX_C3_L1_MASK GENMASK(5, 4)
327
+
#define B_AX_C2_L1_MASK GENMASK(3, 2)
324
328
#define B_AX_C1_L1_MASK GENMASK(1, 0)
325
329
326
330
#define R_AX_AFE_OFF_CTRL1 0x0444
···
609
603
610
604
#define R_AX_SER_DBG_INFO 0x8424
611
605
#define B_AX_L0_TO_L1_EVENT_MASK GENMASK(31, 28)
606
+
#define B_AX_SER_L1_COUNTER_MASK GENMASK(27, 24)
607
+
#define B_AX_RMAC_PPDU_HANG_CNT_MASK GENMASK(23, 16)
608
+
#define B_AX_SER_L0_COUNTER_MASK GENMASK(7, 0)
612
609
613
610
#define R_AX_DLE_EMPTY0 0x8430
614
611
#define B_AX_PLE_EMPTY_QTA_DMAC_CPUIO BIT(26)
···
1967
1958
#define B_AX_B0_PRELD_FEN BIT(31)
1968
1959
#define B_AX_B0_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
1969
1960
#define PRELD_B0_ENT_NUM 10
1961
+
#define PRELD_B01_ENT_NUM_8922D 2
1970
1962
#define PRELD_AMSDU_SIZE 52
1963
+
#define PRELD_NEXT_MIN_SIZE 255
1971
1964
#define B_AX_B0_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)
1972
1965
#define B_AX_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
1973
1966
···
2105
2094
#define B_AX_B1_ISR_ERR_USRCTL_REINIT BIT(0)
2106
2095
2107
2096
#define R_AX_AFE_CTRL1 0x0024
2097
+
#define B_AX_CMAC_CLK_SEL BIT(21)
2108
2098
2109
2099
#define B_AX_R_SYM_WLCMAC1_P4_PC_EN BIT(4)
2110
2100
#define B_AX_R_SYM_WLCMAC1_P3_PC_EN BIT(3)
···
2118
2106
#define B_AX_R_SYM_FEN_WLBBGLB_1 BIT(17)
2119
2107
#define B_AX_R_SYM_FEN_WLBBFUN_1 BIT(16)
2120
2108
#define B_AX_R_SYM_ISO_CMAC12PP BIT(5)
2109
+
2110
+
#define R_AX_SYSON_FSM_MON 0x00A0
2111
+
#define B_AX_FSM_MON_SEL_MASK GENMASK(26, 24)
2112
+
#define B_AX_DOP_ELDO BIT(23)
2113
+
#define B_AX_FSM_MON_UPD BIT(15)
2114
+
#define B_AX_FSM_PAR_MASK GENMASK(14, 0)
2121
2115
2122
2116
#define R_AX_CMAC_REG_START 0xC000
2123
2117
···
3831
3813
#define B_BE_EN_WLON BIT(16)
3832
3814
#define B_BE_APDM_HPDN BIT(15)
3833
3815
#define B_BE_PSUS_OFF_CAPC_EN BIT(14)
3816
+
#define B_BE_USUS_OFFCAPC_EN BIT(13)
3834
3817
#define B_BE_AFSM_PCIE_SUS_EN BIT(12)
3835
3818
#define B_BE_AFSM_WLSUS_EN BIT(11)
3836
3819
#define B_BE_APFM_SWLPS BIT(10)
···
3900
3881
#define B_BE_SYM_PADPDN_WL_RFC0_1P3 BIT(5)
3901
3882
3902
3883
#define R_BE_RSV_CTRL 0x001C
3884
+
#define B_BE_R_SYM_PRST_CPHY_RST BIT(25)
3885
+
#define B_BE_R_SYM_PRST_PDN_EN BIT(24)
3903
3886
#define B_BE_HR_BE_DBG GENMASK(23, 12)
3904
3887
#define B_BE_R_SYM_DIS_PCIE_FLR BIT(9)
3905
3888
#define B_BE_R_EN_HRST_PWRON BIT(8)
···
3948
3927
#define B_BE_R_SYM_WLCMAC0_P2_PC_EN BIT(26)
3949
3928
#define B_BE_R_SYM_WLCMAC0_P1_PC_EN BIT(25)
3950
3929
#define B_BE_R_SYM_WLCMAC0_PC_EN BIT(24)
3930
+
#define B_BE_R_SYM_WLCMAC0_ALL_EN (B_BE_R_SYM_WLCMAC0_PC_EN | \
3931
+
B_BE_R_SYM_WLCMAC0_P1_PC_EN | \
3932
+
B_BE_R_SYM_WLCMAC0_P2_PC_EN | \
3933
+
B_BE_R_SYM_WLCMAC0_P3_PC_EN | \
3934
+
B_BE_R_SYM_WLCMAC0_P4_PC_EN)
3951
3935
#define B_BE_DATAMEM_PC3_EN BIT(23)
3952
3936
#define B_BE_DATAMEM_PC2_EN BIT(22)
3953
3937
#define B_BE_DATAMEM_PC1_EN BIT(21)
···
3974
3948
#define B_BE_R_SYM_WLCMAC1_P2_PC_EN BIT(2)
3975
3949
#define B_BE_R_SYM_WLCMAC1_P1_PC_EN BIT(1)
3976
3950
#define B_BE_R_SYM_WLCMAC1_PC_EN BIT(0)
3977
-
#define B_BE_AFE_CTRL1_SET (B_BE_R_SYM_WLCMAC1_PC_EN | \
3978
-
B_BE_R_SYM_WLCMAC1_P1_PC_EN | \
3979
-
B_BE_R_SYM_WLCMAC1_P2_PC_EN | \
3980
-
B_BE_R_SYM_WLCMAC1_P3_PC_EN | \
3981
-
B_BE_R_SYM_WLCMAC1_P4_PC_EN)
3951
+
#define B_BE_R_SYM_WLCMAC1_ALL_EN (B_BE_R_SYM_WLCMAC1_PC_EN | \
3952
+
B_BE_R_SYM_WLCMAC1_P1_PC_EN | \
3953
+
B_BE_R_SYM_WLCMAC1_P2_PC_EN | \
3954
+
B_BE_R_SYM_WLCMAC1_P3_PC_EN | \
3955
+
B_BE_R_SYM_WLCMAC1_P4_PC_EN)
3982
3956
3983
3957
#define R_BE_EFUSE_CTRL 0x0030
3984
3958
#define B_BE_EF_MODE_SEL_MASK GENMASK(31, 30)
···
4041
4015
4042
4016
#define R_BE_SYS_SDIO_CTRL 0x0070
4043
4017
#define B_BE_MCM_FLASH_EN BIT(28)
4018
+
#define B_BE_SER_DETECT_EN BIT(26)
4044
4019
#define B_BE_PCIE_SEC_LOAD BIT(26)
4045
4020
#define B_BE_PCIE_SER_RSTB BIT(25)
4046
4021
#define B_BE_PCIE_SEC_LOAD_CLR BIT(24)
···
4199
4172
#define B_BE_LPSROP_LOWPWRPLL BIT(7)
4200
4173
#define B_BE_LPSROP_DSWRSD_SEL_MASK GENMASK(5, 4)
4201
4174
4175
+
#define R_BE_SYSON_FSM_MON 0x00A0
4176
+
#define B_BE_FSM_MON_SEL_MASK GENMASK(26, 24)
4177
+
#define B_BE_DOP_ELDO BIT(23)
4178
+
#define B_BE_AFE_PLL_BYPASS BIT(22)
4179
+
#define B_BE_PON_SWR_BYPASS BIT(21)
4180
+
#define B_BE_PON_ADIE_BYPASS BIT(20)
4181
+
#define B_BE_AFE_LS_BYPASS BIT(19)
4182
+
#define B_BE_BTPMC_XTAL_SI_BYPASS BIT(17)
4183
+
#define B_BE_WLPMC_XTAL_SI_BYPASS BIT(16)
4184
+
#define B_BE_FSM_MON_UPD BIT(15)
4185
+
#define B_BE_FSM_PAR_MASK GENMASK(14, 0)
4186
+
#define WLAN_FSM_MASK 0xFFFFFF
4187
+
#define WLAN_FSM_SET 0x4000000
4188
+
#define WLAN_FSM_STATE_MASK 0x1FF
4189
+
#define WLAN_FSM_IDLE 0
4190
+
4202
4191
#define R_BE_EFUSE_CTRL_2_V1 0x00A4
4203
4192
#define B_BE_EF_ENT BIT(31)
4204
4193
#define B_BE_EF_TCOLUMN_EN BIT(29)
···
4230
4187
#define B_BE_EF_HT_SEL BIT(12)
4231
4188
#define B_BE_EF_DSB_EN BIT(11)
4232
4189
#define B_BE_EF_DLY_SEL_MASK GENMASK(3, 0)
4190
+
4191
+
#define R_BE_SCOREBOARD 0x00AC
4192
+
#define B_BE_TOGGLE BIT(31)
4193
+
#define B_BE_DATA_LINE_MASK GENMASK(30, 0)
4233
4194
4234
4195
#define R_BE_PMC_DBG_CTRL2 0x00CC
4235
4196
#define B_BE_EFUSE_BURN_GNT_MASK GENMASK(31, 24)
···
4283
4236
4284
4237
#define R_BE_PCIE_MIO_INTD 0x00E8
4285
4238
#define B_BE_PCIE_MIO_DATA_MASK GENMASK(31, 0)
4239
+
4240
+
#define R_BE_SYS_CHIPINFO 0x00FC
4241
+
#define B_BE_USB2_SEL BIT(31)
4242
+
#define B_BE_U3PHY_RST_V1 BIT(30)
4243
+
#define B_BE_U3_TERM_DETECT BIT(29)
4244
+
#define B_BE_VERIFY_ENV_MASK GENMASK(9, 8)
4245
+
#define B_BE_HW_ID_MASK GENMASK(7, 0)
4286
4246
4287
4247
#define R_BE_HALT_H2C_CTRL 0x0160
4288
4248
#define B_BE_HALT_H2C_TRIGGER BIT(0)
···
4501
4447
#define B_BE_WL_XTAL_SI_DATA_MASK GENMASK(15, 8)
4502
4448
#define B_BE_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)
4503
4449
4450
+
#define R_BE_PCIE_SER_DBG 0x02FC
4451
+
#define B_BE_PCIE_SER_DBG_MASK GENMASK(31, 10)
4452
+
#define B_BE_PCIE_SER_PHY_PROTECT BIT(9)
4453
+
#define B_BE_PCIE_SER_MAC_PROTECT BIT(8)
4454
+
#define B_BE_PCIE_SER_FLUSH_RSTB BIT(4)
4455
+
#define B_BE_PCIE_AXI_BRG_FLUSH_EN BIT(3)
4456
+
#define B_BE_PCIE_SER_AUXCLK_RDY BIT(2)
4457
+
#define B_BE_PCIE_SER_FRZ_REG_RST BIT(1)
4458
+
#define B_BE_PCIE_SER_FRZ_CFG_SPC_RST BIT(0)
4459
+
4504
4460
#define R_BE_IC_PWR_STATE 0x03F0
4505
4461
#define B_BE_WHOLE_SYS_PWR_STE_MASK GENMASK(25, 16)
4506
4462
#define MAC_AX_SYS_ACT 0x220
···
4663
4599
#define R_BE_LTR_LATENCY_IDX2_V1 0x361C
4664
4600
#define R_BE_LTR_LATENCY_IDX3_V1 0x3620
4665
4601
4602
+
#define R_BE_HCI_BUF_IMR 0x6018
4603
+
#define B_BE_HCI_BUF_IMR_CLR 0xC0000303
4604
+
#define B_BE_HCI_BUF_IMR_SET 0xC0000301
4605
+
4666
4606
#define R_BE_H2CREG_DATA0 0x7140
4667
4607
#define R_BE_H2CREG_DATA1 0x7144
4668
4608
#define R_BE_H2CREG_DATA2 0x7148
···
4761
4693
#define B_BE_LTR_CMAC1_RX_USE_PG_TH_MASK GENMASK(27, 16)
4762
4694
#define B_BE_LTR_CMAC0_RX_USE_PG_TH_MASK GENMASK(11, 0)
4763
4695
4696
+
#define R_BE_NO_RX_ERR_CFG 0x841C
4697
+
#define B_BE_NO_RX_ERR_TO_MASK GENMASK(31, 29)
4698
+
4764
4699
#define R_BE_DMAC_TABLE_CTRL 0x8420
4765
4700
#define B_BE_HWAMSDU_PADDING_MODE BIT(31)
4766
4701
#define B_BE_MACID_MPDU_PROCESSOR_OFFSET_MASK GENMASK(26, 16)
···
4775
4704
#define B_BE_SER_L0_PROMOTE_L1_EVENT_MASK GENMASK(31, 28)
4776
4705
#define B_BE_SER_L1_COUNTER_MASK GENMASK(27, 24)
4777
4706
#define B_BE_RMAC_PPDU_HANG_CNT_MASK GENMASK(23, 16)
4778
-
#define B_BE_SER_L0_COUNTER_MASK GENMASK(8, 0)
4707
+
#define B_BE_SER_L0_COUNTER_MASK GENMASK(7, 0)
4779
4708
4780
4709
#define R_BE_DMAC_SYS_CR32B 0x842C
4781
4710
#define B_BE_DMAC_BB_PHY1_MASK GENMASK(31, 16)
···
5097
5026
B_BE_STF_WRFF_UNDERFLOW_ERR_INT_EN | \
5098
5027
B_BE_STF_OQT_OVERFLOW_ERR_INT_EN | \
5099
5028
B_BE_STF_OQT_UNDERFLOW_ERR_INT_EN)
5029
+
#define B_BE_DISP_OTHER_IMR_CLR_V1 0xFFFFFFFF
5030
+
#define B_BE_DISP_OTHER_IMR_SET_V1 0x3F002000
5100
5031
5101
5032
#define R_BE_DISP_HOST_IMR 0x8874
5102
5033
#define B_BE_HR_WRFF_UNDERFLOW_ERR_INT_EN BIT(31)
···
5176
5103
B_BE_HR_DMA_PROCESS_ERR_INT_EN | \
5177
5104
B_BE_HR_WRFF_OVERFLOW_ERR_INT_EN | \
5178
5105
B_BE_HR_WRFF_UNDERFLOW_ERR_INT_EN)
5106
+
#define B_BE_DISP_HOST_IMR_CLR_V1 0xFBFFFFFF
5107
+
#define B_BE_DISP_HOST_IMR_SET_V1 0xC8B3E579
5179
5108
5180
5109
#define R_BE_DISP_CPU_IMR 0x8878
5181
5110
#define B_BE_CR_PLD_LEN_ERR_INT_EN BIT(30)
···
5252
5177
B_BE_CR_DMA_PROCESS_ERR_INT_EN | \
5253
5178
B_BE_CR_WRFF_OVERFLOW_ERR_INT_EN | \
5254
5179
B_BE_CR_WRFF_UNDERFLOW_ERR_INT_EN)
5180
+
#define B_BE_DISP_CPU_IMR_CLR_V1 0x7DFFFFFD
5181
+
#define B_BE_DISP_CPU_IMR_SET_V1 0x34F938FD
5255
5182
5256
5183
#define R_BE_RX_STOP 0x8914
5257
5184
#define B_BE_CPU_RX_STOP BIT(17)
···
5548
5471
#define B_BE_PLE_Q12_MAX_SIZE_MASK GENMASK(27, 16)
5549
5472
#define B_BE_PLE_Q12_MIN_SIZE_MASK GENMASK(11, 0)
5550
5473
5474
+
#define R_BE_PLE_QTA13_CFG 0x9074
5475
+
#define B_BE_PLE_Q13_MAX_SIZE_MASK GENMASK(27, 16)
5476
+
#define B_BE_PLE_Q13_MIN_SIZE_MASK GENMASK(11, 0)
5477
+
5551
5478
#define R_BE_PLE_ERRFLAG1_IMR 0x90C0
5552
5479
#define B_BE_PLE_SRCHPG_PGOFST_IMR BIT(26)
5553
5480
#define B_BE_PLE_SRCHPG_STRPG_IMR BIT(25)
···
5609
5528
B_BE_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \
5610
5529
B_BE_WDRLS_RPT1_FRZTO_ERR_INT_EN)
5611
5530
5531
+
#define R_BE_RLSRPT0_CFG0 0x9440
5532
+
#define B_BE_RLSRPT0_FWRLS BIT(31)
5533
+
#define B_BE_RLSRPT0_FWD_TRGT_MASK GENMASK(23, 16)
5534
+
#define B_BE_RLSRPT0_PID_MASK GENMASK(10, 8)
5535
+
#define B_BE_RLSRPT0_QID_MASK GENMASK(5, 0)
5536
+
#define WDRLS_DEST_QID_POH 1
5537
+
#define WDRLS_DEST_QID_STF 0
5538
+
5612
5539
#define R_BE_RLSRPT0_CFG1 0x9444
5540
+
#define B_BE_RLSRPT0_FLTR_MAP_V1_MASK GENMASK(28, 24)
5541
+
#define S_BE_WDRLS_FLTR_TXOK_V1 BIT(0)
5542
+
#define S_BE_WDRLS_FLTR_RTYLMT_V1 BIT(1)
5543
+
#define S_BE_WDRLS_FLTR_LIFTIM_V1 BIT(2)
5544
+
#define S_BE_WDRLS_FLTR_MACID_V1 BIT(3)
5545
+
#define S_BE_WDRLS_FLTR_RELINK_V1 BIT(4)
5613
5546
#define B_BE_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24)
5614
5547
#define S_BE_WDRLS_FLTR_TXOK 1
5615
5548
#define S_BE_WDRLS_FLTR_RTYLMT 2
···
5917
5822
#define B_BE_MPDUINFO_PKTID_MASK GENMASK(27, 16)
5918
5823
#define B_BE_MPDUINFO_B1_BADDR_MASK GENMASK(5, 0)
5919
5824
#define MPDU_INFO_B1_OFST 18
5825
+
#define MPDU_INFO_TBL_FACTOR 3
5920
5826
5921
5827
#define R_BE_TXPKTCTL_B0_PRELD_CFG0 0x9F48
5922
5828
#define B_BE_B0_PRELD_FEN BIT(31)
5923
5829
#define B_BE_B0_PRELD_USEMAXSZ_MASK GENMASK(25, 16)
5924
5830
#define B_BE_B0_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8)
5831
+
#define PRELD_MISCQ_ENT_NUM_8922A 2
5832
+
#define PRELD_MISCQ_ENT_NUM_8922D 1
5925
5833
#define B_BE_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0)
5834
+
#define PRELD_B0_ACQ_ENT_NUM_8922A 8
5835
+
#define PRELD_B1_ACQ_ENT_NUM_8922A 2
5836
+
#define PRELD_ACQ_ENT_NUM_8922D 1
5926
5837
5927
5838
#define R_BE_TXPKTCTL_B0_PRELD_CFG1 0x9F4C
5928
5839
#define B_BE_B0_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8)
···
6040
5939
#define B_BE_PLRLS_CTL_FRZTO_ISR BIT(0)
6041
5940
6042
5941
#define R_BE_SS_CTRL 0xA310
5942
+
#define R_BE_SS_CTRL_V1 0xA610
6043
5943
#define B_BE_SS_INIT_DONE BIT(31)
6044
5944
#define B_BE_WDE_STA_DIS BIT(30)
6045
5945
#define B_BE_WARM_INIT BIT(29)
···
6079
5977
#define B_BE_PLE_B_PKTID_ERR_ISR BIT(2)
6080
5978
#define B_BE_RPT_TIMEOUT_ISR BIT(1)
6081
5979
#define B_BE_SEARCH_TIMEOUT_ISR BIT(0)
5980
+
5981
+
#define R_BE_PLRLS_ERR_IMR_V1 0xA518
5982
+
#define B_BE_PLRLS_DUMMY_ISR6 BIT(7)
5983
+
#define B_BE_PLRLS_DUMMY_ISR5 BIT(6)
5984
+
#define B_BE_PLRLS_DUMMY_ISR4 BIT(5)
5985
+
#define B_BE_PLRLS_DUMMY_ISR3 BIT(4)
5986
+
#define B_BE_PLRLS_DUMMY_ISR2 BIT(3)
5987
+
#define B_BE_PLRLS_DUMMY_ISR1 BIT(2)
5988
+
#define B_BE_PLRLS_DUMMY_ISR0 BIT(1)
5989
+
#define B_BE_PLRLS_ERR_IMR_V1_CLR 0x1
5990
+
#define B_BE_PLRLS_ERR_IMR_V1_SET 0x1
5991
+
5992
+
#define R_BE_SS_LITE_TXL_MACID 0xA790
5993
+
#define B_BE_RPT_OTHER_BAND_EN BIT(31)
5994
+
#define B_BE_TXL_CMD_EN BIT(30)
5995
+
#define B_BE_TXL_READ_MACID_MASK GENMASK(29, 20)
5996
+
#define B_BE_TXL_MACID_1_MASK GENMASK(19, 10)
5997
+
#define B_BE_TXL_MACID_0_MASK GENMASK(9, 0)
6082
5998
6083
5999
#define R_BE_HAXI_INIT_CFG1 0xB000
6084
6000
#define B_BE_CFG_WD_PERIOD_IDLE_MASK GENMASK(31, 28)
···
6137
6017
#define B_BE_STOP_CH2 BIT(2)
6138
6018
#define B_BE_STOP_CH1 BIT(1)
6139
6019
#define B_BE_STOP_CH0 BIT(0)
6020
+
#define B_BE_TX_STOP1_MASK (B_BE_STOP_CH0 | B_BE_STOP_CH1 | \
6021
+
B_BE_STOP_CH2 | B_BE_STOP_CH3 | \
6022
+
B_BE_STOP_CH4 | B_BE_STOP_CH5 | \
6023
+
B_BE_STOP_CH6 | B_BE_STOP_CH7 | \
6024
+
B_BE_STOP_CH8 | B_BE_STOP_CH9 | \
6025
+
B_BE_STOP_CH10 | B_BE_STOP_CH11 | \
6026
+
B_BE_STOP_CH12 | B_BE_STOP_CH13 | \
6027
+
B_BE_STOP_CH14)
6028
+
#define B_BE_TX_STOP1_MASK_V1 (B_BE_STOP_CH0 | B_BE_STOP_CH2 | \
6029
+
B_BE_STOP_CH4 | B_BE_STOP_CH6 | \
6030
+
B_BE_STOP_CH8 | B_BE_STOP_CH10 | \
6031
+
B_BE_STOP_CH12)
6140
6032
6141
6033
#define R_BE_HAXI_MST_WDT_TIMEOUT_SEL_V1 0xB02C
6142
6034
#define B_BE_HAXI_MST_WDT_TIMEOUT_SEL_MASK GENMASK(4, 0)
···
6201
6069
6202
6070
#define R_BE_CH_PAGE_CTRL 0xB704
6203
6071
#define B_BE_PREC_PAGE_CH12_V1_MASK GENMASK(21, 16)
6072
+
#define B_BE_FULL_WD_PG_MASK GENMASK(15, 8)
6204
6073
#define B_BE_PREC_PAGE_CH011_V1_MASK GENMASK(5, 0)
6205
6074
6206
6075
#define R_BE_CH0_PAGE_CTRL 0xB718
···
6234
6101
#define R_BE_WP_PAGE_CTRL1 0xB7A4
6235
6102
#define B_BE_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16)
6236
6103
#define B_BE_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0)
6104
+
#define B_BE_FULL_PAGE_WP_CH811_MASK GENMASK(31, 24)
6105
+
#define B_BE_PREC_PAGE_WP_CH811_V1_MASK GENMASK(23, 16)
6106
+
#define B_BE_FULL_PAGE_WP_CH07_MASK GENMASK(15, 8)
6107
+
#define B_BE_PREC_PAGE_WP_CH07_V1_MASK GENMASK(7, 0)
6237
6108
6238
6109
#define R_BE_WP_PAGE_CTRL2 0xB7A8
6239
6110
#define B_BE_WP_THRD_MASK GENMASK(12, 0)
···
6295
6158
#define B_BE_GNT_WL_BB0_SWCTRL BIT(2)
6296
6159
#define B_BE_GNT_WL_BB_PWR_VAL BIT(1)
6297
6160
#define B_BE_GNT_WL_BB_PWR_SWCTRL BIT(0)
6161
+
6162
+
#define R_BE_PTA_GNT_SW_CTRL 0x0E348
6163
+
#define B_BE_PTA_WL_ACT0_VAL BIT(19)
6164
+
#define B_BE_PTA_WL_ACT0_SWCTRL BIT(18)
6165
+
#define B_BE_PTA_GNT_BT0_RX_BB1_VAL BIT(17)
6166
+
#define B_BE_PTA_GNT_BT0_RX_BB1_SWCTRL BIT(16)
6167
+
#define B_BE_PTA_GNT_BT0_TX_BB1_VAL BIT(15)
6168
+
#define B_BE_PTA_GNT_BT0_TX_BB1_SWCTRL BIT(14)
6169
+
#define B_BE_PTA_GNT_BT0_RX_BB0_VAL BIT(13)
6170
+
#define B_BE_PTA_GNT_BT0_RX_BB0_SWCTRL BIT(12)
6171
+
#define B_BE_PTA_GNT_BT0_TX_BB0_VAL BIT(11)
6172
+
#define B_BE_PTA_GNT_BT0_TX_BB0_SWCTRL BIT(10)
6173
+
#define B_BE_PTA_GNT_BT0_BB_VAL BIT(9)
6174
+
#define B_BE_PTA_GNT_BT0_BB_SWCTRL BIT(8)
6175
+
#define B_BE_PTA_WL_ACT_RX_BT0_VAL BIT(7)
6176
+
#define B_BE_PTA_WL_ACT_RX_BT0_SWCTRL BIT(6)
6177
+
#define B_BE_PTA_WL_ACT_TX_BT0_VAL BIT(5)
6178
+
#define B_BE_PTA_WL_ACT_TX_BT0_SWCTRL BIT(4)
6179
+
#define B_BE_PTA_GNT_WL_BB1_VAL BIT(3)
6180
+
#define B_BE_PTA_GNT_WL_BB1_SWCTRL BIT(2)
6181
+
#define B_BE_PTA_GNT_WL_BB0_VAL BIT(1)
6182
+
#define B_BE_PTA_GNT_WL_BB0_SWCTRL BIT(0)
6183
+
6184
+
#define R_BE_PTA_GNT_VAL 0x0E34C
6185
+
#define B_BE_PTA_WL_ACT2 BIT(20)
6186
+
#define B_BE_PTA_GNT_ZB_TX_BB1 BIT(19)
6187
+
#define B_BE_PTA_GNT_ZB_TX_BB0 BIT(18)
6188
+
#define B_BE_PTA_WL_ACT1 BIT(17)
6189
+
#define B_BE_PTA_GNT_BT1_RX_BB1 BIT(16)
6190
+
#define B_BE_PTA_GNT_BT1_RX_BB0 BIT(15)
6191
+
#define B_BE_PTA_GNT_BT1_TX_BB1 BIT(14)
6192
+
#define B_BE_PTA_GNT_BT1_TX_BB0 BIT(13)
6193
+
#define B_BE_PTA_WL_ACT_RX_BT1 BIT(12)
6194
+
#define B_BE_PTA_WL_ACT_TX_BT1 BIT(11)
6195
+
#define B_BE_PTA_GNT_BT1_BB BIT(10)
6196
+
#define B_BE_PTA_WL_ACT0 BIT(9)
6197
+
#define B_BE_PTA_GNT_BT0_RX_BB1 BIT(8)
6198
+
#define B_BE_PTA_GNT_BT0_TX_BB1 BIT(7)
6199
+
#define B_BE_PTA_GNT_BT0_RX_BB0 BIT(6)
6200
+
#define B_BE_PTA_GNT_BT0_TX_BB0 BIT(5)
6201
+
#define B_BE_PTA_GNT_BT0_BB BIT(4)
6202
+
#define B_BE_PTA_WL_ACT_RX_BT0 BIT(3)
6203
+
#define B_BE_PTA_WL_ACT_TX_BT0 BIT(2)
6204
+
#define B_BE_PTA_GNT_WL_BB1 BIT(1)
6205
+
#define B_BE_PTA_GNT_WL_BB0 BIT(0)
6206
+
6207
+
#define R_BE_PTA_GNT_ZL_SW_CTRL 0x0E350
6208
+
#define B_BE_PTA_WL_ACT2_VAL BIT(21)
6209
+
#define B_BE_PTA_WL_ACT2_SWCTRL BIT(20)
6210
+
#define B_BE_PTA_GNT_ZB_TX_BB1_VAL BIT(19)
6211
+
#define B_BE_PTA_GNT_ZB_TX_BB1_SWCTRL BIT(18)
6212
+
#define B_BE_PTA_GNT_ZB_TX_BB0_VAL BIT(17)
6213
+
#define B_BE_PTA_GNT_ZB_TX_BB0_SWCTRL BIT(16)
6214
+
#define B_BE_PTA_WL_ACT1_VAL BIT(15)
6215
+
#define B_BE_PTA_WL_ACT1_SWCTRL BIT(14)
6216
+
#define B_BE_PTA_GNT_BT1_RX_BB1_VAL BIT(13)
6217
+
#define B_BE_PTA_GNT_BT1_RX_BB1_SWCTRL BIT(12)
6218
+
#define B_BE_PTA_GNT_BT1_RX_BB0_VAL BIT(11)
6219
+
#define B_BE_PTA_GNT_BT1_RX_BB0_SWCTRL BIT(10)
6220
+
#define B_BE_PTA_GNT_BT1_TX_BB1_VAL BIT(9)
6221
+
#define B_BE_PTA_GNT_BT1_TX_BB1_SWCTRL BIT(8)
6222
+
#define B_BE_PTA_GNT_BT1_TX_BB0_VAL BIT(7)
6223
+
#define B_BE_PTA_GNT_BT1_TX_BB0_SWCTRL BIT(6)
6224
+
#define B_BE_PTA_WL_ACT_RX_BT1_VAL BIT(5)
6225
+
#define B_BE_PTA_WL_ACT_RX_BT1_SWCTRL BIT(4)
6226
+
#define B_BE_PTA_WL_ACT_TX_BT1_VAL BIT(3)
6227
+
#define B_BE_PTA_WL_ACT_TX_BT1_SWCTRL BIT(2)
6228
+
#define B_BE_PTA_GNT_BT1_BB_VAL BIT(1)
6229
+
#define B_BE_PTA_GNT_BT1_BB_SWCTRL BIT(0)
6298
6230
6299
6231
#define R_BE_PWR_MACID_PATH_BASE 0x0E500
6300
6232
#define R_BE_PWR_MACID_LMT_BASE 0x0ED00
···
6463
6257
#define B_BE_RSC_MASK GENMASK(7, 6)
6464
6258
#define B_BE_RRSR_CCK_MASK GENMASK(3, 0)
6465
6259
6260
+
#define R_BE_COMMON_PHYINTF_CTRL_0 0x100B8
6261
+
#define R_BE_COMMON_PHYINTF_CTRL_0_C1 0x140B8
6262
+
#define B_BE_SEQ_EN_GUARD_CYE_MASK GENMASK(23, 20)
6263
+
#define B_BE_PARA_FIFO_CRC_EN BIT(18)
6264
+
#define B_BE_SEQ_FIFO_TO_EN BIT(17)
6265
+
#define B_BE_PARA_FIFO_TO_EN BIT(16)
6266
+
#define B_BE_SEQ_FIFO_CLR_EN BIT(6)
6267
+
#define B_BE_PARA_FIFO_CLR_EN_V1 BIT(5)
6268
+
#define B_BE_CSI_FIFO_CLR_EN_V1 BIT(4)
6269
+
#define B_BE_FTM_FIFO_CLR_EN_V1 BIT(3)
6270
+
#define B_BE_RXD_FIFO_CLR_EN_V1 BIT(2)
6271
+
#define B_BE_TXD_FIFO_CLR_EN_V1 BIT(1)
6272
+
#define B_BE_TXUID_FIFO_CLR_EN_V1 BIT(0)
6273
+
#define CLEAR_DTOP_DIS (BIT(1) | BIT(5) | BIT(6))
6274
+
6466
6275
#define R_BE_CMAC_ERR_IMR 0x10160
6467
6276
#define R_BE_CMAC_ERR_IMR_C1 0x14160
6468
6277
#define B_BE_CMAC_FW_ERR_IDCT_EN BIT(16)
···
6569
6348
#define B_BE_P0_AUTO_SYNC BIT(28)
6570
6349
#define B_BE_P0_SYNC_PORT_SRC_SEL_MASK GENMASK(26, 24)
6571
6350
#define B_BE_P0_TSFTR_SYNC_OFFSET_MASK GENMASK(18, 0)
6351
+
6352
+
#define R_BE_SCH_EDCA_RST_CFG 0x102E4
6353
+
#define R_BE_SCH_EDCA_RST_CFG_C1 0x142E4
6354
+
#define B_BE_EDCCA_S160_RST_EDCA_EN BIT(23)
6355
+
#define B_BE_EDCCA_S80_RST_EDCA_EN BIT(22)
6356
+
#define B_BE_EDCCA_S40_RST_EDCA_EN BIT(21)
6357
+
#define B_BE_EDCCA_S20_RST_EDCA_EN BIT(20)
6358
+
#define B_BE_OFDM_CCA_S160_RST_EDCA_EN BIT(19)
6359
+
#define B_BE_CCA_PEB_BE_BITMAP_RST_EDCA_EN BIT(18)
6360
+
#define B_BE_RX_INTRA_NAV_RST_EDCA_EN BIT(15)
6361
+
#define B_BE_RX_BASIC_NAV_RST_EDCA_EN BIT(14)
6362
+
#define B_BE_EDCCA_PER20_BITMAP_SIFS_RST_EDCA_EN BIT(10)
6363
+
#define B_BE_TX_NAV_RST_EDCA_EN BIT(7)
6364
+
#define B_BE_NO_GNT_WL_RST_EDCA_EN BIT(5)
6365
+
#define B_BE_EDCCA_P20_RST_EDCA_EN BIT(4)
6366
+
#define B_BE_OFDM_CCA_S80_RST_EDCA_EN BIT(3)
6367
+
#define B_BE_OFDM_CCA_S40_RST_EDCA_EN BIT(2)
6368
+
#define B_BE_OFDM_CCA_S20_RST_EDCA_EN BIT(1)
6369
+
#define B_BE_CCA_P20_RST_EDCA_EN BIT(0)
6572
6370
6573
6371
#define R_BE_EDCA_BCNQ_PARAM 0x10324
6574
6372
#define R_BE_EDCA_BCNQ_PARAM_C1 0x14324
···
6879
6639
#define B_BE_CMAC_TX_MODE_1 BIT(1)
6880
6640
#define B_BE_CMAC_TX_MODE_0 BIT(0)
6881
6641
6642
+
#define R_BE_AGG_BK_0 0x10804
6643
+
#define R_BE_AGG_BK_0_C1 0x14804
6644
+
#define B_BE_DIS_SAMPDU_TXIME_SR_CHECK BIT(24)
6645
+
#define B_BE_TX_PAIR_MACID_LEN_EN BIT(23)
6646
+
#define B_BE_DIS_SND_STS_CHECK_SU BIT(22)
6647
+
#define B_BE_MAX_AGG_NUM_FIX_MODE_EN_V1 BIT(21)
6648
+
#define B_BE_DIS_SIFS_BK_AGG_AMPDU BIT(20)
6649
+
#define B_BE_EN_MU2SU_CHK_PROTECT_PPDU BIT(19)
6650
+
#define B_BE_RPT_TXOP_START_PROTECT BIT(18)
6651
+
#define B_BE_RANDOM_GEN_CMD_ABORT_EN BIT(17)
6652
+
#define B_BE_PHYTXON_ENDPS_RESP_CHK BIT(16)
6653
+
#define B_BE_CTN_CHK_SEQ_REQ_EN BIT(15)
6654
+
#define B_BE_PTCL_RLS_ALLFAIL_EN BIT(14)
6655
+
#define B_BE_DIS_MURU_PRI_Q_EMPTY_CHK BIT(13)
6656
+
#define B_BE_DIS_MURU_SEC_Q_EMPTY_CHK BIT(12)
6657
+
#define B_BE_EN_SAMPDU_TXIME_TWT_CHECK BIT(11)
6658
+
#define B_BE_DIS_SAMPDU_TXIME_P2P_CHECK BIT(10)
6659
+
#define B_BE_DIS_SAMPDU_TXIME_BCN_CHECK BIT(9)
6660
+
#define B_BE_DIS_UL_SEQ_ABORT_CHECK BIT(8)
6661
+
#define B_BE_DIS_SND_STS_CHECK BIT(7)
6662
+
#define B_BE_NAV_PAUS_PHB_EN BIT(6)
6663
+
#define B_BE_TXOP_SHT_PHB_EN BIT(5)
6664
+
#define B_BE_AGG_BRK_PHB_EN BIT(4)
6665
+
#define B_BE_DIS_SSN_CHK BIT(3)
6666
+
#define B_BE_WDBK_CFG BIT(2)
6667
+
#define B_BE_EN_RTY_BK BIT(1)
6668
+
#define B_BE_EN_RTY_BK_COD BIT(0)
6669
+
6882
6670
#define R_BE_TB_PPDU_CTRL 0x1080C
6883
6671
#define R_BE_TB_PPDU_CTRL_C1 0x1480C
6884
6672
#define B_BE_TB_PPDU_BK_DIS BIT(15)
···
6921
6653
#define R_BE_AMPDU_AGG_LIMIT_C1 0x14810
6922
6654
#define B_BE_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
6923
6655
#define AMPDU_MAX_TIME 0x9E
6656
+
#define AMPDU_MAX_TIME_V1 0xA4
6924
6657
#define B_BE_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16)
6925
6658
#define B_BE_RTS_MAX_AGG_NUM_MASK GENMASK(15, 8)
6926
6659
#define B_BE_MAX_AGG_NUM_MASK GENMASK(7, 0)
6660
+
#define MAX_TX_AMPDU_NUM_V1 128
6927
6661
6928
6662
#define R_BE_AGG_LEN_HT_0 0x10814
6929
6663
#define R_BE_AGG_LEN_HT_0_C1 0x14814
6930
6664
#define B_BE_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16)
6931
6665
#define B_BE_RTS_TXTIME_TH_MASK GENMASK(15, 8)
6932
6666
#define B_BE_RTS_LEN_TH_MASK GENMASK(7, 0)
6667
+
6668
+
#define R_BE_SPECIAL_TX_SETTING 0x10820
6669
+
#define R_BE_SPECIAL_TX_SETTING_C1 0x14820
6670
+
#define B_BE_TRI_PADDING_EXTEND BIT(31)
6671
+
#define B_BE_TX_SN_BYPASS_EN BIT(30)
6672
+
#define B_BE_USE_DATA_BW BIT(29)
6673
+
#define B_BE_BW_SIGTA_MASK GENMASK(28, 27)
6674
+
#define B_BE_BMC_NAV_PROTECT BIT(26)
6675
+
#define B_BE_F2P_KEEP_NON_SR_CMD BIT(25)
6676
+
#define B_BE_F2P_SU_FIXRATE_OVER_WD BIT(24)
6677
+
#define B_BE_BAR_TXRATE_FOR_NULL_WD_MASK GENMASK(23, 20)
6678
+
#define B_BE_STBC_CFEND_MASK GENMASK(19, 18)
6679
+
#define B_BE_STBC_CFEND_RATE_MASK GENMASK(17, 9)
6680
+
#define B_BE_BASIC_CFEND_RATE_MASK GENMASK(8, 0)
6933
6681
6934
6682
#define R_BE_SIFS_SETTING 0x10824
6935
6683
#define R_BE_SIFS_SETTING_C1 0x14824
···
6979
6695
#define B_BE_RATE_SEL_MASK GENMASK(29, 24)
6980
6696
#define B_BE_PORT_DROP_4_0_MASK GENMASK(20, 16)
6981
6697
#define B_BE_MBSSID_DROP_15_0_MASK GENMASK(15, 0)
6698
+
6699
+
#define R_BE_PTCL_PRELD_CTRL 0x10868
6700
+
#define R_BE_PTCL_PRELD_CTRL_C1 0x14868
6701
+
#define B_BE_PRELD_MGQ2_EN BIT(22)
6702
+
#define B_BE_PRELD_MGQ1_EN BIT(21)
6703
+
#define B_BE_PRELD_MGQ0_EN BIT(20)
6704
+
#define B_BE_PRELD_HIQ_P4_EN BIT(19)
6705
+
#define B_BE_PRELD_HIQ_P3_EN BIT(18)
6706
+
#define B_BE_PRELD_HIQ_P2_EN BIT(17)
6707
+
#define B_BE_PRELD_HIQ_P1_EN BIT(16)
6708
+
#define B_BE_PRELD_HIQ_P0MB15_EN BIT(15)
6709
+
#define B_BE_PRELD_HIQ_P0MB14_EN BIT(14)
6710
+
#define B_BE_PRELD_HIQ_P0MB13_EN BIT(13)
6711
+
#define B_BE_PRELD_HIQ_P0MB12_EN BIT(12)
6712
+
#define B_BE_PRELD_HIQ_P0MB11_EN BIT(11)
6713
+
#define B_BE_PRELD_HIQ_P0MB10_EN BIT(10)
6714
+
#define B_BE_PRELD_HIQ_P0MB9_EN BIT(9)
6715
+
#define B_BE_PRELD_HIQ_P0MB8_EN BIT(8)
6716
+
#define B_BE_PRELD_HIQ_P0MB7_EN BIT(7)
6717
+
#define B_BE_PRELD_HIQ_P0MB6_EN BIT(6)
6718
+
#define B_BE_PRELD_HIQ_P0MB5_EN BIT(5)
6719
+
#define B_BE_PRELD_HIQ_P0MB4_EN BIT(4)
6720
+
#define B_BE_PRELD_HIQ_P0MB3_EN BIT(3)
6721
+
#define B_BE_PRELD_HIQ_P0MB2_EN BIT(2)
6722
+
#define B_BE_PRELD_HIQ_P0MB1_EN BIT(1)
6723
+
#define B_BE_PRELD_HIQ_P0_EN BIT(0)
6724
+
#define B_BE_PRELD_HIQ_ALL_EN (B_BE_PRELD_HIQ_P0_EN | B_BE_PRELD_HIQ_P1_EN | \
6725
+
B_BE_PRELD_HIQ_P2_EN | B_BE_PRELD_HIQ_P3_EN | \
6726
+
B_BE_PRELD_HIQ_P4_EN)
6727
+
#define B_BE_PRELD_HIQ_P0MB_ALL_EN \
6728
+
(B_BE_PRELD_HIQ_P0_EN | B_BE_PRELD_HIQ_P0MB1_EN | \
6729
+
B_BE_PRELD_HIQ_P0MB2_EN | B_BE_PRELD_HIQ_P0MB3_EN | \
6730
+
B_BE_PRELD_HIQ_P0MB4_EN | B_BE_PRELD_HIQ_P0MB5_EN | \
6731
+
B_BE_PRELD_HIQ_P0MB6_EN | B_BE_PRELD_HIQ_P0MB7_EN | \
6732
+
B_BE_PRELD_HIQ_P0MB8_EN | B_BE_PRELD_HIQ_P0MB9_EN | \
6733
+
B_BE_PRELD_HIQ_P0MB10_EN | B_BE_PRELD_HIQ_P0MB11_EN | \
6734
+
B_BE_PRELD_HIQ_P0MB12_EN | B_BE_PRELD_HIQ_P0MB13_EN | \
6735
+
B_BE_PRELD_HIQ_P0MB14_EN | B_BE_PRELD_HIQ_P0MB15_EN)
6982
6736
6983
6737
#define R_BE_BT_PLT 0x1087C
6984
6738
#define R_BE_BT_PLT_C1 0x1487C
···
7258
6936
B_BE_RX_RU1_FSM_HANG_ERROR_IMR | \
7259
6937
B_BE_RX_RU0_FSM_HANG_ERROR_IMR | \
7260
6938
B_BE_RX_GET_NULL_PKT_ERROR_IMR)
6939
+
#define B_BE_RX_ERROR_FLAG_IMR_CLR_V1 0x7FFFFFF8
6940
+
#define B_BE_RX_ERROR_FLAG_IMR_SET_V1 0x7FFFFF38
7261
6941
7262
6942
#define R_BE_RX_CTRL_1 0x10C0C
7263
6943
#define R_BE_RX_CTRL_1_C1 0x14C0C
···
7673
7349
#define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_CCA20 BIT(2)
7674
7350
#define B_BE_ACK_BA_RESP_LEGACY_CHK_EDCCA BIT(1)
7675
7351
#define B_BE_ACK_BA_RESP_LEGACY_CHK_CCA BIT(0)
7352
+
#define RESP_ACK_CFG_BE (B_BE_ACK_BA_RESP_LEGACY_CHK_BTCCA | \
7353
+
B_BE_ACK_BA_RESP_LEGACY_CHK_TX_NAV)
7676
7354
7677
7355
#define R_BE_WMAC_ACK_BA_RESP_HE 0x11204
7678
7356
#define R_BE_WMAC_ACK_BA_RESP_HE_C1 0x15204
···
7716
7390
#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_EDCCA BIT(1)
7717
7391
#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_CCA BIT(0)
7718
7392
7393
+
#define R_BE_WMAC_RX_RTS_RESP_LEGACY 0x1120C
7394
+
#define R_BE_WMAC_RX_RTS_RESP_LEGACY_C1 0x1520C
7395
+
#define B_BE_RX_RTS_RESP_LEGACY_CHK_NSTR BIT(16)
7396
+
#define B_BE_RX_RTS_RESP_LEGACY_CHK_TX_NAV BIT(15)
7397
+
#define B_BE_RX_RTS_RESP_LEGACY_CHK_INTRA_NAV BIT(14)
7398
+
#define B_BE_RX_RTS_RESP_LEGACY_CHK_BASIC_NAV BIT(13)
7399
+
#define B_BE_RX_RTS_RESP_LEGACY_CHK_BTCCA BIT(12)
7400
+
#define B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA160 BIT(11)
7401
+
#define B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA80 BIT(10)
7402
+
#define B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA40 BIT(9)
7403
+
#define B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA20 BIT(8)
7404
+
#define B_BE_RX_RTS_RESP_LEGACY_CHK_EDCCA_PER20_BMP BIT(7)
7405
+
#define B_BE_RX_RTS_RESP_LEGACY_CHK_CCA_PER20_BMP BIT(6)
7406
+
#define B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA160 BIT(5)
7407
+
#define B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA80 BIT(4)
7408
+
#define B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA40 BIT(3)
7409
+
#define B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA20 BIT(2)
7410
+
#define B_BE_RX_RTS_RESP_LEGACY_CHK_EDCCA BIT(1)
7411
+
#define B_BE_RX_RTS_RESP_LEGACY_CHK_CCA BIT(0)
7412
+
#define RESP_RTS_CFG_BE (B_BE_RX_RTS_RESP_LEGACY_CHK_CCA | \
7413
+
B_BE_RX_RTS_RESP_LEGACY_CHK_EDCCA | \
7414
+
B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA20 | \
7415
+
B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA40 | \
7416
+
B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA80 | \
7417
+
B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA160 | \
7418
+
B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA20 | \
7419
+
B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA40 | \
7420
+
B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA80 | \
7421
+
B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA160 | \
7422
+
B_BE_RX_RTS_RESP_LEGACY_CHK_BTCCA | \
7423
+
B_BE_RX_RTS_RESP_LEGACY_CHK_BASIC_NAV | \
7424
+
B_BE_RX_RTS_RESP_LEGACY_CHK_INTRA_NAV | \
7425
+
B_BE_RX_RTS_RESP_LEGACY_CHK_TX_NAV)
7426
+
#define RESP_RTS_PUNC_CFG_BE (B_BE_RX_RTS_RESP_LEGACY_CHK_CCA | \
7427
+
B_BE_RX_RTS_RESP_LEGACY_CHK_EDCCA | \
7428
+
B_BE_RX_RTS_RESP_LEGACY_CHK_CCA_PER20_BMP | \
7429
+
B_BE_RX_RTS_RESP_LEGACY_CHK_EDCCA_PER20_BMP | \
7430
+
B_BE_RX_RTS_RESP_LEGACY_CHK_BTCCA | \
7431
+
B_BE_RX_RTS_RESP_LEGACY_CHK_BASIC_NAV | \
7432
+
B_BE_RX_RTS_RESP_LEGACY_CHK_INTRA_NAV | \
7433
+
B_BE_RX_RTS_RESP_LEGACY_CHK_TX_NAV)
7434
+
#define RESP_NORMAL_CFG_BE (B_BE_RX_RTS_RESP_LEGACY_CHK_CCA | \
7435
+
B_BE_RX_RTS_RESP_LEGACY_CHK_EDCCA | \
7436
+
B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA20 | \
7437
+
B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA40 | \
7438
+
B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA80 | \
7439
+
B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_CCA160 | \
7440
+
B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA20 | \
7441
+
B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA40 | \
7442
+
B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA80 | \
7443
+
B_BE_RX_RTS_RESP_LEGACY_CHK_SEC_EDCCA160 | \
7444
+
B_BE_RX_RTS_RESP_LEGACY_CHK_BTCCA | \
7445
+
B_BE_RX_RTS_RESP_LEGACY_CHK_BASIC_NAV | \
7446
+
B_BE_RX_RTS_RESP_LEGACY_CHK_TX_NAV)
7447
+
#define RESP_NORMAL_PUNC_CFG_BE (B_BE_RX_RTS_RESP_LEGACY_CHK_CCA | \
7448
+
B_BE_RX_RTS_RESP_LEGACY_CHK_EDCCA | \
7449
+
B_BE_RX_RTS_RESP_LEGACY_CHK_CCA_PER20_BMP | \
7450
+
B_BE_RX_RTS_RESP_LEGACY_CHK_EDCCA_PER20_BMP | \
7451
+
B_BE_RX_RTS_RESP_LEGACY_CHK_BTCCA | \
7452
+
B_BE_RX_RTS_RESP_LEGACY_CHK_BASIC_NAV | \
7453
+
B_BE_RX_RTS_RESP_LEGACY_CHK_TX_NAV)
7454
+
7455
+
#define R_BE_WMAC_RX_RTS_RESP_LEGACY_PUNC 0x11210
7456
+
#define R_BE_WMAC_RX_RTS_RESP_LEGACY_PUNC_C1 0x15210
7457
+
#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_NSTR BIT(16)
7458
+
#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_TX_NAV BIT(15)
7459
+
#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_INTRA_NAV BIT(14)
7460
+
#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_BASIC_NAV BIT(13)
7461
+
#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_BTCCA BIT(12)
7462
+
#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_SEC_EDCCA160 BIT(11)
7463
+
#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_SEC_EDCCA80 BIT(10)
7464
+
#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_SEC_EDCCA40 BIT(9)
7465
+
#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_SEC_EDCCA20 BIT(8)
7466
+
#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_EDCCA_PER20_BMP BIT(7)
7467
+
#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_CCA_PER20_BMP BIT(6)
7468
+
#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_SEC_CCA160 BIT(5)
7469
+
#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_SEC_CCA80 BIT(4)
7470
+
#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_SEC_CCA40 BIT(3)
7471
+
#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_SEC_CCA20 BIT(2)
7472
+
#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_EDCCA BIT(1)
7473
+
#define B_BE_RX_RTS_RESP_LEGACY_PUNC_CHK_CCA BIT(0)
7474
+
7475
+
#define R_BE_WMAC_RX_MURTS_RESP_LEGACY 0x11214
7476
+
#define R_BE_WMAC_RX_MURTS_RESP_LEGACY_C1 0x15214
7477
+
#define B_BE_MURTS_RESP_LEGACY_CHK_NSTR BIT(16)
7478
+
#define B_BE_MURTS_RESP_LEGACY_CHK_TX_NAV BIT(15)
7479
+
#define B_BE_MURTS_RESP_LEGACY_CHK_INTRA_NAV BIT(14)
7480
+
#define B_BE_MURTS_RESP_LEGACY_CHK_BASIC_NAV BIT(13)
7481
+
#define B_BE_MURTS_RESP_LEGACY_CHK_BTCCA BIT(12)
7482
+
#define B_BE_MURTS_RESP_LEGACY_CHK_SEC_EDCCA160 BIT(11)
7483
+
#define B_BE_MURTS_RESP_LEGACY_CHK_SEC_EDCCA80 BIT(10)
7484
+
#define B_BE_MURTS_RESP_LEGACY_CHK_SEC_EDCCA40 BIT(9)
7485
+
#define B_BE_MURTS_RESP_LEGACY_CHK_SEC_EDCCA20 BIT(8)
7486
+
#define B_BE_MURTS_RESP_LEGACY_CHK_EDCCA_PER20_BMP BIT(7)
7487
+
#define B_BE_MURTS_RESP_LEGACY_CHK_CCA_PER20_BMP BIT(6)
7488
+
#define B_BE_MURTS_RESP_LEGACY_CHK_SEC_CCA160 BIT(5)
7489
+
#define B_BE_MURTS_RESP_LEGACY_CHK_SEC_CCA80 BIT(4)
7490
+
#define B_BE_MURTS_RESP_LEGACY_CHK_SEC_CCA40 BIT(3)
7491
+
#define B_BE_MURTS_RESP_LEGACY_CHK_SEC_CCA20 BIT(2)
7492
+
#define B_BE_MURTS_RESP_LEGACY_CHK_EDCCA BIT(1)
7493
+
#define B_BE_MURTS_RESP_LEGACY_CHK_CCA BIT(0)
7494
+
7495
+
#define R_BE_WMAC_RX_MURTS_RESP_LEGACY_PUNC 0x11218
7496
+
#define R_BE_WMAC_RX_MURTS_RESP_LEGACY_PUNC_C1 0x15218
7497
+
#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_NSTR BIT(16)
7498
+
#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_TX_NAV BIT(15)
7499
+
#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_INTRA_NAV BIT(14)
7500
+
#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_BASIC_NAV BIT(13)
7501
+
#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_BTCCA BIT(12)
7502
+
#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_SEC_EDCCA160 BIT(11)
7503
+
#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_SEC_EDCCA80 BIT(10)
7504
+
#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_SEC_EDCCA40 BIT(9)
7505
+
#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_SEC_EDCCA20 BIT(8)
7506
+
#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_EDCCA_PER20_BMP BIT(7)
7507
+
#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_CCA_PER20_BMP BIT(6)
7508
+
#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_SEC_CCA160 BIT(5)
7509
+
#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_SEC_CCA80 BIT(4)
7510
+
#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_SEC_CCA40 BIT(3)
7511
+
#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_SEC_CCA20 BIT(2)
7512
+
#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_EDCCA BIT(1)
7513
+
#define B_BE_MURTS_RESP_LEGACY_PUNC_CHK_CCA BIT(0)
7514
+
7515
+
#define R_BE_WMAC_OTHERS_RESP_LEGACY 0x1121C
7516
+
#define R_BE_WMAC_OTHERS_RESP_LEGACY_C1 0x1521C
7517
+
#define B_BE_OTHERS_RESP_LEGACY_CHK_NSTR BIT(16)
7518
+
#define B_BE_OTHERS_RESP_LEGACY_CHK_TX_NAV BIT(15)
7519
+
#define B_BE_OTHERS_RESP_LEGACY_CHK_INTRA_NAV BIT(14)
7520
+
#define B_BE_OTHERS_RESP_LEGACY_CHK_BASIC_NAV BIT(13)
7521
+
#define B_BE_OTHERS_RESP_LEGACY_CHK_BTCCA BIT(12)
7522
+
#define B_BE_OTHERS_RESP_LEGACY_CHK_SEC_EDCCA160 BIT(11)
7523
+
#define B_BE_OTHERS_RESP_LEGACY_CHK_SEC_EDCCA80 BIT(10)
7524
+
#define B_BE_OTHERS_RESP_LEGACY_CHK_SEC_EDCCA40 BIT(9)
7525
+
#define B_BE_OTHERS_RESP_LEGACY_CHK_SEC_EDCCA20 BIT(8)
7526
+
#define B_BE_OTHERS_RESP_LEGACY_CHK_EDCCA_PER20_BMP BIT(7)
7527
+
#define B_BE_OTHERS_RESP_LEGACY_CHK_CCA_PER20_BMP BIT(6)
7528
+
#define B_BE_OTHERS_RESP_LEGACY_CHK_SEC_CCA160 BIT(5)
7529
+
#define B_BE_OTHERS_RESP_LEGACY_CHK_SEC_CCA80 BIT(4)
7530
+
#define B_BE_OTHERS_RESP_LEGACY_CHK_SEC_CCA40 BIT(3)
7531
+
#define B_BE_OTHERS_RESP_LEGACY_CHK_SEC_CCA20 BIT(2)
7532
+
#define B_BE_OTHERS_RESP_LEGACY_CHK_EDCCA BIT(1)
7533
+
#define B_BE_OTHERS_RESP_LEGACY_CHK_CCA BIT(0)
7534
+
7535
+
#define R_BE_WMAC_OTHERS_RESP_HE 0x11220
7536
+
#define R_BE_WMAC_OTHERS_RESP_HE_C1 0x15220
7537
+
#define B_BE_OTHERS_RESP_HE_CHK_NSTR BIT(16)
7538
+
#define B_BE_OTHERS_RESP_HE_CHK_TX_NAV BIT(15)
7539
+
#define B_BE_OTHERS_RESP_HE_CHK_INTRA_NAV BIT(14)
7540
+
#define B_BE_OTHERS_RESP_HE_CHK_BASIC_NAV BIT(13)
7541
+
#define B_BE_OTHERS_RESP_HE_CHK_BTCCA BIT(12)
7542
+
#define B_BE_OTHERS_RESP_HE_CHK_SEC_EDCCA160 BIT(11)
7543
+
#define B_BE_OTHERS_RESP_HE_CHK_SEC_EDCCA80 BIT(10)
7544
+
#define B_BE_OTHERS_RESP_HE_CHK_SEC_EDCCA40 BIT(9)
7545
+
#define B_BE_OTHERS_RESP_HE_CHK_SEC_EDCCA20 BIT(8)
7546
+
#define B_BE_OTHERS_RESP_HE_CHK_EDCCA_PER20_BMP BIT(7)
7547
+
#define B_BE_OTHERS_RESP_HE_CHK_CCA_PER20_BMP BIT(6)
7548
+
#define B_BE_OTHERS_RESP_HE_CHK_SEC_CCA160 BIT(5)
7549
+
#define B_BE_OTHERS_RESP_HE_CHK_SEC_CCA80 BIT(4)
7550
+
#define B_BE_OTHERS_RESP_HE_CHK_SEC_CCA40 BIT(3)
7551
+
#define B_BE_OTHERS_RESP_HE_CHK_SEC_CCA20 BIT(2)
7552
+
#define B_BE_OTHERS_RESP_HE_CHK_EDCCA BIT(1)
7553
+
#define B_BE_OTHERS_RESP_HE_CHK_CCA BIT(0)
7554
+
7555
+
#define R_BE_WMAC_OTHERS_RESP_EHT_LEG_PUNC 0x11224
7556
+
#define R_BE_WMAC_OTHERS_RESP_EHT_LEG_PUNC_C1 0x15224
7557
+
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_NSTR BIT(16)
7558
+
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_TX_NAV BIT(15)
7559
+
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_INTRA_NAV BIT(14)
7560
+
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_BASIC_NAV BIT(13)
7561
+
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_BTCCA BIT(12)
7562
+
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_SEC_EDCCA160 BIT(11)
7563
+
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_SEC_EDCCA80 BIT(10)
7564
+
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_SEC_EDCCA40 BIT(9)
7565
+
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_SEC_EDCCA20 BIT(8)
7566
+
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_EDCCA_PER20_BMP BIT(7)
7567
+
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_CCA_PER20_BMP BIT(6)
7568
+
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_SEC_CCA160 BIT(5)
7569
+
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_SEC_CCA80 BIT(4)
7570
+
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_SEC_CCA40 BIT(3)
7571
+
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_SEC_CCA20 BIT(2)
7572
+
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_EDCCA BIT(1)
7573
+
#define B_BE_OTHERS_RESP_EHT_LEG_PUNC_CHK_CCA BIT(0)
7574
+
7719
7575
#define R_BE_RCR 0x11400
7720
7576
#define R_BE_RCR_C1 0x15400
7721
7577
#define B_BE_BUSY_CHKSN BIT(15)
···
7934
7426
#define B_BE_LSIG_PARITY_CHK_EN BIT(2)
7935
7427
#define B_BE_CCK_SIG_CHK BIT(1)
7936
7428
#define B_BE_CCK_CRC_CHK BIT(0)
7429
+
7430
+
#define R_BE_RXGCK_CTRL 0x11406
7431
+
#define R_BE_RXGCK_CTRL_C1 0x15406
7432
+
#define B_BE_RXGCK_BCNPRS_DISGCLK BIT(12)
7433
+
#define B_BE_RXGCK_GCK_RATE_LIMIT_MASK GENMASK(9, 8)
7434
+
#define RX_GCK_LEGACY 2
7435
+
#define B_BE_RXGCK_DISREG_GCLK BIT(7)
7436
+
#define B_BE_RXGCK_ENTRY_DELAY_MASK GENMASK(6, 4)
7437
+
#define B_BE_RXGCK_GCK_CYCLE_MASK GENMASK(3, 2)
7438
+
#define B_BE_RXGCK_CCA_EN BIT(1)
7439
+
#define B_BE_DISGCLK BIT(0)
7937
7440
7938
7441
#define R_BE_RX_FLTR_OPT 0x11420
7939
7442
#define R_BE_RX_FLTR_OPT_C1 0x15420
···
8040
7521
#define B_BE_CSIPRT_HESU_AID_EN BIT(25)
8041
7522
#define B_BE_CSIPRT_VHTSU_AID_EN BIT(24)
8042
7523
7524
+
#define R_BE_BSR_UPD_CTRL 0x11468
7525
+
#define R_BE_BSR_UPD_CTRL_C1 0x15468
7526
+
#define B_BE_QSIZE_RULE BIT(1)
7527
+
#define B_BE_QSIZE_UPD BIT(0)
7528
+
8043
7529
#define R_BE_DRV_INFO_OPTION 0x11470
8044
7530
#define R_BE_DRV_INFO_OPTION_C1 0x15470
8045
7531
#define B_BE_DRV_INFO_PHYRPT_EN BIT(0)
···
8110
7586
#define B_BE_PLCP_CH20_WIDATA_SRC BIT(1)
8111
7587
#define B_BE_PLCP_PPDU_TYPE_SRC BIT(0)
8112
7588
7589
+
#define R_BE_RX_PLCP_EXT_OPTION_2 0x11518
7590
+
#define R_BE_RX_PLCP_EXT_OPTION_2_C1 0x15518
7591
+
#define B_BE_PLCP_PHASE_B_CRC_CHK_EN BIT(17)
7592
+
#define B_BE_PLCP_PHASE_A_CRC_CHK_EN BIT(16)
7593
+
#define B_BE_EHTTB_EHTSIG_CRC_CHK_EN BIT(3)
7594
+
#define B_BE_EHTTB_USIG_CRC_CHK_EN BIT(2)
7595
+
#define B_BE_EHTMU_EHTSIG_CRC_CHK_EN BIT(1)
7596
+
#define B_BE_EHTMU_USIG_CRC_CHK_EN BIT(0)
7597
+
8113
7598
#define R_BE_RESP_CSI_RESERVED_PAGE 0x11810
8114
7599
#define R_BE_RESP_CSI_RESERVED_PAGE_C1 0x15810
8115
7600
#define B_BE_CSI_RESERVED_PAGE_NUM_MASK GENMASK(27, 16)
8116
7601
#define B_BE_CSI_RESERVED_START_PAGE_MASK GENMASK(11, 0)
7602
+
7603
+
#define R_BE_RESP_IMR1 0x11878
7604
+
#define R_BE_RESP_IMR1_C1 0x15878
7605
+
#define B_BE_RESP_IMR_1_MASK GENMASK(31, 9)
7606
+
#define B_BE_FSM_TIMEOUT_ERR_IMR BIT(8)
7607
+
#define B_BE_SEC_DOUBLE_HIT_ERR_IMR BIT(7)
7608
+
#define B_BE_WRPTR_ERR_IMR BIT(6)
7609
+
#define B_BE_SMR_TOO_MANY_PLD_ERR_IMR BIT(5)
7610
+
#define B_BE_LMR_TOO_MANY_PLD_ERR_IMR BIT(4)
7611
+
#define B_BE_CSI_TOO_MANY_PLD_ERR_IMR BIT(3)
7612
+
#define B_BE_FTM_LMR_PLDID_READY_ERR_IMR BIT(2)
7613
+
#define B_BE_SMR_PLDID_READY_ERR_IMR BIT(1)
7614
+
#define B_BE_CSI_PLDID_READY_ERR_IMR BIT(0)
7615
+
#define B_BE_RESP_IMR1_CLR 0x1FF
7616
+
#define B_BE_RESP_IMR1_SET 0xFF
8117
7617
8118
7618
#define R_BE_RESP_IMR 0x11884
8119
7619
#define R_BE_RESP_IMR_C1 0x15884
···
8183
7635
B_BE_RESP_PLDID_RDY_ERR_ISR_EN | \
8184
7636
B_BE_RESP_WRPTR_CROSS_ERR_ISR_EN | \
8185
7637
B_BE_RESP_SEC_DOUBLE_HIT_ERR_ISR_EN)
7638
+
#define B_BE_RESP_IMR_CLR_V1 0xFFFFFFFF
7639
+
#define B_BE_RESP_IMR_SET_V1 0xFFFFFFFF
8186
7640
8187
7641
#define R_BE_PWR_MODULE 0x11900
8188
7642
#define R_BE_PWR_MODULE_C1 0x15900
···
8262
7712
#define R_BE_TXPWR_ERR_IMR 0x128E0
8263
7713
#define R_BE_TXPWR_ERR_FLAG_C1 0x158E4
8264
7714
#define R_BE_TXPWR_ERR_IMR_C1 0x158E0
7715
+
7716
+
#define R_BE_SCH_EXT_CTRL 0x103FC
7717
+
#define R_BE_SCH_EXT_CTRL_C1 0x143FC
7718
+
#define B_BE_CWCNT_PLUS_MODE BIT(31)
8265
7719
8266
7720
#define CMAC1_START_ADDR_BE 0x14000
8267
7721
#define CMAC1_END_ADDR_BE 0x17FFF
+1
drivers/net/wireless/realtek/rtw89/regd.c
+1
drivers/net/wireless/realtek/rtw89/regd.c
+7
-2
drivers/net/wireless/realtek/rtw89/rtw8851b.c
+7
-2
drivers/net/wireless/realtek/rtw89/rtw8851b.c
···
633
633
efuse->rfe_type = map->rfe_type;
634
634
efuse->xtal_cap = map->xtal_k;
635
635
636
-
rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
637
-
638
636
return 0;
639
637
}
640
638
···
2551
2553
.h2c_default_dmac_tbl = NULL,
2552
2554
.h2c_update_beacon = rtw89_fw_h2c_update_beacon,
2553
2555
.h2c_ba_cam = rtw89_fw_h2c_ba_cam,
2556
+
.h2c_wow_cam_update = rtw89_fw_h2c_wow_cam_update,
2554
2557
2555
2558
.btc_set_rfe = rtw8851b_btc_set_rfe,
2556
2559
.btc_init_cfg = rtw8851b_btc_init_cfg,
···
2589
2590
.small_fifo_size = true,
2590
2591
.dle_scc_rsvd_size = 98304,
2591
2592
.max_amsdu_limit = 3500,
2593
+
.max_vht_mpdu_cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
2594
+
.max_eht_mpdu_cap = 0,
2595
+
.max_tx_agg_num = 128,
2596
+
.max_rx_agg_num = 64,
2592
2597
.dis_2g_40m_ul_ofdma = true,
2593
2598
.rsvd_ple_ofst = 0x2f800,
2594
2599
.hfc_param_ini = {rtw8851b_hfc_param_ini_pcie,
···
2707
2704
.bss_clr_map_reg = R_BSS_CLR_MAP_V1,
2708
2705
.rfkill_init = &rtw8851b_rfkill_regs,
2709
2706
.rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9},
2707
+
.btc_sb = {{{R_AX_SCOREBOARD, R_AX_SCOREBOARD},}},
2710
2708
.dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
2711
2709
BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
2712
2710
BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
···
2716
2712
.wowlan_stub = &rtw_wowlan_stub_8851b,
2717
2713
#endif
2718
2714
.xtal_info = &rtw8851b_xtal_info,
2715
+
.default_quirks = 0,
2719
2716
};
2720
2717
EXPORT_SYMBOL(rtw8851b_chip_info);
2721
2718
+7
-2
drivers/net/wireless/realtek/rtw89/rtw8852a.c
+7
-2
drivers/net/wireless/realtek/rtw89/rtw8852a.c
···
678
678
efuse->rfe_type = map->rfe_type;
679
679
efuse->xtal_cap = map->xtal_k;
680
680
681
-
rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
682
-
683
681
return 0;
684
682
}
685
683
···
2245
2247
.h2c_default_dmac_tbl = NULL,
2246
2248
.h2c_update_beacon = rtw89_fw_h2c_update_beacon,
2247
2249
.h2c_ba_cam = rtw89_fw_h2c_ba_cam,
2250
+
.h2c_wow_cam_update = rtw89_fw_h2c_wow_cam_update,
2248
2251
2249
2252
.btc_set_rfe = rtw8852a_btc_set_rfe,
2250
2253
.btc_init_cfg = rtw8852a_btc_init_cfg,
···
2274
2275
.small_fifo_size = false,
2275
2276
.dle_scc_rsvd_size = 0,
2276
2277
.max_amsdu_limit = 3500,
2278
+
.max_vht_mpdu_cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
2279
+
.max_eht_mpdu_cap = 0,
2280
+
.max_tx_agg_num = 128,
2281
+
.max_rx_agg_num = 64,
2277
2282
.dis_2g_40m_ul_ofdma = true,
2278
2283
.rsvd_ple_ofst = 0x6f800,
2279
2284
.hfc_param_ini = {rtw8852a_hfc_param_ini_pcie,
···
2394
2391
.bss_clr_map_reg = R_BSS_CLR_MAP,
2395
2392
.rfkill_init = &rtw8852a_rfkill_regs,
2396
2393
.rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9},
2394
+
.btc_sb = {{{R_AX_SCOREBOARD, R_AX_SCOREBOARD},}},
2397
2395
.dma_ch_mask = 0,
2398
2396
.edcca_regs = &rtw8852a_edcca_regs,
2399
2397
#ifdef CONFIG_PM
2400
2398
.wowlan_stub = &rtw_wowlan_stub_8852a,
2401
2399
#endif
2402
2400
.xtal_info = &rtw8852a_xtal_info,
2401
+
.default_quirks = 0,
2403
2402
};
2404
2403
EXPORT_SYMBOL(rtw8852a_chip_info);
2405
2404
+4
drivers/net/wireless/realtek/rtw89/rtw8852au.c
+4
drivers/net/wireless/realtek/rtw89/rtw8852au.c
···
52
52
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
53
53
{ USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3321, 0xff, 0xff, 0xff),
54
54
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
55
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3323, 0xff, 0xff, 0xff),
56
+
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
55
57
{ USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x332c, 0xff, 0xff, 0xff),
56
58
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
57
59
{ USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x013f, 0xff, 0xff, 0xff),
···
61
59
{ USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0140, 0xff, 0xff, 0xff),
62
60
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
63
61
{ USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0141, 0xff, 0xff, 0xff),
62
+
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
63
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x3625, 0x010d, 0xff, 0xff, 0xff),
64
64
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
65
65
{ USB_DEVICE_AND_INTERFACE_INFO(0x3625, 0x010f, 0xff, 0xff, 0xff),
66
66
.driver_info = (kernel_ulong_t)&rtw89_8852au_info },
+29
-2
drivers/net/wireless/realtek/rtw89/rtw8852b.c
+29
-2
drivers/net/wireless/realtek/rtw89/rtw8852b.c
···
313
313
rtw89_write16(rtwdev, R_AX_SPS_ANA_ON_CTRL2, RTL8852B_RFE_05_SPS_ANA);
314
314
}
315
315
316
+
static void rtw8852b_pwr_sps_dig_off(struct rtw89_dev *rtwdev)
317
+
{
318
+
struct rtw89_efuse *efuse = &rtwdev->efuse;
319
+
320
+
if (efuse->rfe_type == 0x5) {
321
+
rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0,
322
+
B_AX_C1_L1_MASK, 0x1);
323
+
rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0,
324
+
B_AX_C2_L1_MASK, 0x1);
325
+
rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0,
326
+
B_AX_C3_L1_MASK, 0x2);
327
+
rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0,
328
+
B_AX_R1_L1_MASK, 0x1);
329
+
} else {
330
+
rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0,
331
+
B_AX_C1_L1_MASK, 0x1);
332
+
rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0,
333
+
B_AX_C3_L1_MASK, 0x3);
334
+
}
335
+
}
336
+
316
337
static int rtw8852b_pwr_on_func(struct rtw89_dev *rtwdev)
317
338
{
318
339
u32 val32;
···
359
338
if (ret)
360
339
return ret;
361
340
362
-
rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C1_L1_MASK, 0x1);
363
-
rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C3_L1_MASK, 0x3);
341
+
rtw8852b_pwr_sps_dig_off(rtwdev);
364
342
rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
365
343
rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
366
344
···
878
858
.h2c_default_dmac_tbl = NULL,
879
859
.h2c_update_beacon = rtw89_fw_h2c_update_beacon,
880
860
.h2c_ba_cam = rtw89_fw_h2c_ba_cam,
861
+
.h2c_wow_cam_update = rtw89_fw_h2c_wow_cam_update,
881
862
882
863
.btc_set_rfe = rtw8852b_btc_set_rfe,
883
864
.btc_init_cfg = rtw8852bx_btc_init_cfg,
···
920
899
.small_fifo_size = true,
921
900
.dle_scc_rsvd_size = 98304,
922
901
.max_amsdu_limit = 5000,
902
+
.max_vht_mpdu_cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
903
+
.max_eht_mpdu_cap = 0,
904
+
.max_tx_agg_num = 128,
905
+
.max_rx_agg_num = 64,
923
906
.dis_2g_40m_ul_ofdma = true,
924
907
.rsvd_ple_ofst = 0x2f800,
925
908
.hfc_param_ini = {rtw8852b_hfc_param_ini_pcie,
···
1041
1016
.bss_clr_map_reg = R_BSS_CLR_MAP_V1,
1042
1017
.rfkill_init = &rtw8852b_rfkill_regs,
1043
1018
.rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9},
1019
+
.btc_sb = {{{R_AX_SCOREBOARD, R_AX_SCOREBOARD},}},
1044
1020
.dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
1045
1021
BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
1046
1022
BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
···
1050
1024
.wowlan_stub = &rtw_wowlan_stub_8852b,
1051
1025
#endif
1052
1026
.xtal_info = NULL,
1027
+
.default_quirks = 0,
1053
1028
};
1054
1029
EXPORT_SYMBOL(rtw8852b_chip_info);
1055
1030
-2
drivers/net/wireless/realtek/rtw89/rtw8852b_common.c
-2
drivers/net/wireless/realtek/rtw89/rtw8852b_common.c
+7
drivers/net/wireless/realtek/rtw89/rtw8852bt.c
+7
drivers/net/wireless/realtek/rtw89/rtw8852bt.c
···
724
724
.h2c_default_dmac_tbl = NULL,
725
725
.h2c_update_beacon = rtw89_fw_h2c_update_beacon,
726
726
.h2c_ba_cam = rtw89_fw_h2c_ba_cam,
727
+
.h2c_wow_cam_update = rtw89_fw_h2c_wow_cam_update,
727
728
728
729
.btc_set_rfe = rtw8852bt_btc_set_rfe,
729
730
.btc_init_cfg = rtw8852bx_btc_init_cfg,
···
766
765
.small_fifo_size = true,
767
766
.dle_scc_rsvd_size = 98304,
768
767
.max_amsdu_limit = 5000,
768
+
.max_vht_mpdu_cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
769
+
.max_eht_mpdu_cap = 0,
770
+
.max_tx_agg_num = 128,
771
+
.max_rx_agg_num = 64,
769
772
.dis_2g_40m_ul_ofdma = true,
770
773
.rsvd_ple_ofst = 0x6f800,
771
774
.hfc_param_ini = {rtw8852bt_hfc_param_ini_pcie, NULL, NULL},
···
878
873
.bss_clr_map_reg = R_BSS_CLR_MAP_V1,
879
874
.rfkill_init = &rtw8852bt_rfkill_regs,
880
875
.rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9},
876
+
.btc_sb = {{{R_AX_SCOREBOARD, R_AX_SCOREBOARD},}},
881
877
.dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
882
878
BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
883
879
BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
···
887
881
.wowlan_stub = &rtw_wowlan_stub_8852bt,
888
882
#endif
889
883
.xtal_info = NULL,
884
+
.default_quirks = 0,
890
885
};
891
886
EXPORT_SYMBOL(rtw8852bt_chip_info);
892
887
+2
drivers/net/wireless/realtek/rtw89/rtw8852bu.c
+2
drivers/net/wireless/realtek/rtw89/rtw8852bu.c
···
54
54
.driver_info = (kernel_ulong_t)&rtw89_8852bu_info },
55
55
{ USB_DEVICE_AND_INTERFACE_INFO(0x0db0, 0x6931, 0xff, 0xff, 0xff),
56
56
.driver_info = (kernel_ulong_t)&rtw89_8852bu_info },
57
+
{ USB_DEVICE_AND_INTERFACE_INFO(0x0db0, 0xf0c8, 0xff, 0xff, 0xff),
58
+
.driver_info = (kernel_ulong_t)&rtw89_8852bu_info },
57
59
{ USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3327, 0xff, 0xff, 0xff),
58
60
.driver_info = (kernel_ulong_t)&rtw89_8852bu_info },
59
61
{ USB_DEVICE_AND_INTERFACE_INFO(0x3574, 0x6121, 0xff, 0xff, 0xff),
+7
-2
drivers/net/wireless/realtek/rtw89/rtw8852c.c
+7
-2
drivers/net/wireless/realtek/rtw89/rtw8852c.c
···
600
600
efuse->rfe_type = map->rfe_type;
601
601
efuse->xtal_cap = map->xtal_k;
602
602
603
-
rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
604
-
605
603
return 0;
606
604
}
607
605
···
3086
3088
.h2c_default_dmac_tbl = NULL,
3087
3089
.h2c_update_beacon = rtw89_fw_h2c_update_beacon,
3088
3090
.h2c_ba_cam = rtw89_fw_h2c_ba_cam,
3091
+
.h2c_wow_cam_update = rtw89_fw_h2c_wow_cam_update,
3089
3092
3090
3093
.btc_set_rfe = rtw8852c_btc_set_rfe,
3091
3094
.btc_init_cfg = rtw8852c_btc_init_cfg,
···
3115
3116
.small_fifo_size = false,
3116
3117
.dle_scc_rsvd_size = 0,
3117
3118
.max_amsdu_limit = 8000,
3119
+
.max_vht_mpdu_cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
3120
+
.max_eht_mpdu_cap = 0,
3121
+
.max_tx_agg_num = 128,
3122
+
.max_rx_agg_num = 64,
3118
3123
.dis_2g_40m_ul_ofdma = false,
3119
3124
.rsvd_ple_ofst = 0x6f800,
3120
3125
.hfc_param_ini = {rtw8852c_hfc_param_ini_pcie,
···
3239
3236
.bss_clr_map_reg = R_BSS_CLR_MAP,
3240
3237
.rfkill_init = &rtw8852c_rfkill_regs,
3241
3238
.rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9},
3239
+
.btc_sb = {{{R_AX_SCOREBOARD, R_AX_SCOREBOARD},}},
3242
3240
.dma_ch_mask = 0,
3243
3241
.edcca_regs = &rtw8852c_edcca_regs,
3244
3242
#ifdef CONFIG_PM
3245
3243
.wowlan_stub = &rtw_wowlan_stub_8852c,
3246
3244
#endif
3247
3245
.xtal_info = NULL,
3246
+
.default_quirks = 0,
3248
3247
};
3249
3248
EXPORT_SYMBOL(rtw8852c_chip_info);
3250
3249
+25
-6
drivers/net/wireless/realtek/rtw89/rtw8922a.c
+25
-6
drivers/net/wireless/realtek/rtw89/rtw8922a.c
···
628
628
rtw8922a_efuse_parsing_tssi(rtwdev, map);
629
629
rtw8922a_efuse_parsing_gain_offset(rtwdev, map);
630
630
631
-
rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
632
-
633
631
return 0;
634
632
}
635
633
636
634
static int rtw8922a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
637
635
enum rtw89_efuse_block block)
638
636
{
637
+
struct rtw89_efuse *efuse = &rtwdev->efuse;
638
+
int ret;
639
+
639
640
switch (block) {
640
641
case RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO:
641
-
return rtw8922a_read_efuse_pci_sdio(rtwdev, log_map);
642
+
ret = rtw8922a_read_efuse_pci_sdio(rtwdev, log_map);
643
+
break;
642
644
case RTW89_EFUSE_BLOCK_HCI_DIG_USB:
643
-
return rtw8922a_read_efuse_usb(rtwdev, log_map);
645
+
ret = rtw8922a_read_efuse_usb(rtwdev, log_map);
646
+
break;
644
647
case RTW89_EFUSE_BLOCK_RF:
645
-
return rtw8922a_read_efuse_rf(rtwdev, log_map);
648
+
ret = rtw8922a_read_efuse_rf(rtwdev, log_map);
649
+
break;
646
650
default:
647
-
return 0;
651
+
ret = 0;
652
+
break;
648
653
}
654
+
655
+
if (!ret && is_zero_ether_addr(efuse->addr)) {
656
+
rtw89_info(rtwdev, "efuse mac address is zero, using random mac\n");
657
+
eth_random_addr(efuse->addr);
658
+
}
659
+
660
+
return ret;
649
661
}
650
662
651
663
#define THM_TRIM_POSITIVE_MASK BIT(6)
···
2859
2847
.h2c_default_dmac_tbl = rtw89_fw_h2c_default_dmac_tbl_v2,
2860
2848
.h2c_update_beacon = rtw89_fw_h2c_update_beacon_be,
2861
2849
.h2c_ba_cam = rtw89_fw_h2c_ba_cam_v1,
2850
+
.h2c_wow_cam_update = rtw89_fw_h2c_wow_cam_update,
2862
2851
2863
2852
.btc_set_rfe = rtw8922a_btc_set_rfe,
2864
2853
.btc_init_cfg = rtw8922a_btc_init_cfg,
···
2888
2875
.small_fifo_size = false,
2889
2876
.dle_scc_rsvd_size = 0,
2890
2877
.max_amsdu_limit = 8000,
2878
+
.max_vht_mpdu_cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
2879
+
.max_eht_mpdu_cap = IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991,
2880
+
.max_tx_agg_num = 128,
2881
+
.max_rx_agg_num = 64,
2891
2882
.dis_2g_40m_ul_ofdma = false,
2892
2883
.rsvd_ple_ofst = 0x8f800,
2893
2884
.hfc_param_ini = {rtw8922a_hfc_param_ini_pcie, NULL, NULL},
···
3005
2988
.bss_clr_map_reg = R_BSS_CLR_MAP_V2,
3006
2989
.rfkill_init = &rtw8922a_rfkill_regs,
3007
2990
.rfkill_get = {R_BE_GPIO_EXT_CTRL, B_BE_GPIO_IN_9},
2991
+
.btc_sb = {{{R_BE_SCOREBOARD, R_BE_SCOREBOARD},}},
3008
2992
.dma_ch_mask = 0,
3009
2993
.edcca_regs = &rtw8922a_edcca_regs,
3010
2994
#ifdef CONFIG_PM
3011
2995
.wowlan_stub = &rtw_wowlan_stub_8922a,
3012
2996
#endif
3013
2997
.xtal_info = NULL,
2998
+
.default_quirks = 0,
3014
2999
};
3015
3000
EXPORT_SYMBOL(rtw8922a_chip_info);
3016
3001
+45
-3
drivers/net/wireless/realtek/rtw89/rtw8922a_rfk.c
+45
-3
drivers/net/wireless/realtek/rtw89/rtw8922a_rfk.c
···
205
205
}
206
206
}
207
207
208
-
static u8 rtw8922a_chlk_reload_sel_tbl(struct rtw89_dev *rtwdev,
209
-
const struct rtw89_chan *chan, u8 path)
208
+
static u8 rtw8922a_chlk_reload_sel_tbl_v0(struct rtw89_dev *rtwdev,
209
+
const struct rtw89_chan *chan, u8 path)
210
210
{
211
-
struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
212
211
struct rtw89_rfk_chan_desc desc[__RTW89_RFK_CHS_NR_V1] = {};
212
+
struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
213
213
u8 tbl_sel;
214
214
215
215
for (tbl_sel = 0; tbl_sel < ARRAY_SIZE(desc); tbl_sel++) {
···
229
229
rfk_mcc->data[path].ch[tbl_sel] = chan->channel;
230
230
rfk_mcc->data[path].band[tbl_sel] = chan->band_type;
231
231
rfk_mcc->data[path].bw[tbl_sel] = chan->band_width;
232
+
rfk_mcc->data[path].rf18[tbl_sel] = rtw89_chip_chan_to_rf18_val(rtwdev, chan);
232
233
rfk_mcc->data[path].table_idx = tbl_sel;
233
234
234
235
return tbl_sel;
236
+
}
237
+
238
+
static u8 rtw8922a_chlk_reload_sel_tbl_v1(struct rtw89_dev *rtwdev,
239
+
const struct rtw89_chan *chan, u8 path)
240
+
{
241
+
struct rtw89_rfk_mcc_info_data *rfk_mcc = rtwdev->rfk_mcc.data;
242
+
struct rtw89_rfk_chan_desc desc[__RTW89_RFK_CHS_NR_V1] = {};
243
+
u8 tbl_sel;
244
+
245
+
for (tbl_sel = 0; tbl_sel < ARRAY_SIZE(desc); tbl_sel++) {
246
+
struct rtw89_rfk_chan_desc *p = &desc[tbl_sel];
247
+
248
+
p->ch = rfk_mcc->ch[tbl_sel];
249
+
250
+
p->has_band = true;
251
+
p->band = rfk_mcc->band[tbl_sel];
252
+
253
+
p->has_bw = true;
254
+
p->bw = rfk_mcc->bw[tbl_sel];
255
+
}
256
+
257
+
tbl_sel = rtw89_rfk_chan_lookup(rtwdev, desc, ARRAY_SIZE(desc), chan);
258
+
259
+
rfk_mcc->ch[tbl_sel] = chan->channel;
260
+
rfk_mcc->band[tbl_sel] = chan->band_type;
261
+
rfk_mcc->bw[tbl_sel] = chan->band_width;
262
+
rfk_mcc->rf18[tbl_sel] = rtw89_chip_chan_to_rf18_val(rtwdev, chan);
263
+
264
+
/* shared table array, but tbl_sel can be independent by path */
265
+
rfk_mcc[path].table_idx = tbl_sel;
266
+
267
+
return tbl_sel;
268
+
}
269
+
270
+
static u8 rtw8922a_chlk_reload_sel_tbl(struct rtw89_dev *rtwdev,
271
+
const struct rtw89_chan *chan, u8 path)
272
+
{
273
+
if (RTW89_CHK_FW_FEATURE(RFK_PRE_NOTIFY_MCC_V1, &rtwdev->fw))
274
+
return rtw8922a_chlk_reload_sel_tbl_v1(rtwdev, chan, path);
275
+
else
276
+
return rtw8922a_chlk_reload_sel_tbl_v0(rtwdev, chan, path);
235
277
}
236
278
237
279
static void rtw8922a_chlk_reload(struct rtw89_dev *rtwdev)
+10
drivers/net/wireless/realtek/rtw89/ser.c
+10
drivers/net/wireless/realtek/rtw89/ser.c
···
431
431
rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_RCVY_EN);
432
432
}
433
433
434
+
static void hal_enable_err_imr(struct rtw89_ser *ser)
435
+
{
436
+
struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser);
437
+
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
438
+
439
+
mac->err_imr_ctrl(rtwdev, true);
440
+
}
441
+
434
442
/* state handler */
435
443
static void ser_idle_st_hdl(struct rtw89_ser *ser, u8 evt)
436
444
{
···
560
552
break;
561
553
562
554
case SER_EV_MAC_RESET_DONE:
555
+
hal_enable_err_imr(ser);
556
+
563
557
ser_state_goto(ser, SER_IDLE_ST);
564
558
break;
565
559
+22
drivers/net/wireless/realtek/rtw89/txrx.h
+22
drivers/net/wireless/realtek/rtw89/txrx.h
···
188
188
#define BE_TXD_BODY2_QSEL GENMASK(22, 17)
189
189
#define BE_TXD_BODY2_TID_IND BIT(23)
190
190
#define BE_TXD_BODY2_MACID GENMASK(31, 24)
191
+
#define BE_TXD_BODY2_QSEL_V1 GENMASK(20, 15)
192
+
#define BE_TXD_BODY2_TID_IND_V1 BIT(21)
193
+
#define BE_TXD_BODY2_MACID_V1 GENMASK(31, 22)
191
194
192
195
/* TX WD BODY DWORD 3 */
193
196
#define BE_TXD_BODY3_WIFI_SEQ GENMASK(11, 0)
194
197
#define BE_TXD_BODY3_MLO_FLAG BIT(12)
195
198
#define BE_TXD_BODY3_IS_MLD_SW_EN BIT(13)
196
199
#define BE_TXD_BODY3_TRY_RATE BIT(14)
200
+
#define BE_TXD_BODY3_BK_V1 BIT(14)
197
201
#define BE_TXD_BODY3_RELINK_FLAG_V1 BIT(15)
198
202
#define BE_TXD_BODY3_BAND0_SU_TC_V1 GENMASK(21, 16)
199
203
#define BE_TXD_BODY3_TOTAL_TC GENMASK(27, 22)
···
205
201
#define BE_TXD_BODY3_MU_PRI_RTY BIT(29)
206
202
#define BE_TXD_BODY3_MU_2ND_RTY BIT(30)
207
203
#define BE_TXD_BODY3_BAND1_SU_RTY_V1 BIT(31)
204
+
#define BE_TXD_BODY3_DRIVER_QUEUE_TIME GENMASK(31, 16)
208
205
209
206
/* TX WD BODY DWORD 4 */
210
207
#define BE_TXD_BODY4_TXDESC_CHECKSUM GENMASK(15, 0)
···
229
224
#define BE_TXD_BODY6_EOSP_BIT BIT(15)
230
225
#define BE_TXD_BODY6_S_IDX GENMASK(23, 16)
231
226
#define BE_TXD_BODY6_RU_POS GENMASK(31, 24)
227
+
#define BE_TXD_BODY6_MU_TC_V1 GENMASK(3, 0)
228
+
#define BE_TXD_BODY6_RU_TC_V1 GENMASK(8, 5)
229
+
#define BE_TXD_BODY6_RELINK_EN BIT(9)
230
+
#define BE_TXD_BODY6_RELINK_LAST BIT(10)
232
231
233
232
/* TX WD BODY DWORD 7 */
234
233
#define BE_TXD_BODY7_RTS_TC GENMASK(5, 0)
···
271
262
/* TX WD INFO DWORD 2 */
272
263
#define BE_TXD_INFO2_SEC_CAM_IDX GENMASK(7, 0)
273
264
#define BE_TXD_INFO2_FORCE_KEY_EN BIT(8)
265
+
#define BE_TXD_INFO2_SEC_CAM_IDX_V1 GENMASK(9, 0)
266
+
#define BE_TXD_INFO2_FORCE_KEY_EN_V1 BIT(10)
274
267
#define BE_TXD_INFO2_LIFETIME_SEL GENMASK(15, 13)
275
268
#define BE_TXD_INFO2_FORCE_TXOP BIT(17)
276
269
#define BE_TXD_INFO2_AMPDU_DENSITY GENMASK(20, 18)
···
288
277
#define BE_TXD_INFO3_RTT_EN BIT(9)
289
278
#define BE_TXD_INFO3_HT_DATA_SND_V1 BIT(10)
290
279
#define BE_TXD_INFO3_BT_NULL BIT(11)
280
+
#define BE_TXD_INFO3_DISABLE_TXBF BIT(11)
291
281
#define BE_TXD_INFO3_TRI_FRAME BIT(12)
292
282
#define BE_TXD_INFO3_NULL_0 BIT(13)
293
283
#define BE_TXD_INFO3_NULL_1 BIT(14)
···
304
292
#define BE_TXD_INFO4_PUNC_MODE GENMASK(17, 16)
305
293
#define BE_TXD_INFO4_SW_TX_OK_0 BIT(18)
306
294
#define BE_TXD_INFO4_SW_TX_OK_1 BIT(19)
295
+
#define BE_TXD_INFO4_SW_EHT_NLTF_SWITCH BIT(20)
296
+
#define BE_TXD_INFO4_SW_EHT_NLTF GENMASK(22, 21)
307
297
#define BE_TXD_INFO4_SW_TX_PWR_DBM GENMASK(26, 23)
308
298
#define BE_TXD_INFO4_RTS_EN BIT(27)
309
299
#define BE_TXD_INFO4_CTS2SELF BIT(28)
···
322
308
#define BE_TXD_INFO6_UL_GI_LTF GENMASK(14, 12)
323
309
#define BE_TXD_INFO6_UL_DOPPLER BIT(15)
324
310
#define BE_TXD_INFO6_UL_STBC BIT(16)
311
+
#define BE_TXD_INFO6_UL_MU_MIMO_EN BIT(17)
325
312
#define BE_TXD_INFO6_UL_LENGTH_REF GENMASK(21, 18)
326
313
#define BE_TXD_INFO6_UL_RF_GAIN_IDX GENMASK(31, 22)
327
314
···
337
322
#define BE_TXD_INFO7_UL_HELTF_SYMBOL_NUM GENMASK(19, 17)
338
323
#define BE_TXD_INFO7_ULBW GENMASK(21, 20)
339
324
#define BE_TXD_INFO7_ULBW_EXT GENMASK(23, 22)
325
+
#define BE_TXD_INFO7_UL_TRI_PAD_TSF BIT(24)
340
326
#define BE_TXD_INFO7_USE_WD_UL GENMASK(25, 24)
341
327
#define BE_TXD_INFO7_EXTEND_MODE_SEL GENMASK(31, 28)
342
328
···
504
488
505
489
/* BE RXD dword2 */
506
490
#define BE_RXD_MAC_ID_MASK GENMASK(7, 0)
491
+
#define BE_RXD_MAC_ID_V1 GENMASK(9, 0)
507
492
#define BE_RXD_TYPE_MASK GENMASK(11, 10)
508
493
#define BE_RXD_LAST_MSDU BIT(12)
509
494
#define BE_RXD_AMSDU_CUT BIT(13)
···
536
519
#define BE_RXD_QNULL BIT(22)
537
520
#define BE_RXD_A4_FRAME BIT(23)
538
521
#define BE_RXD_FRAG_MASK GENMASK(27, 24)
522
+
#define BE_RXD_GET_CH_INFO_V2 GENMASK(31, 29)
539
523
#define BE_RXD_GET_CH_INFO_V1_MASK GENMASK(31, 30)
540
524
541
525
/* BE RXD dword4 */
···
552
534
553
535
/* BE RXD dword6 */
554
536
#define BE_RXD_ADDR_CAM_MASK GENMASK(7, 0)
537
+
#define BE_RXD_ADDR_CAM_V1 GENMASK(9, 0)
538
+
#define BE_RXD_RX_STATISTICS_V1 BIT(11)
539
+
#define BE_RXD_SMART_ANT_V1 BIT(12)
555
540
#define BE_RXD_SR_EN BIT(13)
556
541
#define BE_RXD_NON_SRG_PPDU BIT(14)
557
542
#define BE_RXD_INTER_PPDU BIT(15)
558
543
#define BE_RXD_USER_ID_MASK GENMASK(21, 16)
544
+
#define BE_RXD_SEC_CAM_IDX_V1 GENMASK(31, 22)
559
545
#define BE_RXD_RX_STATISTICS BIT(22)
560
546
#define BE_RXD_SMART_ANT BIT(23)
561
547
#define BE_RXD_SEC_CAM_IDX_MASK GENMASK(31, 24)
+1
-1
drivers/net/wireless/realtek/rtw89/usb.c
+1
-1
drivers/net/wireless/realtek/rtw89/usb.c
···
620
620
struct sk_buff *rx_skb;
621
621
int i;
622
622
623
-
rtwusb->rxwq = alloc_workqueue("rtw89_usb: rx wq", WQ_BH, 0);
623
+
rtwusb->rxwq = alloc_workqueue("rtw89_usb: rx wq", WQ_BH | WQ_PERCPU, 0);
624
624
if (!rtwusb->rxwq) {
625
625
rtw89_err(rtwdev, "failed to create RX work queue\n");
626
626
return -ENOMEM;
+6
-2
drivers/net/wireless/realtek/rtw89/wow.c
+6
-2
drivers/net/wireless/realtek/rtw89/wow.c
···
809
809
810
810
reason = rtw89_read8(rtwdev, wow_reason_reg);
811
811
switch (reason) {
812
+
case RTW89_WOW_RSN_RX_DISASSOC:
813
+
wakeup.disconnect = true;
814
+
rtw89_debug(rtwdev, RTW89_DBG_WOW, "WOW: Rx disassoc\n");
815
+
break;
812
816
case RTW89_WOW_RSN_RX_DEAUTH:
813
817
wakeup.disconnect = true;
814
818
rtw89_debug(rtwdev, RTW89_DBG_WOW, "WOW: Rx deauth\n");
···
1074
1070
for (i = 0; i < rtw_wow->pattern_cnt; i++) {
1075
1071
rtw_pattern = &rtw_wow->patterns[i];
1076
1072
rtw_pattern->valid = false;
1077
-
rtw89_fw_wow_cam_update(rtwdev, rtw_pattern);
1073
+
rtw89_chip_h2c_wow_cam_update(rtwdev, rtw_pattern);
1078
1074
}
1079
1075
}
1080
1076
···
1085
1081
int i;
1086
1082
1087
1083
for (i = 0; i < rtw_wow->pattern_cnt; i++)
1088
-
rtw89_fw_wow_cam_update(rtwdev, rtw_pattern + i);
1084
+
rtw89_chip_h2c_wow_cam_update(rtwdev, rtw_pattern + i);
1089
1085
}
1090
1086
1091
1087
static void rtw89_wow_pattern_clear(struct rtw89_dev *rtwdev)
+1
drivers/net/wireless/realtek/rtw89/wow.h
+1
drivers/net/wireless/realtek/rtw89/wow.h