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clk: qcom: dispcc-sm8750: Fix setting rate byte and pixel clocks

On SM8750 the setting rate of pixel and byte clocks, while the parent
DSI PHY PLL, fails with:

disp_cc_mdss_byte0_clk_src: rcg didn't update its configuration.

DSI PHY PLL has to be unprepared and its "PLL Power Down" bits in
CMN_CTRL_0 asserted.

Mark these clocks with CLK_OPS_PARENT_ENABLE to ensure the parent is
enabled during rate changes.

Cc: stable@vger.kernel.org
Fixes: f1080d8dab0f ("clk: qcom: dispcc-sm8750: Add SM8750 Display clock controller")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250520090741.45820-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Krzysztof Kozlowski and committed by
Bjorn Andersson 0acf9e65 077ec7bc

+5 -5
+5 -5
drivers/clk/qcom/dispcc-sm8750.c
··· 393 393 .name = "disp_cc_mdss_byte0_clk_src", 394 394 .parent_data = disp_cc_parent_data_1, 395 395 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 396 - .flags = CLK_SET_RATE_PARENT, 396 + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 397 397 .ops = &clk_byte2_ops, 398 398 }, 399 399 }; ··· 408 408 .name = "disp_cc_mdss_byte1_clk_src", 409 409 .parent_data = disp_cc_parent_data_1, 410 410 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 411 - .flags = CLK_SET_RATE_PARENT, 411 + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 412 412 .ops = &clk_byte2_ops, 413 413 }, 414 414 }; ··· 712 712 .name = "disp_cc_mdss_pclk0_clk_src", 713 713 .parent_data = disp_cc_parent_data_1, 714 714 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 715 - .flags = CLK_SET_RATE_PARENT, 715 + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 716 716 .ops = &clk_pixel_ops, 717 717 }, 718 718 }; ··· 727 727 .name = "disp_cc_mdss_pclk1_clk_src", 728 728 .parent_data = disp_cc_parent_data_1, 729 729 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 730 - .flags = CLK_SET_RATE_PARENT, 730 + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 731 731 .ops = &clk_pixel_ops, 732 732 }, 733 733 }; ··· 742 742 .name = "disp_cc_mdss_pclk2_clk_src", 743 743 .parent_data = disp_cc_parent_data_1, 744 744 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 745 - .flags = CLK_SET_RATE_PARENT, 745 + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 746 746 .ops = &clk_pixel_ops, 747 747 }, 748 748 };