tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma

Pull rdma updates from Jason Gunthorpe:
"Lighter that normal, but the now usual collection of driver fixes and
small improvements:

- Small fixes and minor improvements to cxgb4, bnxt_re, rxe, srp,
efa, cxgb4

- Update mlx4 to use the new umem APIs, avoiding direct use of
scatterlist

- Support ROCEv2 in erdma

- Remove various uncalled functions, constify bin_attribute

- Provide core infrastructure to catch netdev events and route them
to drivers, consolidating duplicated driver code

- Fix rare race condition crashes in mlx5 ODP flows"

* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma: (63 commits)
RDMA/mlx5: Fix implicit ODP use after free
RDMA/mlx5: Fix a race for an ODP MR which leads to CQE with error
RDMA/qib: Constify 'struct bin_attribute'
RDMA/hfi1: Constify 'struct bin_attribute'
RDMA/rxe: Fix the warning "__rxe_cleanup+0x12c/0x170 [rdma_rxe]"
RDMA/cxgb4: Notify rdma stack for IB_EVENT_QP_LAST_WQE_REACHED event
RDMA/bnxt_re: Allocate dev_attr information dynamically
RDMA/bnxt_re: Pass the context for ulp_irq_stop
RDMA/bnxt_re: Add support to handle DCB_CONFIG_CHANGE event
RDMA/bnxt_re: Query firmware defaults of CC params during probe
RDMA/bnxt_re: Add Async event handling support
bnxt_en: Add ULP call to notify async events
RDMA/mlx5: Fix indirect mkey ODP page count
MAINTAINERS: Update the bnxt_re maintainers
RDMA/hns: Clean up the legacy CONFIG_INFINIBAND_HNS
RDMA/rtrs: Add missing deinit() call
RDMA/efa: Align interrupt related fields to same type
RDMA/bnxt_re: Fix to drop reference to the mmap entry in case of error
RDMA/mlx5: Fix link status down event for MPV
RDMA/erdma: Support create_ah/destroy_ah in non-sleepable contexts
...

Linus Torvalds 0afd2209 aa44198a

+2014 -1259
+1
MAINTAINERS
··· 4800 4800 4801 4801 BROADCOM NETXTREME-E ROCE DRIVER 4802 4802 M: Selvin Xavier <selvin.xavier@broadcom.com> 4803 + M: Kalesh AP <kalesh-anakkur.purayil@broadcom.com> 4803 4804 L: linux-rdma@vger.kernel.org 4804 4805 S: Supported 4805 4806 W: http://www.broadcom.com
-35
drivers/infiniband/core/cache.c
··· 1127 1127 } 1128 1128 EXPORT_SYMBOL(ib_find_cached_pkey); 1129 1129 1130 - int ib_find_exact_cached_pkey(struct ib_device *device, u32 port_num, 1131 - u16 pkey, u16 *index) 1132 - { 1133 - struct ib_pkey_cache *cache; 1134 - unsigned long flags; 1135 - int i; 1136 - int ret = -ENOENT; 1137 - 1138 - if (!rdma_is_port_valid(device, port_num)) 1139 - return -EINVAL; 1140 - 1141 - read_lock_irqsave(&device->cache_lock, flags); 1142 - 1143 - cache = device->port_data[port_num].cache.pkey; 1144 - if (!cache) { 1145 - ret = -EINVAL; 1146 - goto err; 1147 - } 1148 - 1149 - *index = -1; 1150 - 1151 - for (i = 0; i < cache->table_len; ++i) 1152 - if (cache->table[i] == pkey) { 1153 - *index = i; 1154 - ret = 0; 1155 - break; 1156 - } 1157 - 1158 - err: 1159 - read_unlock_irqrestore(&device->cache_lock, flags); 1160 - 1161 - return ret; 1162 - } 1163 - EXPORT_SYMBOL(ib_find_exact_cached_pkey); 1164 - 1165 1130 int ib_get_cached_lmc(struct ib_device *device, u32 port_num, u8 *lmc) 1166 1131 { 1167 1132 unsigned long flags;
+92 -24
drivers/infiniband/core/device.c
··· 209 209 printk("%s(NULL ib_device): %pV", level, vaf); 210 210 } 211 211 212 - void ibdev_printk(const char *level, const struct ib_device *ibdev, 213 - const char *format, ...) 214 - { 215 - struct va_format vaf; 216 - va_list args; 217 - 218 - va_start(args, format); 219 - 220 - vaf.fmt = format; 221 - vaf.va = &args; 222 - 223 - __ibdev_printk(level, ibdev, &vaf); 224 - 225 - va_end(args); 226 - } 227 - EXPORT_SYMBOL(ibdev_printk); 228 - 229 212 #define define_ibdev_printk_level(func, level) \ 230 213 void func(const struct ib_device *ibdev, const char *fmt, ...) \ 231 214 { \ ··· 2279 2296 EXPORT_SYMBOL(ib_device_get_netdev); 2280 2297 2281 2298 /** 2299 + * ib_query_netdev_port - Query the port number of a net_device 2300 + * associated with an ibdev 2301 + * @ibdev: IB device 2302 + * @ndev: Network device 2303 + * @port: IB port the net_device is connected to 2304 + */ 2305 + int ib_query_netdev_port(struct ib_device *ibdev, struct net_device *ndev, 2306 + u32 *port) 2307 + { 2308 + struct net_device *ib_ndev; 2309 + u32 port_num; 2310 + 2311 + rdma_for_each_port(ibdev, port_num) { 2312 + ib_ndev = ib_device_get_netdev(ibdev, port_num); 2313 + if (ndev == ib_ndev) { 2314 + *port = port_num; 2315 + dev_put(ib_ndev); 2316 + return 0; 2317 + } 2318 + dev_put(ib_ndev); 2319 + } 2320 + 2321 + return -ENOENT; 2322 + } 2323 + EXPORT_SYMBOL(ib_query_netdev_port); 2324 + 2325 + /** 2282 2326 * ib_device_get_by_netdev - Find an IB device associated with a netdev 2283 2327 * @ndev: netdev to locate 2284 2328 * @driver_id: The driver ID that must match (RDMA_DRIVER_UNKNOWN matches all) ··· 2771 2761 SET_DEVICE_OP(dev_ops, set_vf_guid); 2772 2762 SET_DEVICE_OP(dev_ops, set_vf_link_state); 2773 2763 SET_DEVICE_OP(dev_ops, ufile_hw_cleanup); 2764 + SET_DEVICE_OP(dev_ops, report_port_event); 2774 2765 2775 2766 SET_OBJ_SIZE(dev_ops, ib_ah); 2776 2767 SET_OBJ_SIZE(dev_ops, ib_counters); ··· 2865 2854 }, 2866 2855 }; 2867 2856 2857 + void ib_dispatch_port_state_event(struct ib_device *ibdev, struct net_device *ndev) 2858 + { 2859 + enum ib_port_state curr_state; 2860 + struct ib_event ibevent = {}; 2861 + u32 port; 2862 + 2863 + if (ib_query_netdev_port(ibdev, ndev, &port)) 2864 + return; 2865 + 2866 + curr_state = ib_get_curr_port_state(ndev); 2867 + 2868 + write_lock_irq(&ibdev->cache_lock); 2869 + if (ibdev->port_data[port].cache.last_port_state == curr_state) { 2870 + write_unlock_irq(&ibdev->cache_lock); 2871 + return; 2872 + } 2873 + ibdev->port_data[port].cache.last_port_state = curr_state; 2874 + write_unlock_irq(&ibdev->cache_lock); 2875 + 2876 + ibevent.event = (curr_state == IB_PORT_DOWN) ? 2877 + IB_EVENT_PORT_ERR : IB_EVENT_PORT_ACTIVE; 2878 + ibevent.device = ibdev; 2879 + ibevent.element.port_num = port; 2880 + ib_dispatch_event(&ibevent); 2881 + } 2882 + EXPORT_SYMBOL(ib_dispatch_port_state_event); 2883 + 2884 + static void handle_port_event(struct net_device *ndev, unsigned long event) 2885 + { 2886 + struct ib_device *ibdev; 2887 + 2888 + /* Currently, link events in bonding scenarios are still 2889 + * reported by drivers that support bonding. 2890 + */ 2891 + if (netif_is_lag_master(ndev) || netif_is_lag_port(ndev)) 2892 + return; 2893 + 2894 + ibdev = ib_device_get_by_netdev(ndev, RDMA_DRIVER_UNKNOWN); 2895 + if (!ibdev) 2896 + return; 2897 + 2898 + if (ibdev->ops.report_port_event) { 2899 + ibdev->ops.report_port_event(ibdev, ndev, event); 2900 + goto put_ibdev; 2901 + } 2902 + 2903 + ib_dispatch_port_state_event(ibdev, ndev); 2904 + 2905 + put_ibdev: 2906 + ib_device_put(ibdev); 2907 + }; 2908 + 2868 2909 static int ib_netdevice_event(struct notifier_block *this, 2869 2910 unsigned long event, void *ptr) 2870 2911 { 2871 2912 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 2872 - struct net_device *ib_ndev; 2873 2913 struct ib_device *ibdev; 2874 2914 u32 port; 2875 2915 ··· 2930 2868 if (!ibdev) 2931 2869 return NOTIFY_DONE; 2932 2870 2933 - rdma_for_each_port(ibdev, port) { 2934 - ib_ndev = ib_device_get_netdev(ibdev, port); 2935 - if (ndev == ib_ndev) 2936 - rdma_nl_notify_event(ibdev, port, 2937 - RDMA_NETDEV_RENAME_EVENT); 2938 - dev_put(ib_ndev); 2871 + if (ib_query_netdev_port(ibdev, ndev, &port)) { 2872 + ib_device_put(ibdev); 2873 + break; 2939 2874 } 2875 + 2876 + rdma_nl_notify_event(ibdev, port, RDMA_NETDEV_RENAME_EVENT); 2940 2877 ib_device_put(ibdev); 2941 2878 break; 2879 + 2880 + case NETDEV_UP: 2881 + case NETDEV_CHANGE: 2882 + case NETDEV_DOWN: 2883 + handle_port_event(ndev, event); 2884 + break; 2885 + 2942 2886 default: 2943 2887 break; 2944 2888 }
-83
drivers/infiniband/core/ud_header.c
··· 462 462 return len; 463 463 } 464 464 EXPORT_SYMBOL(ib_ud_header_pack); 465 - 466 - /** 467 - * ib_ud_header_unpack - Unpack UD header struct from wire format 468 - * @header:UD header struct 469 - * @buf:Buffer to pack into 470 - * 471 - * ib_ud_header_pack() unpacks the UD header structure @header from wire 472 - * format in the buffer @buf. 473 - */ 474 - int ib_ud_header_unpack(void *buf, 475 - struct ib_ud_header *header) 476 - { 477 - ib_unpack(lrh_table, ARRAY_SIZE(lrh_table), 478 - buf, &header->lrh); 479 - buf += IB_LRH_BYTES; 480 - 481 - if (header->lrh.link_version != 0) { 482 - pr_warn("Invalid LRH.link_version %u\n", 483 - header->lrh.link_version); 484 - return -EINVAL; 485 - } 486 - 487 - switch (header->lrh.link_next_header) { 488 - case IB_LNH_IBA_LOCAL: 489 - header->grh_present = 0; 490 - break; 491 - 492 - case IB_LNH_IBA_GLOBAL: 493 - header->grh_present = 1; 494 - ib_unpack(grh_table, ARRAY_SIZE(grh_table), 495 - buf, &header->grh); 496 - buf += IB_GRH_BYTES; 497 - 498 - if (header->grh.ip_version != 6) { 499 - pr_warn("Invalid GRH.ip_version %u\n", 500 - header->grh.ip_version); 501 - return -EINVAL; 502 - } 503 - if (header->grh.next_header != 0x1b) { 504 - pr_warn("Invalid GRH.next_header 0x%02x\n", 505 - header->grh.next_header); 506 - return -EINVAL; 507 - } 508 - break; 509 - 510 - default: 511 - pr_warn("Invalid LRH.link_next_header %u\n", 512 - header->lrh.link_next_header); 513 - return -EINVAL; 514 - } 515 - 516 - ib_unpack(bth_table, ARRAY_SIZE(bth_table), 517 - buf, &header->bth); 518 - buf += IB_BTH_BYTES; 519 - 520 - switch (header->bth.opcode) { 521 - case IB_OPCODE_UD_SEND_ONLY: 522 - header->immediate_present = 0; 523 - break; 524 - case IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE: 525 - header->immediate_present = 1; 526 - break; 527 - default: 528 - pr_warn("Invalid BTH.opcode 0x%02x\n", header->bth.opcode); 529 - return -EINVAL; 530 - } 531 - 532 - if (header->bth.transport_header_version != 0) { 533 - pr_warn("Invalid BTH.transport_header_version %u\n", 534 - header->bth.transport_header_version); 535 - return -EINVAL; 536 - } 537 - 538 - ib_unpack(deth_table, ARRAY_SIZE(deth_table), 539 - buf, &header->deth); 540 - buf += IB_DETH_BYTES; 541 - 542 - if (header->immediate_present) 543 - memcpy(&header->immediate_data, buf, sizeof header->immediate_data); 544 - 545 - return 0; 546 - } 547 - EXPORT_SYMBOL(ib_ud_header_unpack);
-42
drivers/infiniband/core/uverbs_marshall.c
··· 171 171 __ib_copy_path_rec_to_user(dst, src); 172 172 } 173 173 EXPORT_SYMBOL(ib_copy_path_rec_to_user); 174 - 175 - void ib_copy_path_rec_from_user(struct sa_path_rec *dst, 176 - struct ib_user_path_rec *src) 177 - { 178 - u32 slid, dlid; 179 - 180 - memset(dst, 0, sizeof(*dst)); 181 - if ((ib_is_opa_gid((union ib_gid *)src->sgid)) || 182 - (ib_is_opa_gid((union ib_gid *)src->dgid))) { 183 - dst->rec_type = SA_PATH_REC_TYPE_OPA; 184 - slid = opa_get_lid_from_gid((union ib_gid *)src->sgid); 185 - dlid = opa_get_lid_from_gid((union ib_gid *)src->dgid); 186 - } else { 187 - dst->rec_type = SA_PATH_REC_TYPE_IB; 188 - slid = ntohs(src->slid); 189 - dlid = ntohs(src->dlid); 190 - } 191 - memcpy(dst->dgid.raw, src->dgid, sizeof dst->dgid); 192 - memcpy(dst->sgid.raw, src->sgid, sizeof dst->sgid); 193 - 194 - sa_path_set_dlid(dst, dlid); 195 - sa_path_set_slid(dst, slid); 196 - sa_path_set_raw_traffic(dst, src->raw_traffic); 197 - dst->flow_label = src->flow_label; 198 - dst->hop_limit = src->hop_limit; 199 - dst->traffic_class = src->traffic_class; 200 - dst->reversible = src->reversible; 201 - dst->numb_path = src->numb_path; 202 - dst->pkey = src->pkey; 203 - dst->sl = src->sl; 204 - dst->mtu_selector = src->mtu_selector; 205 - dst->mtu = src->mtu; 206 - dst->rate_selector = src->rate_selector; 207 - dst->rate = src->rate; 208 - dst->packet_life_time = src->packet_life_time; 209 - dst->preference = src->preference; 210 - dst->packet_life_time_selector = src->packet_life_time_selector; 211 - 212 - /* TODO: No need to set this */ 213 - sa_path_set_dmac_zero(dst); 214 - } 215 - EXPORT_SYMBOL(ib_copy_path_rec_from_user);
+1 -1
drivers/infiniband/hw/Makefile
··· 11 11 obj-$(CONFIG_INFINIBAND_VMWARE_PVRDMA) += vmw_pvrdma/ 12 12 obj-$(CONFIG_INFINIBAND_USNIC) += usnic/ 13 13 obj-$(CONFIG_INFINIBAND_HFI1) += hfi1/ 14 - obj-$(CONFIG_INFINIBAND_HNS) += hns/ 14 + obj-$(CONFIG_INFINIBAND_HNS_HIP08) += hns/ 15 15 obj-$(CONFIG_INFINIBAND_QEDR) += qedr/ 16 16 obj-$(CONFIG_INFINIBAND_BNXT_RE) += bnxt_re/ 17 17 obj-$(CONFIG_INFINIBAND_ERDMA) += erdma/
+4 -1
drivers/infiniband/hw/bnxt_re/bnxt_re.h
··· 204 204 struct bnxt_re_nq_record *nqr; 205 205 206 206 /* Device Resources */ 207 - struct bnxt_qplib_dev_attr dev_attr; 207 + struct bnxt_qplib_dev_attr *dev_attr; 208 208 struct bnxt_qplib_ctx qplib_ctx; 209 209 struct bnxt_qplib_res qplib_res; 210 210 struct bnxt_qplib_dpi dpi_privileged; ··· 229 229 DECLARE_HASHTABLE(srq_hash, MAX_SRQ_HASH_BITS); 230 230 struct dentry *dbg_root; 231 231 struct dentry *qp_debugfs; 232 + unsigned long event_bitmap; 233 + struct bnxt_qplib_cc_param cc_param; 234 + struct workqueue_struct *dcb_wq; 232 235 }; 233 236 234 237 #define to_bnxt_re_dev(ptr, member) \
+1 -10
drivers/infiniband/hw/bnxt_re/hw_counters.c
··· 37 37 * 38 38 */ 39 39 40 - #include <linux/interrupt.h> 41 40 #include <linux/types.h> 42 - #include <linux/spinlock.h> 43 - #include <linux/sched.h> 44 - #include <linux/slab.h> 45 41 #include <linux/pci.h> 46 - #include <linux/prefetch.h> 47 - #include <linux/delay.h> 48 42 49 - #include <rdma/ib_addr.h> 50 - 51 - #include "bnxt_ulp.h" 52 43 #include "roce_hsi.h" 53 44 #include "qplib_res.h" 54 45 #include "qplib_sp.h" ··· 348 357 goto done; 349 358 } 350 359 bnxt_re_copy_err_stats(rdev, stats, err_s); 351 - if (_is_ext_stats_supported(rdev->dev_attr.dev_cap_flags) && 360 + if (_is_ext_stats_supported(rdev->dev_attr->dev_cap_flags) && 352 361 !rdev->is_virtfn) { 353 362 rc = bnxt_re_get_ext_stat(rdev, stats); 354 363 if (rc) {
+23 -24
drivers/infiniband/hw/bnxt_re/ib_verbs.c
··· 52 52 #include <rdma/uverbs_ioctl.h> 53 53 #include <linux/hashtable.h> 54 54 55 - #include "bnxt_ulp.h" 56 - 57 55 #include "roce_hsi.h" 58 56 #include "qplib_res.h" 59 57 #include "qplib_sp.h" ··· 159 161 static void bnxt_re_check_and_set_relaxed_ordering(struct bnxt_re_dev *rdev, 160 162 struct bnxt_qplib_mrw *qplib_mr) 161 163 { 162 - if (_is_relaxed_ordering_supported(rdev->dev_attr.dev_cap_flags2) && 164 + if (_is_relaxed_ordering_supported(rdev->dev_attr->dev_cap_flags2) && 163 165 pcie_relaxed_ordering_enabled(rdev->en_dev->pdev)) 164 166 qplib_mr->flags |= CMDQ_REGISTER_MR_FLAGS_ENABLE_RO; 165 167 } ··· 184 186 struct ib_udata *udata) 185 187 { 186 188 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 187 - struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 189 + struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 188 190 189 191 memset(ib_attr, 0, sizeof(*ib_attr)); 190 192 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver, ··· 273 275 struct ib_port_attr *port_attr) 274 276 { 275 277 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 276 - struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 278 + struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 277 279 int rc; 278 280 279 281 memset(port_attr, 0, sizeof(*port_attr)); ··· 331 333 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 332 334 333 335 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d", 334 - rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1], 335 - rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]); 336 + rdev->dev_attr->fw_ver[0], rdev->dev_attr->fw_ver[1], 337 + rdev->dev_attr->fw_ver[2], rdev->dev_attr->fw_ver[3]); 336 338 } 337 339 338 340 int bnxt_re_query_pkey(struct ib_device *ibdev, u32 port_num, ··· 583 585 mr->qplib_mr.pd = &pd->qplib_pd; 584 586 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 585 587 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags); 586 - if (!_is_alloc_mr_unified(rdev->dev_attr.dev_cap_flags)) { 588 + if (!_is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags)) { 587 589 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 588 590 if (rc) { 589 591 ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n"); ··· 1055 1057 rdev = qp->rdev; 1056 1058 qplqp = &qp->qplib_qp; 1057 1059 sq = &qplqp->sq; 1058 - dev_attr = &rdev->dev_attr; 1060 + dev_attr = rdev->dev_attr; 1059 1061 1060 1062 align = sizeof(struct sq_send_hdr); 1061 1063 ilsize = ALIGN(init_attr->cap.max_inline_data, align); ··· 1275 1277 rdev = qp->rdev; 1276 1278 qplqp = &qp->qplib_qp; 1277 1279 rq = &qplqp->rq; 1278 - dev_attr = &rdev->dev_attr; 1280 + dev_attr = rdev->dev_attr; 1279 1281 1280 1282 if (init_attr->srq) { 1281 1283 struct bnxt_re_srq *srq; ··· 1312 1314 1313 1315 rdev = qp->rdev; 1314 1316 qplqp = &qp->qplib_qp; 1315 - dev_attr = &rdev->dev_attr; 1317 + dev_attr = rdev->dev_attr; 1316 1318 1317 1319 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 1318 1320 qplqp->rq.max_sge = dev_attr->max_qp_sges; ··· 1338 1340 rdev = qp->rdev; 1339 1341 qplqp = &qp->qplib_qp; 1340 1342 sq = &qplqp->sq; 1341 - dev_attr = &rdev->dev_attr; 1343 + dev_attr = rdev->dev_attr; 1342 1344 1343 1345 sq->max_sge = init_attr->cap.max_send_sge; 1344 1346 entries = init_attr->cap.max_send_wr; ··· 1391 1393 1392 1394 rdev = qp->rdev; 1393 1395 qplqp = &qp->qplib_qp; 1394 - dev_attr = &rdev->dev_attr; 1396 + dev_attr = rdev->dev_attr; 1395 1397 1396 1398 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) { 1397 1399 entries = bnxt_re_init_depth(init_attr->cap.max_send_wr + 1, uctx); ··· 1440 1442 1441 1443 rdev = qp->rdev; 1442 1444 qplqp = &qp->qplib_qp; 1443 - dev_attr = &rdev->dev_attr; 1445 + dev_attr = rdev->dev_attr; 1444 1446 1445 1447 /* Setup misc params */ 1446 1448 ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr); ··· 1610 1612 ib_pd = ib_qp->pd; 1611 1613 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1612 1614 rdev = pd->rdev; 1613 - dev_attr = &rdev->dev_attr; 1615 + dev_attr = rdev->dev_attr; 1614 1616 qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1615 1617 1616 1618 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); ··· 1838 1840 ib_pd = ib_srq->pd; 1839 1841 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1840 1842 rdev = pd->rdev; 1841 - dev_attr = &rdev->dev_attr; 1843 + dev_attr = rdev->dev_attr; 1842 1844 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq); 1843 1845 1844 1846 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) { ··· 2042 2044 { 2043 2045 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2044 2046 struct bnxt_re_dev *rdev = qp->rdev; 2045 - struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 2047 + struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 2046 2048 enum ib_qp_state curr_qp_state, new_qp_state; 2047 2049 int rc, entries; 2048 2050 unsigned int flags; ··· 3089 3091 struct ib_udata *udata = &attrs->driver_udata; 3090 3092 struct bnxt_re_ucontext *uctx = 3091 3093 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx); 3092 - struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 3094 + struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 3093 3095 struct bnxt_qplib_chip_ctx *cctx; 3094 3096 int cqe = attr->cqe; 3095 3097 int rc, entries; ··· 3224 3226 3225 3227 cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 3226 3228 rdev = cq->rdev; 3227 - dev_attr = &rdev->dev_attr; 3229 + dev_attr = rdev->dev_attr; 3228 3230 if (!ibcq->uobject) { 3229 3231 ibdev_err(&rdev->ibdev, "Kernel CQ Resize not supported"); 3230 3232 return -EOPNOTSUPP; ··· 4197 4199 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags); 4198 4200 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR; 4199 4201 4200 - if (!_is_alloc_mr_unified(rdev->dev_attr.dev_cap_flags)) { 4202 + if (!_is_alloc_mr_unified(rdev->dev_attr->dev_cap_flags)) { 4201 4203 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 4202 4204 if (rc) { 4203 4205 ibdev_err(&rdev->ibdev, "Failed to allocate MR rc = %d", rc); ··· 4289 4291 struct bnxt_re_ucontext *uctx = 4290 4292 container_of(ctx, struct bnxt_re_ucontext, ib_uctx); 4291 4293 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 4292 - struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 4294 + struct bnxt_qplib_dev_attr *dev_attr = rdev->dev_attr; 4293 4295 struct bnxt_re_user_mmap_entry *entry; 4294 4296 struct bnxt_re_uctx_resp resp = {}; 4295 4297 struct bnxt_re_uctx_req ureq = {}; ··· 4465 4467 case BNXT_RE_MMAP_TOGGLE_PAGE: 4466 4468 /* Driver doesn't expect write access for user space */ 4467 4469 if (vma->vm_flags & VM_WRITE) 4468 - return -EFAULT; 4469 - ret = vm_insert_page(vma, vma->vm_start, 4470 - virt_to_page((void *)bnxt_entry->mem_offset)); 4470 + ret = -EFAULT; 4471 + else 4472 + ret = vm_insert_page(vma, vma->vm_start, 4473 + virt_to_page((void *)bnxt_entry->mem_offset)); 4471 4474 break; 4472 4475 default: 4473 4476 ret = -EINVAL;
+213 -126
drivers/infiniband/hw/bnxt_re/main.c
··· 79 79 /* globals */ 80 80 static DEFINE_MUTEX(bnxt_re_mutex); 81 81 82 - static void bnxt_re_stop_irq(void *handle); 83 - static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev); 84 - static int bnxt_re_netdev_event(struct notifier_block *notifier, 85 - unsigned long event, void *ptr); 86 - static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev); 87 - static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev, u8 op_type); 88 82 static int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev); 89 83 90 84 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len, 91 85 u32 *offset); 92 - static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable); 86 + static void bnxt_re_dispatch_event(struct ib_device *ibdev, struct ib_qp *qp, 87 + u8 port_num, enum ib_event_type event); 93 88 static void bnxt_re_set_db_offset(struct bnxt_re_dev *rdev) 94 89 { 95 90 struct bnxt_qplib_chip_ctx *cctx; ··· 148 153 149 154 if (!rdev->chip_ctx) 150 155 return; 156 + 157 + kfree(rdev->dev_attr); 158 + rdev->dev_attr = NULL; 159 + 151 160 chip_ctx = rdev->chip_ctx; 152 161 rdev->chip_ctx = NULL; 153 162 rdev->rcfw.res = NULL; ··· 165 166 { 166 167 struct bnxt_qplib_chip_ctx *chip_ctx; 167 168 struct bnxt_en_dev *en_dev; 168 - int rc; 169 + int rc = -ENOMEM; 169 170 170 171 en_dev = rdev->en_dev; 171 172 ··· 181 182 182 183 rdev->qplib_res.cctx = rdev->chip_ctx; 183 184 rdev->rcfw.res = &rdev->qplib_res; 184 - rdev->qplib_res.dattr = &rdev->dev_attr; 185 + rdev->dev_attr = kzalloc(sizeof(*rdev->dev_attr), GFP_KERNEL); 186 + if (!rdev->dev_attr) 187 + goto free_chip_ctx; 188 + rdev->qplib_res.dattr = rdev->dev_attr; 185 189 rdev->qplib_res.is_vf = BNXT_EN_VF(en_dev); 186 190 rdev->qplib_res.en_dev = en_dev; 187 191 ··· 192 190 193 191 bnxt_re_set_db_offset(rdev); 194 192 rc = bnxt_qplib_map_db_bar(&rdev->qplib_res); 195 - if (rc) { 196 - kfree(rdev->chip_ctx); 197 - rdev->chip_ctx = NULL; 198 - return rc; 199 - } 193 + if (rc) 194 + goto free_dev_attr; 200 195 201 196 if (bnxt_qplib_determine_atomics(en_dev->pdev)) 202 197 ibdev_info(&rdev->ibdev, 203 198 "platform doesn't support global atomics."); 204 199 return 0; 200 + free_dev_attr: 201 + kfree(rdev->dev_attr); 202 + rdev->dev_attr = NULL; 203 + free_chip_ctx: 204 + kfree(rdev->chip_ctx); 205 + rdev->chip_ctx = NULL; 206 + return rc; 205 207 } 206 208 207 209 /* SR-IOV helper functions */ ··· 227 221 struct bnxt_qplib_ctx *ctx; 228 222 int i; 229 223 230 - attr = &rdev->dev_attr; 224 + attr = rdev->dev_attr; 231 225 ctx = &rdev->qplib_ctx; 232 226 233 227 ctx->qpc_count = min_t(u32, BNXT_RE_MAX_QPC_COUNT, ··· 241 235 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 242 236 for (i = 0; i < MAX_TQM_ALLOC_REQ; i++) 243 237 rdev->qplib_ctx.tqm_ctx.qcount[i] = 244 - rdev->dev_attr.tqm_alloc_reqs[i]; 238 + rdev->dev_attr->tqm_alloc_reqs[i]; 245 239 } 246 240 247 241 static void bnxt_re_limit_vf_res(struct bnxt_qplib_ctx *qplib_ctx, u32 num_vf) ··· 308 302 &rdev->qplib_ctx); 309 303 } 310 304 311 - static void bnxt_re_shutdown(struct auxiliary_device *adev) 312 - { 313 - struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev); 305 + struct bnxt_re_dcb_work { 306 + struct work_struct work; 314 307 struct bnxt_re_dev *rdev; 308 + struct hwrm_async_event_cmpl cmpl; 309 + }; 315 310 316 - rdev = en_info->rdev; 317 - ib_unregister_device(&rdev->ibdev); 318 - bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE); 311 + static bool bnxt_re_is_qp1_qp(struct bnxt_re_qp *qp) 312 + { 313 + return qp->ib_qp.qp_type == IB_QPT_GSI; 319 314 } 320 315 321 - static void bnxt_re_stop_irq(void *handle) 316 + static struct bnxt_re_qp *bnxt_re_get_qp1_qp(struct bnxt_re_dev *rdev) 317 + { 318 + struct bnxt_re_qp *qp; 319 + 320 + mutex_lock(&rdev->qp_lock); 321 + list_for_each_entry(qp, &rdev->qp_list, list) { 322 + if (bnxt_re_is_qp1_qp(qp)) { 323 + mutex_unlock(&rdev->qp_lock); 324 + return qp; 325 + } 326 + } 327 + mutex_unlock(&rdev->qp_lock); 328 + return NULL; 329 + } 330 + 331 + static int bnxt_re_update_qp1_tos_dscp(struct bnxt_re_dev *rdev) 332 + { 333 + struct bnxt_re_qp *qp; 334 + 335 + if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 336 + return 0; 337 + 338 + qp = bnxt_re_get_qp1_qp(rdev); 339 + if (!qp) 340 + return 0; 341 + 342 + qp->qplib_qp.modify_flags = CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP; 343 + qp->qplib_qp.tos_dscp = rdev->cc_param.qp1_tos_dscp; 344 + 345 + return bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 346 + } 347 + 348 + static void bnxt_re_init_dcb_wq(struct bnxt_re_dev *rdev) 349 + { 350 + rdev->dcb_wq = create_singlethread_workqueue("bnxt_re_dcb_wq"); 351 + } 352 + 353 + static void bnxt_re_uninit_dcb_wq(struct bnxt_re_dev *rdev) 354 + { 355 + if (!rdev->dcb_wq) 356 + return; 357 + destroy_workqueue(rdev->dcb_wq); 358 + } 359 + 360 + static void bnxt_re_dcb_wq_task(struct work_struct *work) 361 + { 362 + struct bnxt_re_dcb_work *dcb_work = 363 + container_of(work, struct bnxt_re_dcb_work, work); 364 + struct bnxt_re_dev *rdev = dcb_work->rdev; 365 + struct bnxt_qplib_cc_param *cc_param; 366 + int rc; 367 + 368 + if (!rdev) 369 + goto free_dcb; 370 + 371 + cc_param = &rdev->cc_param; 372 + rc = bnxt_qplib_query_cc_param(&rdev->qplib_res, cc_param); 373 + if (rc) { 374 + ibdev_dbg(&rdev->ibdev, "Failed to query ccparam rc:%d", rc); 375 + goto free_dcb; 376 + } 377 + if (cc_param->qp1_tos_dscp != cc_param->tos_dscp) { 378 + cc_param->qp1_tos_dscp = cc_param->tos_dscp; 379 + rc = bnxt_re_update_qp1_tos_dscp(rdev); 380 + if (rc) { 381 + ibdev_dbg(&rdev->ibdev, "%s: Failed to modify QP1 rc:%d", 382 + __func__, rc); 383 + goto free_dcb; 384 + } 385 + } 386 + 387 + free_dcb: 388 + kfree(dcb_work); 389 + } 390 + 391 + static void bnxt_re_async_notifier(void *handle, struct hwrm_async_event_cmpl *cmpl) 392 + { 393 + struct bnxt_re_dev *rdev = (struct bnxt_re_dev *)handle; 394 + struct bnxt_re_dcb_work *dcb_work; 395 + u32 data1, data2; 396 + u16 event_id; 397 + 398 + event_id = le16_to_cpu(cmpl->event_id); 399 + data1 = le32_to_cpu(cmpl->event_data1); 400 + data2 = le32_to_cpu(cmpl->event_data2); 401 + 402 + ibdev_dbg(&rdev->ibdev, "Async event_id = %d data1 = %d data2 = %d", 403 + event_id, data1, data2); 404 + 405 + switch (event_id) { 406 + case ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE: 407 + dcb_work = kzalloc(sizeof(*dcb_work), GFP_ATOMIC); 408 + if (!dcb_work) 409 + break; 410 + 411 + dcb_work->rdev = rdev; 412 + memcpy(&dcb_work->cmpl, cmpl, sizeof(*cmpl)); 413 + INIT_WORK(&dcb_work->work, bnxt_re_dcb_wq_task); 414 + queue_work(rdev->dcb_wq, &dcb_work->work); 415 + break; 416 + default: 417 + break; 418 + } 419 + } 420 + 421 + static void bnxt_re_stop_irq(void *handle, bool reset) 322 422 { 323 423 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(handle); 324 424 struct bnxt_qplib_rcfw *rcfw; ··· 434 322 435 323 rdev = en_info->rdev; 436 324 rcfw = &rdev->rcfw; 325 + 326 + if (reset) { 327 + set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags); 328 + set_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags); 329 + wake_up_all(&rdev->rcfw.cmdq.waitq); 330 + bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, 331 + IB_EVENT_DEVICE_FATAL); 332 + } 437 333 438 334 for (indx = BNXT_RE_NQ_IDX; indx < rdev->nqr->num_msix; indx++) { 439 335 nq = &rdev->nqr->nq[indx - 1]; ··· 498 378 } 499 379 500 380 static struct bnxt_ulp_ops bnxt_re_ulp_ops = { 381 + .ulp_async_notifier = bnxt_re_async_notifier, 501 382 .ulp_irq_stop = bnxt_re_stop_irq, 502 383 .ulp_irq_restart = bnxt_re_start_irq 503 384 }; ··· 960 839 } 961 840 962 841 /* Device */ 963 - 964 - static struct bnxt_re_dev *bnxt_re_from_netdev(struct net_device *netdev) 965 - { 966 - struct ib_device *ibdev = 967 - ib_device_get_by_netdev(netdev, RDMA_DRIVER_BNXT_RE); 968 - if (!ibdev) 969 - return NULL; 970 - 971 - return container_of(ibdev, struct bnxt_re_dev, ibdev); 972 - } 973 - 974 842 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr, 975 843 char *buf) 976 844 { ··· 1737 1627 1738 1628 /* Configure and allocate resources for qplib */ 1739 1629 rdev->qplib_res.rcfw = &rdev->rcfw; 1740 - rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr); 1630 + rc = bnxt_qplib_get_dev_attr(&rdev->rcfw); 1741 1631 if (rc) 1742 1632 goto fail; 1743 1633 1744 - rc = bnxt_qplib_alloc_res(&rdev->qplib_res, rdev->en_dev->pdev, 1745 - rdev->netdev, &rdev->dev_attr); 1634 + rc = bnxt_qplib_alloc_res(&rdev->qplib_res, rdev->netdev); 1746 1635 if (rc) 1747 1636 goto fail; 1748 1637 ··· 1916 1807 return 0; 1917 1808 } 1918 1809 1810 + static void bnxt_re_net_unregister_async_event(struct bnxt_re_dev *rdev) 1811 + { 1812 + if (rdev->is_virtfn) 1813 + return; 1814 + 1815 + memset(&rdev->event_bitmap, 0, sizeof(rdev->event_bitmap)); 1816 + bnxt_register_async_events(rdev->en_dev, &rdev->event_bitmap, 1817 + ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE); 1818 + } 1819 + 1820 + static void bnxt_re_net_register_async_event(struct bnxt_re_dev *rdev) 1821 + { 1822 + if (rdev->is_virtfn) 1823 + return; 1824 + 1825 + rdev->event_bitmap |= (1 << ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE); 1826 + bnxt_register_async_events(rdev->en_dev, &rdev->event_bitmap, 1827 + ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE); 1828 + } 1829 + 1919 1830 static void bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev *rdev) 1920 1831 { 1921 1832 struct bnxt_en_dev *en_dev = rdev->en_dev; ··· 2014 1885 int rc; 2015 1886 2016 1887 bnxt_re_debugfs_rem_pdev(rdev); 1888 + 1889 + bnxt_re_net_unregister_async_event(rdev); 1890 + bnxt_re_uninit_dcb_wq(rdev); 2017 1891 2018 1892 if (test_and_clear_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags)) 2019 1893 cancel_delayed_work_sync(&rdev->worker); ··· 2164 2032 rdev->pacing.dbr_pacing = false; 2165 2033 } 2166 2034 } 2167 - rc = bnxt_qplib_get_dev_attr(&rdev->rcfw, &rdev->dev_attr); 2035 + rc = bnxt_qplib_get_dev_attr(&rdev->rcfw); 2168 2036 if (rc) 2169 2037 goto disable_rcfw; 2170 2038 ··· 2213 2081 set_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, &rdev->flags); 2214 2082 2215 2083 if (!rdev->is_virtfn) { 2084 + /* Query f/w defaults of CC params */ 2085 + rc = bnxt_qplib_query_cc_param(&rdev->qplib_res, &rdev->cc_param); 2086 + if (rc) 2087 + ibdev_warn(&rdev->ibdev, "Failed to query CC defaults\n"); 2088 + 2216 2089 rc = bnxt_re_setup_qos(rdev); 2217 2090 if (rc) 2218 2091 ibdev_info(&rdev->ibdev, ··· 2236 2099 2237 2100 bnxt_re_debugfs_add_pdev(rdev); 2238 2101 2102 + bnxt_re_init_dcb_wq(rdev); 2103 + bnxt_re_net_register_async_event(rdev); 2104 + 2239 2105 return 0; 2240 2106 free_sctx: 2241 2107 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id); ··· 2255 2115 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE); 2256 2116 2257 2117 return rc; 2118 + } 2119 + 2120 + static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable) 2121 + { 2122 + struct bnxt_qplib_cc_param cc_param = {}; 2123 + 2124 + /* Do not enable congestion control on VFs */ 2125 + if (rdev->is_virtfn) 2126 + return; 2127 + 2128 + /* Currently enabling only for GenP5 adapters */ 2129 + if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 2130 + return; 2131 + 2132 + if (enable) { 2133 + cc_param.enable = 1; 2134 + cc_param.tos_ecn = 1; 2135 + } 2136 + 2137 + cc_param.mask = (CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC | 2138 + CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN); 2139 + 2140 + if (bnxt_qplib_modify_cc(&rdev->qplib_res, &cc_param)) 2141 + ibdev_err(&rdev->ibdev, "Failed to setup CC enable = %d\n", enable); 2258 2142 } 2259 2143 2260 2144 static void bnxt_re_update_en_info_rdev(struct bnxt_re_dev *rdev, ··· 2327 2163 goto re_dev_uninit; 2328 2164 } 2329 2165 2330 - rdev->nb.notifier_call = bnxt_re_netdev_event; 2331 - rc = register_netdevice_notifier(&rdev->nb); 2332 - if (rc) { 2333 - rdev->nb.notifier_call = NULL; 2334 - pr_err("%s: Cannot register to netdevice_notifier", 2335 - ROCE_DRV_MODULE_NAME); 2336 - goto re_dev_unreg; 2337 - } 2338 2166 bnxt_re_setup_cc(rdev, true); 2339 2167 2340 2168 return 0; 2341 2169 2342 - re_dev_unreg: 2343 - ib_unregister_device(&rdev->ibdev); 2344 2170 re_dev_uninit: 2345 2171 bnxt_re_update_en_info_rdev(NULL, en_info, adev); 2346 2172 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE); ··· 2338 2184 ib_dealloc_device(&rdev->ibdev); 2339 2185 exit: 2340 2186 return rc; 2341 - } 2342 - 2343 - static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable) 2344 - { 2345 - struct bnxt_qplib_cc_param cc_param = {}; 2346 - 2347 - /* Do not enable congestion control on VFs */ 2348 - if (rdev->is_virtfn) 2349 - return; 2350 - 2351 - /* Currently enabling only for GenP5 adapters */ 2352 - if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 2353 - return; 2354 - 2355 - if (enable) { 2356 - cc_param.enable = 1; 2357 - cc_param.tos_ecn = 1; 2358 - } 2359 - 2360 - cc_param.mask = (CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC | 2361 - CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN); 2362 - 2363 - if (bnxt_qplib_modify_cc(&rdev->qplib_res, &cc_param)) 2364 - ibdev_err(&rdev->ibdev, "Failed to setup CC enable = %d\n", enable); 2365 - } 2366 - 2367 - /* 2368 - * "Notifier chain callback can be invoked for the same chain from 2369 - * different CPUs at the same time". 2370 - * 2371 - * For cases when the netdev is already present, our call to the 2372 - * register_netdevice_notifier() will actually get the rtnl_lock() 2373 - * before sending NETDEV_REGISTER and (if up) NETDEV_UP 2374 - * events. 2375 - * 2376 - * But for cases when the netdev is not already present, the notifier 2377 - * chain is subjected to be invoked from different CPUs simultaneously. 2378 - * 2379 - * This is protected by the netdev_mutex. 2380 - */ 2381 - static int bnxt_re_netdev_event(struct notifier_block *notifier, 2382 - unsigned long event, void *ptr) 2383 - { 2384 - struct net_device *real_dev, *netdev = netdev_notifier_info_to_dev(ptr); 2385 - struct bnxt_re_dev *rdev; 2386 - 2387 - real_dev = rdma_vlan_dev_real_dev(netdev); 2388 - if (!real_dev) 2389 - real_dev = netdev; 2390 - 2391 - if (real_dev != netdev) 2392 - goto exit; 2393 - 2394 - rdev = bnxt_re_from_netdev(real_dev); 2395 - if (!rdev) 2396 - return NOTIFY_DONE; 2397 - 2398 - 2399 - switch (event) { 2400 - case NETDEV_UP: 2401 - case NETDEV_DOWN: 2402 - case NETDEV_CHANGE: 2403 - bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, 2404 - netif_carrier_ok(real_dev) ? 2405 - IB_EVENT_PORT_ACTIVE : 2406 - IB_EVENT_PORT_ERR); 2407 - break; 2408 - default: 2409 - break; 2410 - } 2411 - ib_device_put(&rdev->ibdev); 2412 - exit: 2413 - return NOTIFY_DONE; 2414 2187 } 2415 2188 2416 2189 #define BNXT_ADEV_NAME "bnxt_en" ··· 2397 2316 2398 2317 rc = bnxt_re_add_device(adev, BNXT_RE_COMPLETE_INIT); 2399 2318 if (rc) 2400 - goto err; 2401 - mutex_unlock(&bnxt_re_mutex); 2402 - return 0; 2319 + kfree(en_info); 2403 2320 2404 - err: 2405 2321 mutex_unlock(&bnxt_re_mutex); 2406 - kfree(en_info); 2407 2322 2408 2323 return rc; 2409 2324 } ··· 2450 2373 mutex_unlock(&bnxt_re_mutex); 2451 2374 2452 2375 return 0; 2376 + } 2377 + 2378 + static void bnxt_re_shutdown(struct auxiliary_device *adev) 2379 + { 2380 + struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev); 2381 + struct bnxt_re_dev *rdev; 2382 + 2383 + rdev = en_info->rdev; 2384 + ib_unregister_device(&rdev->ibdev); 2385 + bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE); 2453 2386 } 2454 2387 2455 2388 static const struct auxiliary_device_id bnxt_re_id_table[] = {
+1
drivers/infiniband/hw/bnxt_re/qplib_fp.h
··· 343 343 u32 msn; 344 344 u32 msn_tbl_sz; 345 345 bool is_host_msn_tbl; 346 + u8 tos_dscp; 346 347 }; 347 348 348 349 #define BNXT_QPLIB_MAX_CQE_ENTRY_SIZE sizeof(struct cq_base)
+3 -4
drivers/infiniband/hw/bnxt_re/qplib_res.c
··· 876 876 bnxt_qplib_free_dpi_tbl(res, &res->dpi_tbl); 877 877 } 878 878 879 - int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev, 880 - struct net_device *netdev, 881 - struct bnxt_qplib_dev_attr *dev_attr) 879 + int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct net_device *netdev) 882 880 { 881 + struct bnxt_qplib_dev_attr *dev_attr; 883 882 int rc; 884 883 885 - res->pdev = pdev; 886 884 res->netdev = netdev; 885 + dev_attr = res->dattr; 887 886 888 887 rc = bnxt_qplib_alloc_sgid_tbl(res, &res->sgid_tbl, dev_attr->max_sgid); 889 888 if (rc)
+1 -3
drivers/infiniband/hw/bnxt_re/qplib_res.h
··· 424 424 void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res); 425 425 int bnxt_qplib_init_res(struct bnxt_qplib_res *res); 426 426 void bnxt_qplib_free_res(struct bnxt_qplib_res *res); 427 - int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev, 428 - struct net_device *netdev, 429 - struct bnxt_qplib_dev_attr *dev_attr); 427 + int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct net_device *netdev); 430 428 void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res, 431 429 struct bnxt_qplib_ctx *ctx); 432 430 int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res,
+115 -2
drivers/infiniband/hw/bnxt_re/qplib_sp.c
··· 88 88 fw_ver[3] = resp.fw_rsvd; 89 89 } 90 90 91 - int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw, 92 - struct bnxt_qplib_dev_attr *attr) 91 + int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw) 93 92 { 93 + struct bnxt_qplib_dev_attr *attr = rcfw->res->dattr; 94 94 struct creq_query_func_resp resp = {}; 95 95 struct bnxt_qplib_cmdqmsg msg = {}; 96 96 struct creq_query_func_resp_sb *sb; ··· 1019 1019 1020 1020 memcpy(resp_va, sbuf.sb, resp_size); 1021 1021 free_mem: 1022 + dma_free_coherent(&rcfw->pdev->dev, sbuf.size, sbuf.sb, sbuf.dma_addr); 1023 + return rc; 1024 + } 1025 + 1026 + static void bnxt_qplib_read_cc_gen1(struct bnxt_qplib_cc_param_ext *cc_ext, 1027 + struct creq_query_roce_cc_gen1_resp_sb_tlv *sb) 1028 + { 1029 + cc_ext->inact_th_hi = le16_to_cpu(sb->inactivity_th_hi); 1030 + cc_ext->min_delta_cnp = le16_to_cpu(sb->min_time_between_cnps); 1031 + cc_ext->init_cp = le16_to_cpu(sb->init_cp); 1032 + cc_ext->tr_update_mode = sb->tr_update_mode; 1033 + cc_ext->tr_update_cyls = sb->tr_update_cycles; 1034 + cc_ext->fr_rtt = sb->fr_num_rtts; 1035 + cc_ext->ai_rate_incr = sb->ai_rate_increase; 1036 + cc_ext->rr_rtt_th = le16_to_cpu(sb->reduction_relax_rtts_th); 1037 + cc_ext->ar_cr_th = le16_to_cpu(sb->additional_relax_cr_th); 1038 + cc_ext->cr_min_th = le16_to_cpu(sb->cr_min_th); 1039 + cc_ext->bw_avg_weight = sb->bw_avg_weight; 1040 + cc_ext->cr_factor = sb->actual_cr_factor; 1041 + cc_ext->cr_th_max_cp = le16_to_cpu(sb->max_cp_cr_th); 1042 + cc_ext->cp_bias_en = sb->cp_bias_en; 1043 + cc_ext->cp_bias = sb->cp_bias; 1044 + cc_ext->cnp_ecn = sb->cnp_ecn; 1045 + cc_ext->rtt_jitter_en = sb->rtt_jitter_en; 1046 + cc_ext->bytes_per_usec = le16_to_cpu(sb->link_bytes_per_usec); 1047 + cc_ext->cc_cr_reset_th = le16_to_cpu(sb->reset_cc_cr_th); 1048 + cc_ext->cr_width = sb->cr_width; 1049 + cc_ext->min_quota = sb->quota_period_min; 1050 + cc_ext->max_quota = sb->quota_period_max; 1051 + cc_ext->abs_max_quota = sb->quota_period_abs_max; 1052 + cc_ext->tr_lb = le16_to_cpu(sb->tr_lower_bound); 1053 + cc_ext->cr_prob_fac = sb->cr_prob_factor; 1054 + cc_ext->tr_prob_fac = sb->tr_prob_factor; 1055 + cc_ext->fair_cr_th = le16_to_cpu(sb->fairness_cr_th); 1056 + cc_ext->red_div = sb->red_div; 1057 + cc_ext->cnp_ratio_th = sb->cnp_ratio_th; 1058 + cc_ext->ai_ext_rtt = le16_to_cpu(sb->exp_ai_rtts); 1059 + cc_ext->exp_crcp_ratio = sb->exp_ai_cr_cp_ratio; 1060 + cc_ext->low_rate_en = sb->use_rate_table; 1061 + cc_ext->cpcr_update_th = le16_to_cpu(sb->cp_exp_update_th); 1062 + cc_ext->ai_rtt_th1 = le16_to_cpu(sb->high_exp_ai_rtts_th1); 1063 + cc_ext->ai_rtt_th2 = le16_to_cpu(sb->high_exp_ai_rtts_th2); 1064 + cc_ext->cf_rtt_th = le16_to_cpu(sb->actual_cr_cong_free_rtts_th); 1065 + cc_ext->sc_cr_th1 = le16_to_cpu(sb->severe_cong_cr_th1); 1066 + cc_ext->sc_cr_th2 = le16_to_cpu(sb->severe_cong_cr_th2); 1067 + cc_ext->l64B_per_rtt = le32_to_cpu(sb->link64B_per_rtt); 1068 + cc_ext->cc_ack_bytes = sb->cc_ack_bytes; 1069 + cc_ext->reduce_cf_rtt_th = le16_to_cpu(sb->reduce_init_cong_free_rtts_th); 1070 + } 1071 + 1072 + int bnxt_qplib_query_cc_param(struct bnxt_qplib_res *res, 1073 + struct bnxt_qplib_cc_param *cc_param) 1074 + { 1075 + struct bnxt_qplib_tlv_query_rcc_sb *ext_sb; 1076 + struct bnxt_qplib_rcfw *rcfw = res->rcfw; 1077 + struct creq_query_roce_cc_resp resp = {}; 1078 + struct creq_query_roce_cc_resp_sb *sb; 1079 + struct bnxt_qplib_cmdqmsg msg = {}; 1080 + struct cmdq_query_roce_cc req = {}; 1081 + struct bnxt_qplib_rcfw_sbuf sbuf; 1082 + size_t resp_size; 1083 + int rc; 1084 + 1085 + /* Query the parameters from chip */ 1086 + bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, CMDQ_BASE_OPCODE_QUERY_ROCE_CC, 1087 + sizeof(req)); 1088 + if (bnxt_qplib_is_chip_gen_p5_p7(res->cctx)) 1089 + resp_size = sizeof(*ext_sb); 1090 + else 1091 + resp_size = sizeof(*sb); 1092 + 1093 + sbuf.size = ALIGN(resp_size, BNXT_QPLIB_CMDQE_UNITS); 1094 + sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size, 1095 + &sbuf.dma_addr, GFP_KERNEL); 1096 + if (!sbuf.sb) 1097 + return -ENOMEM; 1098 + 1099 + req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 1100 + bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 1101 + sizeof(resp), 0); 1102 + rc = bnxt_qplib_rcfw_send_message(res->rcfw, &msg); 1103 + if (rc) 1104 + goto out; 1105 + 1106 + ext_sb = sbuf.sb; 1107 + sb = bnxt_qplib_is_chip_gen_p5_p7(res->cctx) ? &ext_sb->base_sb : 1108 + (struct creq_query_roce_cc_resp_sb *)ext_sb; 1109 + 1110 + cc_param->enable = sb->enable_cc & CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC; 1111 + cc_param->tos_ecn = (sb->tos_dscp_tos_ecn & 1112 + CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK) >> 1113 + CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT; 1114 + cc_param->tos_dscp = (sb->tos_dscp_tos_ecn & 1115 + CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK) >> 1116 + CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_SFT; 1117 + cc_param->alt_tos_dscp = sb->alt_tos_dscp; 1118 + cc_param->alt_vlan_pcp = sb->alt_vlan_pcp; 1119 + 1120 + cc_param->g = sb->g; 1121 + cc_param->nph_per_state = sb->num_phases_per_state; 1122 + cc_param->init_cr = le16_to_cpu(sb->init_cr); 1123 + cc_param->init_tr = le16_to_cpu(sb->init_tr); 1124 + cc_param->cc_mode = sb->cc_mode; 1125 + cc_param->inact_th = le16_to_cpu(sb->inactivity_th); 1126 + cc_param->rtt = le16_to_cpu(sb->rtt); 1127 + cc_param->tcp_cp = le16_to_cpu(sb->tcp_cp); 1128 + cc_param->time_pph = sb->time_per_phase; 1129 + cc_param->pkts_pph = sb->pkts_per_phase; 1130 + if (bnxt_qplib_is_chip_gen_p5_p7(res->cctx)) { 1131 + bnxt_qplib_read_cc_gen1(&cc_param->cc_ext, &ext_sb->gen1_sb); 1132 + cc_param->inact_th |= (cc_param->cc_ext.inact_th_hi & 0x3F) << 16; 1133 + } 1134 + out: 1022 1135 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, sbuf.sb, sbuf.dma_addr); 1023 1136 return rc; 1024 1137 }
+4 -2
drivers/infiniband/hw/bnxt_re/qplib_sp.h
··· 296 296 297 297 struct bnxt_qplib_cc_param { 298 298 u8 alt_vlan_pcp; 299 + u8 qp1_tos_dscp; 299 300 u16 alt_tos_dscp; 300 301 u8 cc_mode; 301 302 u8 enable; ··· 326 325 int bnxt_qplib_update_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 327 326 struct bnxt_qplib_gid *gid, u16 gid_idx, 328 327 const u8 *smac); 329 - int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw, 330 - struct bnxt_qplib_dev_attr *attr); 328 + int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw); 331 329 int bnxt_qplib_set_func_resources(struct bnxt_qplib_res *res, 332 330 struct bnxt_qplib_rcfw *rcfw, 333 331 struct bnxt_qplib_ctx *ctx); ··· 355 355 struct bnxt_qplib_cc_param *cc_param); 356 356 int bnxt_qplib_read_context(struct bnxt_qplib_rcfw *rcfw, u8 type, u32 xid, 357 357 u32 resp_size, void *resp_va); 358 + int bnxt_qplib_query_cc_param(struct bnxt_qplib_res *res, 359 + struct bnxt_qplib_cc_param *cc_param); 358 360 359 361 #define BNXT_VAR_MAX_WQE 4352 360 362 #define BNXT_VAR_MAX_SLOT_ALIGN 256
+4 -2
drivers/infiniband/hw/cxgb4/device.c
··· 1114 1114 * The math here assumes sizeof cpl_pass_accept_req >= sizeof 1115 1115 * cpl_rx_pkt. 1116 1116 */ 1117 - skb = alloc_skb(gl->tot_len + sizeof(struct cpl_pass_accept_req) + 1118 - sizeof(struct rss_header) - pktshift, GFP_ATOMIC); 1117 + skb = alloc_skb(size_add(gl->tot_len, 1118 + sizeof(struct cpl_pass_accept_req) + 1119 + sizeof(struct rss_header)) - pktshift, 1120 + GFP_ATOMIC); 1119 1121 if (unlikely(!skb)) 1120 1122 return NULL; 1121 1123
+8
drivers/infiniband/hw/cxgb4/qp.c
··· 1599 1599 int count; 1600 1600 int rq_flushed = 0, sq_flushed; 1601 1601 unsigned long flag; 1602 + struct ib_event ev; 1602 1603 1603 1604 pr_debug("qhp %p rchp %p schp %p\n", qhp, rchp, schp); 1604 1605 ··· 1608 1607 if (schp != rchp) 1609 1608 spin_lock(&schp->lock); 1610 1609 spin_lock(&qhp->lock); 1610 + if (qhp->srq && qhp->attr.state == C4IW_QP_STATE_ERROR && 1611 + qhp->ibqp.event_handler) { 1612 + ev.device = qhp->ibqp.device; 1613 + ev.element.qp = &qhp->ibqp; 1614 + ev.event = IB_EVENT_QP_LAST_WQE_REACHED; 1615 + qhp->ibqp.event_handler(&ev, qhp->ibqp.qp_context); 1616 + } 1611 1617 1612 1618 if (qhp->wq.flushed) { 1613 1619 spin_unlock(&qhp->lock);
+4 -4
drivers/infiniband/hw/efa/efa.h
··· 1 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2 2 /* 3 - * Copyright 2018-2024 Amazon.com, Inc. or its affiliates. All rights reserved. 3 + * Copyright 2018-2025 Amazon.com, Inc. or its affiliates. All rights reserved. 4 4 */ 5 5 6 6 #ifndef _EFA_H_ ··· 57 57 u64 db_bar_addr; 58 58 u64 db_bar_len; 59 59 60 - unsigned int num_irq_vectors; 61 - int admin_msix_vector_idx; 60 + u32 num_irq_vectors; 61 + u32 admin_msix_vector_idx; 62 62 struct efa_irq admin_irq; 63 63 64 64 struct efa_stats stats; 65 65 66 66 /* Array of completion EQs */ 67 67 struct efa_eq *eqs; 68 - unsigned int neqs; 68 + u32 neqs; 69 69 70 70 /* Only stores CQs with interrupts enabled */ 71 71 struct xarray cqs_xa;
+3 -3
drivers/infiniband/hw/efa/efa_com.h
··· 1 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2 2 /* 3 - * Copyright 2018-2021 Amazon.com, Inc. or its affiliates. All rights reserved. 3 + * Copyright 2018-2025 Amazon.com, Inc. or its affiliates. All rights reserved. 4 4 */ 5 5 6 6 #ifndef _EFA_COM_H_ ··· 65 65 u16 depth; 66 66 struct efa_com_admin_cq cq; 67 67 struct efa_com_admin_sq sq; 68 - u16 msix_vector_idx; 68 + u32 msix_vector_idx; 69 69 70 70 unsigned long state; 71 71 ··· 89 89 struct efa_aenq_handlers *aenq_handlers; 90 90 dma_addr_t dma_addr; 91 91 u32 cc; /* consumer counter */ 92 - u16 msix_vector_idx; 92 + u32 msix_vector_idx; 93 93 u16 depth; 94 94 u8 phase; 95 95 };
+12 -16
drivers/infiniband/hw/efa/efa_main.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2 2 /* 3 - * Copyright 2018-2024 Amazon.com, Inc. or its affiliates. All rights reserved. 3 + * Copyright 2018-2025 Amazon.com, Inc. or its affiliates. All rights reserved. 4 4 */ 5 5 6 6 #include <linux/module.h> ··· 141 141 return 0; 142 142 } 143 143 144 - static void efa_setup_comp_irq(struct efa_dev *dev, struct efa_eq *eq, 145 - int vector) 144 + static void efa_setup_comp_irq(struct efa_dev *dev, struct efa_eq *eq, u32 vector) 146 145 { 147 146 u32 cpu; 148 147 ··· 304 305 efa_free_irq(dev, &eq->irq); 305 306 } 306 307 307 - static int efa_create_eq(struct efa_dev *dev, struct efa_eq *eq, u8 msix_vec) 308 + static int efa_create_eq(struct efa_dev *dev, struct efa_eq *eq, u32 msix_vec) 308 309 { 309 310 int err; 310 311 ··· 327 328 328 329 static int efa_create_eqs(struct efa_dev *dev) 329 330 { 330 - unsigned int neqs = dev->dev_attr.max_eq; 331 - int err; 332 - int i; 331 + u32 neqs = dev->dev_attr.max_eq; 332 + int err, i; 333 333 334 - neqs = min_t(unsigned int, neqs, 335 - dev->num_irq_vectors - EFA_COMP_EQS_VEC_BASE); 336 - 334 + neqs = min_t(u32, neqs, dev->num_irq_vectors - EFA_COMP_EQS_VEC_BASE); 337 335 dev->neqs = neqs; 338 336 dev->eqs = kcalloc(neqs, sizeof(*dev->eqs), GFP_KERNEL); 339 337 if (!dev->eqs) 340 338 return -ENOMEM; 341 339 342 340 for (i = 0; i < neqs; i++) { 343 - err = efa_create_eq(dev, &dev->eqs[i], 344 - i + EFA_COMP_EQS_VEC_BASE); 341 + err = efa_create_eq(dev, &dev->eqs[i], i + EFA_COMP_EQS_VEC_BASE); 345 342 if (err) 346 343 goto err_destroy_eqs; 347 344 } ··· 465 470 ibdev_info(&dev->ibdev, "Unregister ib device\n"); 466 471 ib_unregister_device(&dev->ibdev); 467 472 efa_destroy_eqs(dev); 468 - efa_com_dev_reset(&dev->edev, EFA_REGS_RESET_NORMAL); 469 473 efa_release_doorbell_bar(dev); 470 474 } 471 475 ··· 637 643 return ERR_PTR(err); 638 644 } 639 645 640 - static void efa_remove_device(struct pci_dev *pdev) 646 + static void efa_remove_device(struct pci_dev *pdev, 647 + enum efa_regs_reset_reason_types reset_reason) 641 648 { 642 649 struct efa_dev *dev = pci_get_drvdata(pdev); 643 650 struct efa_com_dev *edev; 644 651 645 652 edev = &dev->edev; 653 + efa_com_dev_reset(edev, reset_reason); 646 654 efa_com_admin_destroy(edev); 647 655 efa_free_irq(dev, &dev->admin_irq); 648 656 efa_disable_msix(dev); ··· 672 676 return 0; 673 677 674 678 err_remove_device: 675 - efa_remove_device(pdev); 679 + efa_remove_device(pdev, EFA_REGS_RESET_INIT_ERR); 676 680 return err; 677 681 } 678 682 ··· 681 685 struct efa_dev *dev = pci_get_drvdata(pdev); 682 686 683 687 efa_ib_device_remove(dev); 684 - efa_remove_device(pdev); 688 + efa_remove_device(pdev, EFA_REGS_RESET_NORMAL); 685 689 } 686 690 687 691 static void efa_shutdown(struct pci_dev *pdev)
+1 -1
drivers/infiniband/hw/erdma/Kconfig
··· 5 5 depends on INFINIBAND_ADDR_TRANS 6 6 depends on INFINIBAND_USER_ACCESS 7 7 help 8 - This is a RDMA/iWarp driver for Alibaba Elastic RDMA Adapter(ERDMA), 8 + This is a RDMA driver for Alibaba Elastic RDMA Adapter(ERDMA), 9 9 which supports RDMA features in Alibaba cloud environment. 10 10 11 11 To compile this driver as module, choose M here. The module will be
+7 -7
drivers/infiniband/hw/erdma/erdma.h
··· 16 16 #include "erdma_hw.h" 17 17 18 18 #define DRV_MODULE_NAME "erdma" 19 - #define ERDMA_NODE_DESC "Elastic RDMA(iWARP) stack" 19 + #define ERDMA_NODE_DESC "Elastic RDMA Adapter stack" 20 20 21 21 struct erdma_eq { 22 22 void *qbuf; ··· 101 101 struct erdma_comp_wait *wait_pool; 102 102 spinlock_t lock; 103 103 104 - bool use_event; 105 - 106 104 struct erdma_cmdq_sq sq; 107 105 struct erdma_cmdq_cq cq; 108 106 struct erdma_eq eq; ··· 146 148 u32 max_mr; 147 149 u32 max_pd; 148 150 u32 max_mw; 151 + u32 max_gid; 152 + u32 max_ah; 149 153 u32 local_dma_key; 150 154 }; 151 155 ··· 177 177 enum { 178 178 ERDMA_RES_TYPE_PD = 0, 179 179 ERDMA_RES_TYPE_STAG_IDX = 1, 180 - ERDMA_RES_CNT = 2, 180 + ERDMA_RES_TYPE_AH = 2, 181 + ERDMA_RES_CNT = 3, 181 182 }; 182 183 183 184 struct erdma_dev { ··· 193 192 u8 __iomem *func_bar; 194 193 195 194 struct erdma_devattr attrs; 196 - /* physical port state (only one port per device) */ 197 - enum ib_port_state state; 198 195 u32 mtu; 199 196 200 197 /* cmdq and aeq use the same msix vector */ ··· 214 215 215 216 struct dma_pool *db_pool; 216 217 struct dma_pool *resp_pool; 218 + enum erdma_proto_type proto; 217 219 }; 218 220 219 221 static inline void *get_queue_entry(void *qbuf, u32 idx, u32 depth, u32 shift) ··· 265 265 266 266 void erdma_cmdq_build_reqhdr(u64 *hdr, u32 mod, u32 op); 267 267 int erdma_post_cmd_wait(struct erdma_cmdq *cmdq, void *req, u32 req_size, 268 - u64 *resp0, u64 *resp1); 268 + u64 *resp0, u64 *resp1, bool sleepable); 269 269 void erdma_cmdq_completion_handler(struct erdma_cmdq *cmdq); 270 270 271 271 int erdma_ceqs_init(struct erdma_dev *dev);
+39 -32
drivers/infiniband/hw/erdma/erdma_cm.c
··· 567 567 568 568 static int erdma_proc_mpareply(struct erdma_cep *cep) 569 569 { 570 - struct erdma_qp_attrs qp_attrs; 570 + enum erdma_qpa_mask_iwarp to_modify_attrs = 0; 571 + struct erdma_mod_qp_params_iwarp params; 571 572 struct erdma_qp *qp = cep->qp; 572 573 struct mpa_rr *rep; 573 574 int ret; ··· 598 597 return -EINVAL; 599 598 } 600 599 601 - memset(&qp_attrs, 0, sizeof(qp_attrs)); 602 - qp_attrs.irq_size = cep->ird; 603 - qp_attrs.orq_size = cep->ord; 604 - qp_attrs.state = ERDMA_QP_STATE_RTS; 600 + memset(&params, 0, sizeof(params)); 601 + params.state = ERDMA_QPS_IWARP_RTS; 602 + params.irq_size = cep->ird; 603 + params.orq_size = cep->ord; 605 604 606 605 down_write(&qp->state_lock); 607 - if (qp->attrs.state > ERDMA_QP_STATE_RTR) { 606 + if (qp->attrs.iwarp.state > ERDMA_QPS_IWARP_RTR) { 608 607 ret = -EINVAL; 609 608 up_write(&qp->state_lock); 610 609 goto out_err; 611 610 } 612 611 613 - qp->attrs.qp_type = ERDMA_QP_ACTIVE; 614 - if (__mpa_ext_cc(cep->mpa.ext_data.bits) != qp->attrs.cc) 615 - qp->attrs.cc = COMPROMISE_CC; 612 + to_modify_attrs = ERDMA_QPA_IWARP_STATE | ERDMA_QPA_IWARP_LLP_HANDLE | 613 + ERDMA_QPA_IWARP_MPA | ERDMA_QPA_IWARP_IRD | 614 + ERDMA_QPA_IWARP_ORD; 616 615 617 - ret = erdma_modify_qp_internal(qp, &qp_attrs, 618 - ERDMA_QP_ATTR_STATE | 619 - ERDMA_QP_ATTR_LLP_HANDLE | 620 - ERDMA_QP_ATTR_MPA); 616 + params.qp_type = ERDMA_QP_ACTIVE; 617 + if (__mpa_ext_cc(cep->mpa.ext_data.bits) != qp->attrs.cc) { 618 + to_modify_attrs |= ERDMA_QPA_IWARP_CC; 619 + params.cc = COMPROMISE_CC; 620 + } 621 + 622 + ret = erdma_modify_qp_state_iwarp(qp, &params, to_modify_attrs); 621 623 622 624 up_write(&qp->state_lock); 623 625 ··· 726 722 __mpa_rr_set_revision(&cep->mpa.hdr.params.bits, MPA_REVISION_EXT_1); 727 723 728 724 memcpy(cep->mpa.hdr.key, MPA_KEY_REQ, MPA_KEY_SIZE); 729 - cep->mpa.ext_data.cookie = cpu_to_be32(cep->qp->attrs.cookie); 725 + cep->mpa.ext_data.cookie = cpu_to_be32(cep->qp->attrs.iwarp.cookie); 730 726 __mpa_ext_set_cc(&cep->mpa.ext_data.bits, cep->qp->attrs.cc); 731 727 732 728 ret = erdma_send_mpareqrep(cep, cep->private_data, cep->pd_len); ··· 1130 1126 1131 1127 int erdma_accept(struct iw_cm_id *id, struct iw_cm_conn_param *params) 1132 1128 { 1133 - struct erdma_dev *dev = to_edev(id->device); 1134 1129 struct erdma_cep *cep = (struct erdma_cep *)id->provider_data; 1130 + struct erdma_mod_qp_params_iwarp mod_qp_params; 1131 + enum erdma_qpa_mask_iwarp to_modify_attrs = 0; 1132 + struct erdma_dev *dev = to_edev(id->device); 1135 1133 struct erdma_qp *qp; 1136 - struct erdma_qp_attrs qp_attrs; 1137 1134 int ret; 1138 1135 1139 1136 erdma_cep_set_inuse(cep); ··· 1161 1156 erdma_qp_get(qp); 1162 1157 1163 1158 down_write(&qp->state_lock); 1164 - if (qp->attrs.state > ERDMA_QP_STATE_RTR) { 1159 + if (qp->attrs.iwarp.state > ERDMA_QPS_IWARP_RTR) { 1165 1160 ret = -EINVAL; 1166 1161 up_write(&qp->state_lock); 1167 1162 goto error; ··· 1186 1181 cep->cm_id = id; 1187 1182 id->add_ref(id); 1188 1183 1189 - memset(&qp_attrs, 0, sizeof(qp_attrs)); 1190 - qp_attrs.orq_size = params->ord; 1191 - qp_attrs.irq_size = params->ird; 1184 + memset(&mod_qp_params, 0, sizeof(mod_qp_params)); 1192 1185 1193 - qp_attrs.state = ERDMA_QP_STATE_RTS; 1186 + mod_qp_params.irq_size = params->ird; 1187 + mod_qp_params.orq_size = params->ord; 1188 + mod_qp_params.state = ERDMA_QPS_IWARP_RTS; 1194 1189 1195 1190 /* Associate QP with CEP */ 1196 1191 erdma_cep_get(cep); ··· 1199 1194 1200 1195 cep->state = ERDMA_EPSTATE_RDMA_MODE; 1201 1196 1202 - qp->attrs.qp_type = ERDMA_QP_PASSIVE; 1203 - qp->attrs.pd_len = params->private_data_len; 1197 + mod_qp_params.qp_type = ERDMA_QP_PASSIVE; 1198 + mod_qp_params.pd_len = params->private_data_len; 1204 1199 1205 - if (qp->attrs.cc != __mpa_ext_cc(cep->mpa.ext_data.bits)) 1206 - qp->attrs.cc = COMPROMISE_CC; 1200 + to_modify_attrs = ERDMA_QPA_IWARP_STATE | ERDMA_QPA_IWARP_ORD | 1201 + ERDMA_QPA_IWARP_LLP_HANDLE | ERDMA_QPA_IWARP_IRD | 1202 + ERDMA_QPA_IWARP_MPA; 1203 + 1204 + if (qp->attrs.cc != __mpa_ext_cc(cep->mpa.ext_data.bits)) { 1205 + to_modify_attrs |= ERDMA_QPA_IWARP_CC; 1206 + mod_qp_params.cc = COMPROMISE_CC; 1207 + } 1207 1208 1208 1209 /* move to rts */ 1209 - ret = erdma_modify_qp_internal(qp, &qp_attrs, 1210 - ERDMA_QP_ATTR_STATE | 1211 - ERDMA_QP_ATTR_ORD | 1212 - ERDMA_QP_ATTR_LLP_HANDLE | 1213 - ERDMA_QP_ATTR_IRD | 1214 - ERDMA_QP_ATTR_MPA); 1210 + ret = erdma_modify_qp_state_iwarp(qp, &mod_qp_params, to_modify_attrs); 1211 + 1215 1212 up_write(&qp->state_lock); 1216 1213 1217 1214 if (ret) ··· 1221 1214 1222 1215 cep->mpa.ext_data.bits = 0; 1223 1216 __mpa_ext_set_cc(&cep->mpa.ext_data.bits, qp->attrs.cc); 1224 - cep->mpa.ext_data.cookie = cpu_to_be32(cep->qp->attrs.cookie); 1217 + cep->mpa.ext_data.cookie = cpu_to_be32(cep->qp->attrs.iwarp.cookie); 1225 1218 1226 1219 ret = erdma_send_mpareqrep(cep, params->private_data, 1227 1220 params->private_data_len);
+12 -14
drivers/infiniband/hw/erdma/erdma_cmdq.c
··· 182 182 int err; 183 183 184 184 cmdq->max_outstandings = ERDMA_CMDQ_MAX_OUTSTANDING; 185 - cmdq->use_event = false; 186 185 187 186 sema_init(&cmdq->credits, cmdq->max_outstandings); 188 187 ··· 222 223 223 224 void erdma_finish_cmdq_init(struct erdma_dev *dev) 224 225 { 225 - /* after device init successfully, change cmdq to event mode. */ 226 - dev->cmdq.use_event = true; 227 226 arm_cmdq_cq(&dev->cmdq); 228 227 } 229 228 ··· 309 312 /* Copy 16B comp data after cqe hdr to outer */ 310 313 be32_to_cpu_array(comp_wait->comp_data, cqe + 2, 4); 311 314 312 - if (cmdq->use_event) 313 - complete(&comp_wait->wait_event); 315 + complete(&comp_wait->wait_event); 314 316 315 317 return 0; 316 318 } ··· 328 332 if (erdma_poll_single_cmd_completion(cmdq)) 329 333 break; 330 334 331 - if (comp_num && cmdq->use_event) 332 - arm_cmdq_cq(cmdq); 333 - 334 335 spin_unlock_irqrestore(&cmdq->cq.lock, flags); 335 336 } 336 337 ··· 335 342 { 336 343 int got_event = 0; 337 344 338 - if (!test_bit(ERDMA_CMDQ_STATE_OK_BIT, &cmdq->state) || 339 - !cmdq->use_event) 345 + if (!test_bit(ERDMA_CMDQ_STATE_OK_BIT, &cmdq->state)) 340 346 return; 341 347 342 348 while (get_next_valid_eqe(&cmdq->eq)) { ··· 346 354 if (got_event) { 347 355 cmdq->cq.cmdsn++; 348 356 erdma_polling_cmd_completions(cmdq); 357 + arm_cmdq_cq(cmdq); 349 358 } 350 359 351 360 notify_eq(&cmdq->eq); ··· 365 372 if (time_is_before_jiffies(comp_timeout)) 366 373 return -ETIME; 367 374 368 - msleep(20); 375 + udelay(20); 369 376 } 370 377 371 378 return 0; ··· 396 403 } 397 404 398 405 int erdma_post_cmd_wait(struct erdma_cmdq *cmdq, void *req, u32 req_size, 399 - u64 *resp0, u64 *resp1) 406 + u64 *resp0, u64 *resp1, bool sleepable) 400 407 { 401 408 struct erdma_comp_wait *comp_wait; 402 409 int ret; ··· 404 411 if (!test_bit(ERDMA_CMDQ_STATE_OK_BIT, &cmdq->state)) 405 412 return -ENODEV; 406 413 407 - down(&cmdq->credits); 414 + if (!sleepable) { 415 + while (down_trylock(&cmdq->credits)) 416 + ; 417 + } else { 418 + down(&cmdq->credits); 419 + } 408 420 409 421 comp_wait = get_comp_wait(cmdq); 410 422 if (IS_ERR(comp_wait)) { ··· 423 425 push_cmdq_sqe(cmdq, req, req_size, comp_wait); 424 426 spin_unlock(&cmdq->sq.lock); 425 427 426 - if (cmdq->use_event) 428 + if (sleepable) 427 429 ret = erdma_wait_cmd_completion(comp_wait, cmdq, 428 430 ERDMA_CMDQ_TIMEOUT_MS); 429 431 else
+65
drivers/infiniband/hw/erdma/erdma_cq.c
··· 105 105 { ERDMA_WC_RETRY_EXC_ERR, IB_WC_RETRY_EXC_ERR, ERDMA_WC_VENDOR_NO_ERR }, 106 106 }; 107 107 108 + static void erdma_process_ud_cqe(struct erdma_cqe *cqe, struct ib_wc *wc) 109 + { 110 + u32 ud_info; 111 + 112 + wc->wc_flags |= (IB_WC_GRH | IB_WC_WITH_NETWORK_HDR_TYPE); 113 + ud_info = be32_to_cpu(cqe->ud.info); 114 + wc->network_hdr_type = FIELD_GET(ERDMA_CQE_NTYPE_MASK, ud_info); 115 + if (wc->network_hdr_type == ERDMA_NETWORK_TYPE_IPV4) 116 + wc->network_hdr_type = RDMA_NETWORK_IPV4; 117 + else 118 + wc->network_hdr_type = RDMA_NETWORK_IPV6; 119 + wc->src_qp = FIELD_GET(ERDMA_CQE_SQPN_MASK, ud_info); 120 + wc->sl = FIELD_GET(ERDMA_CQE_SL_MASK, ud_info); 121 + wc->pkey_index = 0; 122 + } 123 + 108 124 #define ERDMA_POLLCQ_NO_QP 1 109 125 110 126 static int erdma_poll_one_cqe(struct erdma_cq *cq, struct ib_wc *wc) ··· 184 168 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 185 169 } 186 170 171 + if (erdma_device_rocev2(dev) && 172 + (qp->ibqp.qp_type == IB_QPT_UD || qp->ibqp.qp_type == IB_QPT_GSI)) 173 + erdma_process_ud_cqe(cqe, wc); 174 + 187 175 if (syndrome >= ERDMA_NUM_WC_STATUS) 188 176 syndrome = ERDMA_WC_GENERAL_ERR; 189 177 ··· 220 200 spin_unlock_irqrestore(&cq->kern_cq.lock, flags); 221 201 222 202 return npolled; 203 + } 204 + 205 + void erdma_remove_cqes_of_qp(struct ib_cq *ibcq, u32 qpn) 206 + { 207 + struct erdma_cq *cq = to_ecq(ibcq); 208 + struct erdma_cqe *cqe, *dst_cqe; 209 + u32 prev_cq_ci, cur_cq_ci; 210 + u32 ncqe = 0, nqp_cqe = 0; 211 + unsigned long flags; 212 + u8 owner; 213 + 214 + spin_lock_irqsave(&cq->kern_cq.lock, flags); 215 + 216 + prev_cq_ci = cq->kern_cq.ci; 217 + 218 + while (ncqe < cq->depth && (cqe = get_next_valid_cqe(cq)) != NULL) { 219 + ++cq->kern_cq.ci; 220 + ++ncqe; 221 + } 222 + 223 + while (ncqe > 0) { 224 + cur_cq_ci = prev_cq_ci + ncqe - 1; 225 + cqe = get_queue_entry(cq->kern_cq.qbuf, cur_cq_ci, cq->depth, 226 + CQE_SHIFT); 227 + 228 + if (be32_to_cpu(cqe->qpn) == qpn) { 229 + ++nqp_cqe; 230 + } else if (nqp_cqe) { 231 + dst_cqe = get_queue_entry(cq->kern_cq.qbuf, 232 + cur_cq_ci + nqp_cqe, 233 + cq->depth, CQE_SHIFT); 234 + owner = FIELD_GET(ERDMA_CQE_HDR_OWNER_MASK, 235 + be32_to_cpu(dst_cqe->hdr)); 236 + cqe->hdr = cpu_to_be32( 237 + (be32_to_cpu(cqe->hdr) & 238 + ~ERDMA_CQE_HDR_OWNER_MASK) | 239 + FIELD_PREP(ERDMA_CQE_HDR_OWNER_MASK, owner)); 240 + memcpy(dst_cqe, cqe, sizeof(*cqe)); 241 + } 242 + 243 + --ncqe; 244 + } 245 + 246 + cq->kern_cq.ci = prev_cq_ci + nqp_cqe; 247 + spin_unlock_irqrestore(&cq->kern_cq.lock, flags); 223 248 }
+4 -2
drivers/infiniband/hw/erdma/erdma_eq.c
··· 236 236 req.db_dma_addr_l = lower_32_bits(eq->dbrec_dma); 237 237 req.db_dma_addr_h = upper_32_bits(eq->dbrec_dma); 238 238 239 - return erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL); 239 + return erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL, 240 + false); 240 241 } 241 242 242 243 static int erdma_ceq_init_one(struct erdma_dev *dev, u16 ceqn) ··· 279 278 req.qtype = ERDMA_EQ_TYPE_CEQ; 280 279 req.vector_idx = ceqn + 1; 281 280 282 - err = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL); 281 + err = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL, 282 + false); 283 283 if (err) 284 284 return; 285 285
+132 -3
drivers/infiniband/hw/erdma/erdma_hw.h
··· 9 9 10 10 #include <linux/kernel.h> 11 11 #include <linux/types.h> 12 + #include <linux/if_ether.h> 12 13 13 14 /* PCIe device related definition. */ 14 15 #define ERDMA_PCI_WIDTH 64 ··· 22 21 #define ERDMA_NUM_MSIX_VEC 32U 23 22 #define ERDMA_MSIX_VECTOR_CMDQ 0 24 23 24 + /* RoCEv2 related */ 25 + #define ERDMA_ROCEV2_GID_SIZE 16 26 + #define ERDMA_MAX_PKEYS 1 27 + #define ERDMA_DEFAULT_PKEY 0xFFFF 28 + 29 + /* erdma device protocol type */ 30 + enum erdma_proto_type { 31 + ERDMA_PROTO_IWARP = 0, 32 + ERDMA_PROTO_ROCEV2 = 1, 33 + ERDMA_PROTO_COUNT = 2, 34 + }; 35 + 25 36 /* PCIe Bar0 Registers. */ 26 37 #define ERDMA_REGS_VERSION_REG 0x0 38 + #define ERDMA_REGS_DEV_PROTO_REG 0xC 27 39 #define ERDMA_REGS_DEV_CTRL_REG 0x10 28 40 #define ERDMA_REGS_DEV_ST_REG 0x14 29 41 #define ERDMA_REGS_NETDEV_MAC_L_REG 0x18 ··· 150 136 CMDQ_OPCODE_DESTROY_CQ = 5, 151 137 CMDQ_OPCODE_REFLUSH = 6, 152 138 CMDQ_OPCODE_REG_MR = 8, 153 - CMDQ_OPCODE_DEREG_MR = 9 139 + CMDQ_OPCODE_DEREG_MR = 9, 140 + CMDQ_OPCODE_SET_GID = 14, 141 + CMDQ_OPCODE_CREATE_AH = 15, 142 + CMDQ_OPCODE_DESTROY_AH = 16, 143 + CMDQ_OPCODE_QUERY_QP = 17, 154 144 }; 155 145 156 146 enum CMDQ_COMMON_OPCODE { ··· 302 284 u32 cfg; 303 285 }; 304 286 287 + /* create_av cfg0 */ 288 + #define ERDMA_CMD_CREATE_AV_FL_MASK GENMASK(19, 0) 289 + #define ERDMA_CMD_CREATE_AV_NTYPE_MASK BIT(20) 290 + 291 + struct erdma_av_cfg { 292 + u32 cfg0; 293 + u8 traffic_class; 294 + u8 hop_limit; 295 + u8 sl; 296 + u8 rsvd; 297 + u16 udp_sport; 298 + u16 sgid_index; 299 + u8 dmac[ETH_ALEN]; 300 + u8 padding[2]; 301 + u8 dgid[ERDMA_ROCEV2_GID_SIZE]; 302 + }; 303 + 304 + struct erdma_cmdq_create_ah_req { 305 + u64 hdr; 306 + u32 pdn; 307 + u32 ahn; 308 + struct erdma_av_cfg av_cfg; 309 + }; 310 + 311 + struct erdma_cmdq_destroy_ah_req { 312 + u64 hdr; 313 + u32 pdn; 314 + u32 ahn; 315 + }; 316 + 305 317 /* modify qp cfg */ 306 318 #define ERDMA_CMD_MODIFY_QP_STATE_MASK GENMASK(31, 24) 307 319 #define ERDMA_CMD_MODIFY_QP_CC_MASK GENMASK(23, 20) ··· 349 301 u32 recv_nxt; 350 302 }; 351 303 304 + /* modify qp cfg1 for roce device */ 305 + #define ERDMA_CMD_MODIFY_QP_DQPN_MASK GENMASK(19, 0) 306 + 307 + struct erdma_cmdq_mod_qp_req_rocev2 { 308 + u64 hdr; 309 + u32 cfg0; 310 + u32 cfg1; 311 + u32 attr_mask; 312 + u32 qkey; 313 + u32 rq_psn; 314 + u32 sq_psn; 315 + struct erdma_av_cfg av_cfg; 316 + }; 317 + 318 + /* query qp response mask */ 319 + #define ERDMA_CMD_QUERY_QP_RESP_SQ_PSN_MASK GENMASK_ULL(23, 0) 320 + #define ERDMA_CMD_QUERY_QP_RESP_RQ_PSN_MASK GENMASK_ULL(47, 24) 321 + #define ERDMA_CMD_QUERY_QP_RESP_QP_STATE_MASK GENMASK_ULL(55, 48) 322 + #define ERDMA_CMD_QUERY_QP_RESP_SQ_DRAINING_MASK GENMASK_ULL(56, 56) 323 + 324 + struct erdma_cmdq_query_qp_req_rocev2 { 325 + u64 hdr; 326 + u32 qpn; 327 + }; 328 + 329 + enum erdma_qp_type { 330 + ERDMA_QPT_RC = 0, 331 + ERDMA_QPT_UD = 1, 332 + }; 333 + 352 334 /* create qp cfg0 */ 353 335 #define ERDMA_CMD_CREATE_QP_SQ_DEPTH_MASK GENMASK(31, 20) 354 336 #define ERDMA_CMD_CREATE_QP_QPN_MASK GENMASK(19, 0) ··· 386 308 /* create qp cfg1 */ 387 309 #define ERDMA_CMD_CREATE_QP_RQ_DEPTH_MASK GENMASK(31, 20) 388 310 #define ERDMA_CMD_CREATE_QP_PD_MASK GENMASK(19, 0) 311 + 312 + /* create qp cfg2 */ 313 + #define ERDMA_CMD_CREATE_QP_TYPE_MASK GENMASK(3, 0) 389 314 390 315 /* create qp cqn_mtt_cfg */ 391 316 #define ERDMA_CMD_CREATE_QP_PAGE_SIZE_MASK GENMASK(31, 28) ··· 423 342 u64 rq_mtt_entry[3]; 424 343 425 344 u32 db_cfg; 345 + u32 cfg2; 426 346 }; 427 347 428 348 struct erdma_cmdq_destroy_qp_req { ··· 476 394 u64 rx_pps_meter_drop_packets_cnt; 477 395 }; 478 396 397 + enum erdma_network_type { 398 + ERDMA_NETWORK_TYPE_IPV4 = 0, 399 + ERDMA_NETWORK_TYPE_IPV6 = 1, 400 + }; 401 + 402 + enum erdma_set_gid_op { 403 + ERDMA_SET_GID_OP_ADD = 0, 404 + ERDMA_SET_GID_OP_DEL = 1, 405 + }; 406 + 407 + /* set gid cfg */ 408 + #define ERDMA_CMD_SET_GID_SGID_IDX_MASK GENMASK(15, 0) 409 + #define ERDMA_CMD_SET_GID_NTYPE_MASK BIT(16) 410 + #define ERDMA_CMD_SET_GID_OP_MASK BIT(31) 411 + 412 + struct erdma_cmdq_set_gid_req { 413 + u64 hdr; 414 + u32 cfg; 415 + u8 gid[ERDMA_ROCEV2_GID_SIZE]; 416 + }; 417 + 479 418 /* cap qword 0 definition */ 419 + #define ERDMA_CMD_DEV_CAP_MAX_GID_MASK GENMASK_ULL(51, 48) 480 420 #define ERDMA_CMD_DEV_CAP_MAX_CQE_MASK GENMASK_ULL(47, 40) 481 421 #define ERDMA_CMD_DEV_CAP_FLAGS_MASK GENMASK_ULL(31, 24) 482 422 #define ERDMA_CMD_DEV_CAP_MAX_RECV_WR_MASK GENMASK_ULL(23, 16) 423 + #define ERDMA_CMD_DEV_CAP_MAX_AH_MASK GENMASK_ULL(15, 8) 483 424 #define ERDMA_CMD_DEV_CAP_MAX_MR_SIZE_MASK GENMASK_ULL(7, 0) 484 425 485 426 /* cap qword 1 definition */ ··· 531 426 #define ERDMA_CQE_QTYPE_RQ 1 532 427 #define ERDMA_CQE_QTYPE_CMDQ 2 533 428 429 + #define ERDMA_CQE_NTYPE_MASK BIT(31) 430 + #define ERDMA_CQE_SL_MASK GENMASK(27, 20) 431 + #define ERDMA_CQE_SQPN_MASK GENMASK(19, 0) 432 + 534 433 struct erdma_cqe { 535 434 __be32 hdr; 536 435 __be32 qe_idx; ··· 544 435 __be32 inv_rkey; 545 436 }; 546 437 __be32 size; 547 - __be32 rsvd[3]; 438 + union { 439 + struct { 440 + __be32 rsvd[3]; 441 + } rc; 442 + 443 + struct { 444 + __be32 rsvd[2]; 445 + __be32 info; 446 + } ud; 447 + }; 548 448 }; 549 449 550 450 struct erdma_sge { ··· 605 487 struct erdma_sge sgl[]; 606 488 }; 607 489 608 - struct erdma_send_sqe { 490 + struct erdma_send_sqe_rc { 609 491 __le64 hdr; 610 492 union { 611 493 __be32 imm_data; ··· 613 495 }; 614 496 615 497 __le32 length; 498 + struct erdma_sge sgl[]; 499 + }; 500 + 501 + struct erdma_send_sqe_ud { 502 + __le64 hdr; 503 + __be32 imm_data; 504 + __le32 length; 505 + __le32 qkey; 506 + __le32 dst_qpn; 507 + __le32 ahn; 508 + __le32 rsvd; 616 509 struct erdma_sge sgl[]; 617 510 }; 618 511
+41 -21
drivers/infiniband/hw/erdma/erdma_main.c
··· 26 26 goto done; 27 27 28 28 switch (event) { 29 - case NETDEV_UP: 30 - dev->state = IB_PORT_ACTIVE; 31 - erdma_port_event(dev, IB_EVENT_PORT_ACTIVE); 32 - break; 33 - case NETDEV_DOWN: 34 - dev->state = IB_PORT_DOWN; 35 - erdma_port_event(dev, IB_EVENT_PORT_ERR); 36 - break; 37 29 case NETDEV_CHANGEMTU: 38 30 if (dev->mtu != netdev->mtu) { 39 31 erdma_set_mtu(dev, netdev->mtu); ··· 163 171 static int erdma_device_init(struct erdma_dev *dev, struct pci_dev *pdev) 164 172 { 165 173 int ret; 174 + 175 + dev->proto = erdma_reg_read32(dev, ERDMA_REGS_DEV_PROTO_REG); 166 176 167 177 dev->resp_pool = dma_pool_create("erdma_resp_pool", &pdev->dev, 168 178 ERDMA_HW_RESP_SIZE, ERDMA_HW_RESP_SIZE, ··· 384 390 CMDQ_OPCODE_QUERY_DEVICE); 385 391 386 392 err = erdma_post_cmd_wait(&dev->cmdq, &req_hdr, sizeof(req_hdr), &cap0, 387 - &cap1); 393 + &cap1, true); 388 394 if (err) 389 395 return err; 390 396 ··· 392 398 dev->attrs.max_mr_size = 1ULL << ERDMA_GET_CAP(MAX_MR_SIZE, cap0); 393 399 dev->attrs.max_mw = 1 << ERDMA_GET_CAP(MAX_MW, cap1); 394 400 dev->attrs.max_recv_wr = 1 << ERDMA_GET_CAP(MAX_RECV_WR, cap0); 401 + dev->attrs.max_gid = 1 << ERDMA_GET_CAP(MAX_GID, cap0); 402 + dev->attrs.max_ah = 1 << ERDMA_GET_CAP(MAX_AH, cap0); 395 403 dev->attrs.local_dma_key = ERDMA_GET_CAP(DMA_LOCAL_KEY, cap1); 396 404 dev->attrs.cc = ERDMA_GET_CAP(DEFAULT_CC, cap1); 397 405 dev->attrs.max_qp = ERDMA_NQP_PER_QBLOCK * ERDMA_GET_CAP(QBLOCK, cap1); ··· 411 415 412 416 dev->res_cb[ERDMA_RES_TYPE_PD].max_cap = ERDMA_MAX_PD; 413 417 dev->res_cb[ERDMA_RES_TYPE_STAG_IDX].max_cap = dev->attrs.max_mr; 418 + dev->res_cb[ERDMA_RES_TYPE_AH].max_cap = dev->attrs.max_ah; 414 419 415 420 erdma_cmdq_build_reqhdr(&req_hdr, CMDQ_SUBMOD_COMMON, 416 421 CMDQ_OPCODE_QUERY_FW_INFO); 417 422 418 423 err = erdma_post_cmd_wait(&dev->cmdq, &req_hdr, sizeof(req_hdr), &cap0, 419 - &cap1); 424 + &cap1, true); 420 425 if (!err) 421 426 dev->attrs.fw_version = 422 427 FIELD_GET(ERDMA_CMD_INFO0_FW_VER_MASK, cap0); ··· 438 441 req.cfg = FIELD_PREP(ERDMA_CMD_CONFIG_DEVICE_PGSHIFT_MASK, PAGE_SHIFT) | 439 442 FIELD_PREP(ERDMA_CMD_CONFIG_DEVICE_PS_EN_MASK, 1); 440 443 441 - return erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL); 444 + return erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL, 445 + true); 442 446 } 443 447 444 448 static int erdma_res_cb_init(struct erdma_dev *dev) ··· 472 474 bitmap_free(dev->res_cb[i].bitmap); 473 475 } 474 476 477 + static const struct ib_device_ops erdma_device_ops_rocev2 = { 478 + .get_link_layer = erdma_get_link_layer, 479 + .add_gid = erdma_add_gid, 480 + .del_gid = erdma_del_gid, 481 + .query_pkey = erdma_query_pkey, 482 + .create_ah = erdma_create_ah, 483 + .destroy_ah = erdma_destroy_ah, 484 + .query_ah = erdma_query_ah, 485 + 486 + INIT_RDMA_OBJ_SIZE(ib_ah, erdma_ah, ibah), 487 + }; 488 + 489 + static const struct ib_device_ops erdma_device_ops_iwarp = { 490 + .iw_accept = erdma_accept, 491 + .iw_add_ref = erdma_qp_get_ref, 492 + .iw_connect = erdma_connect, 493 + .iw_create_listen = erdma_create_listen, 494 + .iw_destroy_listen = erdma_destroy_listen, 495 + .iw_get_qp = erdma_get_ibqp, 496 + .iw_reject = erdma_reject, 497 + .iw_rem_ref = erdma_qp_put_ref, 498 + }; 499 + 475 500 static const struct ib_device_ops erdma_device_ops = { 476 501 .owner = THIS_MODULE, 477 502 .driver_id = RDMA_DRIVER_ERDMA, ··· 515 494 .get_dma_mr = erdma_get_dma_mr, 516 495 .get_hw_stats = erdma_get_hw_stats, 517 496 .get_port_immutable = erdma_get_port_immutable, 518 - .iw_accept = erdma_accept, 519 - .iw_add_ref = erdma_qp_get_ref, 520 - .iw_connect = erdma_connect, 521 - .iw_create_listen = erdma_create_listen, 522 - .iw_destroy_listen = erdma_destroy_listen, 523 - .iw_get_qp = erdma_get_ibqp, 524 - .iw_reject = erdma_reject, 525 - .iw_rem_ref = erdma_qp_put_ref, 526 497 .map_mr_sg = erdma_map_mr_sg, 527 498 .mmap = erdma_mmap, 528 499 .mmap_free = erdma_mmap_free, 529 - .modify_qp = erdma_modify_qp, 530 500 .post_recv = erdma_post_recv, 531 501 .post_send = erdma_post_send, 532 502 .poll_cq = erdma_poll_cq, ··· 527 515 .query_qp = erdma_query_qp, 528 516 .req_notify_cq = erdma_req_notify_cq, 529 517 .reg_user_mr = erdma_reg_user_mr, 518 + .modify_qp = erdma_modify_qp, 530 519 531 520 INIT_RDMA_OBJ_SIZE(ib_cq, erdma_cq, ibcq), 532 521 INIT_RDMA_OBJ_SIZE(ib_pd, erdma_pd, ibpd), ··· 550 537 if (ret) 551 538 return ret; 552 539 553 - ibdev->node_type = RDMA_NODE_RNIC; 540 + if (erdma_device_iwarp(dev)) { 541 + ibdev->node_type = RDMA_NODE_RNIC; 542 + ib_set_device_ops(ibdev, &erdma_device_ops_iwarp); 543 + } else { 544 + ibdev->node_type = RDMA_NODE_IB_CA; 545 + ib_set_device_ops(ibdev, &erdma_device_ops_rocev2); 546 + } 547 + 554 548 memcpy(ibdev->node_desc, ERDMA_NODE_DESC, sizeof(ERDMA_NODE_DESC)); 555 549 556 550 /*
+231 -70
drivers/infiniband/hw/erdma/erdma_qp.c
··· 11 11 12 12 void erdma_qp_llp_close(struct erdma_qp *qp) 13 13 { 14 - struct erdma_qp_attrs qp_attrs; 14 + struct erdma_mod_qp_params_iwarp params; 15 15 16 16 down_write(&qp->state_lock); 17 17 18 - switch (qp->attrs.state) { 19 - case ERDMA_QP_STATE_RTS: 20 - case ERDMA_QP_STATE_RTR: 21 - case ERDMA_QP_STATE_IDLE: 22 - case ERDMA_QP_STATE_TERMINATE: 23 - qp_attrs.state = ERDMA_QP_STATE_CLOSING; 24 - erdma_modify_qp_internal(qp, &qp_attrs, ERDMA_QP_ATTR_STATE); 18 + switch (qp->attrs.iwarp.state) { 19 + case ERDMA_QPS_IWARP_RTS: 20 + case ERDMA_QPS_IWARP_RTR: 21 + case ERDMA_QPS_IWARP_IDLE: 22 + case ERDMA_QPS_IWARP_TERMINATE: 23 + params.state = ERDMA_QPS_IWARP_CLOSING; 24 + erdma_modify_qp_state_iwarp(qp, &params, ERDMA_QPA_IWARP_STATE); 25 25 break; 26 - case ERDMA_QP_STATE_CLOSING: 27 - qp->attrs.state = ERDMA_QP_STATE_IDLE; 26 + case ERDMA_QPS_IWARP_CLOSING: 27 + qp->attrs.iwarp.state = ERDMA_QPS_IWARP_IDLE; 28 28 break; 29 29 default: 30 30 break; ··· 48 48 return NULL; 49 49 } 50 50 51 - static int erdma_modify_qp_state_to_rts(struct erdma_qp *qp, 52 - struct erdma_qp_attrs *attrs, 53 - enum erdma_qp_attr_mask mask) 51 + static int 52 + erdma_modify_qp_state_to_rts(struct erdma_qp *qp, 53 + struct erdma_mod_qp_params_iwarp *params, 54 + enum erdma_qpa_mask_iwarp mask) 54 55 { 55 56 int ret; 56 57 struct erdma_dev *dev = qp->dev; ··· 60 59 struct erdma_cep *cep = qp->cep; 61 60 struct sockaddr_storage local_addr, remote_addr; 62 61 63 - if (!(mask & ERDMA_QP_ATTR_LLP_HANDLE)) 62 + if (!(mask & ERDMA_QPA_IWARP_LLP_HANDLE)) 64 63 return -EINVAL; 65 64 66 - if (!(mask & ERDMA_QP_ATTR_MPA)) 65 + if (!(mask & ERDMA_QPA_IWARP_MPA)) 67 66 return -EINVAL; 67 + 68 + if (!(mask & ERDMA_QPA_IWARP_CC)) 69 + params->cc = qp->attrs.cc; 68 70 69 71 ret = getname_local(cep->sock, &local_addr); 70 72 if (ret < 0) ··· 77 73 if (ret < 0) 78 74 return ret; 79 75 80 - qp->attrs.state = ERDMA_QP_STATE_RTS; 81 - 82 76 tp = tcp_sk(qp->cep->sock->sk); 83 77 84 78 erdma_cmdq_build_reqhdr(&req.hdr, CMDQ_SUBMOD_RDMA, 85 79 CMDQ_OPCODE_MODIFY_QP); 86 80 87 - req.cfg = FIELD_PREP(ERDMA_CMD_MODIFY_QP_STATE_MASK, qp->attrs.state) | 88 - FIELD_PREP(ERDMA_CMD_MODIFY_QP_CC_MASK, qp->attrs.cc) | 81 + req.cfg = FIELD_PREP(ERDMA_CMD_MODIFY_QP_STATE_MASK, params->state) | 82 + FIELD_PREP(ERDMA_CMD_MODIFY_QP_CC_MASK, params->cc) | 89 83 FIELD_PREP(ERDMA_CMD_MODIFY_QP_QPN_MASK, QP_ID(qp)); 90 84 91 - req.cookie = be32_to_cpu(qp->cep->mpa.ext_data.cookie); 85 + req.cookie = be32_to_cpu(cep->mpa.ext_data.cookie); 92 86 req.dip = to_sockaddr_in(remote_addr).sin_addr.s_addr; 93 87 req.sip = to_sockaddr_in(local_addr).sin_addr.s_addr; 94 88 req.dport = to_sockaddr_in(remote_addr).sin_port; ··· 94 92 95 93 req.send_nxt = tp->snd_nxt; 96 94 /* rsvd tcp seq for mpa-rsp in server. */ 97 - if (qp->attrs.qp_type == ERDMA_QP_PASSIVE) 98 - req.send_nxt += MPA_DEFAULT_HDR_LEN + qp->attrs.pd_len; 95 + if (params->qp_type == ERDMA_QP_PASSIVE) 96 + req.send_nxt += MPA_DEFAULT_HDR_LEN + params->pd_len; 99 97 req.recv_nxt = tp->rcv_nxt; 100 98 101 - return erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL); 99 + ret = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL, 100 + true); 101 + if (ret) 102 + return ret; 103 + 104 + if (mask & ERDMA_QPA_IWARP_IRD) 105 + qp->attrs.irq_size = params->irq_size; 106 + 107 + if (mask & ERDMA_QPA_IWARP_ORD) 108 + qp->attrs.orq_size = params->orq_size; 109 + 110 + if (mask & ERDMA_QPA_IWARP_CC) 111 + qp->attrs.cc = params->cc; 112 + 113 + qp->attrs.iwarp.state = ERDMA_QPS_IWARP_RTS; 114 + 115 + return 0; 102 116 } 103 117 104 - static int erdma_modify_qp_state_to_stop(struct erdma_qp *qp, 105 - struct erdma_qp_attrs *attrs, 106 - enum erdma_qp_attr_mask mask) 118 + static int 119 + erdma_modify_qp_state_to_stop(struct erdma_qp *qp, 120 + struct erdma_mod_qp_params_iwarp *params, 121 + enum erdma_qpa_mask_iwarp mask) 107 122 { 108 123 struct erdma_dev *dev = qp->dev; 109 124 struct erdma_cmdq_modify_qp_req req; 110 - 111 - qp->attrs.state = attrs->state; 125 + int ret; 112 126 113 127 erdma_cmdq_build_reqhdr(&req.hdr, CMDQ_SUBMOD_RDMA, 114 128 CMDQ_OPCODE_MODIFY_QP); 115 129 116 - req.cfg = FIELD_PREP(ERDMA_CMD_MODIFY_QP_STATE_MASK, attrs->state) | 130 + req.cfg = FIELD_PREP(ERDMA_CMD_MODIFY_QP_STATE_MASK, params->state) | 117 131 FIELD_PREP(ERDMA_CMD_MODIFY_QP_QPN_MASK, QP_ID(qp)); 118 132 119 - return erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL); 133 + ret = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL, 134 + true); 135 + if (ret) 136 + return ret; 137 + 138 + qp->attrs.iwarp.state = params->state; 139 + 140 + return 0; 120 141 } 121 142 122 - int erdma_modify_qp_internal(struct erdma_qp *qp, struct erdma_qp_attrs *attrs, 123 - enum erdma_qp_attr_mask mask) 143 + int erdma_modify_qp_state_iwarp(struct erdma_qp *qp, 144 + struct erdma_mod_qp_params_iwarp *params, 145 + int mask) 124 146 { 125 147 bool need_reflush = false; 126 148 int drop_conn, ret = 0; ··· 152 126 if (!mask) 153 127 return 0; 154 128 155 - if (!(mask & ERDMA_QP_ATTR_STATE)) 129 + if (!(mask & ERDMA_QPA_IWARP_STATE)) 156 130 return 0; 157 131 158 - switch (qp->attrs.state) { 159 - case ERDMA_QP_STATE_IDLE: 160 - case ERDMA_QP_STATE_RTR: 161 - if (attrs->state == ERDMA_QP_STATE_RTS) { 162 - ret = erdma_modify_qp_state_to_rts(qp, attrs, mask); 163 - } else if (attrs->state == ERDMA_QP_STATE_ERROR) { 164 - qp->attrs.state = ERDMA_QP_STATE_ERROR; 132 + switch (qp->attrs.iwarp.state) { 133 + case ERDMA_QPS_IWARP_IDLE: 134 + case ERDMA_QPS_IWARP_RTR: 135 + if (params->state == ERDMA_QPS_IWARP_RTS) { 136 + ret = erdma_modify_qp_state_to_rts(qp, params, mask); 137 + } else if (params->state == ERDMA_QPS_IWARP_ERROR) { 138 + qp->attrs.iwarp.state = ERDMA_QPS_IWARP_ERROR; 165 139 need_reflush = true; 166 140 if (qp->cep) { 167 141 erdma_cep_put(qp->cep); 168 142 qp->cep = NULL; 169 143 } 170 - ret = erdma_modify_qp_state_to_stop(qp, attrs, mask); 144 + ret = erdma_modify_qp_state_to_stop(qp, params, mask); 171 145 } 172 146 break; 173 - case ERDMA_QP_STATE_RTS: 147 + case ERDMA_QPS_IWARP_RTS: 174 148 drop_conn = 0; 175 149 176 - if (attrs->state == ERDMA_QP_STATE_CLOSING || 177 - attrs->state == ERDMA_QP_STATE_TERMINATE || 178 - attrs->state == ERDMA_QP_STATE_ERROR) { 179 - ret = erdma_modify_qp_state_to_stop(qp, attrs, mask); 150 + if (params->state == ERDMA_QPS_IWARP_CLOSING || 151 + params->state == ERDMA_QPS_IWARP_TERMINATE || 152 + params->state == ERDMA_QPS_IWARP_ERROR) { 153 + ret = erdma_modify_qp_state_to_stop(qp, params, mask); 180 154 drop_conn = 1; 181 155 need_reflush = true; 182 156 } ··· 185 159 erdma_qp_cm_drop(qp); 186 160 187 161 break; 188 - case ERDMA_QP_STATE_TERMINATE: 189 - if (attrs->state == ERDMA_QP_STATE_ERROR) 190 - qp->attrs.state = ERDMA_QP_STATE_ERROR; 162 + case ERDMA_QPS_IWARP_TERMINATE: 163 + if (params->state == ERDMA_QPS_IWARP_ERROR) 164 + qp->attrs.iwarp.state = ERDMA_QPS_IWARP_ERROR; 191 165 break; 192 - case ERDMA_QP_STATE_CLOSING: 193 - if (attrs->state == ERDMA_QP_STATE_IDLE) { 194 - qp->attrs.state = ERDMA_QP_STATE_IDLE; 195 - } else if (attrs->state == ERDMA_QP_STATE_ERROR) { 196 - ret = erdma_modify_qp_state_to_stop(qp, attrs, mask); 197 - qp->attrs.state = ERDMA_QP_STATE_ERROR; 198 - } else if (attrs->state != ERDMA_QP_STATE_CLOSING) { 166 + case ERDMA_QPS_IWARP_CLOSING: 167 + if (params->state == ERDMA_QPS_IWARP_IDLE) { 168 + qp->attrs.iwarp.state = ERDMA_QPS_IWARP_IDLE; 169 + } else if (params->state == ERDMA_QPS_IWARP_ERROR) { 170 + ret = erdma_modify_qp_state_to_stop(qp, params, mask); 171 + qp->attrs.iwarp.state = ERDMA_QPS_IWARP_ERROR; 172 + } else if (params->state != ERDMA_QPS_IWARP_CLOSING) { 199 173 return -ECONNABORTED; 200 174 } 201 175 break; ··· 210 184 } 211 185 212 186 return ret; 187 + } 188 + 189 + static int modify_qp_cmd_rocev2(struct erdma_qp *qp, 190 + struct erdma_mod_qp_params_rocev2 *params, 191 + enum erdma_qpa_mask_rocev2 attr_mask) 192 + { 193 + struct erdma_cmdq_mod_qp_req_rocev2 req; 194 + 195 + memset(&req, 0, sizeof(req)); 196 + 197 + erdma_cmdq_build_reqhdr(&req.hdr, CMDQ_SUBMOD_RDMA, 198 + CMDQ_OPCODE_MODIFY_QP); 199 + 200 + req.cfg0 = FIELD_PREP(ERDMA_CMD_MODIFY_QP_QPN_MASK, QP_ID(qp)); 201 + 202 + if (attr_mask & ERDMA_QPA_ROCEV2_STATE) 203 + req.cfg0 |= FIELD_PREP(ERDMA_CMD_MODIFY_QP_STATE_MASK, 204 + params->state); 205 + 206 + if (attr_mask & ERDMA_QPA_ROCEV2_DST_QPN) 207 + req.cfg1 = FIELD_PREP(ERDMA_CMD_MODIFY_QP_DQPN_MASK, 208 + params->dst_qpn); 209 + 210 + if (attr_mask & ERDMA_QPA_ROCEV2_QKEY) 211 + req.qkey = params->qkey; 212 + 213 + if (attr_mask & ERDMA_QPA_ROCEV2_AV) 214 + erdma_set_av_cfg(&req.av_cfg, &params->av); 215 + 216 + if (attr_mask & ERDMA_QPA_ROCEV2_SQ_PSN) 217 + req.sq_psn = params->sq_psn; 218 + 219 + if (attr_mask & ERDMA_QPA_ROCEV2_RQ_PSN) 220 + req.rq_psn = params->rq_psn; 221 + 222 + req.attr_mask = attr_mask; 223 + 224 + return erdma_post_cmd_wait(&qp->dev->cmdq, &req, sizeof(req), NULL, 225 + NULL, true); 226 + } 227 + 228 + static void erdma_reset_qp(struct erdma_qp *qp) 229 + { 230 + qp->kern_qp.sq_pi = 0; 231 + qp->kern_qp.sq_ci = 0; 232 + qp->kern_qp.rq_pi = 0; 233 + qp->kern_qp.rq_ci = 0; 234 + memset(qp->kern_qp.swr_tbl, 0, qp->attrs.sq_size * sizeof(u64)); 235 + memset(qp->kern_qp.rwr_tbl, 0, qp->attrs.rq_size * sizeof(u64)); 236 + memset(qp->kern_qp.sq_buf, 0, qp->attrs.sq_size << SQEBB_SHIFT); 237 + memset(qp->kern_qp.rq_buf, 0, qp->attrs.rq_size << RQE_SHIFT); 238 + erdma_remove_cqes_of_qp(&qp->scq->ibcq, QP_ID(qp)); 239 + if (qp->rcq != qp->scq) 240 + erdma_remove_cqes_of_qp(&qp->rcq->ibcq, QP_ID(qp)); 241 + } 242 + 243 + int erdma_modify_qp_state_rocev2(struct erdma_qp *qp, 244 + struct erdma_mod_qp_params_rocev2 *params, 245 + int attr_mask) 246 + { 247 + struct erdma_dev *dev = to_edev(qp->ibqp.device); 248 + int ret; 249 + 250 + ret = modify_qp_cmd_rocev2(qp, params, attr_mask); 251 + if (ret) 252 + return ret; 253 + 254 + if (attr_mask & ERDMA_QPA_ROCEV2_STATE) 255 + qp->attrs.rocev2.state = params->state; 256 + 257 + if (attr_mask & ERDMA_QPA_ROCEV2_QKEY) 258 + qp->attrs.rocev2.qkey = params->qkey; 259 + 260 + if (attr_mask & ERDMA_QPA_ROCEV2_DST_QPN) 261 + qp->attrs.rocev2.dst_qpn = params->dst_qpn; 262 + 263 + if (attr_mask & ERDMA_QPA_ROCEV2_AV) 264 + memcpy(&qp->attrs.rocev2.av, &params->av, 265 + sizeof(struct erdma_av)); 266 + 267 + if (rdma_is_kernel_res(&qp->ibqp.res) && 268 + params->state == ERDMA_QPS_ROCEV2_RESET) 269 + erdma_reset_qp(qp); 270 + 271 + if (rdma_is_kernel_res(&qp->ibqp.res) && 272 + params->state == ERDMA_QPS_ROCEV2_ERROR) { 273 + qp->flags |= ERDMA_QP_IN_FLUSHING; 274 + mod_delayed_work(dev->reflush_wq, &qp->reflush_dwork, 275 + usecs_to_jiffies(100)); 276 + } 277 + 278 + return 0; 213 279 } 214 280 215 281 static void erdma_qp_safe_free(struct kref *ref) ··· 400 282 return 0; 401 283 } 402 284 285 + static void init_send_sqe_rc(struct erdma_qp *qp, struct erdma_send_sqe_rc *sqe, 286 + const struct ib_send_wr *wr, u32 *hw_op) 287 + { 288 + u32 op = ERDMA_OP_SEND; 289 + 290 + if (wr->opcode == IB_WR_SEND_WITH_IMM) { 291 + op = ERDMA_OP_SEND_WITH_IMM; 292 + sqe->imm_data = wr->ex.imm_data; 293 + } else if (wr->opcode == IB_WR_SEND_WITH_INV) { 294 + op = ERDMA_OP_SEND_WITH_INV; 295 + sqe->invalid_stag = cpu_to_le32(wr->ex.invalidate_rkey); 296 + } 297 + 298 + *hw_op = op; 299 + } 300 + 301 + static void init_send_sqe_ud(struct erdma_qp *qp, struct erdma_send_sqe_ud *sqe, 302 + const struct ib_send_wr *wr, u32 *hw_op) 303 + { 304 + const struct ib_ud_wr *uwr = ud_wr(wr); 305 + struct erdma_ah *ah = to_eah(uwr->ah); 306 + u32 op = ERDMA_OP_SEND; 307 + 308 + if (wr->opcode == IB_WR_SEND_WITH_IMM) { 309 + op = ERDMA_OP_SEND_WITH_IMM; 310 + sqe->imm_data = wr->ex.imm_data; 311 + } 312 + 313 + *hw_op = op; 314 + 315 + sqe->ahn = cpu_to_le32(ah->ahn); 316 + sqe->dst_qpn = cpu_to_le32(uwr->remote_qpn); 317 + /* Not allowed to send control qkey */ 318 + if (uwr->remote_qkey & 0x80000000) 319 + sqe->qkey = cpu_to_le32(qp->attrs.rocev2.qkey); 320 + else 321 + sqe->qkey = cpu_to_le32(uwr->remote_qkey); 322 + } 323 + 403 324 static int erdma_push_one_sqe(struct erdma_qp *qp, u16 *pi, 404 325 const struct ib_send_wr *send_wr) 405 326 { 406 327 u32 wqe_size, wqebb_cnt, hw_op, flags, sgl_offset; 407 328 u32 idx = *pi & (qp->attrs.sq_size - 1); 408 329 enum ib_wr_opcode op = send_wr->opcode; 330 + struct erdma_send_sqe_rc *rc_send_sqe; 331 + struct erdma_send_sqe_ud *ud_send_sqe; 409 332 struct erdma_atomic_sqe *atomic_sqe; 410 333 struct erdma_readreq_sqe *read_sqe; 411 334 struct erdma_reg_mr_sqe *regmr_sge; 412 335 struct erdma_write_sqe *write_sqe; 413 - struct erdma_send_sqe *send_sqe; 414 336 struct ib_rdma_wr *rdma_wr; 415 337 struct erdma_sge *sge; 416 338 __le32 *length_field; ··· 458 300 u64 wqe_hdr, *entry; 459 301 u32 attrs; 460 302 int ret; 303 + 304 + if (qp->ibqp.qp_type != IB_QPT_RC && send_wr->opcode != IB_WR_SEND && 305 + send_wr->opcode != IB_WR_SEND_WITH_IMM) 306 + return -EINVAL; 461 307 462 308 entry = get_queue_entry(qp->kern_qp.sq_buf, idx, qp->attrs.sq_size, 463 309 SQEBB_SHIFT); ··· 536 374 case IB_WR_SEND: 537 375 case IB_WR_SEND_WITH_IMM: 538 376 case IB_WR_SEND_WITH_INV: 539 - send_sqe = (struct erdma_send_sqe *)entry; 540 - hw_op = ERDMA_OP_SEND; 541 - if (op == IB_WR_SEND_WITH_IMM) { 542 - hw_op = ERDMA_OP_SEND_WITH_IMM; 543 - send_sqe->imm_data = send_wr->ex.imm_data; 544 - } else if (op == IB_WR_SEND_WITH_INV) { 545 - hw_op = ERDMA_OP_SEND_WITH_INV; 546 - send_sqe->invalid_stag = 547 - cpu_to_le32(send_wr->ex.invalidate_rkey); 377 + if (qp->ibqp.qp_type == IB_QPT_RC) { 378 + rc_send_sqe = (struct erdma_send_sqe_rc *)entry; 379 + init_send_sqe_rc(qp, rc_send_sqe, send_wr, &hw_op); 380 + length_field = &rc_send_sqe->length; 381 + wqe_size = sizeof(struct erdma_send_sqe_rc); 382 + } else { 383 + ud_send_sqe = (struct erdma_send_sqe_ud *)entry; 384 + init_send_sqe_ud(qp, ud_send_sqe, send_wr, &hw_op); 385 + length_field = &ud_send_sqe->length; 386 + wqe_size = sizeof(struct erdma_send_sqe_ud); 548 387 } 549 - wqe_hdr |= FIELD_PREP(ERDMA_SQE_HDR_OPCODE_MASK, hw_op); 550 - length_field = &send_sqe->length; 551 - wqe_size = sizeof(struct erdma_send_sqe); 552 - sgl_offset = wqe_size; 553 388 389 + sgl_offset = wqe_size; 390 + wqe_hdr |= FIELD_PREP(ERDMA_SQE_HDR_OPCODE_MASK, hw_op); 554 391 break; 555 392 case IB_WR_REG_MR: 556 393 wqe_hdr |=
+497 -75
drivers/infiniband/hw/erdma/erdma_verbs.c
··· 55 55 ilog2(qp->attrs.rq_size)) | 56 56 FIELD_PREP(ERDMA_CMD_CREATE_QP_PD_MASK, pd->pdn); 57 57 58 + if (qp->ibqp.qp_type == IB_QPT_RC) 59 + req.cfg2 = FIELD_PREP(ERDMA_CMD_CREATE_QP_TYPE_MASK, 60 + ERDMA_QPT_RC); 61 + else 62 + req.cfg2 = FIELD_PREP(ERDMA_CMD_CREATE_QP_TYPE_MASK, 63 + ERDMA_QPT_UD); 64 + 58 65 if (rdma_is_kernel_res(&qp->ibqp.res)) { 59 66 u32 pgsz_range = ilog2(SZ_1M) - ERDMA_HW_PAGE_SHIFT; 60 67 ··· 126 119 } 127 120 } 128 121 129 - err = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), &resp0, 130 - &resp1); 131 - if (!err) 132 - qp->attrs.cookie = 122 + err = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), &resp0, &resp1, 123 + true); 124 + if (!err && erdma_device_iwarp(dev)) 125 + qp->attrs.iwarp.cookie = 133 126 FIELD_GET(ERDMA_CMDQ_CREATE_QP_RESP_COOKIE_MASK, resp0); 134 127 135 128 return err; ··· 185 178 } 186 179 187 180 post_cmd: 188 - return erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL); 181 + return erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL, 182 + true); 189 183 } 190 184 191 185 static int create_cq_cmd(struct erdma_ucontext *uctx, struct erdma_cq *cq) ··· 248 240 } 249 241 } 250 242 251 - return erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL); 243 + return erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL, 244 + true); 252 245 } 253 246 254 247 static int erdma_alloc_idx(struct erdma_resource_cb *res_cb) ··· 345 336 attr->max_fast_reg_page_list_len = ERDMA_MAX_FRMR_PA; 346 337 attr->page_size_cap = ERDMA_PAGE_SIZE_SUPPORT; 347 338 339 + if (erdma_device_rocev2(dev)) { 340 + attr->max_pkeys = ERDMA_MAX_PKEYS; 341 + attr->max_ah = dev->attrs.max_ah; 342 + } 343 + 348 344 if (dev->attrs.cap_flags & ERDMA_DEV_CAP_FLAGS_ATOMIC) 349 345 attr->atomic_cap = IB_ATOMIC_GLOB; 350 346 ··· 381 367 382 368 memset(attr, 0, sizeof(*attr)); 383 369 384 - attr->gid_tbl_len = 1; 370 + if (erdma_device_iwarp(dev)) { 371 + attr->gid_tbl_len = 1; 372 + } else { 373 + attr->gid_tbl_len = dev->attrs.max_gid; 374 + attr->ip_gids = true; 375 + attr->pkey_tbl_len = ERDMA_MAX_PKEYS; 376 + } 377 + 385 378 attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_DEVICE_MGMT_SUP; 386 379 attr->max_msg_sz = -1; 387 380 ··· 398 377 ib_get_eth_speed(ibdev, port, &attr->active_speed, &attr->active_width); 399 378 attr->max_mtu = ib_mtu_int_to_enum(ndev->mtu); 400 379 attr->active_mtu = ib_mtu_int_to_enum(ndev->mtu); 401 - if (netif_running(ndev) && netif_carrier_ok(ndev)) 402 - dev->state = IB_PORT_ACTIVE; 403 - else 404 - dev->state = IB_PORT_DOWN; 405 - attr->state = dev->state; 380 + attr->state = ib_get_curr_port_state(ndev); 406 381 407 382 out: 408 - if (dev->state == IB_PORT_ACTIVE) 383 + if (attr->state == IB_PORT_ACTIVE) 409 384 attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 410 385 else 411 386 attr->phys_state = IB_PORT_PHYS_STATE_DISABLED; ··· 412 395 int erdma_get_port_immutable(struct ib_device *ibdev, u32 port, 413 396 struct ib_port_immutable *port_immutable) 414 397 { 415 - port_immutable->gid_tbl_len = 1; 416 - port_immutable->core_cap_flags = RDMA_CORE_PORT_IWARP; 398 + struct erdma_dev *dev = to_edev(ibdev); 399 + 400 + if (erdma_device_iwarp(dev)) { 401 + port_immutable->core_cap_flags = RDMA_CORE_PORT_IWARP; 402 + port_immutable->gid_tbl_len = 1; 403 + } else { 404 + port_immutable->core_cap_flags = 405 + RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 406 + port_immutable->max_mad_size = IB_MGMT_MAD_SIZE; 407 + port_immutable->gid_tbl_len = dev->attrs.max_gid; 408 + port_immutable->pkey_tbl_len = ERDMA_MAX_PKEYS; 409 + } 417 410 418 411 return 0; 419 412 } ··· 465 438 req.qpn = QP_ID(qp); 466 439 req.sq_pi = qp->kern_qp.sq_pi; 467 440 req.rq_pi = qp->kern_qp.rq_pi; 468 - erdma_post_cmd_wait(&qp->dev->cmdq, &req, sizeof(req), NULL, NULL); 441 + erdma_post_cmd_wait(&qp->dev->cmdq, &req, sizeof(req), NULL, NULL, 442 + true); 469 443 } 470 444 471 445 static int erdma_qp_validate_cap(struct erdma_dev *dev, ··· 487 459 static int erdma_qp_validate_attr(struct erdma_dev *dev, 488 460 struct ib_qp_init_attr *attrs) 489 461 { 490 - if (attrs->qp_type != IB_QPT_RC) 462 + if (erdma_device_iwarp(dev) && attrs->qp_type != IB_QPT_RC) 463 + return -EOPNOTSUPP; 464 + 465 + if (erdma_device_rocev2(dev) && attrs->qp_type != IB_QPT_RC && 466 + attrs->qp_type != IB_QPT_UD && attrs->qp_type != IB_QPT_GSI) 491 467 return -EOPNOTSUPP; 492 468 493 469 if (attrs->srq) ··· 969 937 udata, struct erdma_ucontext, ibucontext); 970 938 struct erdma_ureq_create_qp ureq; 971 939 struct erdma_uresp_create_qp uresp; 972 - int ret; 940 + void *old_entry; 941 + int ret = 0; 973 942 974 943 ret = erdma_qp_validate_cap(dev, attrs); 975 944 if (ret) ··· 989 956 kref_init(&qp->ref); 990 957 init_completion(&qp->safe_free); 991 958 992 - ret = xa_alloc_cyclic(&dev->qp_xa, &qp->ibqp.qp_num, qp, 993 - XA_LIMIT(1, dev->attrs.max_qp - 1), 994 - &dev->next_alloc_qpn, GFP_KERNEL); 959 + if (qp->ibqp.qp_type == IB_QPT_GSI) { 960 + old_entry = xa_store(&dev->qp_xa, 1, qp, GFP_KERNEL); 961 + if (xa_is_err(old_entry)) 962 + ret = xa_err(old_entry); 963 + } else { 964 + ret = xa_alloc_cyclic(&dev->qp_xa, &qp->ibqp.qp_num, qp, 965 + XA_LIMIT(1, dev->attrs.max_qp - 1), 966 + &dev->next_alloc_qpn, GFP_KERNEL); 967 + } 968 + 995 969 if (ret < 0) { 996 970 ret = -ENOMEM; 997 971 goto err_out; ··· 1035 995 1036 996 qp->attrs.max_send_sge = attrs->cap.max_send_sge; 1037 997 qp->attrs.max_recv_sge = attrs->cap.max_recv_sge; 1038 - qp->attrs.state = ERDMA_QP_STATE_IDLE; 998 + 999 + if (erdma_device_iwarp(qp->dev)) 1000 + qp->attrs.iwarp.state = ERDMA_QPS_IWARP_IDLE; 1001 + else 1002 + qp->attrs.rocev2.state = ERDMA_QPS_ROCEV2_RESET; 1003 + 1039 1004 INIT_DELAYED_WORK(&qp->reflush_dwork, erdma_flush_worker); 1040 1005 1041 1006 ret = create_qp_cmd(uctx, qp); ··· 1264 1219 req.cfg = FIELD_PREP(ERDMA_CMD_MR_MPT_IDX_MASK, ibmr->lkey >> 8) | 1265 1220 FIELD_PREP(ERDMA_CMD_MR_KEY_MASK, ibmr->lkey & 0xFF); 1266 1221 1267 - ret = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL); 1222 + ret = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL, 1223 + true); 1268 1224 if (ret) 1269 1225 return ret; 1270 1226 ··· 1290 1244 CMDQ_OPCODE_DESTROY_CQ); 1291 1245 req.cqn = cq->cqn; 1292 1246 1293 - err = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL); 1247 + err = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL, 1248 + true); 1294 1249 if (err) 1295 1250 return err; 1296 1251 ··· 1316 1269 struct erdma_dev *dev = to_edev(ibqp->device); 1317 1270 struct erdma_ucontext *ctx = rdma_udata_to_drv_context( 1318 1271 udata, struct erdma_ucontext, ibucontext); 1319 - struct erdma_qp_attrs qp_attrs; 1320 - int err; 1321 1272 struct erdma_cmdq_destroy_qp_req req; 1273 + union erdma_mod_qp_params params; 1274 + int err; 1322 1275 1323 1276 down_write(&qp->state_lock); 1324 - qp_attrs.state = ERDMA_QP_STATE_ERROR; 1325 - erdma_modify_qp_internal(qp, &qp_attrs, ERDMA_QP_ATTR_STATE); 1277 + if (erdma_device_iwarp(dev)) { 1278 + params.iwarp.state = ERDMA_QPS_IWARP_ERROR; 1279 + erdma_modify_qp_state_iwarp(qp, &params.iwarp, 1280 + ERDMA_QPA_IWARP_STATE); 1281 + } else { 1282 + params.rocev2.state = ERDMA_QPS_ROCEV2_ERROR; 1283 + erdma_modify_qp_state_rocev2(qp, &params.rocev2, 1284 + ERDMA_QPA_ROCEV2_STATE); 1285 + } 1326 1286 up_write(&qp->state_lock); 1327 1287 1328 1288 cancel_delayed_work_sync(&qp->reflush_dwork); ··· 1338 1284 CMDQ_OPCODE_DESTROY_QP); 1339 1285 req.qpn = QP_ID(qp); 1340 1286 1341 - err = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL); 1287 + err = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL, 1288 + true); 1342 1289 if (err) 1343 1290 return err; 1344 1291 ··· 1437 1382 FIELD_PREP(ERDMA_CMD_EXT_DB_RQ_EN_MASK, 1) | 1438 1383 FIELD_PREP(ERDMA_CMD_EXT_DB_SQ_EN_MASK, 1); 1439 1384 1440 - ret = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), &val0, &val1); 1385 + ret = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), &val0, &val1, 1386 + true); 1441 1387 if (ret) 1442 1388 return ret; 1443 1389 ··· 1473 1417 req.rdb_off = ctx->ext_db.rdb_off; 1474 1418 req.cdb_off = ctx->ext_db.cdb_off; 1475 1419 1476 - ret = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL); 1420 + ret = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL, 1421 + true); 1477 1422 if (ret) 1478 1423 ibdev_err_ratelimited(&dev->ibdev, 1479 1424 "free db resources failed %d", ret); ··· 1563 1506 atomic_dec(&dev->num_ctx); 1564 1507 } 1565 1508 1566 - static int ib_qp_state_to_erdma_qp_state[IB_QPS_ERR + 1] = { 1567 - [IB_QPS_RESET] = ERDMA_QP_STATE_IDLE, 1568 - [IB_QPS_INIT] = ERDMA_QP_STATE_IDLE, 1569 - [IB_QPS_RTR] = ERDMA_QP_STATE_RTR, 1570 - [IB_QPS_RTS] = ERDMA_QP_STATE_RTS, 1571 - [IB_QPS_SQD] = ERDMA_QP_STATE_CLOSING, 1572 - [IB_QPS_SQE] = ERDMA_QP_STATE_TERMINATE, 1573 - [IB_QPS_ERR] = ERDMA_QP_STATE_ERROR 1509 + static void erdma_attr_to_av(const struct rdma_ah_attr *ah_attr, 1510 + struct erdma_av *av, u16 sport) 1511 + { 1512 + const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 1513 + 1514 + av->port = rdma_ah_get_port_num(ah_attr); 1515 + av->sgid_index = grh->sgid_index; 1516 + av->hop_limit = grh->hop_limit; 1517 + av->traffic_class = grh->traffic_class; 1518 + av->sl = rdma_ah_get_sl(ah_attr); 1519 + 1520 + av->flow_label = grh->flow_label; 1521 + av->udp_sport = sport; 1522 + 1523 + ether_addr_copy(av->dmac, ah_attr->roce.dmac); 1524 + memcpy(av->dgid, grh->dgid.raw, ERDMA_ROCEV2_GID_SIZE); 1525 + 1526 + if (ipv6_addr_v4mapped((struct in6_addr *)&grh->dgid)) 1527 + av->ntype = ERDMA_NETWORK_TYPE_IPV4; 1528 + else 1529 + av->ntype = ERDMA_NETWORK_TYPE_IPV6; 1530 + } 1531 + 1532 + static void erdma_av_to_attr(struct erdma_av *av, struct rdma_ah_attr *ah_attr) 1533 + { 1534 + ah_attr->type = RDMA_AH_ATTR_TYPE_ROCE; 1535 + 1536 + rdma_ah_set_sl(ah_attr, av->sl); 1537 + rdma_ah_set_port_num(ah_attr, av->port); 1538 + rdma_ah_set_ah_flags(ah_attr, IB_AH_GRH); 1539 + 1540 + rdma_ah_set_grh(ah_attr, NULL, av->flow_label, av->sgid_index, 1541 + av->hop_limit, av->traffic_class); 1542 + rdma_ah_set_dgid_raw(ah_attr, av->dgid); 1543 + } 1544 + 1545 + static int ib_qps_to_erdma_qps[ERDMA_PROTO_COUNT][IB_QPS_ERR + 1] = { 1546 + [ERDMA_PROTO_IWARP] = { 1547 + [IB_QPS_RESET] = ERDMA_QPS_IWARP_IDLE, 1548 + [IB_QPS_INIT] = ERDMA_QPS_IWARP_IDLE, 1549 + [IB_QPS_RTR] = ERDMA_QPS_IWARP_RTR, 1550 + [IB_QPS_RTS] = ERDMA_QPS_IWARP_RTS, 1551 + [IB_QPS_SQD] = ERDMA_QPS_IWARP_CLOSING, 1552 + [IB_QPS_SQE] = ERDMA_QPS_IWARP_TERMINATE, 1553 + [IB_QPS_ERR] = ERDMA_QPS_IWARP_ERROR, 1554 + }, 1555 + [ERDMA_PROTO_ROCEV2] = { 1556 + [IB_QPS_RESET] = ERDMA_QPS_ROCEV2_RESET, 1557 + [IB_QPS_INIT] = ERDMA_QPS_ROCEV2_INIT, 1558 + [IB_QPS_RTR] = ERDMA_QPS_ROCEV2_RTR, 1559 + [IB_QPS_RTS] = ERDMA_QPS_ROCEV2_RTS, 1560 + [IB_QPS_SQD] = ERDMA_QPS_ROCEV2_SQD, 1561 + [IB_QPS_SQE] = ERDMA_QPS_ROCEV2_SQE, 1562 + [IB_QPS_ERR] = ERDMA_QPS_ROCEV2_ERROR, 1563 + }, 1574 1564 }; 1565 + 1566 + static int erdma_qps_to_ib_qps[ERDMA_PROTO_COUNT][ERDMA_QPS_ROCEV2_COUNT] = { 1567 + [ERDMA_PROTO_IWARP] = { 1568 + [ERDMA_QPS_IWARP_IDLE] = IB_QPS_INIT, 1569 + [ERDMA_QPS_IWARP_RTR] = IB_QPS_RTR, 1570 + [ERDMA_QPS_IWARP_RTS] = IB_QPS_RTS, 1571 + [ERDMA_QPS_IWARP_CLOSING] = IB_QPS_ERR, 1572 + [ERDMA_QPS_IWARP_TERMINATE] = IB_QPS_ERR, 1573 + [ERDMA_QPS_IWARP_ERROR] = IB_QPS_ERR, 1574 + }, 1575 + [ERDMA_PROTO_ROCEV2] = { 1576 + [ERDMA_QPS_ROCEV2_RESET] = IB_QPS_RESET, 1577 + [ERDMA_QPS_ROCEV2_INIT] = IB_QPS_INIT, 1578 + [ERDMA_QPS_ROCEV2_RTR] = IB_QPS_RTR, 1579 + [ERDMA_QPS_ROCEV2_RTS] = IB_QPS_RTS, 1580 + [ERDMA_QPS_ROCEV2_SQD] = IB_QPS_SQD, 1581 + [ERDMA_QPS_ROCEV2_SQE] = IB_QPS_SQE, 1582 + [ERDMA_QPS_ROCEV2_ERROR] = IB_QPS_ERR, 1583 + }, 1584 + }; 1585 + 1586 + static inline enum erdma_qps_iwarp ib_to_iwarp_qps(enum ib_qp_state state) 1587 + { 1588 + return ib_qps_to_erdma_qps[ERDMA_PROTO_IWARP][state]; 1589 + } 1590 + 1591 + static inline enum erdma_qps_rocev2 ib_to_rocev2_qps(enum ib_qp_state state) 1592 + { 1593 + return ib_qps_to_erdma_qps[ERDMA_PROTO_ROCEV2][state]; 1594 + } 1595 + 1596 + static inline enum ib_qp_state iwarp_to_ib_qps(enum erdma_qps_iwarp state) 1597 + { 1598 + return erdma_qps_to_ib_qps[ERDMA_PROTO_IWARP][state]; 1599 + } 1600 + 1601 + static inline enum ib_qp_state rocev2_to_ib_qps(enum erdma_qps_rocev2 state) 1602 + { 1603 + return erdma_qps_to_ib_qps[ERDMA_PROTO_ROCEV2][state]; 1604 + } 1605 + 1606 + static int erdma_check_qp_attrs(struct erdma_qp *qp, struct ib_qp_attr *attr, 1607 + int attr_mask) 1608 + { 1609 + enum ib_qp_state cur_state, nxt_state; 1610 + struct erdma_dev *dev = qp->dev; 1611 + int ret = -EINVAL; 1612 + 1613 + if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) { 1614 + ret = -EOPNOTSUPP; 1615 + goto out; 1616 + } 1617 + 1618 + if ((attr_mask & IB_QP_PORT) && 1619 + !rdma_is_port_valid(&dev->ibdev, attr->port_num)) 1620 + goto out; 1621 + 1622 + if (erdma_device_rocev2(dev)) { 1623 + cur_state = (attr_mask & IB_QP_CUR_STATE) ? 1624 + attr->cur_qp_state : 1625 + rocev2_to_ib_qps(qp->attrs.rocev2.state); 1626 + 1627 + nxt_state = (attr_mask & IB_QP_STATE) ? attr->qp_state : 1628 + cur_state; 1629 + 1630 + if (!ib_modify_qp_is_ok(cur_state, nxt_state, qp->ibqp.qp_type, 1631 + attr_mask)) 1632 + goto out; 1633 + 1634 + if ((attr_mask & IB_QP_AV) && 1635 + erdma_check_gid_attr( 1636 + rdma_ah_read_grh(&attr->ah_attr)->sgid_attr)) 1637 + goto out; 1638 + 1639 + if ((attr_mask & IB_QP_PKEY_INDEX) && 1640 + attr->pkey_index >= ERDMA_MAX_PKEYS) 1641 + goto out; 1642 + } 1643 + 1644 + return 0; 1645 + 1646 + out: 1647 + return ret; 1648 + } 1649 + 1650 + static void erdma_init_mod_qp_params_rocev2( 1651 + struct erdma_qp *qp, struct erdma_mod_qp_params_rocev2 *params, 1652 + int *erdma_attr_mask, struct ib_qp_attr *attr, int ib_attr_mask) 1653 + { 1654 + enum erdma_qpa_mask_rocev2 to_modify_attrs = 0; 1655 + enum erdma_qps_rocev2 cur_state, nxt_state; 1656 + u16 udp_sport; 1657 + 1658 + if (ib_attr_mask & IB_QP_CUR_STATE) 1659 + cur_state = ib_to_rocev2_qps(attr->cur_qp_state); 1660 + else 1661 + cur_state = qp->attrs.rocev2.state; 1662 + 1663 + if (ib_attr_mask & IB_QP_STATE) 1664 + nxt_state = ib_to_rocev2_qps(attr->qp_state); 1665 + else 1666 + nxt_state = cur_state; 1667 + 1668 + to_modify_attrs |= ERDMA_QPA_ROCEV2_STATE; 1669 + params->state = nxt_state; 1670 + 1671 + if (ib_attr_mask & IB_QP_QKEY) { 1672 + to_modify_attrs |= ERDMA_QPA_ROCEV2_QKEY; 1673 + params->qkey = attr->qkey; 1674 + } 1675 + 1676 + if (ib_attr_mask & IB_QP_SQ_PSN) { 1677 + to_modify_attrs |= ERDMA_QPA_ROCEV2_SQ_PSN; 1678 + params->sq_psn = attr->sq_psn; 1679 + } 1680 + 1681 + if (ib_attr_mask & IB_QP_RQ_PSN) { 1682 + to_modify_attrs |= ERDMA_QPA_ROCEV2_RQ_PSN; 1683 + params->rq_psn = attr->rq_psn; 1684 + } 1685 + 1686 + if (ib_attr_mask & IB_QP_DEST_QPN) { 1687 + to_modify_attrs |= ERDMA_QPA_ROCEV2_DST_QPN; 1688 + params->dst_qpn = attr->dest_qp_num; 1689 + } 1690 + 1691 + if (ib_attr_mask & IB_QP_AV) { 1692 + to_modify_attrs |= ERDMA_QPA_ROCEV2_AV; 1693 + udp_sport = rdma_get_udp_sport(attr->ah_attr.grh.flow_label, 1694 + QP_ID(qp), params->dst_qpn); 1695 + erdma_attr_to_av(&attr->ah_attr, &params->av, udp_sport); 1696 + } 1697 + 1698 + *erdma_attr_mask = to_modify_attrs; 1699 + } 1575 1700 1576 1701 int erdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask, 1577 1702 struct ib_udata *udata) 1578 1703 { 1579 - struct erdma_qp_attrs new_attrs; 1580 - enum erdma_qp_attr_mask erdma_attr_mask = 0; 1581 1704 struct erdma_qp *qp = to_eqp(ibqp); 1582 - int ret = 0; 1583 - 1584 - if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 1585 - return -EOPNOTSUPP; 1586 - 1587 - memset(&new_attrs, 0, sizeof(new_attrs)); 1588 - 1589 - if (attr_mask & IB_QP_STATE) { 1590 - new_attrs.state = ib_qp_state_to_erdma_qp_state[attr->qp_state]; 1591 - 1592 - erdma_attr_mask |= ERDMA_QP_ATTR_STATE; 1593 - } 1705 + union erdma_mod_qp_params params; 1706 + int ret = 0, erdma_attr_mask = 0; 1594 1707 1595 1708 down_write(&qp->state_lock); 1596 1709 1597 - ret = erdma_modify_qp_internal(qp, &new_attrs, erdma_attr_mask); 1710 + ret = erdma_check_qp_attrs(qp, attr, attr_mask); 1711 + if (ret) 1712 + goto out; 1598 1713 1714 + if (erdma_device_iwarp(qp->dev)) { 1715 + if (attr_mask & IB_QP_STATE) { 1716 + erdma_attr_mask |= ERDMA_QPA_IWARP_STATE; 1717 + params.iwarp.state = ib_to_iwarp_qps(attr->qp_state); 1718 + } 1719 + 1720 + ret = erdma_modify_qp_state_iwarp(qp, &params.iwarp, 1721 + erdma_attr_mask); 1722 + } else { 1723 + erdma_init_mod_qp_params_rocev2( 1724 + qp, &params.rocev2, &erdma_attr_mask, attr, attr_mask); 1725 + 1726 + ret = erdma_modify_qp_state_rocev2(qp, &params.rocev2, 1727 + erdma_attr_mask); 1728 + } 1729 + 1730 + out: 1599 1731 up_write(&qp->state_lock); 1600 - 1601 1732 return ret; 1602 1733 } 1603 1734 1604 1735 static enum ib_qp_state query_qp_state(struct erdma_qp *qp) 1605 1736 { 1606 - switch (qp->attrs.state) { 1607 - case ERDMA_QP_STATE_IDLE: 1608 - return IB_QPS_INIT; 1609 - case ERDMA_QP_STATE_RTR: 1610 - return IB_QPS_RTR; 1611 - case ERDMA_QP_STATE_RTS: 1612 - return IB_QPS_RTS; 1613 - case ERDMA_QP_STATE_CLOSING: 1614 - return IB_QPS_ERR; 1615 - case ERDMA_QP_STATE_TERMINATE: 1616 - return IB_QPS_ERR; 1617 - case ERDMA_QP_STATE_ERROR: 1618 - return IB_QPS_ERR; 1619 - default: 1620 - return IB_QPS_ERR; 1621 - } 1737 + if (erdma_device_iwarp(qp->dev)) 1738 + return iwarp_to_ib_qps(qp->attrs.iwarp.state); 1739 + else 1740 + return rocev2_to_ib_qps(qp->attrs.rocev2.state); 1622 1741 } 1623 1742 1624 1743 int erdma_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 1625 1744 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 1626 1745 { 1746 + struct erdma_cmdq_query_qp_req_rocev2 req; 1627 1747 struct erdma_dev *dev; 1628 1748 struct erdma_qp *qp; 1749 + u64 resp0, resp1; 1750 + int ret; 1629 1751 1630 1752 if (ibqp && qp_attr && qp_init_attr) { 1631 1753 qp = to_eqp(ibqp); ··· 1831 1595 1832 1596 qp_init_attr->cap = qp_attr->cap; 1833 1597 1834 - qp_attr->qp_state = query_qp_state(qp); 1835 - qp_attr->cur_qp_state = query_qp_state(qp); 1598 + if (erdma_device_rocev2(dev)) { 1599 + /* Query hardware to get some attributes */ 1600 + erdma_cmdq_build_reqhdr(&req.hdr, CMDQ_SUBMOD_RDMA, 1601 + CMDQ_OPCODE_QUERY_QP); 1602 + req.qpn = QP_ID(qp); 1603 + 1604 + ret = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), &resp0, 1605 + &resp1, true); 1606 + if (ret) 1607 + return ret; 1608 + 1609 + qp_attr->sq_psn = 1610 + FIELD_GET(ERDMA_CMD_QUERY_QP_RESP_SQ_PSN_MASK, resp0); 1611 + qp_attr->rq_psn = 1612 + FIELD_GET(ERDMA_CMD_QUERY_QP_RESP_RQ_PSN_MASK, resp0); 1613 + qp_attr->qp_state = rocev2_to_ib_qps(FIELD_GET( 1614 + ERDMA_CMD_QUERY_QP_RESP_QP_STATE_MASK, resp0)); 1615 + qp_attr->cur_qp_state = qp_attr->qp_state; 1616 + qp_attr->sq_draining = FIELD_GET( 1617 + ERDMA_CMD_QUERY_QP_RESP_SQ_DRAINING_MASK, resp0); 1618 + 1619 + qp_attr->pkey_index = 0; 1620 + qp_attr->dest_qp_num = qp->attrs.rocev2.dst_qpn; 1621 + 1622 + if (qp->ibqp.qp_type == IB_QPT_RC) 1623 + erdma_av_to_attr(&qp->attrs.rocev2.av, 1624 + &qp_attr->ah_attr); 1625 + } else { 1626 + qp_attr->qp_state = query_qp_state(qp); 1627 + qp_attr->cur_qp_state = qp_attr->qp_state; 1628 + } 1836 1629 1837 1630 return 0; 1838 1631 } ··· 2001 1736 CMDQ_OPCODE_CONF_MTU); 2002 1737 req.mtu = mtu; 2003 1738 2004 - erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL); 1739 + erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL, true); 2005 1740 } 2006 1741 2007 1742 void erdma_port_event(struct erdma_dev *dev, enum ib_event_type reason) ··· 2071 1806 req.target_addr = dma_addr; 2072 1807 req.target_length = ERDMA_HW_RESP_SIZE; 2073 1808 2074 - err = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL); 1809 + err = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL, 1810 + true); 2075 1811 if (err) 2076 1812 goto out; 2077 1813 ··· 2104 1838 return ret; 2105 1839 2106 1840 return stats->num_counters; 1841 + } 1842 + 1843 + enum rdma_link_layer erdma_get_link_layer(struct ib_device *ibdev, u32 port_num) 1844 + { 1845 + return IB_LINK_LAYER_ETHERNET; 1846 + } 1847 + 1848 + static int erdma_set_gid(struct erdma_dev *dev, u8 op, u32 idx, 1849 + const union ib_gid *gid) 1850 + { 1851 + struct erdma_cmdq_set_gid_req req; 1852 + u8 ntype; 1853 + 1854 + req.cfg = FIELD_PREP(ERDMA_CMD_SET_GID_SGID_IDX_MASK, idx) | 1855 + FIELD_PREP(ERDMA_CMD_SET_GID_OP_MASK, op); 1856 + 1857 + if (op == ERDMA_SET_GID_OP_ADD) { 1858 + if (ipv6_addr_v4mapped((struct in6_addr *)gid)) 1859 + ntype = ERDMA_NETWORK_TYPE_IPV4; 1860 + else 1861 + ntype = ERDMA_NETWORK_TYPE_IPV6; 1862 + 1863 + req.cfg |= FIELD_PREP(ERDMA_CMD_SET_GID_NTYPE_MASK, ntype); 1864 + 1865 + memcpy(&req.gid, gid, ERDMA_ROCEV2_GID_SIZE); 1866 + } 1867 + 1868 + erdma_cmdq_build_reqhdr(&req.hdr, CMDQ_SUBMOD_RDMA, 1869 + CMDQ_OPCODE_SET_GID); 1870 + return erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL, 1871 + true); 1872 + } 1873 + 1874 + int erdma_add_gid(const struct ib_gid_attr *attr, void **context) 1875 + { 1876 + struct erdma_dev *dev = to_edev(attr->device); 1877 + int ret; 1878 + 1879 + ret = erdma_check_gid_attr(attr); 1880 + if (ret) 1881 + return ret; 1882 + 1883 + return erdma_set_gid(dev, ERDMA_SET_GID_OP_ADD, attr->index, 1884 + &attr->gid); 1885 + } 1886 + 1887 + int erdma_del_gid(const struct ib_gid_attr *attr, void **context) 1888 + { 1889 + return erdma_set_gid(to_edev(attr->device), ERDMA_SET_GID_OP_DEL, 1890 + attr->index, NULL); 1891 + } 1892 + 1893 + int erdma_query_pkey(struct ib_device *ibdev, u32 port, u16 index, u16 *pkey) 1894 + { 1895 + if (index >= ERDMA_MAX_PKEYS) 1896 + return -EINVAL; 1897 + 1898 + *pkey = ERDMA_DEFAULT_PKEY; 1899 + return 0; 1900 + } 1901 + 1902 + void erdma_set_av_cfg(struct erdma_av_cfg *av_cfg, struct erdma_av *av) 1903 + { 1904 + av_cfg->cfg0 = FIELD_PREP(ERDMA_CMD_CREATE_AV_FL_MASK, av->flow_label) | 1905 + FIELD_PREP(ERDMA_CMD_CREATE_AV_NTYPE_MASK, av->ntype); 1906 + 1907 + av_cfg->traffic_class = av->traffic_class; 1908 + av_cfg->hop_limit = av->hop_limit; 1909 + av_cfg->sl = av->sl; 1910 + 1911 + av_cfg->udp_sport = av->udp_sport; 1912 + av_cfg->sgid_index = av->sgid_index; 1913 + 1914 + ether_addr_copy(av_cfg->dmac, av->dmac); 1915 + memcpy(av_cfg->dgid, av->dgid, ERDMA_ROCEV2_GID_SIZE); 1916 + } 1917 + 1918 + int erdma_create_ah(struct ib_ah *ibah, struct rdma_ah_init_attr *init_attr, 1919 + struct ib_udata *udata) 1920 + { 1921 + const struct ib_global_route *grh = 1922 + rdma_ah_read_grh(init_attr->ah_attr); 1923 + struct erdma_dev *dev = to_edev(ibah->device); 1924 + struct erdma_pd *pd = to_epd(ibah->pd); 1925 + struct erdma_ah *ah = to_eah(ibah); 1926 + struct erdma_cmdq_create_ah_req req; 1927 + u32 udp_sport; 1928 + int ret; 1929 + 1930 + ret = erdma_check_gid_attr(grh->sgid_attr); 1931 + if (ret) 1932 + return ret; 1933 + 1934 + ret = erdma_alloc_idx(&dev->res_cb[ERDMA_RES_TYPE_AH]); 1935 + if (ret < 0) 1936 + return ret; 1937 + 1938 + ah->ahn = ret; 1939 + 1940 + if (grh->flow_label) 1941 + udp_sport = rdma_flow_label_to_udp_sport(grh->flow_label); 1942 + else 1943 + udp_sport = 1944 + IB_ROCE_UDP_ENCAP_VALID_PORT_MIN + (ah->ahn & 0x3FFF); 1945 + 1946 + erdma_attr_to_av(init_attr->ah_attr, &ah->av, udp_sport); 1947 + 1948 + erdma_cmdq_build_reqhdr(&req.hdr, CMDQ_SUBMOD_RDMA, 1949 + CMDQ_OPCODE_CREATE_AH); 1950 + 1951 + req.pdn = pd->pdn; 1952 + req.ahn = ah->ahn; 1953 + erdma_set_av_cfg(&req.av_cfg, &ah->av); 1954 + 1955 + ret = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL, 1956 + init_attr->flags & RDMA_CREATE_AH_SLEEPABLE); 1957 + if (ret) { 1958 + erdma_free_idx(&dev->res_cb[ERDMA_RES_TYPE_AH], ah->ahn); 1959 + return ret; 1960 + } 1961 + 1962 + return 0; 1963 + } 1964 + 1965 + int erdma_destroy_ah(struct ib_ah *ibah, u32 flags) 1966 + { 1967 + struct erdma_dev *dev = to_edev(ibah->device); 1968 + struct erdma_pd *pd = to_epd(ibah->pd); 1969 + struct erdma_ah *ah = to_eah(ibah); 1970 + struct erdma_cmdq_destroy_ah_req req; 1971 + int ret; 1972 + 1973 + erdma_cmdq_build_reqhdr(&req.hdr, CMDQ_SUBMOD_RDMA, 1974 + CMDQ_OPCODE_DESTROY_AH); 1975 + 1976 + req.pdn = pd->pdn; 1977 + req.ahn = ah->ahn; 1978 + 1979 + ret = erdma_post_cmd_wait(&dev->cmdq, &req, sizeof(req), NULL, NULL, 1980 + flags & RDMA_DESTROY_AH_SLEEPABLE); 1981 + if (ret) 1982 + return ret; 1983 + 1984 + erdma_free_idx(&dev->res_cb[ERDMA_RES_TYPE_AH], ah->ahn); 1985 + 1986 + return 0; 1987 + } 1988 + 1989 + int erdma_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr) 1990 + { 1991 + struct erdma_ah *ah = to_eah(ibah); 1992 + 1993 + memset(ah_attr, 0, sizeof(*ah_attr)); 1994 + erdma_av_to_attr(&ah->av, ah_attr); 1995 + 1996 + return 0; 2107 1997 }
+141 -25
drivers/infiniband/hw/erdma/erdma_verbs.h
··· 136 136 int refcnt; 137 137 }; 138 138 139 + struct erdma_av { 140 + u8 port; 141 + u8 hop_limit; 142 + u8 traffic_class; 143 + u8 sl; 144 + u8 sgid_index; 145 + u16 udp_sport; 146 + u32 flow_label; 147 + u8 dmac[ETH_ALEN]; 148 + u8 dgid[ERDMA_ROCEV2_GID_SIZE]; 149 + enum erdma_network_type ntype; 150 + }; 151 + 152 + struct erdma_ah { 153 + struct ib_ah ibah; 154 + struct erdma_av av; 155 + u32 ahn; 156 + }; 157 + 139 158 struct erdma_uqp { 140 159 struct erdma_mem sq_mem; 141 160 struct erdma_mem rq_mem; ··· 195 176 u8 sig_all; 196 177 }; 197 178 198 - enum erdma_qp_state { 199 - ERDMA_QP_STATE_IDLE = 0, 200 - ERDMA_QP_STATE_RTR = 1, 201 - ERDMA_QP_STATE_RTS = 2, 202 - ERDMA_QP_STATE_CLOSING = 3, 203 - ERDMA_QP_STATE_TERMINATE = 4, 204 - ERDMA_QP_STATE_ERROR = 5, 205 - ERDMA_QP_STATE_UNDEF = 7, 206 - ERDMA_QP_STATE_COUNT = 8 179 + enum erdma_qps_iwarp { 180 + ERDMA_QPS_IWARP_IDLE = 0, 181 + ERDMA_QPS_IWARP_RTR = 1, 182 + ERDMA_QPS_IWARP_RTS = 2, 183 + ERDMA_QPS_IWARP_CLOSING = 3, 184 + ERDMA_QPS_IWARP_TERMINATE = 4, 185 + ERDMA_QPS_IWARP_ERROR = 5, 186 + ERDMA_QPS_IWARP_UNDEF = 6, 187 + ERDMA_QPS_IWARP_COUNT = 7, 207 188 }; 208 189 209 - enum erdma_qp_attr_mask { 210 - ERDMA_QP_ATTR_STATE = (1 << 0), 211 - ERDMA_QP_ATTR_LLP_HANDLE = (1 << 2), 212 - ERDMA_QP_ATTR_ORD = (1 << 3), 213 - ERDMA_QP_ATTR_IRD = (1 << 4), 214 - ERDMA_QP_ATTR_SQ_SIZE = (1 << 5), 215 - ERDMA_QP_ATTR_RQ_SIZE = (1 << 6), 216 - ERDMA_QP_ATTR_MPA = (1 << 7) 190 + enum erdma_qpa_mask_iwarp { 191 + ERDMA_QPA_IWARP_STATE = (1 << 0), 192 + ERDMA_QPA_IWARP_LLP_HANDLE = (1 << 2), 193 + ERDMA_QPA_IWARP_ORD = (1 << 3), 194 + ERDMA_QPA_IWARP_IRD = (1 << 4), 195 + ERDMA_QPA_IWARP_SQ_SIZE = (1 << 5), 196 + ERDMA_QPA_IWARP_RQ_SIZE = (1 << 6), 197 + ERDMA_QPA_IWARP_MPA = (1 << 7), 198 + ERDMA_QPA_IWARP_CC = (1 << 8), 199 + }; 200 + 201 + enum erdma_qps_rocev2 { 202 + ERDMA_QPS_ROCEV2_RESET = 0, 203 + ERDMA_QPS_ROCEV2_INIT = 1, 204 + ERDMA_QPS_ROCEV2_RTR = 2, 205 + ERDMA_QPS_ROCEV2_RTS = 3, 206 + ERDMA_QPS_ROCEV2_SQD = 4, 207 + ERDMA_QPS_ROCEV2_SQE = 5, 208 + ERDMA_QPS_ROCEV2_ERROR = 6, 209 + ERDMA_QPS_ROCEV2_COUNT = 7, 210 + }; 211 + 212 + enum erdma_qpa_mask_rocev2 { 213 + ERDMA_QPA_ROCEV2_STATE = (1 << 0), 214 + ERDMA_QPA_ROCEV2_QKEY = (1 << 1), 215 + ERDMA_QPA_ROCEV2_AV = (1 << 2), 216 + ERDMA_QPA_ROCEV2_SQ_PSN = (1 << 3), 217 + ERDMA_QPA_ROCEV2_RQ_PSN = (1 << 4), 218 + ERDMA_QPA_ROCEV2_DST_QPN = (1 << 5), 217 219 }; 218 220 219 221 enum erdma_qp_flags { 220 222 ERDMA_QP_IN_FLUSHING = (1 << 0), 221 223 }; 222 224 225 + #define ERDMA_QP_ACTIVE 0 226 + #define ERDMA_QP_PASSIVE 1 227 + 228 + struct erdma_mod_qp_params_iwarp { 229 + enum erdma_qps_iwarp state; 230 + enum erdma_cc_alg cc; 231 + u8 qp_type; 232 + u8 pd_len; 233 + u32 irq_size; 234 + u32 orq_size; 235 + }; 236 + 237 + struct erdma_qp_attrs_iwarp { 238 + enum erdma_qps_iwarp state; 239 + u32 cookie; 240 + }; 241 + 242 + struct erdma_mod_qp_params_rocev2 { 243 + enum erdma_qps_rocev2 state; 244 + u32 qkey; 245 + u32 sq_psn; 246 + u32 rq_psn; 247 + u32 dst_qpn; 248 + struct erdma_av av; 249 + }; 250 + 251 + union erdma_mod_qp_params { 252 + struct erdma_mod_qp_params_iwarp iwarp; 253 + struct erdma_mod_qp_params_rocev2 rocev2; 254 + }; 255 + 256 + struct erdma_qp_attrs_rocev2 { 257 + enum erdma_qps_rocev2 state; 258 + u32 qkey; 259 + u32 dst_qpn; 260 + struct erdma_av av; 261 + }; 262 + 223 263 struct erdma_qp_attrs { 224 - enum erdma_qp_state state; 225 264 enum erdma_cc_alg cc; /* Congestion control algorithm */ 226 265 u32 sq_size; 227 266 u32 rq_size; ··· 287 210 u32 irq_size; 288 211 u32 max_send_sge; 289 212 u32 max_recv_sge; 290 - u32 cookie; 291 - #define ERDMA_QP_ACTIVE 0 292 - #define ERDMA_QP_PASSIVE 1 293 - u8 qp_type; 294 - u8 pd_len; 213 + union { 214 + struct erdma_qp_attrs_iwarp iwarp; 215 + struct erdma_qp_attrs_rocev2 rocev2; 216 + }; 295 217 }; 296 218 297 219 struct erdma_qp { ··· 362 286 363 287 void erdma_qp_get(struct erdma_qp *qp); 364 288 void erdma_qp_put(struct erdma_qp *qp); 365 - int erdma_modify_qp_internal(struct erdma_qp *qp, struct erdma_qp_attrs *attrs, 366 - enum erdma_qp_attr_mask mask); 289 + int erdma_modify_qp_state_iwarp(struct erdma_qp *qp, 290 + struct erdma_mod_qp_params_iwarp *params, 291 + int mask); 292 + int erdma_modify_qp_state_rocev2(struct erdma_qp *qp, 293 + struct erdma_mod_qp_params_rocev2 *params, 294 + int attr_mask); 367 295 void erdma_qp_llp_close(struct erdma_qp *qp); 368 296 void erdma_qp_cm_drop(struct erdma_qp *qp); 297 + 298 + static inline bool erdma_device_iwarp(struct erdma_dev *dev) 299 + { 300 + return dev->proto == ERDMA_PROTO_IWARP; 301 + } 302 + 303 + static inline bool erdma_device_rocev2(struct erdma_dev *dev) 304 + { 305 + return dev->proto == ERDMA_PROTO_ROCEV2; 306 + } 369 307 370 308 static inline struct erdma_ucontext *to_ectx(struct ib_ucontext *ibctx) 371 309 { ··· 404 314 static inline struct erdma_cq *to_ecq(struct ib_cq *ibcq) 405 315 { 406 316 return container_of(ibcq, struct erdma_cq, ibcq); 317 + } 318 + 319 + static inline struct erdma_ah *to_eah(struct ib_ah *ibah) 320 + { 321 + return container_of(ibah, struct erdma_ah, ibah); 322 + } 323 + 324 + static inline int erdma_check_gid_attr(const struct ib_gid_attr *attr) 325 + { 326 + u8 ntype = rdma_gid_attr_network_type(attr); 327 + 328 + if (ntype != RDMA_NETWORK_IPV4 && ntype != RDMA_NETWORK_IPV6) 329 + return -EINVAL; 330 + 331 + return 0; 407 332 } 408 333 409 334 static inline struct erdma_user_mmap_entry * ··· 465 360 int erdma_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *recv_wr, 466 361 const struct ib_recv_wr **bad_recv_wr); 467 362 int erdma_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 363 + void erdma_remove_cqes_of_qp(struct ib_cq *ibcq, u32 qpn); 468 364 struct ib_mr *erdma_ib_alloc_mr(struct ib_pd *ibpd, enum ib_mr_type mr_type, 469 365 u32 max_num_sg); 470 366 int erdma_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, ··· 476 370 u32 port_num); 477 371 int erdma_get_hw_stats(struct ib_device *ibdev, struct rdma_hw_stats *stats, 478 372 u32 port, int index); 373 + enum rdma_link_layer erdma_get_link_layer(struct ib_device *ibdev, 374 + u32 port_num); 375 + int erdma_add_gid(const struct ib_gid_attr *attr, void **context); 376 + int erdma_del_gid(const struct ib_gid_attr *attr, void **context); 377 + int erdma_query_pkey(struct ib_device *ibdev, u32 port, u16 index, u16 *pkey); 378 + void erdma_set_av_cfg(struct erdma_av_cfg *av_cfg, struct erdma_av *av); 379 + int erdma_create_ah(struct ib_ah *ibah, struct rdma_ah_init_attr *init_attr, 380 + struct ib_udata *udata); 381 + int erdma_destroy_ah(struct ib_ah *ibah, u32 flags); 382 + int erdma_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 479 383 480 384 #endif
-14
drivers/infiniband/hw/hfi1/hfi.h
··· 2339 2339 dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \ 2340 2340 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), (port), ##__VA_ARGS__) 2341 2341 2342 - /* 2343 - * this is used for formatting hw error messages... 2344 - */ 2345 - struct hfi1_hwerror_msgs { 2346 - u64 mask; 2347 - const char *msg; 2348 - size_t sz; 2349 - }; 2350 - 2351 - /* in intr.c... */ 2352 - void hfi1_format_hwerrors(u64 hwerrs, 2353 - const struct hfi1_hwerror_msgs *hwerrmsgs, 2354 - size_t nhwerrmsgs, char *msg, size_t lmsg); 2355 - 2356 2342 #define USER_OPCODE_CHECK_VAL 0xC0 2357 2343 #define USER_OPCODE_CHECK_MASK 0xC0 2358 2344 #define OPCODE_CHECK_VAL_DISABLED 0x0
-31
drivers/infiniband/hw/hfi1/intr.c
··· 47 47 hfi1_event_pkey_change(ppd->dd, ppd->port); 48 48 } 49 49 50 - /** 51 - * format_hwmsg - format a single hwerror message 52 - * @msg: message buffer 53 - * @msgl: length of message buffer 54 - * @hwmsg: message to add to message buffer 55 - */ 56 - static void format_hwmsg(char *msg, size_t msgl, const char *hwmsg) 57 - { 58 - strlcat(msg, "[", msgl); 59 - strlcat(msg, hwmsg, msgl); 60 - strlcat(msg, "]", msgl); 61 - } 62 - 63 - /** 64 - * hfi1_format_hwerrors - format hardware error messages for display 65 - * @hwerrs: hardware errors bit vector 66 - * @hwerrmsgs: hardware error descriptions 67 - * @nhwerrmsgs: number of hwerrmsgs 68 - * @msg: message buffer 69 - * @msgl: message buffer length 70 - */ 71 - void hfi1_format_hwerrors(u64 hwerrs, const struct hfi1_hwerror_msgs *hwerrmsgs, 72 - size_t nhwerrmsgs, char *msg, size_t msgl) 73 - { 74 - int i; 75 - 76 - for (i = 0; i < nhwerrmsgs; i++) 77 - if (hwerrs & hwerrmsgs[i].mask) 78 - format_hwmsg(msg, msgl, hwerrmsgs[i].msg); 79 - } 80 - 81 50 static void signal_ib_event(struct hfi1_pportdata *ppd, enum ib_event_type ev) 82 51 { 83 52 struct ib_event event;
+7 -7
drivers/infiniband/hw/hfi1/sysfs.c
··· 27 27 * Congestion control table size followed by table entries 28 28 */ 29 29 static ssize_t cc_table_bin_read(struct file *filp, struct kobject *kobj, 30 - struct bin_attribute *bin_attr, char *buf, 31 - loff_t pos, size_t count) 30 + const struct bin_attribute *bin_attr, 31 + char *buf, loff_t pos, size_t count) 32 32 { 33 33 int ret; 34 34 struct hfi1_pportdata *ppd = hfi1_get_pportdata_kobj(kobj); ··· 57 57 58 58 return count; 59 59 } 60 - static BIN_ATTR_RO(cc_table_bin, PAGE_SIZE); 60 + static const BIN_ATTR_RO(cc_table_bin, PAGE_SIZE); 61 61 62 62 /* 63 63 * Congestion settings: port control, control map and an array of 16 ··· 65 65 * trigger threshold and the minimum injection rate delay. 66 66 */ 67 67 static ssize_t cc_setting_bin_read(struct file *filp, struct kobject *kobj, 68 - struct bin_attribute *bin_attr, 68 + const struct bin_attribute *bin_attr, 69 69 char *buf, loff_t pos, size_t count) 70 70 { 71 71 struct hfi1_pportdata *ppd = hfi1_get_pportdata_kobj(kobj); ··· 93 93 94 94 return count; 95 95 } 96 - static BIN_ATTR_RO(cc_setting_bin, PAGE_SIZE); 96 + static const BIN_ATTR_RO(cc_setting_bin, PAGE_SIZE); 97 97 98 - static struct bin_attribute *port_cc_bin_attributes[] = { 98 + static const struct bin_attribute *const port_cc_bin_attributes[] = { 99 99 &bin_attr_cc_setting_bin, 100 100 &bin_attr_cc_table_bin, 101 101 NULL ··· 134 134 static const struct attribute_group port_cc_group = { 135 135 .name = "CCMgtA", 136 136 .attrs = port_cc_attributes, 137 - .bin_attrs = port_cc_bin_attributes, 137 + .bin_attrs_new = port_cc_bin_attributes, 138 138 }; 139 139 140 140 /* Start sc2vl */
+5 -15
drivers/infiniband/hw/hns/Kconfig
··· 1 1 # SPDX-License-Identifier: GPL-2.0-only 2 - config INFINIBAND_HNS 3 - tristate "HNS RoCE Driver" 4 - depends on NET_VENDOR_HISILICON 5 - depends on ARM64 || (COMPILE_TEST && 64BIT) 6 - depends on (HNS_DSAF && HNS_ENET) || HNS3 7 - help 8 - This is a RoCE/RDMA driver for the Hisilicon RoCE engine. 9 - 10 - To compile HIP08 driver as module, choose M here. 11 - 12 2 config INFINIBAND_HNS_HIP08 13 - bool "Hisilicon Hip08 Family RoCE support" 14 - depends on INFINIBAND_HNS && PCI && HNS3 15 - depends on INFINIBAND_HNS=m || HNS3=y 3 + tristate "Hisilicon Hip08 Family RoCE support" 4 + depends on ARM64 || (COMPILE_TEST && 64BIT) 5 + depends on PCI && HNS3 16 6 help 17 7 RoCE driver support for Hisilicon RoCE engine in Hisilicon Hip08 SoC. 18 8 The RoCE engine is a PCI device. 19 9 20 - To compile this driver, choose Y here: if INFINIBAND_HNS is m, this 21 - module will be called hns-roce-hw-v2. 10 + To compile this driver, choose M here. This module will be called 11 + hns-roce-hw-v2.
+3 -6
drivers/infiniband/hw/hns/Makefile
··· 5 5 6 6 ccflags-y := -I $(srctree)/drivers/net/ethernet/hisilicon/hns3 7 7 8 - hns-roce-objs := hns_roce_main.o hns_roce_cmd.o hns_roce_pd.o \ 8 + hns-roce-hw-v2-objs := hns_roce_main.o hns_roce_cmd.o hns_roce_pd.o \ 9 9 hns_roce_ah.o hns_roce_hem.o hns_roce_mr.o hns_roce_qp.o \ 10 10 hns_roce_cq.o hns_roce_alloc.o hns_roce_db.o hns_roce_srq.o hns_roce_restrack.o \ 11 - hns_roce_debugfs.o 11 + hns_roce_debugfs.o hns_roce_hw_v2.o 12 12 13 - ifdef CONFIG_INFINIBAND_HNS_HIP08 14 - hns-roce-hw-v2-objs := hns_roce_hw_v2.o $(hns-roce-objs) 15 - obj-$(CONFIG_INFINIBAND_HNS) += hns-roce-hw-v2.o 16 - endif 13 + obj-$(CONFIG_INFINIBAND_HNS_HIP08) += hns-roce-hw-v2.o
+13
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
··· 7185 7185 return ret; 7186 7186 } 7187 7187 7188 + static void hns_roce_hw_v2_link_status_change(struct hnae3_handle *handle, 7189 + bool linkup) 7190 + { 7191 + struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv; 7192 + struct net_device *netdev = handle->rinfo.netdev; 7193 + 7194 + if (linkup || !hr_dev) 7195 + return; 7196 + 7197 + ib_dispatch_port_state_event(&hr_dev->ib_dev, netdev); 7198 + } 7199 + 7188 7200 static const struct hnae3_client_ops hns_roce_hw_v2_ops = { 7189 7201 .init_instance = hns_roce_hw_v2_init_instance, 7190 7202 .uninit_instance = hns_roce_hw_v2_uninit_instance, 7203 + .link_status_change = hns_roce_hw_v2_link_status_change, 7191 7204 .reset_notify = hns_roce_hw_v2_reset_notify, 7192 7205 }; 7193 7206
-4
drivers/infiniband/hw/irdma/osdep.h
··· 59 59 int irdma_cqp_manage_hmc_fcn_cmd(struct irdma_sc_dev *dev, 60 60 struct irdma_hmc_fcn_info *hmcfcninfo, 61 61 u16 *pmf_idx); 62 - int irdma_cqp_query_fpm_val_cmd(struct irdma_sc_dev *dev, 63 - struct irdma_dma_mem *val_mem, u8 hmc_fn_id); 64 - int irdma_cqp_commit_fpm_val_cmd(struct irdma_sc_dev *dev, 65 - struct irdma_dma_mem *val_mem, u8 hmc_fn_id); 66 62 int irdma_alloc_query_fpm_buf(struct irdma_sc_dev *dev, 67 63 struct irdma_dma_mem *mem); 68 64 void *irdma_remove_cqp_head(struct irdma_sc_dev *dev);
-4
drivers/infiniband/hw/irdma/protos.h
··· 85 85 int irdma_process_bh(struct irdma_sc_dev *dev); 86 86 int irdma_cqp_sds_cmd(struct irdma_sc_dev *dev, 87 87 struct irdma_update_sds_info *info); 88 - int irdma_cqp_query_fpm_val_cmd(struct irdma_sc_dev *dev, 89 - struct irdma_dma_mem *val_mem, u8 hmc_fn_id); 90 - int irdma_cqp_commit_fpm_val_cmd(struct irdma_sc_dev *dev, 91 - struct irdma_dma_mem *val_mem, u8 hmc_fn_id); 92 88 int irdma_alloc_query_fpm_buf(struct irdma_sc_dev *dev, 93 89 struct irdma_dma_mem *mem); 94 90 int irdma_cqp_manage_hmc_fcn_cmd(struct irdma_sc_dev *dev,
-71
drivers/infiniband/hw/irdma/utils.c
··· 320 320 case NETDEV_DOWN: 321 321 iwdev->iw_status = 0; 322 322 fallthrough; 323 - case NETDEV_UP: 324 - irdma_port_ibevent(iwdev); 325 - break; 326 323 default: 327 324 break; 328 325 } ··· 966 969 ret = del_timer(&iwqp->terminate_timer); 967 970 if (ret) 968 971 irdma_qp_rem_ref(&iwqp->ibqp); 969 - } 970 - 971 - /** 972 - * irdma_cqp_query_fpm_val_cmd - send cqp command for fpm 973 - * @dev: function device struct 974 - * @val_mem: buffer for fpm 975 - * @hmc_fn_id: function id for fpm 976 - */ 977 - int irdma_cqp_query_fpm_val_cmd(struct irdma_sc_dev *dev, 978 - struct irdma_dma_mem *val_mem, u8 hmc_fn_id) 979 - { 980 - struct irdma_cqp_request *cqp_request; 981 - struct cqp_cmds_info *cqp_info; 982 - struct irdma_pci_f *rf = dev_to_rf(dev); 983 - int status; 984 - 985 - cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true); 986 - if (!cqp_request) 987 - return -ENOMEM; 988 - 989 - cqp_info = &cqp_request->info; 990 - cqp_request->param = NULL; 991 - cqp_info->in.u.query_fpm_val.cqp = dev->cqp; 992 - cqp_info->in.u.query_fpm_val.fpm_val_pa = val_mem->pa; 993 - cqp_info->in.u.query_fpm_val.fpm_val_va = val_mem->va; 994 - cqp_info->in.u.query_fpm_val.hmc_fn_id = hmc_fn_id; 995 - cqp_info->cqp_cmd = IRDMA_OP_QUERY_FPM_VAL; 996 - cqp_info->post_sq = 1; 997 - cqp_info->in.u.query_fpm_val.scratch = (uintptr_t)cqp_request; 998 - 999 - status = irdma_handle_cqp_op(rf, cqp_request); 1000 - irdma_put_cqp_request(&rf->cqp, cqp_request); 1001 - 1002 - return status; 1003 - } 1004 - 1005 - /** 1006 - * irdma_cqp_commit_fpm_val_cmd - commit fpm values in hw 1007 - * @dev: hardware control device structure 1008 - * @val_mem: buffer with fpm values 1009 - * @hmc_fn_id: function id for fpm 1010 - */ 1011 - int irdma_cqp_commit_fpm_val_cmd(struct irdma_sc_dev *dev, 1012 - struct irdma_dma_mem *val_mem, u8 hmc_fn_id) 1013 - { 1014 - struct irdma_cqp_request *cqp_request; 1015 - struct cqp_cmds_info *cqp_info; 1016 - struct irdma_pci_f *rf = dev_to_rf(dev); 1017 - int status; 1018 - 1019 - cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true); 1020 - if (!cqp_request) 1021 - return -ENOMEM; 1022 - 1023 - cqp_info = &cqp_request->info; 1024 - cqp_request->param = NULL; 1025 - cqp_info->in.u.commit_fpm_val.cqp = dev->cqp; 1026 - cqp_info->in.u.commit_fpm_val.fpm_val_pa = val_mem->pa; 1027 - cqp_info->in.u.commit_fpm_val.fpm_val_va = val_mem->va; 1028 - cqp_info->in.u.commit_fpm_val.hmc_fn_id = hmc_fn_id; 1029 - cqp_info->cqp_cmd = IRDMA_OP_COMMIT_FPM_VAL; 1030 - cqp_info->post_sq = 1; 1031 - cqp_info->in.u.commit_fpm_val.scratch = (uintptr_t)cqp_request; 1032 - 1033 - status = irdma_handle_cqp_op(rf, cqp_request); 1034 - irdma_put_cqp_request(&rf->cqp, cqp_request); 1035 - 1036 - return status; 1037 972 } 1038 973 1039 974 /**
+5 -1
drivers/infiniband/hw/mlx4/cq.c
··· 150 150 return PTR_ERR(*umem); 151 151 152 152 shift = mlx4_ib_umem_calc_optimal_mtt_size(*umem, 0, &n); 153 - err = mlx4_mtt_init(dev->dev, n, shift, &buf->mtt); 153 + if (shift < 0) { 154 + err = shift; 155 + goto err_buf; 156 + } 154 157 158 + err = mlx4_mtt_init(dev->dev, n, shift, &buf->mtt); 155 159 if (err) 156 160 goto err_buf; 157 161
+34 -32
drivers/infiniband/hw/mlx4/main.c
··· 351 351 struct mlx4_port_gid_table *port_gid_table; 352 352 int ret = 0; 353 353 int hw_update = 0; 354 - struct gid_entry *gids; 354 + struct gid_entry *gids = NULL; 355 355 356 356 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num)) 357 357 return -EINVAL; ··· 389 389 } 390 390 spin_unlock_bh(&iboe->lock); 391 391 392 - if (!ret && hw_update) { 392 + if (gids) 393 393 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num); 394 - kfree(gids); 395 - } 394 + 395 + kfree(gids); 396 396 return ret; 397 397 } 398 398 ··· 2341 2341 2342 2342 iboe->netdevs[dev->dev_port] = event != NETDEV_UNREGISTER ? dev : NULL; 2343 2343 2344 - if (event == NETDEV_UP || event == NETDEV_DOWN) { 2345 - enum ib_port_state port_state; 2346 - struct ib_event ibev = { }; 2347 - 2348 - if (ib_get_cached_port_state(&ibdev->ib_dev, dev->dev_port + 1, 2349 - &port_state)) 2350 - goto iboe_out; 2351 - 2352 - if (event == NETDEV_UP && 2353 - (port_state != IB_PORT_ACTIVE || 2354 - iboe->last_port_state[dev->dev_port] != IB_PORT_DOWN)) 2355 - goto iboe_out; 2356 - if (event == NETDEV_DOWN && 2357 - (port_state != IB_PORT_DOWN || 2358 - iboe->last_port_state[dev->dev_port] != IB_PORT_ACTIVE)) 2359 - goto iboe_out; 2360 - iboe->last_port_state[dev->dev_port] = port_state; 2361 - 2362 - ibev.device = &ibdev->ib_dev; 2363 - ibev.element.port_num = dev->dev_port + 1; 2364 - ibev.event = event == NETDEV_UP ? IB_EVENT_PORT_ACTIVE : 2365 - IB_EVENT_PORT_ERR; 2366 - ib_dispatch_event(&ibev); 2367 - } 2368 - 2369 - iboe_out: 2370 2344 spin_unlock_bh(&iboe->lock); 2371 2345 2372 - if (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER || 2373 - event == NETDEV_UP || event == NETDEV_CHANGE) 2346 + if (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER) 2374 2347 mlx4_ib_update_qps(ibdev, dev, dev->dev_port + 1); 2348 + } 2349 + 2350 + static void mlx4_ib_port_event(struct ib_device *ibdev, struct net_device *ndev, 2351 + unsigned long event) 2352 + { 2353 + struct mlx4_ib_dev *mlx4_ibdev = 2354 + container_of(ibdev, struct mlx4_ib_dev, ib_dev); 2355 + struct mlx4_ib_iboe *iboe = &mlx4_ibdev->iboe; 2356 + 2357 + if (!net_eq(dev_net(ndev), &init_net)) 2358 + return; 2359 + 2360 + ASSERT_RTNL(); 2361 + 2362 + if (ndev->dev.parent != mlx4_ibdev->ib_dev.dev.parent) 2363 + return; 2364 + 2365 + spin_lock_bh(&iboe->lock); 2366 + 2367 + iboe->netdevs[ndev->dev_port] = event != NETDEV_UNREGISTER ? ndev : NULL; 2368 + 2369 + if (event == NETDEV_UP || event == NETDEV_DOWN) 2370 + ib_dispatch_port_state_event(&mlx4_ibdev->ib_dev, ndev); 2371 + 2372 + spin_unlock_bh(&iboe->lock); 2373 + 2374 + if (event == NETDEV_UP || event == NETDEV_CHANGE) 2375 + mlx4_ib_update_qps(mlx4_ibdev, ndev, ndev->dev_port + 1); 2375 2376 } 2376 2377 2377 2378 static int mlx4_ib_netdev_event(struct notifier_block *this, ··· 2570 2569 .req_notify_cq = mlx4_ib_arm_cq, 2571 2570 .rereg_user_mr = mlx4_ib_rereg_user_mr, 2572 2571 .resize_cq = mlx4_ib_resize_cq, 2572 + .report_port_event = mlx4_ib_port_event, 2573 2573 2574 2574 INIT_RDMA_OBJ_SIZE(ib_ah, mlx4_ib_ah, ibah), 2575 2575 INIT_RDMA_OBJ_SIZE(ib_cq, mlx4_ib_cq, ibcq),
+16 -2
drivers/infiniband/hw/mlx4/mlx4_ib.h
··· 667 667 __u32 reserved; 668 668 }; 669 669 670 + /* 4k - 4G */ 671 + #define MLX4_PAGE_SIZE_SUPPORTED ((unsigned long)GENMASK_ULL(31, 12)) 672 + 670 673 static inline struct mlx4_ib_dev *to_mdev(struct ib_device *ibdev) 671 674 { 672 675 return container_of(ibdev, struct mlx4_ib_dev, ib_dev); ··· 939 936 { 940 937 return 0; 941 938 } 942 - int mlx4_ib_umem_calc_optimal_mtt_size(struct ib_umem *umem, u64 start_va, 943 - int *num_of_mtts); 939 + static inline int mlx4_ib_umem_calc_optimal_mtt_size(struct ib_umem *umem, 940 + u64 start, 941 + int *num_of_mtts) 942 + { 943 + unsigned long pg_sz; 944 + 945 + pg_sz = ib_umem_find_best_pgsz(umem, MLX4_PAGE_SIZE_SUPPORTED, start); 946 + if (!pg_sz) 947 + return -EOPNOTSUPP; 948 + 949 + *num_of_mtts = ib_umem_num_dma_blocks(umem, pg_sz); 950 + return order_base_2(pg_sz); 951 + } 944 952 945 953 int mlx4_ib_cm_init(void); 946 954 void mlx4_ib_cm_destroy(void);
+12 -274
drivers/infiniband/hw/mlx4/mr.c
··· 87 87 return ERR_PTR(err); 88 88 } 89 89 90 - enum { 91 - MLX4_MAX_MTT_SHIFT = 31 92 - }; 93 - 94 - static int mlx4_ib_umem_write_mtt_block(struct mlx4_ib_dev *dev, 95 - struct mlx4_mtt *mtt, 96 - u64 mtt_size, u64 mtt_shift, u64 len, 97 - u64 cur_start_addr, u64 *pages, 98 - int *start_index, int *npages) 99 - { 100 - u64 cur_end_addr = cur_start_addr + len; 101 - u64 cur_end_addr_aligned = 0; 102 - u64 mtt_entries; 103 - int err = 0; 104 - int k; 105 - 106 - len += (cur_start_addr & (mtt_size - 1ULL)); 107 - cur_end_addr_aligned = round_up(cur_end_addr, mtt_size); 108 - len += (cur_end_addr_aligned - cur_end_addr); 109 - if (len & (mtt_size - 1ULL)) { 110 - pr_warn("write_block: len %llx is not aligned to mtt_size %llx\n", 111 - len, mtt_size); 112 - return -EINVAL; 113 - } 114 - 115 - mtt_entries = (len >> mtt_shift); 116 - 117 - /* 118 - * Align the MTT start address to the mtt_size. 119 - * Required to handle cases when the MR starts in the middle of an MTT 120 - * record. Was not required in old code since the physical addresses 121 - * provided by the dma subsystem were page aligned, which was also the 122 - * MTT size. 123 - */ 124 - cur_start_addr = round_down(cur_start_addr, mtt_size); 125 - /* A new block is started ... */ 126 - for (k = 0; k < mtt_entries; ++k) { 127 - pages[*npages] = cur_start_addr + (mtt_size * k); 128 - (*npages)++; 129 - /* 130 - * Be friendly to mlx4_write_mtt() and pass it chunks of 131 - * appropriate size. 132 - */ 133 - if (*npages == PAGE_SIZE / sizeof(u64)) { 134 - err = mlx4_write_mtt(dev->dev, mtt, *start_index, 135 - *npages, pages); 136 - if (err) 137 - return err; 138 - 139 - (*start_index) += *npages; 140 - *npages = 0; 141 - } 142 - } 143 - 144 - return 0; 145 - } 146 - 147 - static inline u64 alignment_of(u64 ptr) 148 - { 149 - return ilog2(ptr & (~(ptr - 1))); 150 - } 151 - 152 - static int mlx4_ib_umem_calc_block_mtt(u64 next_block_start, 153 - u64 current_block_end, 154 - u64 block_shift) 155 - { 156 - /* Check whether the alignment of the new block is aligned as well as 157 - * the previous block. 158 - * Block address must start with zeros till size of entity_size. 159 - */ 160 - if ((next_block_start & ((1ULL << block_shift) - 1ULL)) != 0) 161 - /* 162 - * It is not as well aligned as the previous block-reduce the 163 - * mtt size accordingly. Here we take the last right bit which 164 - * is 1. 165 - */ 166 - block_shift = alignment_of(next_block_start); 167 - 168 - /* 169 - * Check whether the alignment of the end of previous block - is it 170 - * aligned as well as the start of the block 171 - */ 172 - if (((current_block_end) & ((1ULL << block_shift) - 1ULL)) != 0) 173 - /* 174 - * It is not as well aligned as the start of the block - 175 - * reduce the mtt size accordingly. 176 - */ 177 - block_shift = alignment_of(current_block_end); 178 - 179 - return block_shift; 180 - } 181 - 182 90 int mlx4_ib_umem_write_mtt(struct mlx4_ib_dev *dev, struct mlx4_mtt *mtt, 183 91 struct ib_umem *umem) 184 92 { 185 - u64 *pages; 186 - u64 len = 0; 187 - int err = 0; 188 - u64 mtt_size; 189 - u64 cur_start_addr = 0; 190 - u64 mtt_shift; 191 - int start_index = 0; 192 - int npages = 0; 193 - struct scatterlist *sg; 194 - int i; 93 + struct ib_block_iter biter; 94 + int err, i = 0; 95 + u64 addr; 195 96 196 - pages = (u64 *) __get_free_page(GFP_KERNEL); 197 - if (!pages) 198 - return -ENOMEM; 199 - 200 - mtt_shift = mtt->page_shift; 201 - mtt_size = 1ULL << mtt_shift; 202 - 203 - for_each_sgtable_dma_sg(&umem->sgt_append.sgt, sg, i) { 204 - if (cur_start_addr + len == sg_dma_address(sg)) { 205 - /* still the same block */ 206 - len += sg_dma_len(sg); 207 - continue; 208 - } 209 - /* 210 - * A new block is started ... 211 - * If len is malaligned, write an extra mtt entry to cover the 212 - * misaligned area (round up the division) 213 - */ 214 - err = mlx4_ib_umem_write_mtt_block(dev, mtt, mtt_size, 215 - mtt_shift, len, 216 - cur_start_addr, 217 - pages, &start_index, 218 - &npages); 97 + rdma_umem_for_each_dma_block(umem, &biter, BIT(mtt->page_shift)) { 98 + addr = rdma_block_iter_dma_address(&biter); 99 + err = mlx4_write_mtt(dev->dev, mtt, i++, 1, &addr); 219 100 if (err) 220 - goto out; 221 - 222 - cur_start_addr = sg_dma_address(sg); 223 - len = sg_dma_len(sg); 101 + return err; 224 102 } 225 - 226 - /* Handle the last block */ 227 - if (len > 0) { 228 - /* 229 - * If len is malaligned, write an extra mtt entry to cover 230 - * the misaligned area (round up the division) 231 - */ 232 - err = mlx4_ib_umem_write_mtt_block(dev, mtt, mtt_size, 233 - mtt_shift, len, 234 - cur_start_addr, pages, 235 - &start_index, &npages); 236 - if (err) 237 - goto out; 238 - } 239 - 240 - if (npages) 241 - err = mlx4_write_mtt(dev->dev, mtt, start_index, npages, pages); 242 - 243 - out: 244 - free_page((unsigned long) pages); 245 - return err; 246 - } 247 - 248 - /* 249 - * Calculate optimal mtt size based on contiguous pages. 250 - * Function will return also the number of pages that are not aligned to the 251 - * calculated mtt_size to be added to total number of pages. For that we should 252 - * check the first chunk length & last chunk length and if not aligned to 253 - * mtt_size we should increment the non_aligned_pages number. All chunks in the 254 - * middle already handled as part of mtt shift calculation for both their start 255 - * & end addresses. 256 - */ 257 - int mlx4_ib_umem_calc_optimal_mtt_size(struct ib_umem *umem, u64 start_va, 258 - int *num_of_mtts) 259 - { 260 - u64 block_shift = MLX4_MAX_MTT_SHIFT; 261 - u64 min_shift = PAGE_SHIFT; 262 - u64 last_block_aligned_end = 0; 263 - u64 current_block_start = 0; 264 - u64 first_block_start = 0; 265 - u64 current_block_len = 0; 266 - u64 last_block_end = 0; 267 - struct scatterlist *sg; 268 - u64 current_block_end; 269 - u64 misalignment_bits; 270 - u64 next_block_start; 271 - u64 total_len = 0; 272 - int i; 273 - 274 - *num_of_mtts = ib_umem_num_dma_blocks(umem, PAGE_SIZE); 275 - 276 - for_each_sgtable_dma_sg(&umem->sgt_append.sgt, sg, i) { 277 - /* 278 - * Initialization - save the first chunk start as the 279 - * current_block_start - block means contiguous pages. 280 - */ 281 - if (current_block_len == 0 && current_block_start == 0) { 282 - current_block_start = sg_dma_address(sg); 283 - first_block_start = current_block_start; 284 - /* 285 - * Find the bits that are different between the physical 286 - * address and the virtual address for the start of the 287 - * MR. 288 - * umem_get aligned the start_va to a page boundary. 289 - * Therefore, we need to align the start va to the same 290 - * boundary. 291 - * misalignment_bits is needed to handle the case of a 292 - * single memory region. In this case, the rest of the 293 - * logic will not reduce the block size. If we use a 294 - * block size which is bigger than the alignment of the 295 - * misalignment bits, we might use the virtual page 296 - * number instead of the physical page number, resulting 297 - * in access to the wrong data. 298 - */ 299 - misalignment_bits = 300 - (start_va & (~(((u64)(PAGE_SIZE)) - 1ULL))) ^ 301 - current_block_start; 302 - block_shift = min(alignment_of(misalignment_bits), 303 - block_shift); 304 - } 305 - 306 - /* 307 - * Go over the scatter entries and check if they continue the 308 - * previous scatter entry. 309 - */ 310 - next_block_start = sg_dma_address(sg); 311 - current_block_end = current_block_start + current_block_len; 312 - /* If we have a split (non-contig.) between two blocks */ 313 - if (current_block_end != next_block_start) { 314 - block_shift = mlx4_ib_umem_calc_block_mtt 315 - (next_block_start, 316 - current_block_end, 317 - block_shift); 318 - 319 - /* 320 - * If we reached the minimum shift for 4k page we stop 321 - * the loop. 322 - */ 323 - if (block_shift <= min_shift) 324 - goto end; 325 - 326 - /* 327 - * If not saved yet we are in first block - we save the 328 - * length of first block to calculate the 329 - * non_aligned_pages number at the end. 330 - */ 331 - total_len += current_block_len; 332 - 333 - /* Start a new block */ 334 - current_block_start = next_block_start; 335 - current_block_len = sg_dma_len(sg); 336 - continue; 337 - } 338 - /* The scatter entry is another part of the current block, 339 - * increase the block size. 340 - * An entry in the scatter can be larger than 4k (page) as of 341 - * dma mapping which merge some blocks together. 342 - */ 343 - current_block_len += sg_dma_len(sg); 344 - } 345 - 346 - /* Account for the last block in the total len */ 347 - total_len += current_block_len; 348 - /* Add to the first block the misalignment that it suffers from. */ 349 - total_len += (first_block_start & ((1ULL << block_shift) - 1ULL)); 350 - last_block_end = current_block_start + current_block_len; 351 - last_block_aligned_end = round_up(last_block_end, 1ULL << block_shift); 352 - total_len += (last_block_aligned_end - last_block_end); 353 - 354 - if (total_len & ((1ULL << block_shift) - 1ULL)) 355 - pr_warn("misaligned total length detected (%llu, %llu)!", 356 - total_len, block_shift); 357 - 358 - *num_of_mtts = total_len >> block_shift; 359 - end: 360 - if (block_shift < min_shift) { 361 - /* 362 - * If shift is less than the min we set a warning and return the 363 - * min shift. 364 - */ 365 - pr_warn("umem_calc_optimal_mtt_size - unexpected shift %lld\n", block_shift); 366 - 367 - block_shift = min_shift; 368 - } 369 - return block_shift; 103 + return 0; 370 104 } 371 105 372 106 static struct ib_umem *mlx4_get_umem_mr(struct ib_device *device, u64 start, ··· 158 424 } 159 425 160 426 shift = mlx4_ib_umem_calc_optimal_mtt_size(mr->umem, start, &n); 427 + if (shift < 0) { 428 + err = shift; 429 + goto err_umem; 430 + } 161 431 162 432 err = mlx4_mr_alloc(dev->dev, to_mpd(pd)->pdn, virt_addr, length, 163 433 convert_access(access_flags), n, shift, &mr->mmr);
+10 -2
drivers/infiniband/hw/mlx4/qp.c
··· 925 925 } 926 926 927 927 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n); 928 - err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt); 928 + if (shift < 0) { 929 + err = shift; 930 + goto err_buf; 931 + } 929 932 933 + err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt); 930 934 if (err) 931 935 goto err_buf; 932 936 ··· 1112 1108 } 1113 1109 1114 1110 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n); 1115 - err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt); 1111 + if (shift < 0) { 1112 + err = shift; 1113 + goto err_buf; 1114 + } 1116 1115 1116 + err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt); 1117 1117 if (err) 1118 1118 goto err_buf; 1119 1119
+4
drivers/infiniband/hw/mlx5/main.c
··· 242 242 case NETDEV_DOWN: { 243 243 struct net_device *upper = NULL; 244 244 245 + if (!netif_is_lag_master(ndev) && !netif_is_lag_port(ndev) && 246 + !mlx5_core_mp_enabled(mdev)) 247 + return NOTIFY_DONE; 248 + 245 249 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 246 250 struct net_device *lag_ndev; 247 251
+6
drivers/infiniband/hw/mlx5/mlx5_ib.h
··· 669 669 #define mlx5_update_odp_stats(mr, counter_name, value) \ 670 670 atomic64_add(value, &((mr)->odp_stats.counter_name)) 671 671 672 + #define mlx5_update_odp_stats_with_handled(mr, counter_name, value) \ 673 + do { \ 674 + mlx5_update_odp_stats(mr, counter_name, value); \ 675 + atomic64_add(1, &((mr)->odp_stats.counter_name##_handled)); \ 676 + } while (0) 677 + 672 678 struct mlx5_ib_mr { 673 679 struct ib_mr ibmr; 674 680 struct mlx5_ib_mkey mmkey;
+15 -2
drivers/infiniband/hw/mlx5/mr.c
··· 2021 2021 { 2022 2022 struct mlx5_ib_dev *dev = to_mdev(mr->ibmr.device); 2023 2023 struct mlx5_cache_ent *ent = mr->mmkey.cache_ent; 2024 + bool is_odp = is_odp_mr(mr); 2025 + int ret = 0; 2026 + 2027 + if (is_odp) 2028 + mutex_lock(&to_ib_umem_odp(mr->umem)->umem_mutex); 2024 2029 2025 2030 if (mr->mmkey.cacheable && !mlx5r_umr_revoke_mr(mr) && !cache_ent_find_and_store(dev, mr)) { 2026 2031 ent = mr->mmkey.cache_ent; ··· 2037 2032 ent->tmp_cleanup_scheduled = true; 2038 2033 } 2039 2034 spin_unlock_irq(&ent->mkeys_queue.lock); 2040 - return 0; 2035 + goto out; 2041 2036 } 2042 2037 2043 2038 if (ent) { ··· 2046 2041 mr->mmkey.cache_ent = NULL; 2047 2042 spin_unlock_irq(&ent->mkeys_queue.lock); 2048 2043 } 2049 - return destroy_mkey(dev, mr); 2044 + ret = destroy_mkey(dev, mr); 2045 + out: 2046 + if (is_odp) { 2047 + if (!ret) 2048 + to_ib_umem_odp(mr->umem)->private = NULL; 2049 + mutex_unlock(&to_ib_umem_odp(mr->umem)->umem_mutex); 2050 + } 2051 + 2052 + return ret; 2050 2053 } 2051 2054 2052 2055 static int __mlx5_ib_dereg_mr(struct ib_mr *ibmr)
+42 -28
drivers/infiniband/hw/mlx5/odp.c
··· 228 228 unsigned long idx = ib_umem_start(odp) >> MLX5_IMR_MTT_SHIFT; 229 229 struct mlx5_ib_mr *imr = mr->parent; 230 230 231 + /* 232 + * If userspace is racing freeing the parent implicit ODP MR then we can 233 + * loose the race with parent destruction. In this case 234 + * mlx5_ib_free_odp_mr() will free everything in the implicit_children 235 + * xarray so NOP is fine. This child MR cannot be destroyed here because 236 + * we are under its umem_mutex. 237 + */ 231 238 if (!refcount_inc_not_zero(&imr->mmkey.usecount)) 232 239 return; 233 240 234 - xa_erase(&imr->implicit_children, idx); 241 + xa_lock(&imr->implicit_children); 242 + if (__xa_cmpxchg(&imr->implicit_children, idx, mr, NULL, GFP_KERNEL) != 243 + mr) { 244 + xa_unlock(&imr->implicit_children); 245 + return; 246 + } 247 + 235 248 if (MLX5_CAP_ODP(mr_to_mdev(mr)->mdev, mem_page_fault)) 236 - xa_erase(&mr_to_mdev(mr)->odp_mkeys, 237 - mlx5_base_mkey(mr->mmkey.key)); 249 + __xa_erase(&mr_to_mdev(mr)->odp_mkeys, 250 + mlx5_base_mkey(mr->mmkey.key)); 251 + xa_unlock(&imr->implicit_children); 238 252 239 253 /* Freeing a MR is a sleeping operation, so bounce to a work queue */ 240 254 INIT_WORK(&mr->odp_destroy.work, free_implicit_child_mr_work); ··· 282 268 if (!umem_odp->npages) 283 269 goto out; 284 270 mr = umem_odp->private; 271 + if (!mr) 272 + goto out; 285 273 286 274 start = max_t(u64, ib_umem_start(umem_odp), range->start); 287 275 end = min_t(u64, ib_umem_end(umem_odp), range->end); ··· 329 313 MLX5_IB_UPD_XLT_ZAP | 330 314 MLX5_IB_UPD_XLT_ATOMIC); 331 315 332 - mlx5_update_odp_stats(mr, invalidations, invalidations); 316 + mlx5_update_odp_stats_with_handled(mr, invalidations, invalidations); 333 317 334 318 /* 335 319 * We are now sure that the device will not access the ··· 516 500 refcount_inc(&ret->mmkey.usecount); 517 501 goto out_lock; 518 502 } 519 - xa_unlock(&imr->implicit_children); 520 503 521 504 if (MLX5_CAP_ODP(dev->mdev, mem_page_fault)) { 522 - ret = xa_store(&dev->odp_mkeys, mlx5_base_mkey(mr->mmkey.key), 523 - &mr->mmkey, GFP_KERNEL); 505 + ret = __xa_store(&dev->odp_mkeys, mlx5_base_mkey(mr->mmkey.key), 506 + &mr->mmkey, GFP_KERNEL); 524 507 if (xa_is_err(ret)) { 525 508 ret = ERR_PTR(xa_err(ret)); 526 - xa_erase(&imr->implicit_children, idx); 527 - goto out_mr; 509 + __xa_erase(&imr->implicit_children, idx); 510 + goto out_lock; 528 511 } 529 512 mr->mmkey.type = MLX5_MKEY_IMPLICIT_CHILD; 530 513 } 514 + xa_unlock(&imr->implicit_children); 531 515 mlx5_ib_dbg(mr_to_mdev(imr), "key %x mr %p\n", mr->mmkey.key, mr); 532 516 return mr; 533 517 ··· 960 944 /* 961 945 * Handle a single data segment in a page-fault WQE or RDMA region. 962 946 * 963 - * Returns number of OS pages retrieved on success. The caller may continue to 964 - * the next data segment. 947 + * Returns zero on success. The caller may continue to the next data segment. 965 948 * Can return the following error codes: 966 949 * -EAGAIN to designate a temporary error. The caller will abort handling the 967 950 * page fault and resolve it. ··· 973 958 u32 *bytes_committed, 974 959 u32 *bytes_mapped) 975 960 { 976 - int npages = 0, ret, i, outlen, cur_outlen = 0, depth = 0; 961 + int ret, i, outlen, cur_outlen = 0, depth = 0, pages_in_range; 977 962 struct pf_frame *head = NULL, *frame; 978 963 struct mlx5_ib_mkey *mmkey; 979 964 struct mlx5_ib_mr *mr; ··· 1008 993 case MLX5_MKEY_MR: 1009 994 mr = container_of(mmkey, struct mlx5_ib_mr, mmkey); 1010 995 996 + pages_in_range = (ALIGN(io_virt + bcnt, PAGE_SIZE) - 997 + (io_virt & PAGE_MASK)) >> 998 + PAGE_SHIFT; 1011 999 ret = pagefault_mr(mr, io_virt, bcnt, bytes_mapped, 0, false); 1012 1000 if (ret < 0) 1013 1001 goto end; 1014 1002 1015 - mlx5_update_odp_stats(mr, faults, ret); 1003 + mlx5_update_odp_stats_with_handled(mr, faults, ret); 1016 1004 1017 - npages += ret; 1005 + if (ret < pages_in_range) { 1006 + ret = -EFAULT; 1007 + goto end; 1008 + } 1009 + 1018 1010 ret = 0; 1019 1011 break; 1020 1012 ··· 1112 1090 kfree(out); 1113 1091 1114 1092 *bytes_committed = 0; 1115 - return ret ? ret : npages; 1093 + return ret; 1116 1094 } 1117 1095 1118 1096 /* ··· 1131 1109 * the committed bytes). 1132 1110 * @receive_queue: receive WQE end of sg list 1133 1111 * 1134 - * Returns the number of pages loaded if positive, zero for an empty WQE, or a 1135 - * negative error code. 1112 + * Returns zero for success or a negative error code. 1136 1113 */ 1137 1114 static int pagefault_data_segments(struct mlx5_ib_dev *dev, 1138 1115 struct mlx5_pagefault *pfault, ··· 1139 1118 void *wqe_end, u32 *bytes_mapped, 1140 1119 u32 *total_wqe_bytes, bool receive_queue) 1141 1120 { 1142 - int ret = 0, npages = 0; 1121 + int ret = 0; 1143 1122 u64 io_virt; 1144 1123 __be32 key; 1145 1124 u32 byte_count; ··· 1196 1175 bytes_mapped); 1197 1176 if (ret < 0) 1198 1177 break; 1199 - npages += ret; 1200 1178 } 1201 1179 1202 - return ret < 0 ? ret : npages; 1180 + return ret; 1203 1181 } 1204 1182 1205 1183 /* ··· 1434 1414 free_page((unsigned long)wqe_start); 1435 1415 } 1436 1416 1437 - static int pages_in_range(u64 address, u32 length) 1438 - { 1439 - return (ALIGN(address + length, PAGE_SIZE) - 1440 - (address & PAGE_MASK)) >> PAGE_SHIFT; 1441 - } 1442 - 1443 1417 static void mlx5_ib_mr_rdma_pfault_handler(struct mlx5_ib_dev *dev, 1444 1418 struct mlx5_pagefault *pfault) 1445 1419 { ··· 1472 1458 if (ret == -EAGAIN) { 1473 1459 /* We're racing with an invalidation, don't prefetch */ 1474 1460 prefetch_activated = 0; 1475 - } else if (ret < 0 || pages_in_range(address, length) > ret) { 1461 + } else if (ret < 0) { 1476 1462 mlx5_ib_page_fault_resume(dev, pfault, 1); 1477 1463 if (ret != -ENOENT) 1478 1464 mlx5_ib_dbg(dev, "PAGE FAULT error %d. QP 0x%llx, type: 0x%x\n", ··· 1543 1529 goto err; 1544 1530 } 1545 1531 1546 - mlx5_update_odp_stats(mr, faults, ret); 1532 + mlx5_update_odp_stats_with_handled(mr, faults, ret); 1547 1533 mlx5r_deref_odp_mkey(mmkey); 1548 1534 1549 1535 if (pfault->memory.flags & MLX5_MEMORY_PAGE_FAULT_FLAGS_LAST)
+9
drivers/infiniband/hw/mlx5/restrack.c
··· 96 96 atomic64_read(&mr->odp_stats.faults))) 97 97 goto err_table; 98 98 if (rdma_nl_stat_hwcounter_entry( 99 + msg, "page_faults_handled", 100 + atomic64_read(&mr->odp_stats.faults_handled))) 101 + goto err_table; 102 + if (rdma_nl_stat_hwcounter_entry( 99 103 msg, "page_invalidations", 100 104 atomic64_read(&mr->odp_stats.invalidations))) 101 105 goto err_table; 106 + if (rdma_nl_stat_hwcounter_entry( 107 + msg, "page_invalidations_handled", 108 + atomic64_read(&mr->odp_stats.invalidations_handled))) 109 + goto err_table; 110 + 102 111 if (rdma_nl_stat_hwcounter_entry(msg, "page_prefetch", 103 112 atomic64_read(&mr->odp_stats.prefetch))) 104 113 goto err_table;
+8 -8
drivers/infiniband/hw/qib/qib_sysfs.c
··· 214 214 * Congestion control table size followed by table entries 215 215 */ 216 216 static ssize_t cc_table_bin_read(struct file *filp, struct kobject *kobj, 217 - struct bin_attribute *bin_attr, char *buf, 218 - loff_t pos, size_t count) 217 + const struct bin_attribute *bin_attr, 218 + char *buf, loff_t pos, size_t count) 219 219 { 220 220 struct qib_pportdata *ppd = qib_get_pportdata_kobj(kobj); 221 221 int ret; ··· 241 241 242 242 return count; 243 243 } 244 - static BIN_ATTR_RO(cc_table_bin, PAGE_SIZE); 244 + static const BIN_ATTR_RO(cc_table_bin, PAGE_SIZE); 245 245 246 246 /* 247 247 * Congestion settings: port control, control map and an array of 16 ··· 249 249 * trigger threshold and the minimum injection rate delay. 250 250 */ 251 251 static ssize_t cc_setting_bin_read(struct file *filp, struct kobject *kobj, 252 - struct bin_attribute *bin_attr, char *buf, 253 - loff_t pos, size_t count) 252 + const struct bin_attribute *bin_attr, 253 + char *buf, loff_t pos, size_t count) 254 254 { 255 255 struct qib_pportdata *ppd = qib_get_pportdata_kobj(kobj); 256 256 int ret; ··· 274 274 275 275 return count; 276 276 } 277 - static BIN_ATTR_RO(cc_setting_bin, PAGE_SIZE); 277 + static const BIN_ATTR_RO(cc_setting_bin, PAGE_SIZE); 278 278 279 - static struct bin_attribute *port_ccmgta_attributes[] = { 279 + static const struct bin_attribute *const port_ccmgta_attributes[] = { 280 280 &bin_attr_cc_setting_bin, 281 281 &bin_attr_cc_table_bin, 282 282 NULL, ··· 295 295 static const struct attribute_group port_ccmgta_attribute_group = { 296 296 .name = "CCMgtA", 297 297 .is_bin_visible = qib_ccmgta_is_bin_visible, 298 - .bin_attrs = port_ccmgta_attributes, 298 + .bin_attrs_new = port_ccmgta_attributes, 299 299 }; 300 300 301 301 /* Start sl2vl */
+45 -28
drivers/infiniband/hw/usnic/usnic_ib_main.c
··· 151 151 ib_event.element.port_num = 1; 152 152 ib_dispatch_event(&ib_event); 153 153 break; 154 - case NETDEV_UP: 155 - case NETDEV_DOWN: 156 - case NETDEV_CHANGE: 157 - if (!us_ibdev->ufdev->link_up && 158 - netif_carrier_ok(netdev)) { 159 - usnic_fwd_carrier_up(us_ibdev->ufdev); 160 - usnic_info("Link UP on %s\n", 161 - dev_name(&us_ibdev->ib_dev.dev)); 162 - ib_event.event = IB_EVENT_PORT_ACTIVE; 163 - ib_event.device = &us_ibdev->ib_dev; 164 - ib_event.element.port_num = 1; 165 - ib_dispatch_event(&ib_event); 166 - } else if (us_ibdev->ufdev->link_up && 167 - !netif_carrier_ok(netdev)) { 168 - usnic_fwd_carrier_down(us_ibdev->ufdev); 169 - usnic_info("Link DOWN on %s\n", 170 - dev_name(&us_ibdev->ib_dev.dev)); 171 - usnic_ib_qp_grp_modify_active_to_err(us_ibdev); 172 - ib_event.event = IB_EVENT_PORT_ERR; 173 - ib_event.device = &us_ibdev->ib_dev; 174 - ib_event.element.port_num = 1; 175 - ib_dispatch_event(&ib_event); 176 - } else { 177 - usnic_dbg("Ignoring %s on %s\n", 178 - netdev_cmd_to_name(event), 179 - dev_name(&us_ibdev->ib_dev.dev)); 180 - } 181 - break; 182 154 case NETDEV_CHANGEADDR: 183 155 if (!memcmp(us_ibdev->ufdev->mac, netdev->dev_addr, 184 156 sizeof(us_ibdev->ufdev->mac))) { ··· 186 214 usnic_dbg("Ignoring event %s on %s", 187 215 netdev_cmd_to_name(event), 188 216 dev_name(&us_ibdev->ib_dev.dev)); 217 + } 218 + mutex_unlock(&us_ibdev->usdev_lock); 219 + } 220 + 221 + static void usnic_ib_handle_port_event(struct ib_device *ibdev, 222 + struct net_device *netdev, 223 + unsigned long event) 224 + { 225 + struct usnic_ib_dev *us_ibdev = 226 + container_of(ibdev, struct usnic_ib_dev, ib_dev); 227 + struct ib_event ib_event; 228 + 229 + mutex_lock(&us_ibdev->usdev_lock); 230 + switch (event) { 231 + case NETDEV_UP: 232 + case NETDEV_DOWN: 233 + case NETDEV_CHANGE: 234 + if (!us_ibdev->ufdev->link_up && 235 + netif_carrier_ok(netdev)) { 236 + usnic_fwd_carrier_up(us_ibdev->ufdev); 237 + usnic_info("Link UP on %s\n", 238 + dev_name(&us_ibdev->ib_dev.dev)); 239 + ib_event.event = IB_EVENT_PORT_ACTIVE; 240 + ib_event.device = &us_ibdev->ib_dev; 241 + ib_event.element.port_num = 1; 242 + ib_dispatch_event(&ib_event); 243 + } else if (us_ibdev->ufdev->link_up && 244 + !netif_carrier_ok(netdev)) { 245 + usnic_fwd_carrier_down(us_ibdev->ufdev); 246 + usnic_info("Link DOWN on %s\n", 247 + dev_name(&us_ibdev->ib_dev.dev)); 248 + usnic_ib_qp_grp_modify_active_to_err(us_ibdev); 249 + ib_event.event = IB_EVENT_PORT_ERR; 250 + ib_event.device = &us_ibdev->ib_dev; 251 + ib_event.element.port_num = 1; 252 + ib_dispatch_event(&ib_event); 253 + } else { 254 + usnic_dbg("Ignoring %s on %s\n", 255 + netdev_cmd_to_name(event), 256 + dev_name(&us_ibdev->ib_dev.dev)); 257 + } 258 + break; 259 + default: 260 + break; 189 261 } 190 262 mutex_unlock(&us_ibdev->usdev_lock); 191 263 } ··· 374 358 .query_port = usnic_ib_query_port, 375 359 .query_qp = usnic_ib_query_qp, 376 360 .reg_user_mr = usnic_ib_reg_mr, 361 + .report_port_event = usnic_ib_handle_port_event, 377 362 INIT_RDMA_OBJ_SIZE(ib_pd, usnic_ib_pd, ibpd), 378 363 INIT_RDMA_OBJ_SIZE(ib_cq, usnic_ib_cq, ibcq), 379 364 INIT_RDMA_OBJ_SIZE(ib_qp, usnic_ib_qp_grp, ibqp),
+41 -25
drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c
··· 143 143 return 0; 144 144 } 145 145 146 + static void pvrdma_dispatch_event(struct pvrdma_dev *dev, int port, 147 + enum ib_event_type event) 148 + { 149 + struct ib_event ib_event; 150 + 151 + memset(&ib_event, 0, sizeof(ib_event)); 152 + ib_event.device = &dev->ib_dev; 153 + ib_event.element.port_num = port; 154 + ib_event.event = event; 155 + ib_dispatch_event(&ib_event); 156 + } 157 + 158 + static void pvrdma_report_event_handle(struct ib_device *ibdev, 159 + struct net_device *ndev, 160 + unsigned long event) 161 + { 162 + struct pvrdma_dev *dev = container_of(ibdev, struct pvrdma_dev, ib_dev); 163 + 164 + switch (event) { 165 + case NETDEV_DOWN: 166 + pvrdma_dispatch_event(dev, 1, IB_EVENT_PORT_ERR); 167 + break; 168 + case NETDEV_UP: 169 + pvrdma_write_reg(dev, PVRDMA_REG_CTL, 170 + PVRDMA_DEVICE_CTL_UNQUIESCE); 171 + 172 + mb(); 173 + 174 + if (pvrdma_read_reg(dev, PVRDMA_REG_ERR)) 175 + dev_err(&dev->pdev->dev, 176 + "failed to activate device during link up\n"); 177 + else 178 + pvrdma_dispatch_event(dev, 1, IB_EVENT_PORT_ACTIVE); 179 + break; 180 + 181 + default: 182 + break; 183 + } 184 + } 185 + 146 186 static const struct ib_device_ops pvrdma_dev_ops = { 147 187 .owner = THIS_MODULE, 148 188 .driver_id = RDMA_DRIVER_VMW_PVRDMA, ··· 221 181 .query_qp = pvrdma_query_qp, 222 182 .reg_user_mr = pvrdma_reg_user_mr, 223 183 .req_notify_cq = pvrdma_req_notify_cq, 184 + .report_port_event = pvrdma_report_event_handle, 224 185 225 186 INIT_RDMA_OBJ_SIZE(ib_ah, pvrdma_ah, ibah), 226 187 INIT_RDMA_OBJ_SIZE(ib_cq, pvrdma_cq, ibcq), ··· 401 360 if (refcount_dec_and_test(&srq->refcnt)) 402 361 complete(&srq->free); 403 362 } 404 - } 405 - 406 - static void pvrdma_dispatch_event(struct pvrdma_dev *dev, int port, 407 - enum ib_event_type event) 408 - { 409 - struct ib_event ib_event; 410 - 411 - memset(&ib_event, 0, sizeof(ib_event)); 412 - ib_event.device = &dev->ib_dev; 413 - ib_event.element.port_num = port; 414 - ib_event.event = event; 415 - ib_dispatch_event(&ib_event); 416 363 } 417 364 418 365 static void pvrdma_dev_event(struct pvrdma_dev *dev, u8 port, int type) ··· 695 666 696 667 switch (event) { 697 668 case NETDEV_REBOOT: 698 - case NETDEV_DOWN: 699 669 pvrdma_dispatch_event(dev, 1, IB_EVENT_PORT_ERR); 700 - break; 701 - case NETDEV_UP: 702 - pvrdma_write_reg(dev, PVRDMA_REG_CTL, 703 - PVRDMA_DEVICE_CTL_UNQUIESCE); 704 - 705 - mb(); 706 - 707 - if (pvrdma_read_reg(dev, PVRDMA_REG_ERR)) 708 - dev_err(&dev->pdev->dev, 709 - "failed to activate device during link up\n"); 710 - else 711 - pvrdma_dispatch_event(dev, 1, IB_EVENT_PORT_ACTIVE); 712 670 break; 713 671 case NETDEV_UNREGISTER: 714 672 ib_device_set_netdev(&dev->ib_dev, NULL, 1);
+4 -18
drivers/infiniband/sw/rxe/rxe_net.c
··· 571 571 /* Caller must hold net_info_lock */ 572 572 void rxe_port_up(struct rxe_dev *rxe) 573 573 { 574 - struct rxe_port *port; 575 - 576 - port = &rxe->port; 577 - port->attr.state = IB_PORT_ACTIVE; 578 - 579 574 rxe_port_event(rxe, IB_EVENT_PORT_ACTIVE); 580 575 dev_info(&rxe->ib_dev.dev, "set active\n"); 581 576 } ··· 578 583 /* Caller must hold net_info_lock */ 579 584 void rxe_port_down(struct rxe_dev *rxe) 580 585 { 581 - struct rxe_port *port; 582 - 583 - port = &rxe->port; 584 - port->attr.state = IB_PORT_DOWN; 585 - 586 586 rxe_port_event(rxe, IB_EVENT_PORT_ERR); 587 587 rxe_counter_inc(rxe, RXE_CNT_LINK_DOWNED); 588 588 dev_info(&rxe->ib_dev.dev, "set down\n"); ··· 591 601 if (!ndev) 592 602 return; 593 603 594 - if (netif_running(ndev) && netif_carrier_ok(ndev)) 604 + if (ib_get_curr_port_state(ndev) == IB_PORT_ACTIVE) 595 605 rxe_port_up(rxe); 596 606 else 597 607 rxe_port_down(rxe); ··· 613 623 case NETDEV_UNREGISTER: 614 624 ib_unregister_device_queued(&rxe->ib_dev); 615 625 break; 616 - case NETDEV_UP: 617 - rxe_port_up(rxe); 618 - break; 619 - case NETDEV_DOWN: 620 - rxe_port_down(rxe); 621 - break; 622 626 case NETDEV_CHANGEMTU: 623 627 rxe_dbg_dev(rxe, "%s changed mtu to %d\n", ndev->name, ndev->mtu); 624 628 rxe_set_mtu(rxe, ndev->mtu); 625 629 break; 630 + case NETDEV_DOWN: 626 631 case NETDEV_CHANGE: 627 - rxe_set_port_state(rxe); 632 + if (ib_get_curr_port_state(ndev) == IB_PORT_DOWN) 633 + rxe_counter_inc(rxe, RXE_CNT_LINK_DOWNED); 628 634 break; 629 635 case NETDEV_REBOOT: 630 636 case NETDEV_GOING_DOWN:
+1 -1
drivers/infiniband/sw/rxe/rxe_param.h
··· 129 129 enum rxe_port_param { 130 130 RXE_PORT_GID_TBL_LEN = 1024, 131 131 RXE_PORT_PORT_CAP_FLAGS = IB_PORT_CM_SUP, 132 - RXE_PORT_MAX_MSG_SZ = 0x800000, 132 + RXE_PORT_MAX_MSG_SZ = (1UL << 31), 133 133 RXE_PORT_BAD_PKEY_CNTR = 0, 134 134 RXE_PORT_QKEY_VIOL_CNTR = 0, 135 135 RXE_PORT_LID = 0,
+5 -6
drivers/infiniband/sw/rxe/rxe_pool.c
··· 178 178 { 179 179 struct rxe_pool *pool = elem->pool; 180 180 struct xarray *xa = &pool->xa; 181 - static int timeout = RXE_POOL_TIMEOUT; 182 181 int ret, err = 0; 183 182 void *xa_ret; 184 183 ··· 201 202 * return to rdma-core 202 203 */ 203 204 if (sleepable) { 204 - if (!completion_done(&elem->complete) && timeout) { 205 + if (!completion_done(&elem->complete)) { 205 206 ret = wait_for_completion_timeout(&elem->complete, 206 - timeout); 207 + msecs_to_jiffies(50000)); 207 208 208 209 /* Shouldn't happen. There are still references to 209 210 * the object but, rather than deadlock, free the 210 211 * object or pass back to rdma-core. 211 212 */ 212 213 if (WARN_ON(!ret)) 213 - err = -EINVAL; 214 + err = -ETIMEDOUT; 214 215 } 215 216 } else { 216 - unsigned long until = jiffies + timeout; 217 + unsigned long until = jiffies + RXE_POOL_TIMEOUT; 217 218 218 219 /* AH objects are unique in that the destroy_ah verb 219 220 * can be called in atomic context. This delay ··· 225 226 mdelay(1); 226 227 227 228 if (WARN_ON(!completion_done(&elem->complete))) 228 - err = -EINVAL; 229 + err = -ETIMEDOUT; 229 230 } 230 231 231 232 if (pool->cleanup)
+3 -3
drivers/infiniband/sw/rxe/rxe_verbs.c
··· 62 62 ret = ib_get_eth_speed(ibdev, port_num, &attr->active_speed, 63 63 &attr->active_width); 64 64 65 + attr->state = ib_get_curr_port_state(ndev); 65 66 if (attr->state == IB_PORT_ACTIVE) 66 67 attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 67 68 else if (dev_get_flags(ndev) & IFF_UP) ··· 697 696 for (i = 0; i < ibwr->num_sge; i++) 698 697 length += ibwr->sg_list[i].length; 699 698 700 - if (length > (1UL << 31)) { 699 + if (length > RXE_PORT_MAX_MSG_SZ) { 701 700 rxe_err_qp(qp, "message length too long\n"); 702 701 break; 703 702 } ··· 981 980 for (i = 0; i < num_sge; i++) 982 981 length += ibwr->sg_list[i].length; 983 982 984 - /* IBA max message size is 2^31 */ 985 - if (length >= (1UL<<31)) { 983 + if (length > RXE_PORT_MAX_MSG_SZ) { 986 984 err = -EINVAL; 987 985 rxe_dbg("message length too long\n"); 988 986 goto err_out;
-8
drivers/infiniband/sw/siw/siw_main.c
··· 379 379 sdev = to_siw_dev(base_dev); 380 380 381 381 switch (event) { 382 - case NETDEV_UP: 383 - siw_port_event(sdev, 1, IB_EVENT_PORT_ACTIVE); 384 - break; 385 - 386 - case NETDEV_DOWN: 387 - siw_port_event(sdev, 1, IB_EVENT_PORT_ERR); 388 - break; 389 - 390 382 case NETDEV_REGISTER: 391 383 /* 392 384 * Device registration now handled only by
+2 -3
drivers/infiniband/sw/siw/siw_verbs.c
··· 189 189 attr->max_msg_sz = -1; 190 190 attr->max_mtu = ib_mtu_int_to_enum(ndev->max_mtu); 191 191 attr->active_mtu = ib_mtu_int_to_enum(READ_ONCE(ndev->mtu)); 192 - attr->phys_state = (netif_running(ndev) && netif_carrier_ok(ndev)) ? 192 + attr->state = ib_get_curr_port_state(ndev); 193 + attr->phys_state = attr->state == IB_PORT_ACTIVE ? 193 194 IB_PORT_PHYS_STATE_LINK_UP : IB_PORT_PHYS_STATE_DISABLED; 194 - attr->state = attr->phys_state == IB_PORT_PHYS_STATE_LINK_UP ? 195 - IB_PORT_ACTIVE : IB_PORT_DOWN; 196 195 attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_DEVICE_MGMT_SUP; 197 196 /* 198 197 * All zero
+3
drivers/infiniband/ulp/rtrs/rtrs.c
··· 584 584 list_del(&dev->entry); 585 585 mutex_unlock(&pool->mutex); 586 586 587 + if (pool->ops && pool->ops->deinit) 588 + pool->ops->deinit(dev); 589 + 587 590 ib_dealloc_pd(dev->ib_pd); 588 591 kfree(dev); 589 592 }
-1
drivers/infiniband/ulp/srp/ib_srp.c
··· 3978 3978 return host; 3979 3979 3980 3980 put_host: 3981 - device_del(&host->dev); 3982 3981 put_device(&host->dev); 3983 3982 return NULL; 3984 3983 }
+1
drivers/net/ethernet/broadcom/bnxt/bnxt.c
··· 2854 2854 } 2855 2855 __bnxt_queue_sp_work(bp); 2856 2856 async_event_process_exit: 2857 + bnxt_ulp_async_events(bp, cmpl); 2857 2858 return 0; 2858 2859 } 2859 2860
+34 -5
drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c
··· 298 298 { 299 299 struct bnxt_en_dev *edev = bp->edev; 300 300 struct bnxt_ulp_ops *ops; 301 + bool reset = false; 301 302 302 303 if (!edev || !(edev->flags & BNXT_EN_FLAG_MSIX_REQUESTED)) 303 304 return; ··· 312 311 ops = rtnl_dereference(ulp->ulp_ops); 313 312 if (!ops || !ops->ulp_irq_stop) 314 313 return; 315 - ops->ulp_irq_stop(ulp->handle); 314 + if (test_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) 315 + reset = true; 316 + ops->ulp_irq_stop(ulp->handle, reset); 316 317 } 317 318 } 318 319 ··· 349 346 } 350 347 } 351 348 352 - int bnxt_register_async_events(struct bnxt_en_dev *edev, 353 - unsigned long *events_bmap, 354 - u16 max_id) 349 + void bnxt_ulp_async_events(struct bnxt *bp, struct hwrm_async_event_cmpl *cmpl) 350 + { 351 + u16 event_id = le16_to_cpu(cmpl->event_id); 352 + struct bnxt_en_dev *edev = bp->edev; 353 + struct bnxt_ulp_ops *ops; 354 + struct bnxt_ulp *ulp; 355 + 356 + if (!bnxt_ulp_registered(edev)) 357 + return; 358 + ulp = edev->ulp_tbl; 359 + 360 + rcu_read_lock(); 361 + 362 + ops = rcu_dereference(ulp->ulp_ops); 363 + if (!ops || !ops->ulp_async_notifier) 364 + goto exit_unlock_rcu; 365 + if (!ulp->async_events_bmap || event_id > ulp->max_async_event_id) 366 + goto exit_unlock_rcu; 367 + 368 + /* Read max_async_event_id first before testing the bitmap. */ 369 + smp_rmb(); 370 + 371 + if (test_bit(event_id, ulp->async_events_bmap)) 372 + ops->ulp_async_notifier(ulp->handle, cmpl); 373 + exit_unlock_rcu: 374 + rcu_read_unlock(); 375 + } 376 + 377 + void bnxt_register_async_events(struct bnxt_en_dev *edev, 378 + unsigned long *events_bmap, u16 max_id) 355 379 { 356 380 struct net_device *dev = edev->net; 357 381 struct bnxt *bp = netdev_priv(dev); ··· 390 360 smp_wmb(); 391 361 ulp->max_async_event_id = max_id; 392 362 bnxt_hwrm_func_drv_rgtr(bp, events_bmap, max_id + 1, true); 393 - return 0; 394 363 } 395 364 EXPORT_SYMBOL(bnxt_register_async_events); 396 365
+5 -3
drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.h
··· 30 30 }; 31 31 32 32 struct bnxt_ulp_ops { 33 - void (*ulp_irq_stop)(void *); 33 + /* async_notifier() cannot sleep (in BH context) */ 34 + void (*ulp_async_notifier)(void *, struct hwrm_async_event_cmpl *); 35 + void (*ulp_irq_stop)(void *, bool); 34 36 void (*ulp_irq_restart)(void *, struct bnxt_msix_entry *); 35 37 }; 36 38 ··· 128 126 void *handle); 129 127 void bnxt_unregister_dev(struct bnxt_en_dev *edev); 130 128 int bnxt_send_msg(struct bnxt_en_dev *edev, struct bnxt_fw_msg *fw_msg); 131 - int bnxt_register_async_events(struct bnxt_en_dev *edev, 132 - unsigned long *events_bmap, u16 max_id); 129 + void bnxt_register_async_events(struct bnxt_en_dev *edev, 130 + unsigned long *events_bmap, u16 max_id); 133 131 #endif
-16
include/rdma/ib_cache.h
··· 64 64 u16 *index); 65 65 66 66 /** 67 - * ib_find_exact_cached_pkey - Returns the PKey table index where a specified 68 - * PKey value occurs. Comparison uses the FULL 16 bits (incl membership bit) 69 - * @device: The device to query. 70 - * @port_num: The port number of the device to search for the PKey. 71 - * @pkey: The PKey value to search for. 72 - * @index: The index into the cached PKey table where the PKey was found. 73 - * 74 - * ib_find_exact_cached_pkey() searches the specified PKey table in 75 - * the local software cache. 76 - */ 77 - int ib_find_exact_cached_pkey(struct ib_device *device, 78 - u32 port_num, 79 - u16 pkey, 80 - u16 *index); 81 - 82 - /** 83 67 * ib_get_cached_lmc - Returns a cached lmc table entry 84 68 * @device: The device to query. 85 69 * @port_num: The port number of the device to query.
-3
include/rdma/ib_marshall.h
··· 22 22 void ib_copy_path_rec_to_user(struct ib_user_path_rec *dst, 23 23 struct sa_path_rec *src); 24 24 25 - void ib_copy_path_rec_from_user(struct sa_path_rec *dst, 26 - struct ib_user_path_rec *src); 27 - 28 25 #endif /* IB_USER_MARSHALL_H */
-3
include/rdma/ib_pack.h
··· 283 283 int ib_ud_header_pack(struct ib_ud_header *header, 284 284 void *buf); 285 285 286 - int ib_ud_header_unpack(void *buf, 287 - struct ib_ud_header *header); 288 - 289 286 #endif /* IB_PACK_H */
+21 -3
include/rdma/ib_verbs.h
··· 59 59 60 60 struct ib_ucq_object; 61 61 62 - __printf(3, 4) __cold 63 - void ibdev_printk(const char *level, const struct ib_device *ibdev, 64 - const char *format, ...); 65 62 __printf(2, 3) __cold 66 63 void ibdev_emerg(const struct ib_device *ibdev, const char *format, ...); 67 64 __printf(2, 3) __cold ··· 2174 2177 struct ib_gid_table *gid; 2175 2178 u8 lmc; 2176 2179 enum ib_port_state port_state; 2180 + enum ib_port_state last_port_state; 2177 2181 }; 2178 2182 2179 2183 struct ib_port_immutable { ··· 2254 2256 2255 2257 struct ib_odp_counters { 2256 2258 atomic64_t faults; 2259 + atomic64_t faults_handled; 2257 2260 atomic64_t invalidations; 2261 + atomic64_t invalidations_handled; 2258 2262 atomic64_t prefetch; 2259 2263 }; 2260 2264 ··· 2680 2680 * the ufile. 2681 2681 */ 2682 2682 void (*ufile_hw_cleanup)(struct ib_uverbs_file *ufile); 2683 + 2684 + /** 2685 + * report_port_event - Drivers need to implement this if they have 2686 + * some private stuff to handle when link status changes. 2687 + */ 2688 + void (*report_port_event)(struct ib_device *ibdev, 2689 + struct net_device *ndev, unsigned long event); 2683 2690 2684 2691 DECLARE_RDMA_OBJ_SIZE(ib_ah); 2685 2692 DECLARE_RDMA_OBJ_SIZE(ib_counters); ··· 4476 4469 unsigned int port); 4477 4470 struct net_device *ib_device_get_netdev(struct ib_device *ib_dev, 4478 4471 u32 port); 4472 + int ib_query_netdev_port(struct ib_device *ibdev, struct net_device *ndev, 4473 + u32 *port); 4474 + 4475 + static inline enum ib_port_state ib_get_curr_port_state(struct net_device *net_dev) 4476 + { 4477 + return (netif_running(net_dev) && netif_carrier_ok(net_dev)) ? 4478 + IB_PORT_ACTIVE : IB_PORT_DOWN; 4479 + } 4480 + 4481 + void ib_dispatch_port_state_event(struct ib_device *ibdev, 4482 + struct net_device *ndev); 4479 4483 struct ib_wq *ib_create_wq(struct ib_pd *pd, 4480 4484 struct ib_wq_init_attr *init_attr); 4481 4485 int ib_destroy_wq_user(struct ib_wq *wq, struct ib_udata *udata);