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clk: renesas: rzg2l: Deassert reset on assert timeout

If the assert() fails due to timeout error, set the reset register bit
back to deasserted state. This change is needed especially for handling
assert error in suspend() callback that expect the device to be in
operational state in case of failure.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260108123433.104464-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Biju Das and committed by
Geert Uytterhoeven 0b0201f2 cda6a5de

+5 -4
+5 -4
drivers/clk/renesas/rzg2l-cpg.c
··· 1647 1647 u32 mask = BIT(info->resets[id].bit); 1648 1648 s8 monbit = info->resets[id].monbit; 1649 1649 u32 value = mask << 16; 1650 + u32 mon; 1650 1651 int ret; 1651 1652 1652 1653 dev_dbg(rcdev->dev, "%s id:%ld offset:0x%x\n", ··· 1668 1667 return 0; 1669 1668 } 1670 1669 1671 - ret = readl_poll_timeout_atomic(priv->base + reg, value, 1672 - assert == !!(value & mask), 10, 200); 1673 - if (ret && !assert) { 1674 - value = mask << 16; 1670 + ret = readl_poll_timeout_atomic(priv->base + reg, mon, 1671 + assert == !!(mon & mask), 10, 200); 1672 + if (ret) { 1673 + value ^= mask; 1675 1674 writel(value, priv->base + CLK_RST_R(info->resets[id].off)); 1676 1675 } 1677 1676