Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/radeon/kms: make sure pci max read request size is valid on evergreen+ (v2)
drm/radeon/kms: set a default max_pixel_clock
+33
+27
drivers/gpu/drm/radeon/evergreen.c
+27
drivers/gpu/drm/radeon/evergreen.c
···
41
41
void evergreen_fini(struct radeon_device *rdev);
42
42
static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
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43
44
+
void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
45
+
{
46
+
u16 ctl, v;
47
+
int cap, err;
48
+
49
+
cap = pci_pcie_cap(rdev->pdev);
50
+
if (!cap)
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+
return;
52
+
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+
err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
54
+
if (err)
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+
return;
56
+
57
+
v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
58
+
59
+
/* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
60
+
* to avoid hangs or perfomance issues
61
+
*/
62
+
if ((v == 0) || (v == 6) || (v == 7)) {
63
+
ctl &= ~PCI_EXP_DEVCTL_READRQ;
64
+
ctl |= (2 << 12);
65
+
pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
66
+
}
67
+
}
68
+
44
69
void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
45
70
{
46
71
/* enable the pflip int */
···
1887
1862
}
1888
1863
1889
1864
WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1865
+
1866
+
evergreen_fix_pci_max_read_req_size(rdev);
1890
1867
1891
1868
cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1892
1869
+3
drivers/gpu/drm/radeon/ni.c
+3
drivers/gpu/drm/radeon/ni.c
···
39
39
extern void evergreen_mc_program(struct radeon_device *rdev);
40
40
extern void evergreen_irq_suspend(struct radeon_device *rdev);
41
41
extern int evergreen_mc_init(struct radeon_device *rdev);
42
+
extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
42
43
43
44
#define EVERGREEN_PFP_UCODE_SIZE 1120
44
45
#define EVERGREEN_PM4_UCODE_SIZE 1376
···
669
668
}
670
669
671
670
WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
671
+
672
+
evergreen_fix_pci_max_read_req_size(rdev);
672
673
673
674
mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
674
675
mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
+3
drivers/gpu/drm/radeon/radeon_clocks.c
+3
drivers/gpu/drm/radeon/radeon_clocks.c