Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arm-soc/for-6.4/devicetree' of https://github.com/Broadcom/stblinux into soc/dt
This pull request contains Broadcom ARM-based SoCs Device Tree changes
for 6.4, please pull the following:
- William adds the new-style High Speed SPI controller node to the BCA
SoCs
* tag 'arm-soc/for-6.4/devicetree' of https://github.com/Broadcom/stblinux:
ARM: dts: broadcom: bcmbca: Add spi controller node
Link: https://lore.kernel.org/r/20230410232606.1917803-1-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+184
+18
arch/arm/boot/dts/bcm47622.dtsi
+18
arch/arm/boot/dts/bcm47622.dtsi
···
88
88
clock-div = <4>;
89
89
clock-mult = <1>;
90
90
};
91
+
92
+
hsspi_pll: hsspi-pll {
93
+
compatible = "fixed-clock";
94
+
#clock-cells = <0>;
95
+
clock-frequency = <200000000>;
96
+
};
91
97
};
92
98
93
99
psci {
···
124
118
#address-cells = <1>;
125
119
#size-cells = <1>;
126
120
ranges = <0 0xff800000 0x800000>;
121
+
122
+
hsspi: spi@1000 {
123
+
#address-cells = <1>;
124
+
#size-cells = <0>;
125
+
compatible = "brcm,bcm47622-hsspi", "brcm,bcmbca-hsspi-v1.0";
126
+
reg = <0x1000 0x600>;
127
+
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
128
+
clocks = <&hsspi_pll &hsspi_pll>;
129
+
clock-names = "hsspi", "pll";
130
+
num-cs = <8>;
131
+
status = "disabled";
132
+
};
127
133
128
134
uart0: serial@12000 {
129
135
compatible = "arm,pl011", "arm,primecell";
+18
arch/arm/boot/dts/bcm63138.dtsi
+18
arch/arm/boot/dts/bcm63138.dtsi
···
66
66
clock-div = <4>;
67
67
clock-mult = <1>;
68
68
};
69
+
70
+
hsspi_pll: hsspi-pll {
71
+
compatible = "fixed-clock";
72
+
#clock-cells = <0>;
73
+
clock-frequency = <400000000>;
74
+
};
69
75
};
70
76
71
77
/* ARM bus */
···
206
200
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
207
201
clocks = <&periph_clk>;
208
202
clock-names = "periph";
203
+
status = "disabled";
204
+
};
205
+
206
+
hsspi: spi@1000 {
207
+
#address-cells = <1>;
208
+
#size-cells = <0>;
209
+
compatible = "brcm,bcm63138-hsspi", "brcm,bcmbca-hsspi-v1.0";
210
+
reg = <0x1000 0x600>;
211
+
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
212
+
clocks = <&hsspi_pll &hsspi_pll>;
213
+
clock-names = "hsspi", "pll";
214
+
num-cs = <8>;
209
215
status = "disabled";
210
216
};
211
217
+18
arch/arm/boot/dts/bcm63148.dtsi
+18
arch/arm/boot/dts/bcm63148.dtsi
···
60
60
#clock-cells = <0>;
61
61
clock-frequency = <50000000>;
62
62
};
63
+
64
+
hsspi_pll: hsspi-pll {
65
+
compatible = "fixed-clock";
66
+
#clock-cells = <0>;
67
+
clock-frequency = <400000000>;
68
+
};
63
69
};
64
70
65
71
psci {
···
104
98
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
105
99
clocks = <&periph_clk>;
106
100
clock-names = "refclk";
101
+
status = "disabled";
102
+
};
103
+
104
+
hsspi: spi@1000 {
105
+
#address-cells = <1>;
106
+
#size-cells = <0>;
107
+
compatible = "brcm,bcm63148-hsspi", "brcm,bcmbca-hsspi-v1.0";
108
+
reg = <0x1000 0x600>;
109
+
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
110
+
clocks = <&hsspi_pll &hsspi_pll>;
111
+
clock-names = "hsspi", "pll";
112
+
num-cs = <8>;
107
113
status = "disabled";
108
114
};
109
115
};
+19
arch/arm/boot/dts/bcm63178.dtsi
+19
arch/arm/boot/dts/bcm63178.dtsi
···
71
71
#clock-cells = <0>;
72
72
clock-frequency = <200000000>;
73
73
};
74
+
74
75
uart_clk: uart-clk {
75
76
compatible = "fixed-factor-clock";
76
77
#clock-cells = <0>;
77
78
clocks = <&periph_clk>;
78
79
clock-div = <4>;
79
80
clock-mult = <1>;
81
+
};
82
+
83
+
hsspi_pll: hsspi-pll {
84
+
compatible = "fixed-clock";
85
+
#clock-cells = <0>;
86
+
clock-frequency = <200000000>;
80
87
};
81
88
};
82
89
···
115
108
#address-cells = <1>;
116
109
#size-cells = <1>;
117
110
ranges = <0 0xff800000 0x800000>;
111
+
112
+
hsspi: spi@1000 {
113
+
#address-cells = <1>;
114
+
#size-cells = <0>;
115
+
compatible = "brcm,bcm63178-hsspi", "brcm,bcmbca-hsspi-v1.0";
116
+
reg = <0x1000 0x600>;
117
+
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
118
+
clocks = <&hsspi_pll &hsspi_pll>;
119
+
clock-names = "hsspi", "pll";
120
+
num-cs = <8>;
121
+
status = "disabled";
122
+
};
118
123
119
124
uart0: serial@12000 {
120
125
compatible = "arm,pl011", "arm,primecell";
+19
arch/arm/boot/dts/bcm6756.dtsi
+19
arch/arm/boot/dts/bcm6756.dtsi
···
88
88
clock-div = <4>;
89
89
clock-mult = <1>;
90
90
};
91
+
92
+
hsspi_pll: hsspi-pll {
93
+
compatible = "fixed-clock";
94
+
#clock-cells = <0>;
95
+
clock-frequency = <200000000>;
96
+
};
91
97
};
92
98
93
99
psci {
···
124
118
#address-cells = <1>;
125
119
#size-cells = <1>;
126
120
ranges = <0 0xff800000 0x800000>;
121
+
122
+
hsspi: spi@1000 {
123
+
#address-cells = <1>;
124
+
#size-cells = <0>;
125
+
compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1";
126
+
reg = <0x1000 0x600>, <0x2610 0x4>;
127
+
reg-names = "hsspi", "spim-ctrl";
128
+
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
129
+
clocks = <&hsspi_pll &hsspi_pll>;
130
+
clock-names = "hsspi", "pll";
131
+
num-cs = <8>;
132
+
status = "disabled";
133
+
};
127
134
128
135
uart0: serial@12000 {
129
136
compatible = "arm,pl011", "arm,primecell";
+18
arch/arm/boot/dts/bcm6846.dtsi
+18
arch/arm/boot/dts/bcm6846.dtsi
···
61
61
#clock-cells = <0>;
62
62
clock-frequency = <200000000>;
63
63
};
64
+
65
+
hsspi_pll: hsspi-pll {
66
+
compatible = "fixed-clock";
67
+
#clock-cells = <0>;
68
+
clock-frequency = <400000000>;
69
+
};
64
70
};
65
71
66
72
psci {
···
104
98
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
105
99
clocks = <&periph_clk>;
106
100
clock-names = "refclk";
101
+
status = "disabled";
102
+
};
103
+
104
+
hsspi: spi@1000 {
105
+
#address-cells = <1>;
106
+
#size-cells = <0>;
107
+
compatible = "brcm,bcm6846-hsspi", "brcm,bcmbca-hsspi-v1.0";
108
+
reg = <0x1000 0x600>;
109
+
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
110
+
clocks = <&hsspi_pll &hsspi_pll>;
111
+
clock-names = "hsspi", "pll";
112
+
num-cs = <8>;
107
113
status = "disabled";
108
114
};
109
115
};
+19
arch/arm/boot/dts/bcm6855.dtsi
+19
arch/arm/boot/dts/bcm6855.dtsi
···
78
78
clock-div = <4>;
79
79
clock-mult = <1>;
80
80
};
81
+
82
+
hsspi_pll: hsspi-pll {
83
+
compatible = "fixed-clock";
84
+
#clock-cells = <0>;
85
+
clock-frequency = <200000000>;
86
+
};
81
87
};
82
88
83
89
psci {
···
114
108
#address-cells = <1>;
115
109
#size-cells = <1>;
116
110
ranges = <0 0xff800000 0x800000>;
111
+
112
+
hsspi: spi@1000 {
113
+
#address-cells = <1>;
114
+
#size-cells = <0>;
115
+
compatible = "brcm,bcm6855-hsspi", "brcm,bcmbca-hsspi-v1.1";
116
+
reg = <0x1000 0x600>, <0x2610 0x4>;
117
+
reg-names = "hsspi", "spim-ctrl";
118
+
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
119
+
clocks = <&hsspi_pll &hsspi_pll>;
120
+
clock-names = "hsspi", "pll";
121
+
num-cs = <8>;
122
+
status = "disabled";
123
+
};
117
124
118
125
uart0: serial@12000 {
119
126
compatible = "arm,pl011", "arm,primecell";
+19
arch/arm/boot/dts/bcm6878.dtsi
+19
arch/arm/boot/dts/bcm6878.dtsi
···
61
61
#clock-cells = <0>;
62
62
clock-frequency = <200000000>;
63
63
};
64
+
64
65
uart_clk: uart-clk {
65
66
compatible = "fixed-factor-clock";
66
67
#clock-cells = <0>;
67
68
clocks = <&periph_clk>;
68
69
clock-div = <4>;
69
70
clock-mult = <1>;
71
+
};
72
+
73
+
hsspi_pll: hsspi-pll {
74
+
compatible = "fixed-clock";
75
+
#clock-cells = <0>;
76
+
clock-frequency = <200000000>;
70
77
};
71
78
};
72
79
···
106
99
#address-cells = <1>;
107
100
#size-cells = <1>;
108
101
ranges = <0 0xff800000 0x800000>;
102
+
103
+
hsspi: spi@1000 {
104
+
#address-cells = <1>;
105
+
#size-cells = <0>;
106
+
compatible = "brcm,bcm6878-hsspi", "brcm,bcmbca-hsspi-v1.0";
107
+
reg = <0x1000 0x600>;
108
+
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
109
+
clocks = <&hsspi_pll &hsspi_pll>;
110
+
clock-names = "hsspi", "pll";
111
+
num-cs = <8>;
112
+
status = "disabled";
113
+
};
109
114
110
115
uart0: serial@12000 {
111
116
compatible = "arm,pl011", "arm,primecell";
+4
arch/arm/boot/dts/bcm947622.dts
+4
arch/arm/boot/dts/bcm947622.dts
+4
arch/arm/boot/dts/bcm963138.dts
+4
arch/arm/boot/dts/bcm963138.dts
+4
arch/arm/boot/dts/bcm963138dvt.dts
+4
arch/arm/boot/dts/bcm963138dvt.dts
+4
arch/arm/boot/dts/bcm963148.dts
+4
arch/arm/boot/dts/bcm963148.dts
+4
arch/arm/boot/dts/bcm963178.dts
+4
arch/arm/boot/dts/bcm963178.dts
+4
arch/arm/boot/dts/bcm96756.dts
+4
arch/arm/boot/dts/bcm96756.dts
+4
arch/arm/boot/dts/bcm96846.dts
+4
arch/arm/boot/dts/bcm96846.dts
+4
arch/arm/boot/dts/bcm96855.dts
+4
arch/arm/boot/dts/bcm96855.dts