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drm/amdgpu: add initial support for gfx950

add gfx950 basic support

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Le Ma and committed by
Alex Deucher
0b58a55a ebc7d1ac

+36 -11
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 1401 1401 1402 1402 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1403 1403 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 1404 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0) || 1404 1405 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) { 1405 1406 amdgpu_psp_wait_for_bootloader(adev); 1406 1407 ret = amdgpu_atomfirmware_asic_init(adev, true);
+5
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
··· 1836 1836 case IP_VERSION(9, 4, 2): 1837 1837 case IP_VERSION(9, 4, 3): 1838 1838 case IP_VERSION(9, 4, 4): 1839 + case IP_VERSION(9, 5, 0): 1839 1840 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1840 1841 break; 1841 1842 case IP_VERSION(10, 1, 10): ··· 1891 1890 case IP_VERSION(9, 4, 2): 1892 1891 case IP_VERSION(9, 4, 3): 1893 1892 case IP_VERSION(9, 4, 4): 1893 + case IP_VERSION(9, 5, 0): 1894 1894 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1895 1895 break; 1896 1896 case IP_VERSION(10, 1, 10): ··· 2186 2184 break; 2187 2185 case IP_VERSION(9, 4, 3): 2188 2186 case IP_VERSION(9, 4, 4): 2187 + case IP_VERSION(9, 5, 0): 2189 2188 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 2190 2189 break; 2191 2190 case IP_VERSION(10, 1, 10): ··· 2408 2405 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2409 2406 case IP_VERSION(9, 4, 3): 2410 2407 case IP_VERSION(9, 4, 4): 2408 + case IP_VERSION(9, 5, 0): 2411 2409 aqua_vanjaram_init_soc_config(adev); 2412 2410 break; 2413 2411 default: ··· 2656 2652 case IP_VERSION(9, 4, 2): 2657 2653 case IP_VERSION(9, 4, 3): 2658 2654 case IP_VERSION(9, 4, 4): 2655 + case IP_VERSION(9, 5, 0): 2659 2656 adev->family = AMDGPU_FAMILY_AI; 2660 2657 break; 2661 2658 case IP_VERSION(9, 1, 0):
+2 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
··· 1762 1762 1763 1763 if (!adev->bios && 1764 1764 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1765 - amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4))) 1765 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 1766 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))) 1766 1767 reserve_size = max(reserve_size, (uint32_t)280 << 20); 1767 1768 else if (!reserve_size) 1768 1769 reserve_size = DISCOVERY_TMR_OFFSET;
+3
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
··· 937 937 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 938 938 case IP_VERSION(9, 4, 3): 939 939 case IP_VERSION(9, 4, 4): 940 + case IP_VERSION(9, 5, 0): 940 941 adev->gfx.config.max_hw_contexts = 8; 941 942 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 942 943 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; ··· 4863 4862 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4864 4863 case IP_VERSION(9, 4, 3): 4865 4864 case IP_VERSION(9, 4, 4): 4865 + case IP_VERSION(9, 5, 0): 4866 4866 /* 9.4.3 removed all the GDS internal memory, 4867 4867 * only support GWS opcode in kernel, like barrier 4868 4868 * semaphore.etc */ ··· 4877 4875 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4878 4876 case IP_VERSION(9, 4, 3): 4879 4877 case IP_VERSION(9, 4, 4): 4878 + case IP_VERSION(9, 5, 0): 4880 4879 /* deprecated for 9.4.3, no usage at all */ 4881 4880 adev->gds.gds_compute_max_wave_id = 0; 4882 4881 break;
+3 -1
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
··· 368 368 amdgpu_ip_version(adev, GC_HWIP, 0) == 369 369 IP_VERSION(9, 4, 3) || 370 370 amdgpu_ip_version(adev, GC_HWIP, 0) == 371 - IP_VERSION(9, 4, 4)); 371 + IP_VERSION(9, 4, 4) || 372 + amdgpu_ip_version(adev, GC_HWIP, 0) == 373 + IP_VERSION(9, 5, 0)); 372 374 WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL, 373 375 i * hub->ctx_distance, tmp); 374 376 WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),
+21 -9
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
··· 645 645 soc15_ih_clientid_name[entry->client_id]); 646 646 647 647 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 648 - amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 648 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 649 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 649 650 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n", 650 651 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4, 651 652 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : ""); ··· 796 795 { 797 796 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 798 797 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 799 - amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 798 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 799 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 800 800 return false; 801 801 802 802 return ((vmhub == AMDGPU_MMHUB0(0) || ··· 1184 1182 break; 1185 1183 case IP_VERSION(9, 4, 3): 1186 1184 case IP_VERSION(9, 4, 4): 1185 + case IP_VERSION(9, 5, 0): 1187 1186 /* Only local VRAM BOs or system memory on non-NUMA APUs 1188 1187 * can be assumed to be local in their entirety. Choose 1189 1188 * MTYPE_NC as safe fallback for all system memory BOs on ··· 1276 1273 * memory can use more efficient MTYPEs. 1277 1274 */ 1278 1275 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3) && 1279 - amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) 1276 + amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) && 1277 + amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 5, 0)) 1280 1278 return; 1281 1279 1282 1280 /* Only direct-mapped memory allows us to determine the NUMA node from ··· 1553 1549 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1554 1550 { 1555 1551 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1556 - amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 1552 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 1553 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 1557 1554 adev->gfxhub.funcs = &gfxhub_v1_2_funcs; 1558 1555 else 1559 1556 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; ··· 1795 1790 case IP_VERSION(9, 4, 2): 1796 1791 case IP_VERSION(9, 4, 3): 1797 1792 case IP_VERSION(9, 4, 4): 1793 + case IP_VERSION(9, 5, 0): 1798 1794 default: 1799 1795 adev->gmc.gart_size = 512ULL << 20; 1800 1796 break; ··· 2074 2068 spin_lock_init(&adev->gmc.invalidate_lock); 2075 2069 2076 2070 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2077 - amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { 2071 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 2072 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) { 2078 2073 gmc_v9_4_3_init_vram_info(adev); 2079 2074 } else if (!adev->bios) { 2080 2075 if (adev->flags & AMD_IS_APU) { ··· 2159 2152 break; 2160 2153 case IP_VERSION(9, 4, 3): 2161 2154 case IP_VERSION(9, 4, 4): 2155 + case IP_VERSION(9, 5, 0): 2162 2156 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0), 2163 2157 NUM_XCC(adev->gfx.xcc_mask)); 2164 2158 ··· 2226 2218 amdgpu_gmc_get_vbios_allocations(adev); 2227 2219 2228 2220 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2229 - amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { 2221 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 2222 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) { 2230 2223 r = gmc_v9_0_init_mem_ranges(adev); 2231 2224 if (r) 2232 2225 return r; ··· 2257 2248 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 2258 2249 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 2259 2250 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2260 - amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) ? 2251 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 2252 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) ? 2261 2253 3 : 2262 2254 8; 2263 2255 ··· 2271 2261 return r; 2272 2262 2273 2263 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2274 - amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 2264 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 2265 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 2275 2266 amdgpu_gmc_sysfs_init(adev); 2276 2267 2277 2268 return 0; ··· 2283 2272 struct amdgpu_device *adev = ip_block->adev; 2284 2273 2285 2274 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2286 - amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 2275 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 2276 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 2287 2277 amdgpu_gmc_sysfs_fini(adev); 2288 2278 2289 2279 amdgpu_gmc_ras_fini(adev);
+1
drivers/gpu/drm/amd/amdgpu/soc15.c
··· 1177 1177 break; 1178 1178 case IP_VERSION(9, 4, 3): 1179 1179 case IP_VERSION(9, 4, 4): 1180 + case IP_VERSION(9, 5, 0): 1180 1181 adev->asic_funcs = &aqua_vanjaram_asic_funcs; 1181 1182 adev->cg_flags = 1182 1183 AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG |