Merge branch 'implement-more-features-for-txgbe-devices'

+59 -2

drivers/net/ethernet/wangxun/libwx/wx_ethtool.c

··· 51 51 WX_STAT("fdir_miss", stats.fdirmiss), 52 52 }; 53 53 54 + static const struct wx_stats wx_gstrings_rsc_stats[] = { 55 + WX_STAT("rsc_aggregated", rsc_count), 56 + WX_STAT("rsc_flushed", rsc_flush), 57 + }; 58 + 54 59 /* drivers allocates num_tx_queues and num_rx_queues symmetrically so 55 60 * we set the num_rx_queues to evaluate to num_tx_queues. This is 56 61 * used because we do not have a good way to get the max number of ··· 69 64 (sizeof(struct wx_queue_stats) / sizeof(u64))) 70 65 #define WX_GLOBAL_STATS_LEN ARRAY_SIZE(wx_gstrings_stats) 71 66 #define WX_FDIR_STATS_LEN ARRAY_SIZE(wx_gstrings_fdir_stats) 67 + #define WX_RSC_STATS_LEN ARRAY_SIZE(wx_gstrings_rsc_stats) 72 68 #define WX_STATS_LEN (WX_GLOBAL_STATS_LEN + WX_QUEUE_STATS_LEN) 73 69 74 70 int wx_get_sset_count(struct net_device *netdev, int sset) 75 71 { 76 72 struct wx *wx = netdev_priv(netdev); 73 + int len = WX_STATS_LEN; 77 74 78 75 switch (sset) { 79 76 case ETH_SS_STATS: 80 - return (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)) ? 81 - WX_STATS_LEN + WX_FDIR_STATS_LEN : WX_STATS_LEN; 77 + if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)) 78 + len += WX_FDIR_STATS_LEN; 79 + if (test_bit(WX_FLAG_RSC_CAPABLE, wx->flags)) 80 + len += WX_RSC_STATS_LEN; 81 + return len; 82 82 default: 83 83 return -EOPNOTSUPP; 84 84 } ··· 103 93 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)) { 104 94 for (i = 0; i < WX_FDIR_STATS_LEN; i++) 105 95 ethtool_puts(&p, wx_gstrings_fdir_stats[i].stat_string); 96 + } 97 + if (test_bit(WX_FLAG_RSC_CAPABLE, wx->flags)) { 98 + for (i = 0; i < WX_RSC_STATS_LEN; i++) 99 + ethtool_puts(&p, wx_gstrings_rsc_stats[i].stat_string); 106 100 } 107 101 for (i = 0; i < netdev->num_tx_queues; i++) { 108 102 ethtool_sprintf(&p, "tx_queue_%u_packets", i); ··· 141 127 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)) { 142 128 for (k = 0; k < WX_FDIR_STATS_LEN; k++) { 143 129 p = (char *)wx + wx_gstrings_fdir_stats[k].stat_offset; 130 + data[i++] = *(u64 *)p; 131 + } 132 + } 133 + 134 + if (test_bit(WX_FLAG_RSC_CAPABLE, wx->flags)) { 135 + for (k = 0; k < WX_RSC_STATS_LEN; k++) { 136 + p = (char *)wx + wx_gstrings_rsc_stats[k].stat_offset; 144 137 data[i++] = *(u64 *)p; 145 138 } 146 139 } ··· 343 322 } 344 323 EXPORT_SYMBOL(wx_get_coalesce); 345 324 325 + static void wx_update_rsc(struct wx *wx) 326 + { 327 + struct net_device *netdev = wx->netdev; 328 + bool need_reset = false; 329 + 330 + /* nothing to do if LRO or RSC are not enabled */ 331 + if (!test_bit(WX_FLAG_RSC_CAPABLE, wx->flags) || 332 + !(netdev->features & NETIF_F_LRO)) 333 + return; 334 + 335 + /* check the feature flag value and enable RSC if necessary */ 336 + if (wx->rx_itr_setting == 1 || 337 + wx->rx_itr_setting > WX_MIN_RSC_ITR) { 338 + if (!test_bit(WX_FLAG_RSC_ENABLED, wx->flags)) { 339 + set_bit(WX_FLAG_RSC_ENABLED, wx->flags); 340 + dev_info(&wx->pdev->dev, 341 + "rx-usecs value high enough to re-enable RSC\n"); 342 + 343 + need_reset = true; 344 + } 345 + /* if interrupt rate is too high then disable RSC */ 346 + } else if (test_bit(WX_FLAG_RSC_ENABLED, wx->flags)) { 347 + clear_bit(WX_FLAG_RSC_ENABLED, wx->flags); 348 + dev_info(&wx->pdev->dev, 349 + "rx-usecs set too low, disabling RSC\n"); 350 + 351 + need_reset = true; 352 + } 353 + 354 + /* reset the device to apply the new RSC setting */ 355 + if (need_reset && wx->do_reset) 356 + wx->do_reset(netdev); 357 + } 358 + 346 359 int wx_set_coalesce(struct net_device *netdev, 347 360 struct ethtool_coalesce *ec, 348 361 struct kernel_ethtool_coalesce *kernel_coal, ··· 468 413 q_vector->itr = rx_itr_param; 469 414 wx_write_eitr(q_vector); 470 415 } 416 + 417 + wx_update_rsc(wx); 471 418 472 419 return 0; 473 420 }

+67 -2

drivers/net/ethernet/wangxun/libwx/wx_hw.c

··· 1779 1779 static void wx_set_rx_buffer_len(struct wx *wx) 1780 1780 { 1781 1781 struct net_device *netdev = wx->netdev; 1782 + struct wx_ring *rx_ring; 1782 1783 u32 mhadd, max_frame; 1784 + int i; 1783 1785 1784 1786 max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 1785 1787 /* adjust max frame to be at least the size of a standard frame */ ··· 1791 1789 mhadd = rd32(wx, WX_PSR_MAX_SZ); 1792 1790 if (max_frame != mhadd) 1793 1791 wr32(wx, WX_PSR_MAX_SZ, max_frame); 1792 + 1793 + /* 1794 + * Setup the HW Rx Head and Tail Descriptor Pointers and 1795 + * the Base and Length of the Rx Descriptor Ring 1796 + */ 1797 + for (i = 0; i < wx->num_rx_queues; i++) { 1798 + rx_ring = wx->rx_ring[i]; 1799 + rx_ring->rx_buf_len = WX_RXBUFFER_2K; 1800 + #if (PAGE_SIZE < 8192) 1801 + if (test_bit(WX_FLAG_RSC_ENABLED, wx->flags)) 1802 + rx_ring->rx_buf_len = WX_RXBUFFER_3K; 1803 + #endif 1804 + } 1794 1805 } 1795 1806 1796 1807 /** ··· 1880 1865 srrctl |= WX_RXBUFFER_256 << WX_PX_RR_CFG_BHDRSIZE_SHIFT; 1881 1866 1882 1867 /* configure the packet buffer length */ 1883 - srrctl |= WX_RX_BUFSZ >> WX_PX_RR_CFG_BSIZEPKT_SHIFT; 1868 + srrctl |= rx_ring->rx_buf_len >> WX_PX_RR_CFG_BSIZEPKT_SHIFT; 1884 1869 1885 1870 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl); 1871 + } 1872 + 1873 + static void wx_configure_rscctl(struct wx *wx, 1874 + struct wx_ring *ring) 1875 + { 1876 + u8 reg_idx = ring->reg_idx; 1877 + u32 rscctrl; 1878 + 1879 + if (!test_bit(WX_FLAG_RSC_ENABLED, wx->flags)) 1880 + return; 1881 + 1882 + rscctrl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 1883 + rscctrl |= WX_PX_RR_CFG_RSC; 1884 + rscctrl |= WX_PX_RR_CFG_MAX_RSCBUF_16; 1885 + 1886 + wr32(wx, WX_PX_RR_CFG(reg_idx), rscctrl); 1886 1887 } 1887 1888 1888 1889 static void wx_configure_tx_ring(struct wx *wx, ··· 1936 1905 memset(ring->tx_buffer_info, 0, 1937 1906 sizeof(struct wx_tx_buffer) * ring->count); 1938 1907 1908 + if (ring->headwb_mem) { 1909 + wr32(wx, WX_PX_TR_HEAD_ADDRL(reg_idx), 1910 + ring->headwb_dma & DMA_BIT_MASK(32)); 1911 + wr32(wx, WX_PX_TR_HEAD_ADDRH(reg_idx), 1912 + upper_32_bits(ring->headwb_dma)); 1913 + 1914 + txdctl |= WX_PX_TR_CFG_HEAD_WB; 1915 + } 1916 + 1939 1917 /* enable queue */ 1940 1918 wr32(wx, WX_PX_TR_CFG(reg_idx), txdctl); 1941 1919 ··· 1975 1935 rxdctl |= (ring->count / 128) << WX_PX_RR_CFG_RR_SIZE_SHIFT; 1976 1936 1977 1937 rxdctl |= 0x1 << WX_PX_RR_CFG_RR_THER_SHIFT; 1938 + 1939 + if (test_bit(WX_FLAG_RX_MERGE_ENABLED, wx->flags)) 1940 + rxdctl |= WX_PX_RR_CFG_DESC_MERGE; 1941 + 1978 1942 wr32(wx, WX_PX_RR_CFG(reg_idx), rxdctl); 1979 1943 1980 1944 /* reset head and tail pointers */ ··· 1987 1943 ring->tail = wx->hw_addr + WX_PX_RR_WP(reg_idx); 1988 1944 1989 1945 wx_configure_srrctl(wx, ring); 1946 + wx_configure_rscctl(wx, ring); 1990 1947 1991 1948 /* initialize rx_buffer_info */ 1992 1949 memset(ring->rx_buffer_info, 0, ··· 2226 2181 /* RSC Setup */ 2227 2182 psrctl = rd32(wx, WX_PSR_CTL); 2228 2183 psrctl |= WX_PSR_CTL_RSC_ACK; /* Disable RSC for ACK packets */ 2229 - psrctl |= WX_PSR_CTL_RSC_DIS; 2184 + psrctl &= ~WX_PSR_CTL_RSC_DIS; 2185 + if (!test_bit(WX_FLAG_RSC_ENABLED, wx->flags)) 2186 + psrctl |= WX_PSR_CTL_RSC_DIS; 2230 2187 wr32(wx, WX_PSR_CTL, psrctl); 2231 2188 } 2232 2189 ··· 2237 2190 /* set_rx_buffer_len must be called before ring initialization */ 2238 2191 wx_set_rx_buffer_len(wx); 2239 2192 2193 + if (test_bit(WX_FLAG_RX_MERGE_ENABLED, wx->flags)) { 2194 + wr32(wx, WX_RDM_DCACHE_CTL, WX_RDM_DCACHE_CTL_EN); 2195 + wr32m(wx, WX_RDM_RSC_CTL, 2196 + WX_RDM_RSC_CTL_FREE_CTL | WX_RDM_RSC_CTL_FREE_CNT_DIS, 2197 + WX_RDM_RSC_CTL_FREE_CTL); 2198 + } 2240 2199 /* Setup the HW Rx Head and Tail Descriptor Pointers and 2241 2200 * the Base and Length of the Rx Descriptor Ring 2242 2201 */ ··· 2857 2804 wx->alloc_rx_buff_failed = alloc_rx_buff_failed; 2858 2805 wx->hw_csum_rx_error = hw_csum_rx_error; 2859 2806 wx->hw_csum_rx_good = hw_csum_rx_good; 2807 + 2808 + if (test_bit(WX_FLAG_RSC_ENABLED, wx->flags)) { 2809 + u64 rsc_count = 0; 2810 + u64 rsc_flush = 0; 2811 + 2812 + for (i = 0; i < wx->num_rx_queues; i++) { 2813 + rsc_count += wx->rx_ring[i]->rx_stats.rsc_count; 2814 + rsc_flush += wx->rx_ring[i]->rx_stats.rsc_flush; 2815 + } 2816 + wx->rsc_count = rsc_count; 2817 + wx->rsc_flush = rsc_flush; 2818 + } 2860 2819 2861 2820 for (i = 0; i < wx->num_tx_queues; i++) { 2862 2821 struct wx_ring *tx_ring = wx->tx_ring[i];

+134 -9

drivers/net/ethernet/wangxun/libwx/wx_lib.c

··· 235 235 { 236 236 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 237 237 #if (PAGE_SIZE < 8192) 238 - unsigned int truesize = WX_RX_BUFSZ; 238 + unsigned int truesize = wx_rx_pg_size(rx_ring) / 2; 239 239 #else 240 240 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 241 241 #endif ··· 341 341 /* sync the buffer for use by the device */ 342 342 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 343 343 bi->page_offset, 344 - WX_RX_BUFSZ, 344 + rx_ring->rx_buf_len, 345 345 DMA_FROM_DEVICE); 346 346 347 347 rx_desc->read.pkt_addr = ··· 404 404 union wx_rx_desc *rx_desc, 405 405 struct sk_buff *skb) 406 406 { 407 + struct wx *wx = rx_ring->q_vector->wx; 407 408 u32 ntc = rx_ring->next_to_clean + 1; 408 409 409 410 /* fetch, update, and store next to clean */ ··· 412 411 rx_ring->next_to_clean = ntc; 413 412 414 413 prefetch(WX_RX_DESC(rx_ring, ntc)); 414 + 415 + /* update RSC append count if present */ 416 + if (test_bit(WX_FLAG_RSC_ENABLED, wx->flags)) { 417 + __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 418 + cpu_to_le32(WX_RXD_RSCCNT_MASK); 419 + 420 + if (unlikely(rsc_enabled)) { 421 + u32 rsc_cnt = le32_to_cpu(rsc_enabled); 422 + 423 + rsc_cnt >>= WX_RXD_RSCCNT_SHIFT; 424 + WX_CB(skb)->append_cnt += rsc_cnt - 1; 425 + 426 + /* update ntc based on RSC value */ 427 + ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 428 + ntc &= WX_RXD_NEXTP_MASK; 429 + ntc >>= WX_RXD_NEXTP_SHIFT; 430 + } 431 + } 415 432 416 433 /* if we are the last buffer then there is nothing else to do */ 417 434 if (likely(wx_test_staterr(rx_desc, WX_RXD_STAT_EOP))) ··· 601 582 } 602 583 } 603 584 585 + static void wx_set_rsc_gso_size(struct wx_ring *ring, 586 + struct sk_buff *skb) 587 + { 588 + u16 hdr_len = skb_headlen(skb); 589 + 590 + /* set gso_size to avoid messing up TCP MSS */ 591 + skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 592 + WX_CB(skb)->append_cnt); 593 + skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 594 + } 595 + 596 + static void wx_update_rsc_stats(struct wx_ring *rx_ring, 597 + struct sk_buff *skb) 598 + { 599 + /* if append_cnt is 0 then frame is not RSC */ 600 + if (!WX_CB(skb)->append_cnt) 601 + return; 602 + 603 + rx_ring->rx_stats.rsc_count += WX_CB(skb)->append_cnt; 604 + rx_ring->rx_stats.rsc_flush++; 605 + 606 + wx_set_rsc_gso_size(rx_ring, skb); 607 + 608 + /* gso_size is computed using append_cnt so always clear it last */ 609 + WX_CB(skb)->append_cnt = 0; 610 + } 611 + 604 612 /** 605 613 * wx_process_skb_fields - Populate skb header fields from Rx descriptor 606 614 * @rx_ring: rx descriptor ring packet is being transacted on ··· 643 597 struct sk_buff *skb) 644 598 { 645 599 struct wx *wx = netdev_priv(rx_ring->netdev); 600 + 601 + if (test_bit(WX_FLAG_RSC_CAPABLE, wx->flags)) 602 + wx_update_rsc_stats(rx_ring, skb); 646 603 647 604 wx_rx_hash(rx_ring, rx_desc, skb); 648 605 wx_rx_checksum(rx_ring, rx_desc, skb); ··· 784 735 /* prevent any other reads prior to eop_desc */ 785 736 smp_rmb(); 786 737 787 - /* if DD is not set pending work has not been completed */ 788 - if (!(eop_desc->wb.status & cpu_to_le32(WX_TXD_STAT_DD))) 738 + if (tx_ring->headwb_mem) { 739 + u32 head = *tx_ring->headwb_mem; 740 + 741 + if (head == tx_ring->next_to_clean) 742 + break; 743 + else if (head > tx_ring->next_to_clean && 744 + !(tx_buffer->next_eop >= tx_ring->next_to_clean && 745 + tx_buffer->next_eop < head)) 746 + break; 747 + else if (!(tx_buffer->next_eop >= tx_ring->next_to_clean || 748 + tx_buffer->next_eop < head)) 749 + break; 750 + } else if (!(eop_desc->wb.status & cpu_to_le32(WX_TXD_STAT_DD))) { 751 + /* if DD is not set pending work has not been completed */ 789 752 break; 753 + } 790 754 791 755 /* clear next_to_watch to prevent false hangs */ 792 756 tx_buffer->next_to_watch = NULL; ··· 1136 1074 1137 1075 /* set next_to_watch value indicating a packet is present */ 1138 1076 first->next_to_watch = tx_desc; 1077 + 1078 + /* set next_eop for amlite tx head wb */ 1079 + if (tx_ring->headwb_mem) 1080 + first->next_eop = i; 1139 1081 1140 1082 i++; 1141 1083 if (i == tx_ring->count) ··· 2598 2532 dma_sync_single_range_for_cpu(rx_ring->dev, 2599 2533 rx_buffer->dma, 2600 2534 rx_buffer->page_offset, 2601 - WX_RX_BUFSZ, 2535 + rx_ring->rx_buf_len, 2602 2536 DMA_FROM_DEVICE); 2603 2537 2604 2538 /* free resources associated with mapping */ ··· 2749 2683 } 2750 2684 EXPORT_SYMBOL(wx_clean_all_tx_rings); 2751 2685 2686 + static void wx_free_headwb_resources(struct wx_ring *tx_ring) 2687 + { 2688 + if (!tx_ring->headwb_mem) 2689 + return; 2690 + 2691 + dma_free_coherent(tx_ring->dev, sizeof(u32), 2692 + tx_ring->headwb_mem, tx_ring->headwb_dma); 2693 + tx_ring->headwb_mem = NULL; 2694 + } 2695 + 2752 2696 /** 2753 2697 * wx_free_tx_resources - Free Tx Resources per Queue 2754 2698 * @tx_ring: Tx descriptor ring for a specific queue ··· 2778 2702 dma_free_coherent(tx_ring->dev, tx_ring->size, 2779 2703 tx_ring->desc, tx_ring->dma); 2780 2704 tx_ring->desc = NULL; 2705 + 2706 + wx_free_headwb_resources(tx_ring); 2781 2707 } 2782 2708 2783 2709 /** ··· 2809 2731 2810 2732 struct page_pool_params pp_params = { 2811 2733 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 2812 - .order = 0, 2813 - .pool_size = rx_ring->count, 2734 + .order = wx_rx_pg_order(rx_ring), 2735 + .pool_size = rx_ring->count * rx_ring->rx_buf_len / 2736 + wx_rx_pg_size(rx_ring), 2814 2737 .nid = dev_to_node(rx_ring->dev), 2815 2738 .dev = rx_ring->dev, 2816 2739 .dma_dir = DMA_FROM_DEVICE, 2817 2740 .offset = 0, 2818 - .max_len = PAGE_SIZE, 2741 + .max_len = wx_rx_pg_size(rx_ring), 2819 2742 }; 2820 2743 2821 2744 rx_ring->page_pool = page_pool_create(&pp_params); ··· 2919 2840 return err; 2920 2841 } 2921 2842 2843 + static void wx_setup_headwb_resources(struct wx_ring *tx_ring) 2844 + { 2845 + struct wx *wx = netdev_priv(tx_ring->netdev); 2846 + 2847 + if (!test_bit(WX_FLAG_TXHEAD_WB_ENABLED, wx->flags)) 2848 + return; 2849 + 2850 + if (!tx_ring->q_vector) 2851 + return; 2852 + 2853 + tx_ring->headwb_mem = dma_alloc_coherent(tx_ring->dev, 2854 + sizeof(u32), 2855 + &tx_ring->headwb_dma, 2856 + GFP_KERNEL); 2857 + if (!tx_ring->headwb_mem) 2858 + dev_info(tx_ring->dev, "Allocate headwb memory failed, disable it\n"); 2859 + } 2860 + 2922 2861 /** 2923 2862 * wx_setup_tx_resources - allocate Tx resources (Descriptors) 2924 2863 * @tx_ring: tx descriptor ring (for a specific queue) to setup ··· 2976 2879 2977 2880 if (!tx_ring->desc) 2978 2881 goto err; 2882 + 2883 + wx_setup_headwb_resources(tx_ring); 2979 2884 2980 2885 tx_ring->next_to_use = 0; 2981 2886 tx_ring->next_to_clean = 0; ··· 3125 3026 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_FILTER)) 3126 3027 wx_set_rx_mode(netdev); 3127 3028 3029 + if (test_bit(WX_FLAG_RSC_CAPABLE, wx->flags)) { 3030 + if (!(features & NETIF_F_LRO)) { 3031 + if (test_bit(WX_FLAG_RSC_ENABLED, wx->flags)) 3032 + need_reset = true; 3033 + clear_bit(WX_FLAG_RSC_ENABLED, wx->flags); 3034 + } else if (!(test_bit(WX_FLAG_RSC_ENABLED, wx->flags))) { 3035 + if (wx->rx_itr_setting == 1 || 3036 + wx->rx_itr_setting > WX_MIN_RSC_ITR) { 3037 + set_bit(WX_FLAG_RSC_ENABLED, wx->flags); 3038 + need_reset = true; 3039 + } else if (changed & NETIF_F_LRO) { 3040 + dev_info(&wx->pdev->dev, 3041 + "rx-usecs set too low, disable RSC\n"); 3042 + } 3043 + } 3044 + } 3045 + 3128 3046 if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags))) 3129 - return 0; 3047 + goto out; 3130 3048 3131 3049 /* Check if Flow Director n-tuple support was enabled or disabled. If 3132 3050 * the state changed, we need to reset. ··· 3169 3053 break; 3170 3054 } 3171 3055 3056 + out: 3172 3057 if (need_reset && wx->do_reset) 3173 3058 wx->do_reset(netdev); 3174 3059 ··· 3218 3101 wx_err(wx, "802.1Q and 802.1ad VLAN filtering must be either both on or both off."); 3219 3102 } 3220 3103 } 3104 + 3105 + /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 3106 + if (!(features & NETIF_F_RXCSUM)) 3107 + features &= ~NETIF_F_LRO; 3108 + 3109 + /* Turn off LRO if not RSC capable */ 3110 + if (!test_bit(WX_FLAG_RSC_CAPABLE, wx->flags)) 3111 + features &= ~NETIF_F_LRO; 3221 3112 3222 3113 return features; 3223 3114 }

+4

drivers/net/ethernet/wangxun/libwx/wx_sriov.c

··· 122 122 WX_CFG_PORT_CTL_NUM_VT_MASK, 123 123 value); 124 124 125 + /* Disable RSC when in SR-IOV mode */ 126 + clear_bit(WX_FLAG_RSC_CAPABLE, wx->flags); 127 + clear_bit(WX_FLAG_RSC_ENABLED, wx->flags); 128 + 125 129 return ret; 126 130 } 127 131

+41 -6

drivers/net/ethernet/wangxun/libwx/wx_type.h

··· 83 83 84 84 /*********************** Receive DMA registers **************************/ 85 85 #define WX_RDM_VF_RE(_i) (0x12004 + ((_i) * 4)) 86 + #define WX_RDM_RSC_CTL 0x1200C 87 + #define WX_RDM_RSC_CTL_FREE_CNT_DIS BIT(8) 88 + #define WX_RDM_RSC_CTL_FREE_CTL BIT(7) 86 89 #define WX_RDM_PF_QDE(_i) (0x12080 + ((_i) * 4)) 87 90 #define WX_RDM_VFRE_CLR(_i) (0x120A0 + ((_i) * 4)) 91 + #define WX_RDM_DCACHE_CTL 0x120A8 92 + #define WX_RDM_DCACHE_CTL_EN BIT(0) 88 93 #define WX_RDM_DRP_PKT 0x12500 89 94 #define WX_RDM_PKT_CNT 0x12504 90 95 #define WX_RDM_BYTE_CNT_LSB 0x12508 ··· 424 419 #define WX_7K_ITR 595 425 420 #define WX_12K_ITR 336 426 421 #define WX_20K_ITR 200 422 + #define WX_MIN_RSC_ITR 24 427 423 #define WX_SP_MAX_EITR 0x00000FF8U 428 424 #define WX_AML_MAX_EITR 0x00000FFFU 429 425 #define WX_EM_MAX_EITR 0x00007FFCU ··· 435 429 #define WX_PX_TR_WP(_i) (0x03008 + ((_i) * 0x40)) 436 430 #define WX_PX_TR_RP(_i) (0x0300C + ((_i) * 0x40)) 437 431 #define WX_PX_TR_CFG(_i) (0x03010 + ((_i) * 0x40)) 432 + #define WX_PX_TR_HEAD_ADDRL(_i) (0x03028 + ((_i) * 0x40)) 433 + #define WX_PX_TR_HEAD_ADDRH(_i) (0x0302C + ((_i) * 0x40)) 438 434 /* Transmit Config masks */ 439 435 #define WX_PX_TR_CFG_ENABLE BIT(0) /* Ena specific Tx Queue */ 440 436 #define WX_PX_TR_CFG_TR_SIZE_SHIFT 1 /* tx desc number per ring */ 441 437 #define WX_PX_TR_CFG_SWFLSH BIT(26) /* Tx Desc. wr-bk flushing */ 442 438 #define WX_PX_TR_CFG_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 443 439 #define WX_PX_TR_CFG_THRE_SHIFT 8 440 + #define WX_PX_TR_CFG_HEAD_WB BIT(27) 444 441 445 442 /* Receive DMA Registers */ 446 443 #define WX_PX_RR_BAL(_i) (0x01000 + ((_i) * 0x40)) ··· 455 446 /* PX_RR_CFG bit definitions */ 456 447 #define WX_PX_RR_CFG_VLAN BIT(31) 457 448 #define WX_PX_RR_CFG_DROP_EN BIT(30) 449 + #define WX_PX_RR_CFG_RSC BIT(29) 458 450 #define WX_PX_RR_CFG_SPLIT_MODE BIT(26) 451 + #define WX_PX_RR_CFG_MAX_RSCBUF_16 FIELD_PREP(GENMASK(24, 23), 3) 452 + #define WX_PX_RR_CFG_DESC_MERGE BIT(19) 459 453 #define WX_PX_RR_CFG_RR_THER_SHIFT 16 460 454 #define WX_PX_RR_CFG_RR_HDR_SZ GENMASK(15, 12) 461 455 #define WX_PX_RR_CFG_RR_BUF_SZ GENMASK(11, 8) ··· 554 542 /* Supported Rx Buffer Sizes */ 555 543 #define WX_RXBUFFER_256 256 /* Used for skb receive header */ 556 544 #define WX_RXBUFFER_2K 2048 545 + #define WX_RXBUFFER_3K 3072 557 546 #define WX_MAX_RXBUFFER 16384 /* largest size for single descriptor */ 558 - 559 - #if MAX_SKB_FRAGS < 8 560 - #define WX_RX_BUFSZ ALIGN(WX_MAX_RXBUFFER / MAX_SKB_FRAGS, 1024) 561 - #else 562 - #define WX_RX_BUFSZ WX_RXBUFFER_2K 563 - #endif 564 547 565 548 #define WX_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 566 549 ··· 650 643 651 644 #define WX_RXD_PKTTYPE(_rxd) \ 652 645 ((le32_to_cpu((_rxd)->wb.lower.lo_dword.data) >> 9) & 0xFF) 646 + 647 + #define WX_RXD_RSCCNT_MASK GENMASK(20, 17) 648 + #define WX_RXD_RSCCNT_SHIFT 17 649 + #define WX_RXD_NEXTP_MASK GENMASK(19, 4) 650 + #define WX_RXD_NEXTP_SHIFT 4 651 + 653 652 /*********************** Transmit Descriptor Config Masks ****************/ 654 653 #define WX_TXD_STAT_DD BIT(0) /* Descriptor Done */ 655 654 #define WX_TXD_DTYP_DATA 0 /* Adv Data Descriptor */ ··· 1018 1005 DEFINE_DMA_UNMAP_LEN(len); 1019 1006 __be16 protocol; 1020 1007 u32 tx_flags; 1008 + u32 next_eop; 1021 1009 }; 1022 1010 1023 1011 struct wx_rx_buffer { ··· 1043 1029 u64 csum_good_cnt; 1044 1030 u64 csum_err; 1045 1031 u64 alloc_rx_buff_failed; 1032 + u64 rsc_count; 1033 + u64 rsc_flush; 1046 1034 }; 1047 1035 1048 1036 /* iterator for handling rings in ring container */ ··· 1072 1056 }; 1073 1057 u8 __iomem *tail; 1074 1058 dma_addr_t dma; /* phys. address of descriptor ring */ 1059 + dma_addr_t headwb_dma; 1060 + u32 *headwb_mem; 1075 1061 unsigned int size; /* length in bytes */ 1076 1062 1077 1063 u16 count; /* amount of descriptors */ ··· 1087 1069 */ 1088 1070 u16 next_to_use; 1089 1071 u16 next_to_clean; 1072 + u16 rx_buf_len; 1090 1073 union { 1091 1074 u16 next_to_alloc; 1092 1075 struct { ··· 1244 1225 WX_FLAG_FDIR_HASH, 1245 1226 WX_FLAG_FDIR_PERFECT, 1246 1227 WX_FLAG_RSC_CAPABLE, 1228 + WX_FLAG_RSC_ENABLED, 1247 1229 WX_FLAG_RX_HWTSTAMP_ENABLED, 1248 1230 WX_FLAG_RX_HWTSTAMP_IN_REGISTER, 1249 1231 WX_FLAG_PTP_PPS_ENABLED, ··· 1252 1232 WX_FLAG_NEED_SFP_RESET, 1253 1233 WX_FLAG_NEED_UPDATE_LINK, 1254 1234 WX_FLAG_NEED_DO_RESET, 1235 + WX_FLAG_RX_MERGE_ENABLED, 1236 + WX_FLAG_TXHEAD_WB_ENABLED, 1255 1237 WX_PF_FLAGS_NBITS /* must be last */ 1256 1238 }; 1257 1239 ··· 1360 1338 u64 hw_csum_rx_good; 1361 1339 u64 hw_csum_rx_error; 1362 1340 u64 alloc_rx_buff_failed; 1341 + u64 rsc_count; 1342 + u64 rsc_flush; 1363 1343 unsigned int num_vfs; 1364 1344 struct vf_data_storage *vfinfo; 1365 1345 struct vf_macvlans vf_mvs; ··· 1492 1468 1493 1469 return 0; 1494 1470 } 1471 + 1472 + static inline unsigned int wx_rx_pg_order(struct wx_ring *ring) 1473 + { 1474 + #if (PAGE_SIZE < 8192) 1475 + if (ring->rx_buf_len == WX_RXBUFFER_3K) 1476 + return 1; 1477 + #endif 1478 + return 0; 1479 + } 1480 + 1481 + #define wx_rx_pg_size(_ring) (PAGE_SIZE << wx_rx_pg_order(_ring)) 1495 1482 1496 1483 #endif /* _WX_TYPE_H_ */

+4

drivers/net/ethernet/wangxun/libwx/wx_vf.h

··· 74 74 #define WX_VXRXDCTL_BUFSZ(f) FIELD_PREP(GENMASK(11, 8), f) 75 75 #define WX_VXRXDCTL_HDRSZ_MASK GENMASK(15, 12) 76 76 #define WX_VXRXDCTL_HDRSZ(f) FIELD_PREP(GENMASK(15, 12), f) 77 + #define WX_VXRXDCTL_DESC_MERGE BIT(19) 77 78 #define WX_VXRXDCTL_RSCMAX_MASK GENMASK(24, 23) 78 79 #define WX_VXRXDCTL_RSCMAX(f) FIELD_PREP(GENMASK(24, 23), f) 79 80 #define WX_VXRXDCTL_RSCEN BIT(29) ··· 92 91 #define WX_VXTXDCTL_PTHRESH(f) FIELD_PREP(GENMASK(11, 8), f) 93 92 #define WX_VXTXDCTL_WTHRESH(f) FIELD_PREP(GENMASK(22, 16), f) 94 93 #define WX_VXTXDCTL_FLUSH BIT(26) 94 + #define WX_VXTXDCTL_HEAD_WB BIT(27) 95 + #define WX_VXTXD_HEAD_ADDRL(r) (0x3028 + (0x40 * (r))) 96 + #define WX_VXTXD_HEAD_ADDRH(r) (0x302C + (0x40 * (r))) 95 97 96 98 #define WX_PFLINK_STATUS(g) FIELD_GET(BIT(0), g) 97 99 #define WX_PFLINK_SPEED(g) FIELD_GET(GENMASK(31, 1), g)

+12

drivers/net/ethernet/wangxun/libwx/wx_vf_lib.c

··· 132 132 txdctl |= WX_VXTXDCTL_BUFLEN(wx_buf_len(ring->count)); 133 133 txdctl |= WX_VXTXDCTL_ENABLE; 134 134 135 + if (ring->headwb_mem) { 136 + wr32(wx, WX_VXTXD_HEAD_ADDRL(reg_idx), 137 + ring->headwb_dma & DMA_BIT_MASK(32)); 138 + wr32(wx, WX_VXTXD_HEAD_ADDRH(reg_idx), 139 + upper_32_bits(ring->headwb_dma)); 140 + 141 + txdctl |= WX_VXTXDCTL_HEAD_WB; 142 + } 143 + 135 144 /* reinitialize tx_buffer_info */ 136 145 memset(ring->tx_buffer_info, 0, 137 146 sizeof(struct wx_tx_buffer) * ring->count); ··· 280 271 rxdctl &= ~WX_VXRXDCTL_RSCMAX_MASK; 281 272 rxdctl |= WX_VXRXDCTL_RSCMAX(0); 282 273 rxdctl |= WX_VXRXDCTL_RSCEN; 274 + 275 + if (test_bit(WX_FLAG_RX_MERGE_ENABLED, wx->flags)) 276 + rxdctl |= WX_VXRXDCTL_DESC_MERGE; 283 277 284 278 wr32(wx, WX_VXRXDCTL(reg_idx), rxdctl); 285 279

+5

drivers/net/ethernet/wangxun/txgbe/txgbe_main.c

··· 398 398 wx->configure_fdir = txgbe_configure_fdir; 399 399 400 400 set_bit(WX_FLAG_RSC_CAPABLE, wx->flags); 401 + set_bit(WX_FLAG_RSC_ENABLED, wx->flags); 401 402 set_bit(WX_FLAG_MULTI_64_FUNC, wx->flags); 402 403 403 404 /* enable itr by default in dynamic mode */ ··· 424 423 break; 425 424 case wx_mac_aml: 426 425 case wx_mac_aml40: 426 + set_bit(WX_FLAG_RX_MERGE_ENABLED, wx->flags); 427 + set_bit(WX_FLAG_TXHEAD_WB_ENABLED, wx->flags); 427 428 set_bit(WX_FLAG_SWFW_RING, wx->flags); 428 429 wx->swfw_index = 0; 429 430 break; ··· 804 801 netdev->features |= NETIF_F_HIGHDMA; 805 802 netdev->hw_features |= NETIF_F_GRO; 806 803 netdev->features |= NETIF_F_GRO; 804 + netdev->hw_features |= NETIF_F_LRO; 805 + netdev->features |= NETIF_F_LRO; 807 806 netdev->features |= NETIF_F_RX_UDP_TUNNEL_PORT; 808 807 809 808 netdev->priv_flags |= IFF_UNICAST_FLT;

+12

drivers/net/ethernet/wangxun/txgbevf/txgbevf_main.c

··· 157 157 158 158 wx->set_num_queues = txgbevf_set_num_queues; 159 159 160 + switch (wx->mac.type) { 161 + case wx_mac_sp: 162 + break; 163 + case wx_mac_aml: 164 + case wx_mac_aml40: 165 + set_bit(WX_FLAG_RX_MERGE_ENABLED, wx->flags); 166 + set_bit(WX_FLAG_TXHEAD_WB_ENABLED, wx->flags); 167 + break; 168 + default: 169 + break; 170 + } 171 + 160 172 return 0; 161 173 err_reset_hw: 162 174 kfree(wx->vfinfo);

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