Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: exynos5-usbdrd: gs101: configure SS lanes based on orientation
USB SS lanes need to be configured based on the connector orientation -
at most two lanes will be in use for USB (and the remaining two for
alternate modes like DP).
For the USB link to come up in SS, the lane configuration registers
have to be programmed accordingly.
While we still need a way to be notified of the actual connector
orientation and then reprogram the registers accordingly (at the moment
the configuration happens just once during phy_init() and never again),
we can prepare the code doing the configuration to take the orientation
into account.
Do so.
Note: the mutex is needed to synchronize this with the upcoming
connector orientation callback.
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-5-f5961268b149@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
André Draszik
and committed by
Vinod Koul
0bccdcb3
21860f34
+51
-21
+51
-21
drivers/phy/samsung/phy-exynos5-usbdrd.c
+51
-21
drivers/phy/samsung/phy-exynos5-usbdrd.c
···
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/soc/samsung/exynos-regs-pmu.h>
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#include <linux/usb/typec.h>
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/* Exynos USB PHY registers */
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#define EXYNOS5_FSEL_9MHZ6 0x0
···
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#define EXYNOS9_PMA_USBDP_CMN_REG00B8 0x02e0
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#define CMN_REG00B8_LANE_MUX_SEL_DP GENMASK(3, 0)
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#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE3 BIT(3)
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#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE2 BIT(2)
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#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE1 BIT(1)
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#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE0 BIT(0)
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#define EXYNOS9_PMA_USBDP_CMN_REG01C0 0x0700
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#define CMN_REG01C0_ANA_LCPLL_LOCK_DONE BIT(7)
···
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* @clks: clocks for register access
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* @core_clks: core clocks for phy (ref, pipe3, utmi+, ITP, etc. as required)
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* @drv_data: pointer to SoC level driver data structure
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* @phy_mutex: mutex protecting phy_init/exit & TCPC callbacks
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* @phys: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
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* instances each with its 'phy' and 'phy_cfg'.
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* @extrefclk: frequency select settings when using 'separate
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* reference clocks' for SS and HS operations
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* @regulators: regulators for phy
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* @orientation: TypeC connector orientation - normal or flipped
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*/
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struct exynos5_usbdrd_phy {
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struct device *dev;
···
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struct clk_bulk_data *clks;
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struct clk_bulk_data *core_clks;
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const struct exynos5_usbdrd_phy_drvdata *drv_data;
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struct mutex phy_mutex;
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struct phy_usb_instance {
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struct phy *phy;
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u32 index;
···
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} phys[EXYNOS5_DRDPHYS_NUM];
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u32 extrefclk;
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struct regulator_bulk_data *regulators;
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enum typec_orientation orientation;
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};
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static inline
···
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/* lane configuration: USB on all lanes */
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reg = readl(regs_base + EXYNOS9_PMA_USBDP_CMN_REG00B8);
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reg &= ~CMN_REG00B8_LANE_MUX_SEL_DP;
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/*
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* USB on lanes 0 & 1 in normal mode, or 2 & 3 if reversed, DP on the
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* other ones.
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*/
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reg |= FIELD_PREP(CMN_REG00B8_LANE_MUX_SEL_DP,
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((phy_drd->orientation == TYPEC_ORIENTATION_NORMAL)
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? (CMN_REG00B8_LANE_MUX_SEL_DP_LANE3
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| CMN_REG00B8_LANE_MUX_SEL_DP_LANE2)
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: (CMN_REG00B8_LANE_MUX_SEL_DP_LANE1
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| CMN_REG00B8_LANE_MUX_SEL_DP_LANE0)));
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writel(reg, regs_base + EXYNOS9_PMA_USBDP_CMN_REG00B8);
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/*
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* FIXME: below code supports one connector orientation only. It needs
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* updating once we can receive connector events.
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*/
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/* override of TX receiver detector and comparator: lane 1 */
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reg = readl(regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0413);
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reg &= ~TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN;
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reg &= ~TRSV_REG0413_OVRD_LN1_TX_RXD_EN;
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if (phy_drd->orientation == TYPEC_ORIENTATION_NORMAL) {
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reg &= ~TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN;
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reg &= ~TRSV_REG0413_OVRD_LN1_TX_RXD_EN;
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} else {
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reg |= TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN;
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reg |= TRSV_REG0413_OVRD_LN1_TX_RXD_EN;
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}
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writel(reg, regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0413);
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/* lane 3 */
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reg = readl(regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0813);
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reg |= TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN;
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reg |= TRSV_REG0813_OVRD_LN3_TX_RXD_EN;
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if (phy_drd->orientation == TYPEC_ORIENTATION_NORMAL) {
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reg |= TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN;
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reg |= TRSV_REG0813_OVRD_LN3_TX_RXD_EN;
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} else {
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reg &= ~TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN;
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reg &= ~TRSV_REG0813_OVRD_LN3_TX_RXD_EN;
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}
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writel(reg, regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0813);
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}
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···
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int err;
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err = readl_poll_timeout(
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phy_drd->reg_pma + EXYNOS9_PMA_USBDP_TRSV_REG03C3,
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reg, (reg & locked) == locked, sleep_us, timeout_us);
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if (!err)
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return;
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dev_err(phy_drd->dev,
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"timed out waiting for CDR lock (l0): %#.8x, retrying\n", reg);
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/* based on cable orientation, this might be on the other phy port */
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err = readl_poll_timeout(
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phy_drd->reg_pma + EXYNOS9_PMA_USBDP_TRSV_REG07C3,
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/* lane depends on cable orientation */
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(phy_drd->reg_pma
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+ ((phy_drd->orientation == TYPEC_ORIENTATION_NORMAL)
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? EXYNOS9_PMA_USBDP_TRSV_REG03C3
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: EXYNOS9_PMA_USBDP_TRSV_REG07C3)),
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reg, (reg & locked) == locked, sleep_us, timeout_us);
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if (err)
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dev_err(phy_drd->dev,
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"timed out waiting for CDR lock (l2): %#.8x\n", reg);
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"timed out waiting for CDR(l%d) lock: %#.8x\n",
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((phy_drd->orientation == TYPEC_ORIENTATION_NORMAL)
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? 0
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: 2), reg);
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}
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static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
···
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return ret;
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/* UTMI or PIPE3 specific init */
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inst->phy_cfg->phy_init(phy_drd);
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scoped_guard(mutex, &phy_drd->phy_mutex)
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inst->phy_cfg->phy_init(phy_drd);
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clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
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···
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ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
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if (ret)
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return ret;
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guard(mutex)(&phy_drd->phy_mutex);
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/* Set PHY clock and control HS PHY */
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reg = readl(regs_base + EXYNOS850_DRD_UTMI);
···
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if (!drv_data)
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return -EINVAL;
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phy_drd->drv_data = drv_data;
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ret = devm_mutex_init(dev, &phy_drd->phy_mutex);
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if (ret)
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return ret;
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if (of_property_present(dev->of_node, "reg-names")) {
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void __iomem *reg;