Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'gpio-v5.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO fixes from Linus Walleij:
"Some late GPIO fixes for the v5.9 series:
- Fix compiler warnings on the OMAP when PM is disabled
- Clear the interrupt when setting edge sensitivity on the Spreadtrum
driver.
- Fix up spurious interrupts on the TC35894.
- Support threaded interrupts on the Siox controller.
- Fix resource leaks on the mockup driver.
- Fix line event handling in syscall compatible mode for the
character device.
- Fix an unitialized variable in the PCA953A driver.
- Fix access to all GPIO IRQs on the Aspeed AST2600.
- Fix line direction on the AMD FCH driver.
- Use the bitmap API instead of compiler intrinsics for bit
manipulation in the PCA953x driver"
* tag 'gpio-v5.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio:
gpio: pca953x: Correctly initialize registers 6 and 7 for PCA957x
gpio: pca953x: Use bitmap API over implicit GCC extension
gpio: amd-fch: correct logic of GPIO_LINE_DIRECTION
gpio: aspeed: fix ast2600 bank properties
gpio/aspeed-sgpio: don't enable all interrupts by default
gpio/aspeed-sgpio: enable access to all 80 input & output sgpios
gpio: pca953x: Fix uninitialized pending variable
gpiolib: Fix line event handling in syscall compatible mode
gpio: mockup: fix resource leak in error path
gpio: siox: explicitly support only threaded irqs
gpio: tc35894: fix up tc35894 interrupt configuration
gpio: sprd: Clear interrupt when setting the type as edge
gpio: omap: Fix warnings if PM is disabled
+138
-60
+3
-2
Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
+3
-2
Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
···
20
20
- gpio-controller : Marks the device node as a GPIO controller
21
21
- interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt
22
22
- interrupt-controller : Mark the GPIO controller as an interrupt-controller
23
-
- ngpios : number of GPIO lines, see gpio.txt
24
-
(should be multiple of 8, up to 80 pins)
23
+
- ngpios : number of *hardware* GPIO lines, see gpio.txt. This will expose
24
+
2 software GPIOs per hardware GPIO: one for hardware input, one for hardware
25
+
output. Up to 80 pins, must be a multiple of 8.
25
26
- clocks : A phandle to the APB clock for SGPM clock division
26
27
- bus-frequency : SGPM CLK frequency
27
28
+1
-1
drivers/gpio/gpio-amd-fch.c
+1
-1
drivers/gpio/gpio-amd-fch.c
···
92
92
ret = (readl_relaxed(ptr) & AMD_FCH_GPIO_FLAG_DIRECTION);
93
93
spin_unlock_irqrestore(&priv->lock, flags);
94
94
95
-
return ret ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
95
+
return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
96
96
}
97
97
98
98
static void amd_fch_gpio_set(struct gpio_chip *gc,
+87
-47
drivers/gpio/gpio-aspeed-sgpio.c
+87
-47
drivers/gpio/gpio-aspeed-sgpio.c
···
17
17
#include <linux/spinlock.h>
18
18
#include <linux/string.h>
19
19
20
-
#define MAX_NR_SGPIO 80
20
+
/*
21
+
* MAX_NR_HW_GPIO represents the number of actual hardware-supported GPIOs (ie,
22
+
* slots within the clocked serial GPIO data). Since each HW GPIO is both an
23
+
* input and an output, we provide MAX_NR_HW_GPIO * 2 lines on our gpiochip
24
+
* device.
25
+
*
26
+
* We use SGPIO_OUTPUT_OFFSET to define the split between the inputs and
27
+
* outputs; the inputs start at line 0, the outputs start at OUTPUT_OFFSET.
28
+
*/
29
+
#define MAX_NR_HW_SGPIO 80
30
+
#define SGPIO_OUTPUT_OFFSET MAX_NR_HW_SGPIO
21
31
22
32
#define ASPEED_SGPIO_CTRL 0x54
23
33
···
40
30
struct clk *pclk;
41
31
spinlock_t lock;
42
32
void __iomem *base;
43
-
uint32_t dir_in[3];
44
33
int irq;
34
+
int n_sgpio;
45
35
};
46
36
47
37
struct aspeed_sgpio_bank {
···
121
111
}
122
112
}
123
113
124
-
#define GPIO_BANK(x) ((x) >> 5)
125
-
#define GPIO_OFFSET(x) ((x) & 0x1f)
114
+
#define GPIO_BANK(x) ((x % SGPIO_OUTPUT_OFFSET) >> 5)
115
+
#define GPIO_OFFSET(x) ((x % SGPIO_OUTPUT_OFFSET) & 0x1f)
126
116
#define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
127
117
128
118
static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
129
119
{
130
-
unsigned int bank = GPIO_BANK(offset);
120
+
unsigned int bank;
121
+
122
+
bank = GPIO_BANK(offset);
131
123
132
124
WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
133
125
return &aspeed_sgpio_banks[bank];
126
+
}
127
+
128
+
static int aspeed_sgpio_init_valid_mask(struct gpio_chip *gc,
129
+
unsigned long *valid_mask, unsigned int ngpios)
130
+
{
131
+
struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
132
+
int n = sgpio->n_sgpio;
133
+
int c = SGPIO_OUTPUT_OFFSET - n;
134
+
135
+
WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
136
+
137
+
/* input GPIOs in the lower range */
138
+
bitmap_set(valid_mask, 0, n);
139
+
bitmap_clear(valid_mask, n, c);
140
+
141
+
/* output GPIOS above SGPIO_OUTPUT_OFFSET */
142
+
bitmap_set(valid_mask, SGPIO_OUTPUT_OFFSET, n);
143
+
bitmap_clear(valid_mask, SGPIO_OUTPUT_OFFSET + n, c);
144
+
145
+
return 0;
146
+
}
147
+
148
+
static void aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
149
+
unsigned long *valid_mask, unsigned int ngpios)
150
+
{
151
+
struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
152
+
int n = sgpio->n_sgpio;
153
+
154
+
WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
155
+
156
+
/* input GPIOs in the lower range */
157
+
bitmap_set(valid_mask, 0, n);
158
+
bitmap_clear(valid_mask, n, ngpios - n);
159
+
}
160
+
161
+
static bool aspeed_sgpio_is_input(unsigned int offset)
162
+
{
163
+
return offset < SGPIO_OUTPUT_OFFSET;
134
164
}
135
165
136
166
static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
···
179
129
const struct aspeed_sgpio_bank *bank = to_bank(offset);
180
130
unsigned long flags;
181
131
enum aspeed_sgpio_reg reg;
182
-
bool is_input;
183
132
int rc = 0;
184
133
185
134
spin_lock_irqsave(&gpio->lock, flags);
186
135
187
-
is_input = gpio->dir_in[GPIO_BANK(offset)] & GPIO_BIT(offset);
188
-
reg = is_input ? reg_val : reg_rdata;
136
+
reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
189
137
rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
190
138
191
139
spin_unlock_irqrestore(&gpio->lock, flags);
···
191
143
return rc;
192
144
}
193
145
194
-
static void sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
146
+
static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
195
147
{
196
148
struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
197
149
const struct aspeed_sgpio_bank *bank = to_bank(offset);
198
-
void __iomem *addr;
150
+
void __iomem *addr_r, *addr_w;
199
151
u32 reg = 0;
200
152
201
-
addr = bank_reg(gpio, bank, reg_val);
202
-
reg = ioread32(addr);
153
+
if (aspeed_sgpio_is_input(offset))
154
+
return -EINVAL;
155
+
156
+
/* Since this is an output, read the cached value from rdata, then
157
+
* update val. */
158
+
addr_r = bank_reg(gpio, bank, reg_rdata);
159
+
addr_w = bank_reg(gpio, bank, reg_val);
160
+
161
+
reg = ioread32(addr_r);
203
162
204
163
if (val)
205
164
reg |= GPIO_BIT(offset);
206
165
else
207
166
reg &= ~GPIO_BIT(offset);
208
167
209
-
iowrite32(reg, addr);
168
+
iowrite32(reg, addr_w);
169
+
170
+
return 0;
210
171
}
211
172
212
173
static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
···
232
175
233
176
static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
234
177
{
235
-
struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
236
-
unsigned long flags;
237
-
238
-
spin_lock_irqsave(&gpio->lock, flags);
239
-
gpio->dir_in[GPIO_BANK(offset)] |= GPIO_BIT(offset);
240
-
spin_unlock_irqrestore(&gpio->lock, flags);
241
-
242
-
return 0;
178
+
return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
243
179
}
244
180
245
181
static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
246
182
{
247
183
struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
248
184
unsigned long flags;
185
+
int rc;
186
+
187
+
/* No special action is required for setting the direction; we'll
188
+
* error-out in sgpio_set_value if this isn't an output GPIO */
249
189
250
190
spin_lock_irqsave(&gpio->lock, flags);
251
-
252
-
gpio->dir_in[GPIO_BANK(offset)] &= ~GPIO_BIT(offset);
253
-
sgpio_set_value(gc, offset, val);
254
-
191
+
rc = sgpio_set_value(gc, offset, val);
255
192
spin_unlock_irqrestore(&gpio->lock, flags);
256
193
257
-
return 0;
194
+
return rc;
258
195
}
259
196
260
197
static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
261
198
{
262
-
int dir_status;
263
-
struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
264
-
unsigned long flags;
265
-
266
-
spin_lock_irqsave(&gpio->lock, flags);
267
-
dir_status = gpio->dir_in[GPIO_BANK(offset)] & GPIO_BIT(offset);
268
-
spin_unlock_irqrestore(&gpio->lock, flags);
269
-
270
-
return dir_status;
271
-
199
+
return !!aspeed_sgpio_is_input(offset);
272
200
}
273
201
274
202
static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
···
444
402
445
403
irq = &gpio->chip.irq;
446
404
irq->chip = &aspeed_sgpio_irqchip;
405
+
irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask;
447
406
irq->handler = handle_bad_irq;
448
407
irq->default_type = IRQ_TYPE_NONE;
449
408
irq->parent_handler = aspeed_sgpio_irq_handler;
···
452
409
irq->parents = &gpio->irq;
453
410
irq->num_parents = 1;
454
411
455
-
/* set IRQ settings and Enable Interrupt */
412
+
/* Apply default IRQ settings */
456
413
for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
457
414
bank = &aspeed_sgpio_banks[i];
458
415
/* set falling or level-low irq */
459
416
iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0));
460
417
/* trigger type is edge */
461
418
iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1));
462
-
/* dual edge trigger mode. */
463
-
iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_type2));
464
-
/* enable irq */
465
-
iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_enable));
419
+
/* single edge trigger */
420
+
iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type2));
466
421
}
467
422
468
423
return 0;
···
493
452
if (rc < 0) {
494
453
dev_err(&pdev->dev, "Could not read ngpios property\n");
495
454
return -EINVAL;
496
-
} else if (nr_gpios > MAX_NR_SGPIO) {
455
+
} else if (nr_gpios > MAX_NR_HW_SGPIO) {
497
456
dev_err(&pdev->dev, "Number of GPIOs exceeds the maximum of %d: %d\n",
498
-
MAX_NR_SGPIO, nr_gpios);
457
+
MAX_NR_HW_SGPIO, nr_gpios);
499
458
return -EINVAL;
500
459
}
460
+
gpio->n_sgpio = nr_gpios;
501
461
502
462
rc = of_property_read_u32(pdev->dev.of_node, "bus-frequency", &sgpio_freq);
503
463
if (rc < 0) {
···
539
497
spin_lock_init(&gpio->lock);
540
498
541
499
gpio->chip.parent = &pdev->dev;
542
-
gpio->chip.ngpio = nr_gpios;
500
+
gpio->chip.ngpio = MAX_NR_HW_SGPIO * 2;
501
+
gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask;
543
502
gpio->chip.direction_input = aspeed_sgpio_dir_in;
544
503
gpio->chip.direction_output = aspeed_sgpio_dir_out;
545
504
gpio->chip.get_direction = aspeed_sgpio_get_direction;
···
551
508
gpio->chip.set_config = NULL;
552
509
gpio->chip.label = dev_name(&pdev->dev);
553
510
gpio->chip.base = -1;
554
-
555
-
/* set all SGPIO pins as input (1). */
556
-
memset(gpio->dir_in, 0xff, sizeof(gpio->dir_in));
557
511
558
512
aspeed_sgpio_setup_irqs(gpio, pdev);
559
513
+2
-2
drivers/gpio/gpio-aspeed.c
+2
-2
drivers/gpio/gpio-aspeed.c
···
1114
1114
1115
1115
static const struct aspeed_bank_props ast2600_bank_props[] = {
1116
1116
/* input output */
1117
-
{5, 0xffffffff, 0x0000ffff}, /* U/V/W/X */
1118
-
{6, 0xffff0000, 0x0fff0000}, /* Y/Z */
1117
+
{5, 0xffffffff, 0xffffff00}, /* U/V/W/X */
1118
+
{6, 0x0000ffff, 0x0000ffff}, /* Y/Z */
1119
1119
{ },
1120
1120
};
1121
1121
+2
drivers/gpio/gpio-mockup.c
+2
drivers/gpio/gpio-mockup.c
···
552
552
err = platform_driver_register(&gpio_mockup_driver);
553
553
if (err) {
554
554
gpio_mockup_err("error registering platform driver\n");
555
+
debugfs_remove_recursive(gpio_mockup_dbg_dir);
555
556
return err;
556
557
}
557
558
···
583
582
gpio_mockup_err("error registering device");
584
583
platform_driver_unregister(&gpio_mockup_driver);
585
584
gpio_mockup_unregister_pdevs();
585
+
debugfs_remove_recursive(gpio_mockup_dbg_dir);
586
586
return PTR_ERR(pdev);
587
587
}
588
588
+2
-2
drivers/gpio/gpio-omap.c
+2
-2
drivers/gpio/gpio-omap.c
···
1516
1516
return 0;
1517
1517
}
1518
1518
1519
-
static int omap_gpio_suspend(struct device *dev)
1519
+
static int __maybe_unused omap_gpio_suspend(struct device *dev)
1520
1520
{
1521
1521
struct gpio_bank *bank = dev_get_drvdata(dev);
1522
1522
···
1528
1528
return omap_gpio_runtime_suspend(dev);
1529
1529
}
1530
1530
1531
-
static int omap_gpio_resume(struct device *dev)
1531
+
static int __maybe_unused omap_gpio_resume(struct device *dev)
1532
1532
{
1533
1533
struct gpio_bank *bank = dev_get_drvdata(dev);
1534
1534
+6
-1
drivers/gpio/gpio-pca953x.c
+6
-1
drivers/gpio/gpio-pca953x.c
···
818
818
int level;
819
819
bool ret;
820
820
821
+
bitmap_zero(pending, MAX_LINE);
822
+
821
823
mutex_lock(&chip->i2c_lock);
822
824
ret = pca953x_irq_pending(chip, pending);
823
825
mutex_unlock(&chip->i2c_lock);
···
942
940
static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
943
941
{
944
942
DECLARE_BITMAP(val, MAX_LINE);
943
+
unsigned int i;
945
944
int ret;
946
945
947
946
ret = device_pca95xx_init(chip, invert);
···
950
947
goto out;
951
948
952
949
/* To enable register 6, 7 to control pull up and pull down */
953
-
memset(val, 0x02, NBANK(chip));
950
+
for (i = 0; i < NBANK(chip); i++)
951
+
bitmap_set_value8(val, 0x02, i * BANK_SZ);
952
+
954
953
ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
955
954
if (ret)
956
955
goto out;
+1
drivers/gpio/gpio-siox.c
+1
drivers/gpio/gpio-siox.c
+3
drivers/gpio/gpio-sprd.c
+3
drivers/gpio/gpio-sprd.c
···
149
149
sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
150
150
sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
151
151
sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 1);
152
+
sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
152
153
irq_set_handler_locked(data, handle_edge_irq);
153
154
break;
154
155
case IRQ_TYPE_EDGE_FALLING:
155
156
sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
156
157
sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
157
158
sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 0);
159
+
sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
158
160
irq_set_handler_locked(data, handle_edge_irq);
159
161
break;
160
162
case IRQ_TYPE_EDGE_BOTH:
161
163
sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
162
164
sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 1);
165
+
sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
163
166
irq_set_handler_locked(data, handle_edge_irq);
164
167
break;
165
168
case IRQ_TYPE_LEVEL_HIGH:
+1
-1
drivers/gpio/gpio-tc3589x.c
+1
-1
drivers/gpio/gpio-tc3589x.c
+30
-4
drivers/gpio/gpiolib-cdev.c
+30
-4
drivers/gpio/gpiolib-cdev.c
···
423
423
return events;
424
424
}
425
425
426
+
static ssize_t lineevent_get_size(void)
427
+
{
428
+
#ifdef __x86_64__
429
+
/* i386 has no padding after 'id' */
430
+
if (in_ia32_syscall()) {
431
+
struct compat_gpioeevent_data {
432
+
compat_u64 timestamp;
433
+
u32 id;
434
+
};
435
+
436
+
return sizeof(struct compat_gpioeevent_data);
437
+
}
438
+
#endif
439
+
return sizeof(struct gpioevent_data);
440
+
}
426
441
427
442
static ssize_t lineevent_read(struct file *file,
428
443
char __user *buf,
···
447
432
struct lineevent_state *le = file->private_data;
448
433
struct gpioevent_data ge;
449
434
ssize_t bytes_read = 0;
435
+
ssize_t ge_size;
450
436
int ret;
451
437
452
-
if (count < sizeof(ge))
438
+
/*
439
+
* When compatible system call is being used the struct gpioevent_data,
440
+
* in case of at least ia32, has different size due to the alignment
441
+
* differences. Because we have first member 64 bits followed by one of
442
+
* 32 bits there is no gap between them. The only difference is the
443
+
* padding at the end of the data structure. Hence, we calculate the
444
+
* actual sizeof() and pass this as an argument to copy_to_user() to
445
+
* drop unneeded bytes from the output.
446
+
*/
447
+
ge_size = lineevent_get_size();
448
+
if (count < ge_size)
453
449
return -EINVAL;
454
450
455
451
do {
···
496
470
break;
497
471
}
498
472
499
-
if (copy_to_user(buf + bytes_read, &ge, sizeof(ge)))
473
+
if (copy_to_user(buf + bytes_read, &ge, ge_size))
500
474
return -EFAULT;
501
-
bytes_read += sizeof(ge);
502
-
} while (count >= bytes_read + sizeof(ge));
475
+
bytes_read += ge_size;
476
+
} while (count >= bytes_read + ge_size);
503
477
504
478
return bytes_read;
505
479
}