Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer updates from Thomas Gleixner:
"This updates contains:
- A revert which addresses a boot failure on ARM Sun5i platforms
- A new clocksource driver, which has been delayed beyond rc1 due to
an interrupt driver issue which was unearthed by this driver. The
debugging of that issue and the discussion about the proper
solution made this driver miss the merge window. There is no point
in delaying it for a full cycle as it completes the basic mainline
support for the new JCore platform and does not create any risk
outside of that platform"
* 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
Revert "clocksource/drivers/timer_sun5i: Replace code by clocksource_mmio_init"
clocksource: Add J-Core timer/clocksource driver
of: Add J-Core timer bindings
+299
-2
+24
Documentation/devicetree/bindings/timer/jcore,pit.txt
+24
Documentation/devicetree/bindings/timer/jcore,pit.txt
···
1
+
J-Core Programmable Interval Timer and Clocksource
2
+
3
+
Required properties:
4
+
5
+
- compatible: Must be "jcore,pit".
6
+
7
+
- reg: Memory region(s) for timer/clocksource registers. For SMP,
8
+
there should be one region per cpu, indexed by the sequential,
9
+
zero-based hardware cpu number.
10
+
11
+
- interrupts: An interrupt to assign for the timer. The actual pit
12
+
core is integrated with the aic and allows the timer interrupt
13
+
assignment to be programmed by software, but this property is
14
+
required in order to reserve an interrupt number that doesn't
15
+
conflict with other devices.
16
+
17
+
18
+
Example:
19
+
20
+
timer@200 {
21
+
compatible = "jcore,pit";
22
+
reg = < 0x200 0x30 0x500 0x30 >;
23
+
interrupts = < 0x48 >;
24
+
};
+10
drivers/clocksource/Kconfig
+10
drivers/clocksource/Kconfig
···
417
417
config SYS_SUPPORTS_EM_STI
418
418
bool
419
419
420
+
config CLKSRC_JCORE_PIT
421
+
bool "J-Core PIT timer driver" if COMPILE_TEST
422
+
depends on OF
423
+
depends on GENERIC_CLOCKEVENTS
424
+
depends on HAS_IOMEM
425
+
select CLKSRC_MMIO
426
+
help
427
+
This enables build of clocksource and clockevent driver for
428
+
the integrated PIT in the J-Core synthesizable, open source SoC.
429
+
420
430
config SH_TIMER_CMT
421
431
bool "Renesas CMT timer driver" if COMPILE_TEST
422
432
depends on GENERIC_CLOCKEVENTS
+1
drivers/clocksource/Makefile
+1
drivers/clocksource/Makefile
···
5
5
obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
6
6
obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
7
7
obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += cs5535-clockevt.o
8
+
obj-$(CONFIG_CLKSRC_JCORE_PIT) += jcore-pit.o
8
9
obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o
9
10
obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o
10
11
obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o
+249
drivers/clocksource/jcore-pit.c
+249
drivers/clocksource/jcore-pit.c
···
1
+
/*
2
+
* J-Core SoC PIT/clocksource driver
3
+
*
4
+
* Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
5
+
*
6
+
* This file is subject to the terms and conditions of the GNU General Public
7
+
* License. See the file "COPYING" in the main directory of this archive
8
+
* for more details.
9
+
*/
10
+
11
+
#include <linux/kernel.h>
12
+
#include <linux/slab.h>
13
+
#include <linux/interrupt.h>
14
+
#include <linux/clockchips.h>
15
+
#include <linux/clocksource.h>
16
+
#include <linux/sched_clock.h>
17
+
#include <linux/cpu.h>
18
+
#include <linux/cpuhotplug.h>
19
+
#include <linux/of_address.h>
20
+
#include <linux/of_irq.h>
21
+
22
+
#define PIT_IRQ_SHIFT 12
23
+
#define PIT_PRIO_SHIFT 20
24
+
#define PIT_ENABLE_SHIFT 26
25
+
#define PIT_PRIO_MASK 0xf
26
+
27
+
#define REG_PITEN 0x00
28
+
#define REG_THROT 0x10
29
+
#define REG_COUNT 0x14
30
+
#define REG_BUSPD 0x18
31
+
#define REG_SECHI 0x20
32
+
#define REG_SECLO 0x24
33
+
#define REG_NSEC 0x28
34
+
35
+
struct jcore_pit {
36
+
struct clock_event_device ced;
37
+
void __iomem *base;
38
+
unsigned long periodic_delta;
39
+
u32 enable_val;
40
+
};
41
+
42
+
static void __iomem *jcore_pit_base;
43
+
static struct jcore_pit __percpu *jcore_pit_percpu;
44
+
45
+
static notrace u64 jcore_sched_clock_read(void)
46
+
{
47
+
u32 seclo, nsec, seclo0;
48
+
__iomem void *base = jcore_pit_base;
49
+
50
+
seclo = readl(base + REG_SECLO);
51
+
do {
52
+
seclo0 = seclo;
53
+
nsec = readl(base + REG_NSEC);
54
+
seclo = readl(base + REG_SECLO);
55
+
} while (seclo0 != seclo);
56
+
57
+
return seclo * NSEC_PER_SEC + nsec;
58
+
}
59
+
60
+
static cycle_t jcore_clocksource_read(struct clocksource *cs)
61
+
{
62
+
return jcore_sched_clock_read();
63
+
}
64
+
65
+
static int jcore_pit_disable(struct jcore_pit *pit)
66
+
{
67
+
writel(0, pit->base + REG_PITEN);
68
+
return 0;
69
+
}
70
+
71
+
static int jcore_pit_set(unsigned long delta, struct jcore_pit *pit)
72
+
{
73
+
jcore_pit_disable(pit);
74
+
writel(delta, pit->base + REG_THROT);
75
+
writel(pit->enable_val, pit->base + REG_PITEN);
76
+
return 0;
77
+
}
78
+
79
+
static int jcore_pit_set_state_shutdown(struct clock_event_device *ced)
80
+
{
81
+
struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
82
+
83
+
return jcore_pit_disable(pit);
84
+
}
85
+
86
+
static int jcore_pit_set_state_oneshot(struct clock_event_device *ced)
87
+
{
88
+
struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
89
+
90
+
return jcore_pit_disable(pit);
91
+
}
92
+
93
+
static int jcore_pit_set_state_periodic(struct clock_event_device *ced)
94
+
{
95
+
struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
96
+
97
+
return jcore_pit_set(pit->periodic_delta, pit);
98
+
}
99
+
100
+
static int jcore_pit_set_next_event(unsigned long delta,
101
+
struct clock_event_device *ced)
102
+
{
103
+
struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
104
+
105
+
return jcore_pit_set(delta, pit);
106
+
}
107
+
108
+
static int jcore_pit_local_init(unsigned cpu)
109
+
{
110
+
struct jcore_pit *pit = this_cpu_ptr(jcore_pit_percpu);
111
+
unsigned buspd, freq;
112
+
113
+
pr_info("Local J-Core PIT init on cpu %u\n", cpu);
114
+
115
+
buspd = readl(pit->base + REG_BUSPD);
116
+
freq = DIV_ROUND_CLOSEST(NSEC_PER_SEC, buspd);
117
+
pit->periodic_delta = DIV_ROUND_CLOSEST(NSEC_PER_SEC, HZ * buspd);
118
+
119
+
clockevents_config_and_register(&pit->ced, freq, 1, ULONG_MAX);
120
+
121
+
return 0;
122
+
}
123
+
124
+
static irqreturn_t jcore_timer_interrupt(int irq, void *dev_id)
125
+
{
126
+
struct jcore_pit *pit = this_cpu_ptr(dev_id);
127
+
128
+
if (clockevent_state_oneshot(&pit->ced))
129
+
jcore_pit_disable(pit);
130
+
131
+
pit->ced.event_handler(&pit->ced);
132
+
133
+
return IRQ_HANDLED;
134
+
}
135
+
136
+
static int __init jcore_pit_init(struct device_node *node)
137
+
{
138
+
int err;
139
+
unsigned pit_irq, cpu;
140
+
unsigned long hwirq;
141
+
u32 irqprio, enable_val;
142
+
143
+
jcore_pit_base = of_iomap(node, 0);
144
+
if (!jcore_pit_base) {
145
+
pr_err("Error: Cannot map base address for J-Core PIT\n");
146
+
return -ENXIO;
147
+
}
148
+
149
+
pit_irq = irq_of_parse_and_map(node, 0);
150
+
if (!pit_irq) {
151
+
pr_err("Error: J-Core PIT has no IRQ\n");
152
+
return -ENXIO;
153
+
}
154
+
155
+
pr_info("Initializing J-Core PIT at %p IRQ %d\n",
156
+
jcore_pit_base, pit_irq);
157
+
158
+
err = clocksource_mmio_init(jcore_pit_base, "jcore_pit_cs",
159
+
NSEC_PER_SEC, 400, 32,
160
+
jcore_clocksource_read);
161
+
if (err) {
162
+
pr_err("Error registering clocksource device: %d\n", err);
163
+
return err;
164
+
}
165
+
166
+
sched_clock_register(jcore_sched_clock_read, 32, NSEC_PER_SEC);
167
+
168
+
jcore_pit_percpu = alloc_percpu(struct jcore_pit);
169
+
if (!jcore_pit_percpu) {
170
+
pr_err("Failed to allocate memory for clock event device\n");
171
+
return -ENOMEM;
172
+
}
173
+
174
+
err = request_irq(pit_irq, jcore_timer_interrupt,
175
+
IRQF_TIMER | IRQF_PERCPU,
176
+
"jcore_pit", jcore_pit_percpu);
177
+
if (err) {
178
+
pr_err("pit irq request failed: %d\n", err);
179
+
free_percpu(jcore_pit_percpu);
180
+
return err;
181
+
}
182
+
183
+
/*
184
+
* The J-Core PIT is not hard-wired to a particular IRQ, but
185
+
* integrated with the interrupt controller such that the IRQ it
186
+
* generates is programmable, as follows:
187
+
*
188
+
* The bit layout of the PIT enable register is:
189
+
*
190
+
* .....e..ppppiiiiiiii............
191
+
*
192
+
* where the .'s indicate unrelated/unused bits, e is enable,
193
+
* p is priority, and i is hard irq number.
194
+
*
195
+
* For the PIT included in AIC1 (obsolete but still in use),
196
+
* any hard irq (trap number) can be programmed via the 8
197
+
* iiiiiiii bits, and a priority (0-15) is programmable
198
+
* separately in the pppp bits.
199
+
*
200
+
* For the PIT included in AIC2 (current), the programming
201
+
* interface is equivalent modulo interrupt mapping. This is
202
+
* why a different compatible tag was not used. However only
203
+
* traps 64-127 (the ones actually intended to be used for
204
+
* interrupts, rather than syscalls/exceptions/etc.) can be
205
+
* programmed (the high 2 bits of i are ignored) and the
206
+
* priority pppp is <<2'd and or'd onto the irq number. This
207
+
* choice seems to have been made on the hardware engineering
208
+
* side under an assumption that preserving old AIC1 priority
209
+
* mappings was important. Future models will likely ignore
210
+
* the pppp field.
211
+
*/
212
+
hwirq = irq_get_irq_data(pit_irq)->hwirq;
213
+
irqprio = (hwirq >> 2) & PIT_PRIO_MASK;
214
+
enable_val = (1U << PIT_ENABLE_SHIFT)
215
+
| (hwirq << PIT_IRQ_SHIFT)
216
+
| (irqprio << PIT_PRIO_SHIFT);
217
+
218
+
for_each_present_cpu(cpu) {
219
+
struct jcore_pit *pit = per_cpu_ptr(jcore_pit_percpu, cpu);
220
+
221
+
pit->base = of_iomap(node, cpu);
222
+
if (!pit->base) {
223
+
pr_err("Unable to map PIT for cpu %u\n", cpu);
224
+
continue;
225
+
}
226
+
227
+
pit->ced.name = "jcore_pit";
228
+
pit->ced.features = CLOCK_EVT_FEAT_PERIODIC
229
+
| CLOCK_EVT_FEAT_ONESHOT
230
+
| CLOCK_EVT_FEAT_PERCPU;
231
+
pit->ced.cpumask = cpumask_of(cpu);
232
+
pit->ced.rating = 400;
233
+
pit->ced.irq = pit_irq;
234
+
pit->ced.set_state_shutdown = jcore_pit_set_state_shutdown;
235
+
pit->ced.set_state_periodic = jcore_pit_set_state_periodic;
236
+
pit->ced.set_state_oneshot = jcore_pit_set_state_oneshot;
237
+
pit->ced.set_next_event = jcore_pit_set_next_event;
238
+
239
+
pit->enable_val = enable_val;
240
+
}
241
+
242
+
cpuhp_setup_state(CPUHP_AP_JCORE_TIMER_STARTING,
243
+
"AP_JCORE_TIMER_STARTING",
244
+
jcore_pit_local_init, NULL);
245
+
246
+
return 0;
247
+
}
248
+
249
+
CLOCKSOURCE_OF_DECLARE(jcore_pit, "jcore,pit", jcore_pit_init);
+14
-2
drivers/clocksource/timer-sun5i.c
+14
-2
drivers/clocksource/timer-sun5i.c
···
152
152
return IRQ_HANDLED;
153
153
}
154
154
155
+
static cycle_t sun5i_clksrc_read(struct clocksource *clksrc)
156
+
{
157
+
struct sun5i_timer_clksrc *cs = to_sun5i_timer_clksrc(clksrc);
158
+
159
+
return ~readl(cs->timer.base + TIMER_CNTVAL_LO_REG(1));
160
+
}
161
+
155
162
static int sun5i_rate_cb_clksrc(struct notifier_block *nb,
156
163
unsigned long event, void *data)
157
164
{
···
217
210
writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
218
211
base + TIMER_CTL_REG(1));
219
212
220
-
ret = clocksource_mmio_init(base + TIMER_CNTVAL_LO_REG(1), node->name,
221
-
rate, 340, 32, clocksource_mmio_readl_down);
213
+
cs->clksrc.name = node->name;
214
+
cs->clksrc.rating = 340;
215
+
cs->clksrc.read = sun5i_clksrc_read;
216
+
cs->clksrc.mask = CLOCKSOURCE_MASK(32);
217
+
cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
218
+
219
+
ret = clocksource_register_hz(&cs->clksrc, rate);
222
220
if (ret) {
223
221
pr_err("Couldn't register clock source.\n");
224
222
goto err_remove_notifier;
+1
include/linux/cpuhotplug.h
+1
include/linux/cpuhotplug.h