Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6

+9

arch/x86/pci/acpi.c

··· 360 360 } 361 361 } 362 362 363 + /* After the PCI-E bus has been walked and all devices discovered, 364 + * configure any settings of the fabric that might be necessary. 365 + */ 366 + if (bus) { 367 + struct pci_bus *child; 368 + list_for_each_entry(child, &bus->children, node) 369 + pcie_bus_configure_settings(child, child->self->pcie_mpss); 370 + } 371 + 363 372 if (!bus) 364 373 kfree(sd); 365 374

+1 -44

drivers/pci/hotplug/pcihp_slot.c

··· 158 158 */ 159 159 } 160 160 161 - /* Program PCIE MaxPayload setting on device: ensure parent maxpayload <= device */ 162 - static int pci_set_payload(struct pci_dev *dev) 163 - { 164 - int pos, ppos; 165 - u16 pctl, psz; 166 - u16 dctl, dsz, dcap, dmax; 167 - struct pci_dev *parent; 168 - 169 - parent = dev->bus->self; 170 - pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 171 - if (!pos) 172 - return 0; 173 - 174 - /* Read Device MaxPayload capability and setting */ 175 - pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &dctl); 176 - pci_read_config_word(dev, pos + PCI_EXP_DEVCAP, &dcap); 177 - dsz = (dctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5; 178 - dmax = (dcap & PCI_EXP_DEVCAP_PAYLOAD); 179 - 180 - /* Read Parent MaxPayload setting */ 181 - ppos = pci_find_capability(parent, PCI_CAP_ID_EXP); 182 - if (!ppos) 183 - return 0; 184 - pci_read_config_word(parent, ppos + PCI_EXP_DEVCTL, &pctl); 185 - psz = (pctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5; 186 - 187 - /* If parent payload > device max payload -> error 188 - * If parent payload > device payload -> set speed 189 - * If parent payload <= device payload -> do nothing 190 - */ 191 - if (psz > dmax) 192 - return -1; 193 - else if (psz > dsz) { 194 - dev_info(&dev->dev, "Setting MaxPayload to %d\n", 128 << psz); 195 - pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, 196 - (dctl & ~PCI_EXP_DEVCTL_PAYLOAD) + 197 - (psz << 5)); 198 - } 199 - return 0; 200 - } 201 - 202 161 void pci_configure_slot(struct pci_dev *dev) 203 162 { 204 163 struct pci_dev *cdev; ··· 169 210 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI))) 170 211 return; 171 212 172 - ret = pci_set_payload(dev); 173 - if (ret) 174 - dev_warn(&dev->dev, "could not set device max payload\n"); 213 + pcie_bus_configure_settings(dev->bus, dev->bus->self->pcie_mpss); 175 214 176 215 memset(&hpp, 0, sizeof(hpp)); 177 216 ret = pci_get_hp_params(dev, &hpp);

+1 -1

drivers/pci/of.c

··· 55 55 */ 56 56 if (bus->bridge->of_node) 57 57 return of_node_get(bus->bridge->of_node); 58 - if (bus->bridge->parent->of_node) 58 + if (bus->bridge->parent && bus->bridge->parent->of_node) 59 59 return of_node_get(bus->bridge->parent->of_node); 60 60 return NULL; 61 61 }

+67

drivers/pci/pci.c

··· 77 77 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; 78 78 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; 79 79 80 + enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE; 81 + 80 82 /* 81 83 * The default CLS is used if arch didn't set CLS explicitly and not 82 84 * all pci devices agree on the same value. Arch can override either ··· 3225 3223 EXPORT_SYMBOL(pcie_set_readrq); 3226 3224 3227 3225 /** 3226 + * pcie_get_mps - get PCI Express maximum payload size 3227 + * @dev: PCI device to query 3228 + * 3229 + * Returns maximum payload size in bytes 3230 + * or appropriate error value. 3231 + */ 3232 + int pcie_get_mps(struct pci_dev *dev) 3233 + { 3234 + int ret, cap; 3235 + u16 ctl; 3236 + 3237 + cap = pci_pcie_cap(dev); 3238 + if (!cap) 3239 + return -EINVAL; 3240 + 3241 + ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); 3242 + if (!ret) 3243 + ret = 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 3244 + 3245 + return ret; 3246 + } 3247 + 3248 + /** 3249 + * pcie_set_mps - set PCI Express maximum payload size 3250 + * @dev: PCI device to query 3251 + * @rq: maximum payload size in bytes 3252 + * valid values are 128, 256, 512, 1024, 2048, 4096 3253 + * 3254 + * If possible sets maximum payload size 3255 + */ 3256 + int pcie_set_mps(struct pci_dev *dev, int mps) 3257 + { 3258 + int cap, err = -EINVAL; 3259 + u16 ctl, v; 3260 + 3261 + if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) 3262 + goto out; 3263 + 3264 + v = ffs(mps) - 8; 3265 + if (v > dev->pcie_mpss) 3266 + goto out; 3267 + v <<= 5; 3268 + 3269 + cap = pci_pcie_cap(dev); 3270 + if (!cap) 3271 + goto out; 3272 + 3273 + err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); 3274 + if (err) 3275 + goto out; 3276 + 3277 + if ((ctl & PCI_EXP_DEVCTL_PAYLOAD) != v) { 3278 + ctl &= ~PCI_EXP_DEVCTL_PAYLOAD; 3279 + ctl |= v; 3280 + err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl); 3281 + } 3282 + out: 3283 + return err; 3284 + } 3285 + 3286 + /** 3228 3287 * pci_select_bars - Make BAR mask from the type of resource 3229 3288 * @dev: the PCI device for which BAR mask is made 3230 3289 * @flags: resource type mask to be selected ··· 3568 3505 pci_hotplug_io_size = memparse(str + 9, &str); 3569 3506 } else if (!strncmp(str, "hpmemsize=", 10)) { 3570 3507 pci_hotplug_mem_size = memparse(str + 10, &str); 3508 + } else if (!strncmp(str, "pcie_bus_safe", 13)) { 3509 + pcie_bus_config = PCIE_BUS_SAFE; 3510 + } else if (!strncmp(str, "pcie_bus_perf", 13)) { 3511 + pcie_bus_config = PCIE_BUS_PERFORMANCE; 3571 3512 } else { 3572 3513 printk(KERN_ERR "PCI: Unknown option `%s'\n", 3573 3514 str);

+4

drivers/pci/pci.h

··· 283 283 284 284 #endif /* CONFIG_PCI_IOV */ 285 285 286 + extern unsigned long pci_cardbus_resource_alignment(struct resource *); 287 + 286 288 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 287 289 struct resource *res) 288 290 { ··· 294 292 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 295 293 return pci_sriov_resource_alignment(dev, resno); 296 294 #endif 295 + if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 296 + return pci_cardbus_resource_alignment(res); 297 297 return resource_alignment(res); 298 298 } 299 299

+146

drivers/pci/probe.c

··· 856 856 pdev->pcie_cap = pos; 857 857 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16); 858 858 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; 859 + pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16); 860 + pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 859 861 } 860 862 861 863 void set_pcie_hotplug_bridge(struct pci_dev *pdev) ··· 1327 1325 1328 1326 return nr; 1329 1327 } 1328 + 1329 + static int pcie_find_smpss(struct pci_dev *dev, void *data) 1330 + { 1331 + u8 *smpss = data; 1332 + 1333 + if (!pci_is_pcie(dev)) 1334 + return 0; 1335 + 1336 + /* For PCIE hotplug enabled slots not connected directly to a 1337 + * PCI-E root port, there can be problems when hotplugging 1338 + * devices. This is due to the possibility of hotplugging a 1339 + * device into the fabric with a smaller MPS that the devices 1340 + * currently running have configured. Modifying the MPS on the 1341 + * running devices could cause a fatal bus error due to an 1342 + * incoming frame being larger than the newly configured MPS. 1343 + * To work around this, the MPS for the entire fabric must be 1344 + * set to the minimum size. Any devices hotplugged into this 1345 + * fabric will have the minimum MPS set. If the PCI hotplug 1346 + * slot is directly connected to the root port and there are not 1347 + * other devices on the fabric (which seems to be the most 1348 + * common case), then this is not an issue and MPS discovery 1349 + * will occur as normal. 1350 + */ 1351 + if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) || 1352 + dev->bus->self->pcie_type != PCI_EXP_TYPE_ROOT_PORT)) 1353 + *smpss = 0; 1354 + 1355 + if (*smpss > dev->pcie_mpss) 1356 + *smpss = dev->pcie_mpss; 1357 + 1358 + return 0; 1359 + } 1360 + 1361 + static void pcie_write_mps(struct pci_dev *dev, int mps) 1362 + { 1363 + int rc, dev_mpss; 1364 + 1365 + dev_mpss = 128 << dev->pcie_mpss; 1366 + 1367 + if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 1368 + if (dev->bus->self) { 1369 + dev_dbg(&dev->bus->dev, "Bus MPSS %d\n", 1370 + 128 << dev->bus->self->pcie_mpss); 1371 + 1372 + /* For "MPS Force Max", the assumption is made that 1373 + * downstream communication will never be larger than 1374 + * the MRRS. So, the MPS only needs to be configured 1375 + * for the upstream communication. This being the case, 1376 + * walk from the top down and set the MPS of the child 1377 + * to that of the parent bus. 1378 + */ 1379 + mps = 128 << dev->bus->self->pcie_mpss; 1380 + if (mps > dev_mpss) 1381 + dev_warn(&dev->dev, "MPS configured higher than" 1382 + " maximum supported by the device. If" 1383 + " a bus issue occurs, try running with" 1384 + " pci=pcie_bus_safe.\n"); 1385 + } 1386 + 1387 + dev->pcie_mpss = ffs(mps) - 8; 1388 + } 1389 + 1390 + rc = pcie_set_mps(dev, mps); 1391 + if (rc) 1392 + dev_err(&dev->dev, "Failed attempting to set the MPS\n"); 1393 + } 1394 + 1395 + static void pcie_write_mrrs(struct pci_dev *dev, int mps) 1396 + { 1397 + int rc, mrrs; 1398 + 1399 + if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 1400 + int dev_mpss = 128 << dev->pcie_mpss; 1401 + 1402 + /* For Max performance, the MRRS must be set to the largest 1403 + * supported value. However, it cannot be configured larger 1404 + * than the MPS the device or the bus can support. This assumes 1405 + * that the largest MRRS available on the device cannot be 1406 + * smaller than the device MPSS. 1407 + */ 1408 + mrrs = mps < dev_mpss ? mps : dev_mpss; 1409 + } else 1410 + /* In the "safe" case, configure the MRRS for fairness on the 1411 + * bus by making all devices have the same size 1412 + */ 1413 + mrrs = mps; 1414 + 1415 + 1416 + /* MRRS is a R/W register. Invalid values can be written, but a 1417 + * subsiquent read will verify if the value is acceptable or not. 1418 + * If the MRRS value provided is not acceptable (e.g., too large), 1419 + * shrink the value until it is acceptable to the HW. 1420 + */ 1421 + while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 1422 + rc = pcie_set_readrq(dev, mrrs); 1423 + if (rc) 1424 + dev_err(&dev->dev, "Failed attempting to set the MRRS\n"); 1425 + 1426 + mrrs /= 2; 1427 + } 1428 + } 1429 + 1430 + static int pcie_bus_configure_set(struct pci_dev *dev, void *data) 1431 + { 1432 + int mps = 128 << *(u8 *)data; 1433 + 1434 + if (!pci_is_pcie(dev)) 1435 + return 0; 1436 + 1437 + dev_info(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n", 1438 + pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev)); 1439 + 1440 + pcie_write_mps(dev, mps); 1441 + pcie_write_mrrs(dev, mps); 1442 + 1443 + dev_info(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n", 1444 + pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev)); 1445 + 1446 + return 0; 1447 + } 1448 + 1449 + /* pcie_bus_configure_mps requires that pci_walk_bus work in a top-down, 1450 + * parents then children fashion. If this changes, then this code will not 1451 + * work as designed. 1452 + */ 1453 + void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss) 1454 + { 1455 + u8 smpss = mpss; 1456 + 1457 + if (!bus->self) 1458 + return; 1459 + 1460 + if (!pci_is_pcie(bus->self)) 1461 + return; 1462 + 1463 + if (pcie_bus_config == PCIE_BUS_SAFE) { 1464 + pcie_find_smpss(bus->self, &smpss); 1465 + pci_walk_bus(bus, pcie_find_smpss, &smpss); 1466 + } 1467 + 1468 + pcie_bus_configure_set(bus->self, &smpss); 1469 + pci_walk_bus(bus, pcie_bus_configure_set, &smpss); 1470 + } 1471 + EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); 1330 1472 1331 1473 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) 1332 1474 {

+116 -50

drivers/pci/setup-bus.c

··· 34 34 resource_size_t start; 35 35 resource_size_t end; 36 36 resource_size_t add_size; 37 + resource_size_t min_align; 37 38 unsigned long flags; 38 39 }; 39 40 ··· 66 65 */ 67 66 static void add_to_list(struct resource_list_x *head, 68 67 struct pci_dev *dev, struct resource *res, 69 - resource_size_t add_size) 68 + resource_size_t add_size, resource_size_t min_align) 70 69 { 71 70 struct resource_list_x *list = head; 72 71 struct resource_list_x *ln = list->next; ··· 85 84 tmp->end = res->end; 86 85 tmp->flags = res->flags; 87 86 tmp->add_size = add_size; 87 + tmp->min_align = min_align; 88 88 list->next = tmp; 89 89 } 90 90 91 91 static void add_to_failed_list(struct resource_list_x *head, 92 92 struct pci_dev *dev, struct resource *res) 93 93 { 94 - add_to_list(head, dev, res, 0); 94 + add_to_list(head, dev, res, 95 + 0 /* dont care */, 96 + 0 /* dont care */); 95 97 } 96 98 97 99 static void __dev_sort_resources(struct pci_dev *dev, ··· 125 121 } 126 122 127 123 /** 128 - * adjust_resources_sorted() - satisfy any additional resource requests 124 + * reassign_resources_sorted() - satisfy any additional resource requests 129 125 * 130 - * @add_head : head of the list tracking requests requiring additional 126 + * @realloc_head : head of the list tracking requests requiring additional 131 127 * resources 132 128 * @head : head of the list tracking requests with allocated 133 129 * resources 134 130 * 135 - * Walk through each element of the add_head and try to procure 131 + * Walk through each element of the realloc_head and try to procure 136 132 * additional resources for the element, provided the element 137 133 * is in the head list. 138 134 */ 139 - static void adjust_resources_sorted(struct resource_list_x *add_head, 135 + static void reassign_resources_sorted(struct resource_list_x *realloc_head, 140 136 struct resource_list *head) 141 137 { 142 138 struct resource *res; ··· 145 141 resource_size_t add_size; 146 142 int idx; 147 143 148 - prev = add_head; 149 - for (list = add_head->next; list;) { 144 + prev = realloc_head; 145 + for (list = realloc_head->next; list;) { 150 146 res = list->res; 151 147 /* skip resource that has been reset */ 152 148 if (!res->flags) ··· 163 159 164 160 idx = res - &list->dev->resource[0]; 165 161 add_size=list->add_size; 166 - if (!resource_size(res) && add_size) { 167 - res->end = res->start + add_size - 1; 168 - if(pci_assign_resource(list->dev, idx)) 162 + if (!resource_size(res)) { 163 + res->start = list->start; 164 + res->end = res->start + add_size - 1; 165 + if(pci_assign_resource(list->dev, idx)) 169 166 reset_resource(res); 170 - } else if (add_size) { 171 - adjust_resource(res, res->start, 172 - resource_size(res) + add_size); 167 + } else { 168 + resource_size_t align = list->min_align; 169 + res->flags |= list->flags & (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); 170 + if (pci_reassign_resource(list->dev, idx, add_size, align)) 171 + dev_printk(KERN_DEBUG, &list->dev->dev, "failed to add optional resources res=%pR\n", 172 + res); 173 173 } 174 174 out: 175 175 tmp = list; ··· 218 210 } 219 211 220 212 static void __assign_resources_sorted(struct resource_list *head, 221 - struct resource_list_x *add_head, 213 + struct resource_list_x *realloc_head, 222 214 struct resource_list_x *fail_head) 223 215 { 224 216 /* Satisfy the must-have resource requests */ 225 217 assign_requested_resources_sorted(head, fail_head); 226 218 227 - /* Try to satisfy any additional nice-to-have resource 219 + /* Try to satisfy any additional optional resource 228 220 requests */ 229 - if (add_head) 230 - adjust_resources_sorted(add_head, head); 221 + if (realloc_head) 222 + reassign_resources_sorted(realloc_head, head); 231 223 free_list(resource_list, head); 232 224 } 233 225 ··· 243 235 } 244 236 245 237 static void pbus_assign_resources_sorted(const struct pci_bus *bus, 246 - struct resource_list_x *add_head, 238 + struct resource_list_x *realloc_head, 247 239 struct resource_list_x *fail_head) 248 240 { 249 241 struct pci_dev *dev; ··· 253 245 list_for_each_entry(dev, &bus->devices, bus_list) 254 246 __dev_sort_resources(dev, &head); 255 247 256 - __assign_resources_sorted(&head, add_head, fail_head); 248 + __assign_resources_sorted(&head, realloc_head, fail_head); 257 249 } 258 250 259 251 void pci_setup_cardbus(struct pci_bus *bus) ··· 548 540 return size; 549 541 } 550 542 543 + static resource_size_t get_res_add_size(struct resource_list_x *realloc_head, 544 + struct resource *res) 545 + { 546 + struct resource_list_x *list; 547 + 548 + /* check if it is in realloc_head list */ 549 + for (list = realloc_head->next; list && list->res != res; 550 + list = list->next); 551 + if (list) 552 + return list->add_size; 553 + 554 + return 0; 555 + } 556 + 551 557 /** 552 558 * pbus_size_io() - size the io window of a given bus 553 559 * 554 560 * @bus : the bus 555 561 * @min_size : the minimum io window that must to be allocated 556 562 * @add_size : additional optional io window 557 - * @add_head : track the additional io window on this list 563 + * @realloc_head : track the additional io window on this list 558 564 * 559 565 * Sizing the IO windows of the PCI-PCI bridge is trivial, 560 566 * since these windows have 4K granularity and the IO ranges ··· 576 554 * We must be careful with the ISA aliasing though. 577 555 */ 578 556 static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, 579 - resource_size_t add_size, struct resource_list_x *add_head) 557 + resource_size_t add_size, struct resource_list_x *realloc_head) 580 558 { 581 559 struct pci_dev *dev; 582 560 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); 583 561 unsigned long size = 0, size0 = 0, size1 = 0; 562 + resource_size_t children_add_size = 0; 584 563 585 564 if (!b_res) 586 565 return; ··· 602 579 size += r_size; 603 580 else 604 581 size1 += r_size; 582 + 583 + if (realloc_head) 584 + children_add_size += get_res_add_size(realloc_head, r); 605 585 } 606 586 } 607 587 size0 = calculate_iosize(size, min_size, size1, 608 588 resource_size(b_res), 4096); 609 - size1 = (!add_head || (add_head && !add_size)) ? size0 : 589 + if (children_add_size > add_size) 590 + add_size = children_add_size; 591 + size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : 610 592 calculate_iosize(size, min_size+add_size, size1, 611 593 resource_size(b_res), 4096); 612 594 if (!size0 && !size1) { ··· 626 598 b_res->start = 4096; 627 599 b_res->end = b_res->start + size0 - 1; 628 600 b_res->flags |= IORESOURCE_STARTALIGN; 629 - if (size1 > size0 && add_head) 630 - add_to_list(add_head, bus->self, b_res, size1-size0); 601 + if (size1 > size0 && realloc_head) 602 + add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096); 631 603 } 632 604 633 605 /** ··· 636 608 * @bus : the bus 637 609 * @min_size : the minimum memory window that must to be allocated 638 610 * @add_size : additional optional memory window 639 - * @add_head : track the additional memory window on this list 611 + * @realloc_head : track the additional memory window on this list 640 612 * 641 613 * Calculate the size of the bus and minimal alignment which 642 614 * guarantees that all child resources fit in this size. ··· 644 616 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, 645 617 unsigned long type, resource_size_t min_size, 646 618 resource_size_t add_size, 647 - struct resource_list_x *add_head) 619 + struct resource_list_x *realloc_head) 648 620 { 649 621 struct pci_dev *dev; 650 622 resource_size_t min_align, align, size, size0, size1; ··· 652 624 int order, max_order; 653 625 struct resource *b_res = find_free_bus_resource(bus, type); 654 626 unsigned int mem64_mask = 0; 627 + resource_size_t children_add_size = 0; 655 628 656 629 if (!b_res) 657 630 return 0; ··· 674 645 if (r->parent || (r->flags & mask) != type) 675 646 continue; 676 647 r_size = resource_size(r); 648 + #ifdef CONFIG_PCI_IOV 649 + /* put SRIOV requested res to the optional list */ 650 + if (realloc_head && i >= PCI_IOV_RESOURCES && 651 + i <= PCI_IOV_RESOURCE_END) { 652 + r->end = r->start - 1; 653 + add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */); 654 + children_add_size += r_size; 655 + continue; 656 + } 657 + #endif 677 658 /* For bridges size != alignment */ 678 659 align = pci_resource_alignment(dev, r); 679 660 order = __ffs(align) - 20; ··· 704 665 if (order > max_order) 705 666 max_order = order; 706 667 mem64_mask &= r->flags & IORESOURCE_MEM_64; 668 + 669 + if (realloc_head) 670 + children_add_size += get_res_add_size(realloc_head, r); 707 671 } 708 672 } 709 673 align = 0; ··· 723 681 align += aligns[order]; 724 682 } 725 683 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align); 726 - size1 = (!add_head || (add_head && !add_size)) ? size0 : 684 + if (children_add_size > add_size) 685 + add_size = children_add_size; 686 + size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : 727 687 calculate_memsize(size, min_size+add_size, 0, 728 688 resource_size(b_res), min_align); 729 689 if (!size0 && !size1) { ··· 739 695 b_res->start = min_align; 740 696 b_res->end = size0 + min_align - 1; 741 697 b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask; 742 - if (size1 > size0 && add_head) 743 - add_to_list(add_head, bus->self, b_res, size1-size0); 698 + if (size1 > size0 && realloc_head) 699 + add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align); 744 700 return 1; 745 701 } 746 702 747 - static void pci_bus_size_cardbus(struct pci_bus *bus) 703 + unsigned long pci_cardbus_resource_alignment(struct resource *res) 704 + { 705 + if (res->flags & IORESOURCE_IO) 706 + return pci_cardbus_io_size; 707 + if (res->flags & IORESOURCE_MEM) 708 + return pci_cardbus_mem_size; 709 + return 0; 710 + } 711 + 712 + static void pci_bus_size_cardbus(struct pci_bus *bus, 713 + struct resource_list_x *realloc_head) 748 714 { 749 715 struct pci_dev *bridge = bus->self; 750 716 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; ··· 765 711 * a fixed amount of bus space for CardBus bridges. 766 712 */ 767 713 b_res[0].start = 0; 768 - b_res[0].end = pci_cardbus_io_size - 1; 769 714 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; 715 + if (realloc_head) 716 + add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, 0 /* dont care */); 770 717 771 718 b_res[1].start = 0; 772 - b_res[1].end = pci_cardbus_io_size - 1; 773 719 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; 720 + if (realloc_head) 721 + add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, 0 /* dont care */); 774 722 775 723 /* 776 724 * Check whether prefetchable memory is supported ··· 792 736 */ 793 737 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { 794 738 b_res[2].start = 0; 795 - b_res[2].end = pci_cardbus_mem_size - 1; 796 739 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN; 740 + if (realloc_head) 741 + add_to_list(realloc_head, bridge, b_res+2, pci_cardbus_mem_size, 0 /* dont care */); 797 742 798 743 b_res[3].start = 0; 799 - b_res[3].end = pci_cardbus_mem_size - 1; 800 744 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; 745 + if (realloc_head) 746 + add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size, 0 /* dont care */); 801 747 } else { 802 748 b_res[3].start = 0; 803 - b_res[3].end = pci_cardbus_mem_size * 2 - 1; 804 749 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; 750 + if (realloc_head) 751 + add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size * 2, 0 /* dont care */); 805 752 } 753 + 754 + /* set the size of the resource to zero, so that the resource does not 755 + * get assigned during required-resource allocation cycle but gets assigned 756 + * during the optional-resource allocation cycle. 757 + */ 758 + b_res[0].start = b_res[1].start = b_res[2].start = b_res[3].start = 1; 759 + b_res[0].end = b_res[1].end = b_res[2].end = b_res[3].end = 0; 806 760 } 807 761 808 762 void __ref __pci_bus_size_bridges(struct pci_bus *bus, 809 - struct resource_list_x *add_head) 763 + struct resource_list_x *realloc_head) 810 764 { 811 765 struct pci_dev *dev; 812 766 unsigned long mask, prefmask; ··· 829 763 830 764 switch (dev->class >> 8) { 831 765 case PCI_CLASS_BRIDGE_CARDBUS: 832 - pci_bus_size_cardbus(b); 766 + pci_bus_size_cardbus(b, realloc_head); 833 767 break; 834 768 835 769 case PCI_CLASS_BRIDGE_PCI: 836 770 default: 837 - __pci_bus_size_bridges(b, add_head); 771 + __pci_bus_size_bridges(b, realloc_head); 838 772 break; 839 773 } 840 774 } ··· 858 792 * Follow thru 859 793 */ 860 794 default: 861 - pbus_size_io(bus, 0, additional_io_size, add_head); 795 + pbus_size_io(bus, 0, additional_io_size, realloc_head); 862 796 /* If the bridge supports prefetchable range, size it 863 797 separately. If it doesn't, or its prefetchable window 864 798 has already been allocated by arch code, try ··· 866 800 resources. */ 867 801 mask = IORESOURCE_MEM; 868 802 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; 869 - if (pbus_size_mem(bus, prefmask, prefmask, 0, additional_mem_size, add_head)) 803 + if (pbus_size_mem(bus, prefmask, prefmask, 0, additional_mem_size, realloc_head)) 870 804 mask = prefmask; /* Success, size non-prefetch only. */ 871 805 else 872 806 additional_mem_size += additional_mem_size; 873 - pbus_size_mem(bus, mask, IORESOURCE_MEM, 0, additional_mem_size, add_head); 807 + pbus_size_mem(bus, mask, IORESOURCE_MEM, 0, additional_mem_size, realloc_head); 874 808 break; 875 809 } 876 810 } ··· 882 816 EXPORT_SYMBOL(pci_bus_size_bridges); 883 817 884 818 static void __ref __pci_bus_assign_resources(const struct pci_bus *bus, 885 - struct resource_list_x *add_head, 819 + struct resource_list_x *realloc_head, 886 820 struct resource_list_x *fail_head) 887 821 { 888 822 struct pci_bus *b; 889 823 struct pci_dev *dev; 890 824 891 - pbus_assign_resources_sorted(bus, add_head, fail_head); 825 + pbus_assign_resources_sorted(bus, realloc_head, fail_head); 892 826 893 827 list_for_each_entry(dev, &bus->devices, bus_list) { 894 828 b = dev->subordinate; 895 829 if (!b) 896 830 continue; 897 831 898 - __pci_bus_assign_resources(b, add_head, fail_head); 832 + __pci_bus_assign_resources(b, realloc_head, fail_head); 899 833 900 834 switch (dev->class >> 8) { 901 835 case PCI_CLASS_BRIDGE_PCI: ··· 1105 1039 pci_assign_unassigned_resources(void) 1106 1040 { 1107 1041 struct pci_bus *bus; 1108 - struct resource_list_x add_list; /* list of resources that 1042 + struct resource_list_x realloc_list; /* list of resources that 1109 1043 want additional resources */ 1110 1044 int tried_times = 0; 1111 1045 enum release_type rel_type = leaf_only; ··· 1118 1052 1119 1053 1120 1054 head.next = NULL; 1121 - add_list.next = NULL; 1055 + realloc_list.next = NULL; 1122 1056 1123 1057 pci_try_num = max_depth + 1; 1124 1058 printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n", ··· 1128 1062 /* Depth first, calculate sizes and alignments of all 1129 1063 subordinate buses. */ 1130 1064 list_for_each_entry(bus, &pci_root_buses, node) 1131 - __pci_bus_size_bridges(bus, &add_list); 1065 + __pci_bus_size_bridges(bus, &realloc_list); 1132 1066 1133 1067 /* Depth last, allocate resources and update the hardware. */ 1134 1068 list_for_each_entry(bus, &pci_root_buses, node) 1135 - __pci_bus_assign_resources(bus, &add_list, &head); 1136 - BUG_ON(add_list.next); 1069 + __pci_bus_assign_resources(bus, &realloc_list, &head); 1070 + BUG_ON(realloc_list.next); 1137 1071 tried_times++; 1138 1072 1139 1073 /* any device complain? */

+99 -61

drivers/pci/setup-res.c

··· 128 128 } 129 129 #endif /* CONFIG_PCI_QUIRKS */ 130 130 131 + 132 + 131 133 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, 132 - int resno) 134 + int resno, resource_size_t size, resource_size_t align) 133 135 { 134 136 struct resource *res = dev->resource + resno; 135 - resource_size_t size, min, align; 137 + resource_size_t min; 136 138 int ret; 137 139 138 - size = resource_size(res); 139 140 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; 140 - align = pci_resource_alignment(dev, res); 141 141 142 142 /* First, try exact prefetching match.. */ 143 143 ret = pci_bus_alloc_resource(bus, res, size, align, min, ··· 154 154 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0, 155 155 pcibios_align_resource, dev); 156 156 } 157 - 158 - if (ret < 0 && dev->fw_addr[resno]) { 159 - struct resource *root, *conflict; 160 - resource_size_t start, end; 161 - 162 - /* 163 - * If we failed to assign anything, let's try the address 164 - * where firmware left it. That at least has a chance of 165 - * working, which is better than just leaving it disabled. 166 - */ 167 - 168 - if (res->flags & IORESOURCE_IO) 169 - root = &ioport_resource; 170 - else 171 - root = &iomem_resource; 172 - 173 - start = res->start; 174 - end = res->end; 175 - res->start = dev->fw_addr[resno]; 176 - res->end = res->start + size - 1; 177 - dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n", 178 - resno, res); 179 - conflict = request_resource_conflict(root, res); 180 - if (conflict) { 181 - dev_info(&dev->dev, 182 - "BAR %d: %pR conflicts with %s %pR\n", resno, 183 - res, conflict->name, conflict); 184 - res->start = start; 185 - res->end = end; 186 - } else 187 - ret = 0; 188 - } 189 - 190 - if (!ret) { 191 - res->flags &= ~IORESOURCE_STARTALIGN; 192 - dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res); 193 - if (resno < PCI_BRIDGE_RESOURCES) 194 - pci_update_resource(dev, resno); 195 - } 196 - 197 157 return ret; 198 158 } 199 159 200 - int pci_assign_resource(struct pci_dev *dev, int resno) 160 + static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, 161 + int resno, resource_size_t size) 162 + { 163 + struct resource *root, *conflict; 164 + resource_size_t start, end; 165 + int ret = 0; 166 + 167 + if (res->flags & IORESOURCE_IO) 168 + root = &ioport_resource; 169 + else 170 + root = &iomem_resource; 171 + 172 + start = res->start; 173 + end = res->end; 174 + res->start = dev->fw_addr[resno]; 175 + res->end = res->start + size - 1; 176 + dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n", 177 + resno, res); 178 + conflict = request_resource_conflict(root, res); 179 + if (conflict) { 180 + dev_info(&dev->dev, 181 + "BAR %d: %pR conflicts with %s %pR\n", resno, 182 + res, conflict->name, conflict); 183 + res->start = start; 184 + res->end = end; 185 + ret = 1; 186 + } 187 + return ret; 188 + } 189 + 190 + static int _pci_assign_resource(struct pci_dev *dev, int resno, int size, resource_size_t min_align) 201 191 { 202 192 struct resource *res = dev->resource + resno; 203 - resource_size_t align; 204 193 struct pci_bus *bus; 205 194 int ret; 206 195 char *type; 207 196 208 - align = pci_resource_alignment(dev, res); 209 - if (!align) { 210 - dev_info(&dev->dev, "BAR %d: can't assign %pR " 211 - "(bogus alignment)\n", resno, res); 212 - return -EINVAL; 213 - } 214 - 215 197 bus = dev->bus; 216 - while ((ret = __pci_assign_resource(bus, dev, resno))) { 217 - if (bus->parent && bus->self->transparent) 218 - bus = bus->parent; 219 - else 220 - bus = NULL; 221 - if (bus) 222 - continue; 223 - break; 198 + while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) { 199 + if (!bus->parent || !bus->self->transparent) 200 + break; 201 + bus = bus->parent; 224 202 } 225 203 226 204 if (ret) { ··· 218 240 219 241 return ret; 220 242 } 243 + 244 + int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize, 245 + resource_size_t min_align) 246 + { 247 + struct resource *res = dev->resource + resno; 248 + resource_size_t new_size; 249 + int ret; 250 + 251 + if (!res->parent) { 252 + dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resouce %pR " 253 + "\n", resno, res); 254 + return -EINVAL; 255 + } 256 + 257 + new_size = resource_size(res) + addsize + min_align; 258 + ret = _pci_assign_resource(dev, resno, new_size, min_align); 259 + if (!ret) { 260 + res->flags &= ~IORESOURCE_STARTALIGN; 261 + dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res); 262 + if (resno < PCI_BRIDGE_RESOURCES) 263 + pci_update_resource(dev, resno); 264 + } 265 + return ret; 266 + } 267 + 268 + int pci_assign_resource(struct pci_dev *dev, int resno) 269 + { 270 + struct resource *res = dev->resource + resno; 271 + resource_size_t align, size; 272 + struct pci_bus *bus; 273 + int ret; 274 + 275 + align = pci_resource_alignment(dev, res); 276 + if (!align) { 277 + dev_info(&dev->dev, "BAR %d: can't assign %pR " 278 + "(bogus alignment)\n", resno, res); 279 + return -EINVAL; 280 + } 281 + 282 + bus = dev->bus; 283 + size = resource_size(res); 284 + ret = _pci_assign_resource(dev, resno, size, align); 285 + 286 + /* 287 + * If we failed to assign anything, let's try the address 288 + * where firmware left it. That at least has a chance of 289 + * working, which is better than just leaving it disabled. 290 + */ 291 + if (ret < 0 && dev->fw_addr[resno]) 292 + ret = pci_revert_fw_address(res, dev, resno, size); 293 + 294 + if (!ret) { 295 + res->flags &= ~IORESOURCE_STARTALIGN; 296 + dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res); 297 + if (resno < PCI_BRIDGE_RESOURCES) 298 + pci_update_resource(dev, resno); 299 + } 300 + return ret; 301 + } 302 + 221 303 222 304 /* Sort resources by alignment */ 223 305 void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)

+15 -1

include/linux/pci.h

··· 251 251 u8 revision; /* PCI revision, low byte of class word */ 252 252 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 253 253 u8 pcie_cap; /* PCI-E capability offset */ 254 - u8 pcie_type; /* PCI-E device/port type */ 254 + u8 pcie_type:4; /* PCI-E device/port type */ 255 + u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ 255 256 u8 rom_base_reg; /* which config register controls the ROM */ 256 257 u8 pin; /* which interrupt pin this device uses */ 257 258 ··· 618 617 /* these external functions are only available when PCI support is enabled */ 619 618 #ifdef CONFIG_PCI 620 619 620 + extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss); 621 + 622 + enum pcie_bus_config_types { 623 + PCIE_BUS_PERFORMANCE, 624 + PCIE_BUS_SAFE, 625 + PCIE_BUS_PEER2PEER, 626 + }; 627 + 628 + extern enum pcie_bus_config_types pcie_bus_config; 629 + 621 630 extern struct bus_type pci_bus_type; 622 631 623 632 /* Do NOT directly access these two variables, unless you are arch specific pci ··· 807 796 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 808 797 int pcie_get_readrq(struct pci_dev *dev); 809 798 int pcie_set_readrq(struct pci_dev *dev, int rq); 799 + int pcie_get_mps(struct pci_dev *dev); 800 + int pcie_set_mps(struct pci_dev *dev, int mps); 810 801 int __pci_reset_function(struct pci_dev *dev); 811 802 int pci_reset_function(struct pci_dev *dev); 812 803 void pci_update_resource(struct pci_dev *dev, int resno); 813 804 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 805 + int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 814 806 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 815 807 816 808 /* ROM control related routines */

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