Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm exynos/intel updates from Dave Airlie:
"Two minor updates from Jesse for Intel SNB fixes, and a few fixes from
Samsung for exynos. The pull req has Alan's commit in it since Intel
based their tree on my tree at that time, but it all seems fine wrt
merging."
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm exynos: use drm_fb_helper_set_par directly
drm/exynos: Fix fb_videomode <-> drm_mode_modeinfo conversion
drm/exynos: fix runtime_pm fimd device state on probe
drm/exynos: use correct 'exynos-drm' name for platform device
drm/i915: support 32 bit BGR formats in sprite planes
drm/i915: fix color order for BGR formats on SNB
drm/gma500: Fix Cedarview boot failures in 3.3-rc
+21
-51
+8
-8
drivers/gpu/drm/exynos/exynos_drm_connector.c
+8
-8
drivers/gpu/drm/exynos/exynos_drm_connector.c
···
54
54
mode->vrefresh = timing->refresh;
55
55
56
56
mode->hdisplay = timing->xres;
57
-
mode->hsync_start = mode->hdisplay + timing->left_margin;
57
+
mode->hsync_start = mode->hdisplay + timing->right_margin;
58
58
mode->hsync_end = mode->hsync_start + timing->hsync_len;
59
-
mode->htotal = mode->hsync_end + timing->right_margin;
59
+
mode->htotal = mode->hsync_end + timing->left_margin;
60
60
61
61
mode->vdisplay = timing->yres;
62
-
mode->vsync_start = mode->vdisplay + timing->upper_margin;
62
+
mode->vsync_start = mode->vdisplay + timing->lower_margin;
63
63
mode->vsync_end = mode->vsync_start + timing->vsync_len;
64
-
mode->vtotal = mode->vsync_end + timing->lower_margin;
64
+
mode->vtotal = mode->vsync_end + timing->upper_margin;
65
65
mode->width_mm = panel->width_mm;
66
66
mode->height_mm = panel->height_mm;
67
67
···
85
85
timing->refresh = drm_mode_vrefresh(mode);
86
86
87
87
timing->xres = mode->hdisplay;
88
-
timing->left_margin = mode->hsync_start - mode->hdisplay;
88
+
timing->right_margin = mode->hsync_start - mode->hdisplay;
89
89
timing->hsync_len = mode->hsync_end - mode->hsync_start;
90
-
timing->right_margin = mode->htotal - mode->hsync_end;
90
+
timing->left_margin = mode->htotal - mode->hsync_end;
91
91
92
92
timing->yres = mode->vdisplay;
93
-
timing->upper_margin = mode->vsync_start - mode->vdisplay;
93
+
timing->lower_margin = mode->vsync_start - mode->vdisplay;
94
94
timing->vsync_len = mode->vsync_end - mode->vsync_start;
95
-
timing->lower_margin = mode->vtotal - mode->vsync_end;
95
+
timing->upper_margin = mode->vtotal - mode->vsync_end;
96
96
97
97
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
98
98
timing->vmode = FB_VMODE_INTERLACED;
+1
-1
drivers/gpu/drm/exynos/exynos_drm_drv.c
+1
-1
drivers/gpu/drm/exynos/exynos_drm_drv.c
+1
-27
drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+1
-27
drivers/gpu/drm/exynos/exynos_drm_fbdev.c
···
46
46
struct exynos_drm_gem_obj *exynos_gem_obj;
47
47
};
48
48
49
-
static int exynos_drm_fbdev_set_par(struct fb_info *info)
50
-
{
51
-
struct fb_var_screeninfo *var = &info->var;
52
-
53
-
switch (var->bits_per_pixel) {
54
-
case 32:
55
-
case 24:
56
-
case 18:
57
-
case 16:
58
-
case 12:
59
-
info->fix.visual = FB_VISUAL_TRUECOLOR;
60
-
break;
61
-
case 1:
62
-
info->fix.visual = FB_VISUAL_MONO01;
63
-
break;
64
-
default:
65
-
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
66
-
break;
67
-
}
68
-
69
-
info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
70
-
71
-
return drm_fb_helper_set_par(info);
72
-
}
73
-
74
-
75
49
static struct fb_ops exynos_drm_fb_ops = {
76
50
.owner = THIS_MODULE,
77
51
.fb_fillrect = cfb_fillrect,
78
52
.fb_copyarea = cfb_copyarea,
79
53
.fb_imageblit = cfb_imageblit,
80
54
.fb_check_var = drm_fb_helper_check_var,
81
-
.fb_set_par = exynos_drm_fbdev_set_par,
55
+
.fb_set_par = drm_fb_helper_set_par,
82
56
.fb_blank = drm_fb_helper_blank,
83
57
.fb_pan_display = drm_fb_helper_pan_display,
84
58
.fb_setcmap = drm_fb_helper_setcmap,
+6
-11
drivers/gpu/drm/exynos/exynos_drm_fimd.c
+6
-11
drivers/gpu/drm/exynos/exynos_drm_fimd.c
···
817
817
goto err_clk_get;
818
818
}
819
819
820
-
clk_enable(ctx->bus_clk);
821
-
822
820
ctx->lcd_clk = clk_get(dev, "sclk_fimd");
823
821
if (IS_ERR(ctx->lcd_clk)) {
824
822
dev_err(dev, "failed to get lcd clock\n");
825
823
ret = PTR_ERR(ctx->lcd_clk);
826
824
goto err_bus_clk;
827
825
}
828
-
829
-
clk_enable(ctx->lcd_clk);
830
826
831
827
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
832
828
if (!res) {
···
860
864
goto err_req_irq;
861
865
}
862
866
863
-
ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing);
864
867
ctx->vidcon0 = pdata->vidcon0;
865
868
ctx->vidcon1 = pdata->vidcon1;
866
869
ctx->default_win = pdata->default_win;
867
870
ctx->panel = panel;
868
-
869
-
panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
870
-
871
-
DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
872
-
panel->timing.pixclock, ctx->clkdiv);
873
871
874
872
subdrv = &ctx->subdrv;
875
873
···
879
889
880
890
platform_set_drvdata(pdev, ctx);
881
891
882
-
pm_runtime_set_active(dev);
883
892
pm_runtime_enable(dev);
884
893
pm_runtime_get_sync(dev);
894
+
895
+
ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing);
896
+
panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
897
+
898
+
DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
899
+
panel->timing.pixclock, ctx->clkdiv);
885
900
886
901
for (win = 0; win < WINDOWS_NR; win++)
887
902
fimd_clear_win(ctx, win);
+1
-1
drivers/gpu/drm/i915/i915_reg.h
+1
-1
drivers/gpu/drm/i915/i915_reg.h
···
2689
2689
#define DVS_FORMAT_RGBX888 (2<<25)
2690
2690
#define DVS_FORMAT_RGBX161616 (3<<25)
2691
2691
#define DVS_SOURCE_KEY (1<<22)
2692
-
#define DVS_RGB_ORDER_RGBX (1<<20)
2692
+
#define DVS_RGB_ORDER_XBGR (1<<20)
2693
2693
#define DVS_YUV_BYTE_ORDER_MASK (3<<16)
2694
2694
#define DVS_YUV_ORDER_YUYV (0<<16)
2695
2695
#define DVS_YUV_ORDER_UYVY (1<<16)
+1
drivers/gpu/drm/i915/intel_display.c
+1
drivers/gpu/drm/i915/intel_display.c
+3
-3
drivers/gpu/drm/i915/intel_sprite.c
+3
-3
drivers/gpu/drm/i915/intel_sprite.c
···
225
225
226
226
/* Mask out pixel format bits in case we change it */
227
227
dvscntr &= ~DVS_PIXFORMAT_MASK;
228
-
dvscntr &= ~DVS_RGB_ORDER_RGBX;
228
+
dvscntr &= ~DVS_RGB_ORDER_XBGR;
229
229
dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
230
230
231
231
switch (fb->pixel_format) {
232
232
case DRM_FORMAT_XBGR8888:
233
-
dvscntr |= DVS_FORMAT_RGBX888;
233
+
dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
234
234
pixel_size = 4;
235
235
break;
236
236
case DRM_FORMAT_XRGB8888:
237
-
dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_RGBX;
237
+
dvscntr |= DVS_FORMAT_RGBX888;
238
238
pixel_size = 4;
239
239
break;
240
240
case DRM_FORMAT_YUYV: