+4 -3

Documentation/thermal/nouveau_thermal

reviewed

··· 4 4 Supported chips: 5 5 * NV43+ 6 6 7 7 - Authors: Martin Peres (mupuf) <martin.peres@labri.fr> 7 7 + Authors: Martin Peres (mupuf) <martin.peres@free.fr> 8 8 9 9 Description 10 10 --------- ··· 68 68 69 69 NOTE: Be sure to use the manual mode if you want to drive the fan speed manually 70 70 71 71 - NOTE2: Not all fan management modes may be supported on all chipsets. We are 72 72 - working on it. 71 71 + NOTE2: When operating in manual mode outside the vbios-defined 72 72 + [PWM_min, PWM_max] range, the reported fan speed (RPM) may not be accurate 73 73 + depending on your hardware. 73 74 74 75 Bug reports 75 76 ---------

+1

drivers/gpu/drm/drm_modeset_lock.c

reviewed

··· 64 64 void drm_modeset_acquire_init(struct drm_modeset_acquire_ctx *ctx, 65 65 uint32_t flags) 66 66 { 67 67 + memset(ctx, 0, sizeof(*ctx)); 67 68 ww_acquire_init(&ctx->ww_ctx, &crtc_ww_class); 68 69 INIT_LIST_HEAD(&ctx->locked); 69 70 }

+42 -5

drivers/gpu/drm/i915/i915_dma.c

reviewed

··· 36 36 #include "i915_drv.h" 37 37 #include "i915_trace.h" 38 38 #include <linux/pci.h> 39 39 + #include <linux/console.h> 40 40 + #include <linux/vt.h> 39 41 #include <linux/vgaarb.h> 40 42 #include <linux/acpi.h> 41 43 #include <linux/pnp.h> ··· 1388 1386 i915_gem_context_fini(dev); 1389 1387 mutex_unlock(&dev->struct_mutex); 1390 1388 WARN_ON(dev_priv->mm.aliasing_ppgtt); 1391 1391 - drm_mm_takedown(&dev_priv->gtt.base.mm); 1392 1389 cleanup_irq: 1393 1390 drm_irq_uninstall(dev); 1394 1391 cleanup_gem_stolen: ··· 1448 1447 #else 1449 1448 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) 1450 1449 { 1450 1450 + } 1451 1451 + #endif 1452 1452 + 1453 1453 + #if !defined(CONFIG_VGA_CONSOLE) 1454 1454 + static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) 1455 1455 + { 1456 1456 + return 0; 1457 1457 + } 1458 1458 + #elif !defined(CONFIG_DUMMY_CONSOLE) 1459 1459 + static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) 1460 1460 + { 1461 1461 + return -ENODEV; 1462 1462 + } 1463 1463 + #else 1464 1464 + static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv) 1465 1465 + { 1466 1466 + int ret; 1467 1467 + 1468 1468 + DRM_INFO("Replacing VGA console driver\n"); 1469 1469 + 1470 1470 + console_lock(); 1471 1471 + ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1); 1472 1472 + if (ret == 0) { 1473 1473 + ret = do_unregister_con_driver(&vga_con); 1474 1474 + 1475 1475 + /* Ignore "already unregistered". */ 1476 1476 + if (ret == -ENODEV) 1477 1477 + ret = 0; 1478 1478 + } 1479 1479 + console_unlock(); 1480 1480 + 1481 1481 + return ret; 1451 1482 } 1452 1483 #endif 1453 1484 ··· 1656 1623 if (ret) 1657 1624 goto out_regs; 1658 1625 1659 1659 - if (drm_core_check_feature(dev, DRIVER_MODESET)) 1626 1626 + if (drm_core_check_feature(dev, DRIVER_MODESET)) { 1627 1627 + ret = i915_kick_out_vgacon(dev_priv); 1628 1628 + if (ret) { 1629 1629 + DRM_ERROR("failed to remove conflicting VGA console\n"); 1630 1630 + goto out_gtt; 1631 1631 + } 1632 1632 + 1660 1633 i915_kick_out_firmware_fb(dev_priv); 1634 1634 + } 1661 1635 1662 1636 pci_set_master(dev->pdev); 1663 1637 ··· 1796 1756 arch_phys_wc_del(dev_priv->gtt.mtrr); 1797 1757 io_mapping_free(dev_priv->gtt.mappable); 1798 1758 out_gtt: 1799 1799 - list_del(&dev_priv->gtt.base.global_link); 1800 1800 - drm_mm_takedown(&dev_priv->gtt.base.mm); 1801 1759 dev_priv->gtt.base.cleanup(&dev_priv->gtt.base); 1802 1760 out_regs: 1803 1761 intel_uncore_fini(dev); ··· 1884 1846 i915_free_hws(dev); 1885 1847 } 1886 1848 1887 1887 - list_del(&dev_priv->gtt.base.global_link); 1888 1849 WARN_ON(!list_empty(&dev_priv->vm_list)); 1889 1850 1890 1851 drm_vblank_cleanup(dev);

+8 -1

drivers/gpu/drm/i915/i915_gem_gtt.c

reviewed

··· 1992 1992 1993 1993 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); 1994 1994 1995 1995 - drm_mm_takedown(&vm->mm); 1995 1995 + if (drm_mm_initialized(&vm->mm)) { 1996 1996 + drm_mm_takedown(&vm->mm); 1997 1997 + list_del(&vm->global_link); 1998 1998 + } 1996 1999 iounmap(gtt->gsm); 1997 2000 teardown_scratch_page(vm->dev); 1998 2001 } ··· 2028 2025 2029 2026 static void i915_gmch_remove(struct i915_address_space *vm) 2030 2027 { 2028 2028 + if (drm_mm_initialized(&vm->mm)) { 2029 2029 + drm_mm_takedown(&vm->mm); 2030 2030 + list_del(&vm->global_link); 2031 2031 + } 2031 2032 intel_gmch_remove(); 2032 2033 } 2033 2034

+2 -1

drivers/gpu/drm/i915/i915_gpu_error.c

reviewed

··· 888 888 for (i = 0; i < I915_NUM_RINGS; i++) { 889 889 struct intel_engine_cs *ring = &dev_priv->ring[i]; 890 890 891 891 + error->ring[i].pid = -1; 892 892 + 891 893 if (ring->dev == NULL) 892 894 continue; 893 895 ··· 897 895 898 896 i915_record_ring_state(dev, ring, &error->ring[i]); 899 897 900 900 - error->ring[i].pid = -1; 901 898 request = i915_gem_find_active_request(ring); 902 899 if (request) { 903 900 /* We need to copy these to an anonymous buffer

+14 -4

drivers/gpu/drm/i915/i915_irq.c

reviewed

··· 2847 2847 struct intel_engine_cs *signaller; 2848 2848 u32 seqno, ctl; 2849 2849 2850 2850 - ring->hangcheck.deadlock = true; 2850 2850 + ring->hangcheck.deadlock++; 2851 2851 2852 2852 signaller = semaphore_waits_for(ring, &seqno); 2853 2853 - if (signaller == NULL || signaller->hangcheck.deadlock) 2853 2853 + if (signaller == NULL) 2854 2854 + return -1; 2855 2855 + 2856 2856 + /* Prevent pathological recursion due to driver bugs */ 2857 2857 + if (signaller->hangcheck.deadlock >= I915_NUM_RINGS) 2854 2858 return -1; 2855 2859 2856 2860 /* cursory check for an unkickable deadlock */ ··· 2862 2858 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) 2863 2859 return -1; 2864 2860 2865 2865 - return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); 2861 2861 + if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno)) 2862 2862 + return 1; 2863 2863 + 2864 2864 + if (signaller->hangcheck.deadlock) 2865 2865 + return -1; 2866 2866 + 2867 2867 + return 0; 2866 2868 } 2867 2869 2868 2870 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) ··· 2877 2867 int i; 2878 2868 2879 2869 for_each_ring(ring, dev_priv, i) 2880 2880 - ring->hangcheck.deadlock = false; 2870 2870 + ring->hangcheck.deadlock = 0; 2881 2871 } 2882 2872 2883 2873 static enum intel_ring_hangcheck_action

+2 -3

drivers/gpu/drm/i915/intel_panel.c

reviewed

··· 798 798 ctl = freq << 16; 799 799 I915_WRITE(BLC_PWM_CTL, ctl); 800 800 801 801 - /* XXX: combine this into above write? */ 802 802 - intel_panel_actually_set_backlight(connector, panel->backlight.level); 803 803 - 804 801 ctl2 = BLM_PIPE(pipe); 805 802 if (panel->backlight.combination_mode) 806 803 ctl2 |= BLM_COMBINATION_MODE; ··· 806 809 I915_WRITE(BLC_PWM_CTL2, ctl2); 807 810 POSTING_READ(BLC_PWM_CTL2); 808 811 I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); 812 812 + 813 813 + intel_panel_actually_set_backlight(connector, panel->backlight.level); 809 814 } 810 815 811 816 static void vlv_enable_backlight(struct intel_connector *connector)

+2 -7

drivers/gpu/drm/i915/intel_pm.c

reviewed

··· 511 511 obj = intel_fb->obj; 512 512 adjusted_mode = &intel_crtc->config.adjusted_mode; 513 513 514 514 - if (i915.enable_fbc < 0 && 515 515 - INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) { 514 514 + if (i915.enable_fbc < 0) { 516 515 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) 517 516 DRM_DEBUG_KMS("disabled per chip default\n"); 518 517 goto out_disable; ··· 3505 3506 3506 3507 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 3507 3508 3508 3508 - /* WaDisablePwrmtrEvent:chv (pre-production hw) */ 3509 3509 - I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff); 3510 3510 - I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00); 3511 3511 - 3512 3509 /* 5: Enable RPS */ 3513 3510 I915_WRITE(GEN6_RP_CONTROL, 3514 3511 GEN6_RP_MEDIA_TURBO | 3515 3512 GEN6_RP_MEDIA_HW_NORMAL_MODE | 3516 3516 - GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */ 3513 3513 + GEN6_RP_MEDIA_IS_GFX | 3517 3514 GEN6_RP_ENABLE | 3518 3515 GEN6_RP_UP_BUSY_AVG | 3519 3516 GEN6_RP_DOWN_IDLE_AVG);

+1 -1

drivers/gpu/drm/i915/intel_ringbuffer.h

reviewed

··· 55 55 u32 seqno; 56 56 int score; 57 57 enum intel_ring_hangcheck_action action; 58 58 - bool deadlock; 58 58 + int deadlock; 59 59 }; 60 60 61 61 struct intel_ringbuffer {

+3 -1

drivers/gpu/drm/i915/intel_sdvo.c

reviewed

··· 1385 1385 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1386 1386 } 1387 1387 1388 1388 - dotclock = pipe_config->port_clock / pipe_config->pixel_multiplier; 1388 1388 + dotclock = pipe_config->port_clock; 1389 1389 + if (pipe_config->pixel_multiplier) 1390 1390 + dotclock /= pipe_config->pixel_multiplier; 1389 1391 1390 1392 if (HAS_PCH_SPLIT(dev)) 1391 1393 ironlake_check_encoder_dotclock(pipe_config, dotclock);

+2 -1

drivers/gpu/drm/i915/intel_uncore.c

reviewed

··· 320 320 struct drm_i915_private *dev_priv = dev->dev_private; 321 321 unsigned long irqflags; 322 322 323 323 - del_timer_sync(&dev_priv->uncore.force_wake_timer); 323 323 + if (del_timer_sync(&dev_priv->uncore.force_wake_timer)) 324 324 + gen6_force_wake_timer((unsigned long)dev_priv); 324 325 325 326 /* Hold uncore.lock across reset to prevent any register access 326 327 * with forcewake not set correctly

+1

drivers/gpu/drm/nouveau/Makefile

reviewed

··· 140 140 nouveau-y += core/subdev/i2c/nv50.o 141 141 nouveau-y += core/subdev/i2c/nv94.o 142 142 nouveau-y += core/subdev/i2c/nvd0.o 143 143 + nouveau-y += core/subdev/i2c/gf117.o 143 144 nouveau-y += core/subdev/i2c/nve0.o 144 145 nouveau-y += core/subdev/ibus/nvc0.o 145 146 nouveau-y += core/subdev/ibus/nve0.o

+1 -1

drivers/gpu/drm/nouveau/core/engine/device/nvc0.c

reviewed

··· 314 314 device->cname = "GF117"; 315 315 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; 316 316 device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass; 317 317 - device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; 317 317 + device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass; 318 318 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; 319 319 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; 320 320 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;

+4 -2

drivers/gpu/drm/nouveau/core/engine/disp/base.c

reviewed

··· 99 99 100 100 nouveau_event_destroy(&disp->vblank); 101 101 102 102 - list_for_each_entry_safe(outp, outt, &disp->outp, head) { 103 103 - nouveau_object_ref(NULL, (struct nouveau_object **)&outp); 102 102 + if (disp->outp.next) { 103 103 + list_for_each_entry_safe(outp, outt, &disp->outp, head) { 104 104 + nouveau_object_ref(NULL, (struct nouveau_object **)&outp); 105 105 + } 104 106 } 105 107 106 108 nouveau_engine_destroy(&disp->base);

+3 -4

drivers/gpu/drm/nouveau/core/engine/disp/dport.c

reviewed

··· 241 241 dp_set_training_pattern(dp, 2); 242 242 243 243 do { 244 244 - if (dp_link_train_update(dp, dp->pc2, 400)) 244 244 + if ((tries && 245 245 + dp_link_train_commit(dp, dp->pc2)) || 246 246 + dp_link_train_update(dp, dp->pc2, 400)) 245 247 break; 246 248 247 249 eq_done = !!(dp->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE); ··· 255 253 !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) 256 254 eq_done = false; 257 255 } 258 258 - 259 259 - if (dp_link_train_commit(dp, dp->pc2)) 260 260 - break; 261 256 } while (!eq_done && cr_done && ++tries <= 5); 262 257 263 258 return eq_done ? 0 : -1;

+1 -1

drivers/gpu/drm/nouveau/core/engine/disp/nv50.c

reviewed

··· 1270 1270 i--; 1271 1271 1272 1272 outp = exec_lookup(priv, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info1); 1273 1273 - if (!data) 1273 1273 + if (!outp) 1274 1274 return NULL; 1275 1275 1276 1276 if (outp->info.location == 0) {

+1 -1

drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc

reviewed

··· 54 54 #ifdef INCLUDE_CODE 55 55 // reports an exception to the host 56 56 // 57 57 - // In: $r15 error code (see nvc0.fuc) 57 57 + // In: $r15 error code (see os.h) 58 58 // 59 59 error: 60 60 push $r14

+15 -3

drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc

reviewed

··· 49 49 #ifdef INCLUDE_CODE 50 50 // reports an exception to the host 51 51 // 52 52 - // In: $r15 error code (see nvc0.fuc) 52 52 + // In: $r15 error code (see os.h) 53 53 // 54 54 error: 55 55 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15) ··· 343 343 ih_no_ctxsw: 344 344 and $r11 $r10 NV_PGRAPH_FECS_INTR_FWMTHD 345 345 bra e #ih_no_fwmthd 346 346 - // none we handle, ack, and fall-through to unhandled 346 346 + // none we handle; report to host and ack 347 347 + nv_rd32($r15, NV_PGRAPH_TRAPPED_DATA_LO) 348 348 + nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(4), 0, $r15) 349 349 + nv_rd32($r15, NV_PGRAPH_TRAPPED_ADDR) 350 350 + nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(3), 0, $r15) 351 351 + extr $r14 $r15 16:18 352 352 + shl b32 $r14 $r14 2 353 353 + imm32($r15, NV_PGRAPH_FE_OBJECT_TABLE(0)) 354 354 + add b32 $r14 $r15 355 355 + call(nv_rd32) 356 356 + nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(2), 0, $r15) 357 357 + mov $r15 E_BAD_FWMTHD 358 358 + call(error) 347 359 mov $r11 0x100 348 360 nv_wr32(0x400144, $r11) 349 361 350 362 // anything we didn't handle, bring it to the host's attention 351 363 ih_no_fwmthd: 352 352 - mov $r11 0x104 // FIFO | CHSW 364 364 + mov $r11 0x504 // FIFO | CHSW | FWMTHD 353 365 not b32 $r11 354 366 and $r11 $r10 $r11 355 367 bra e #ih_no_other

+233 -233

drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h

reviewed

··· 478 478 0x01040080, 479 479 0xbd0001f6, 480 480 0x01004104, 481 481 - 0x627e020f, 482 482 - 0x717e0006, 481 481 + 0xa87e020f, 482 482 + 0xb77e0006, 483 483 0x100f0006, 484 484 - 0x0006b37e, 484 484 + 0x0006f97e, 485 485 0x98000e98, 486 486 0x207e010f, 487 487 0x14950001, ··· 523 523 0x800040b7, 524 524 0xf40132b6, 525 525 0x000fb41b, 526 526 - 0x0006b37e, 527 527 - 0x627e000f, 526 526 + 0x0006f97e, 527 527 + 0xa87e000f, 528 528 0x00800006, 529 529 0x01f60201, 530 530 0xbd04bd00, ··· 554 554 0x0009f602, 555 555 0x32f404bd, 556 556 0x0231f401, 557 557 - 0x0008367e, 557 557 + 0x00087c7e, 558 558 0x99f094bd, 559 559 0x17008007, 560 560 0x0009f602, ··· 563 563 0x37008006, 564 564 0x0009f602, 565 565 0x31f404bd, 566 566 - 0x08367e01, 566 566 + 0x087c7e01, 567 567 0xf094bd00, 568 568 0x00800699, 569 569 0x09f60217, ··· 572 572 0x20f92f0e, 573 573 0x32f412b2, 574 574 0x0232f401, 575 575 - 0x0008367e, 575 575 + 0x00087c7e, 576 576 0x008020fc, 577 577 0x02f602c0, 578 578 0xf404bd00, ··· 580 580 0x23c8130e, 581 581 0x0d0bf41f, 582 582 0xf40131f4, 583 583 - 0x367e0232, 583 583 + 0x7c7e0232, 584 584 /* 0x054e: chsw_done */ 585 585 0x01020008, 586 586 0x02c30080, ··· 593 593 0xb0ff2a0e, 594 594 0x1bf401e4, 595 595 0x7ef2b20c, 596 596 - 0xf40007d6, 596 596 + 0xf400081c, 597 597 /* 0x057a: main_not_ctx_chan */ 598 598 0xe4b0400e, 599 599 0x2c1bf402, ··· 602 602 0x0009f602, 603 603 0x32f404bd, 604 604 0x0232f401, 605 605 - 0x0008367e, 605 605 + 0x00087c7e, 606 606 0x99f094bd, 607 607 0x17008007, 608 608 0x0009f602, ··· 642 642 /* 0x061a: ih_no_ctxsw */ 643 643 0xabe40000, 644 644 0x0bf40400, 645 645 - 0x01004b10, 646 646 - 0x448ebfb2, 647 647 - 0x8f7e4001, 648 648 - /* 0x062e: ih_no_fwmthd */ 649 649 - 0x044b0000, 650 650 - 0xffb0bd01, 651 651 - 0x0bf4b4ab, 652 652 - 0x0700800c, 653 653 - 0x000bf603, 654 654 - /* 0x0642: ih_no_other */ 655 655 - 0x004004bd, 656 656 - 0x000af601, 657 657 - 0xf0fc04bd, 658 658 - 0xd0fce0fc, 659 659 - 0xa0fcb0fc, 660 660 - 0x80fc90fc, 661 661 - 0xfc0088fe, 662 662 - 0x0032f480, 663 663 - /* 0x0662: ctx_4170s */ 664 664 - 0xf5f001f8, 665 665 - 0x8effb210, 666 666 - 0x7e404170, 667 667 - 0xf800008f, 668 668 - /* 0x0671: ctx_4170w */ 669 669 - 0x41708e00, 645 645 + 0x07088e56, 670 646 0x00657e40, 671 671 - 0xf0ffb200, 672 672 - 0x1bf410f4, 673 673 - /* 0x0683: ctx_redswitch */ 674 674 - 0x4e00f8f3, 675 675 - 0xe5f00200, 676 676 - 0x20e5f040, 677 677 - 0x8010e5f0, 678 678 - 0xf6018500, 679 679 - 0x04bd000e, 680 680 - /* 0x069a: ctx_redswitch_delay */ 681 681 - 0xf2b6080f, 682 682 - 0xfd1bf401, 683 683 - 0x0400e5f1, 684 684 - 0x0100e5f1, 685 685 - 0x01850080, 686 686 - 0xbd000ef6, 687 687 - /* 0x06b3: ctx_86c */ 688 688 - 0x8000f804, 689 689 - 0xf6022300, 647 647 + 0x80ffb200, 648 648 + 0xf6020400, 690 649 0x04bd000f, 691 691 - 0x148effb2, 692 692 - 0x8f7e408a, 693 693 - 0xffb20000, 694 694 - 0x41a88c8e, 695 695 - 0x00008f7e, 696 696 - /* 0x06d2: ctx_mem */ 697 697 - 0x008000f8, 698 698 - 0x0ff60284, 699 699 - /* 0x06db: ctx_mem_wait */ 700 700 - 0x8f04bd00, 701 701 - 0xcf028400, 702 702 - 0xfffd00ff, 703 703 - 0xf61bf405, 704 704 - /* 0x06ea: ctx_load */ 705 705 - 0x94bd00f8, 706 706 - 0x800599f0, 707 707 - 0xf6023700, 708 708 - 0x04bd0009, 709 709 - 0xb87e0c0a, 710 710 - 0xf4bd0000, 711 711 - 0x02890080, 650 650 + 0x4007048e, 651 651 + 0x0000657e, 652 652 + 0x0080ffb2, 653 653 + 0x0ff60203, 654 654 + 0xc704bd00, 655 655 + 0xee9450fe, 656 656 + 0x07008f02, 657 657 + 0x00efbb40, 658 658 + 0x0000657e, 659 659 + 0x02020080, 712 660 0xbd000ff6, 713 713 - 0xc1008004, 714 714 - 0x0002f602, 715 715 - 0x008004bd, 716 716 - 0x02f60283, 717 717 - 0x0f04bd00, 718 718 - 0x06d27e07, 719 719 - 0xc0008000, 720 720 - 0x0002f602, 721 721 - 0x0bfe04bd, 722 722 - 0x1f2af000, 723 723 - 0xb60424b6, 724 724 - 0x94bd0220, 725 725 - 0x800899f0, 726 726 - 0xf6023700, 727 727 - 0x04bd0009, 728 728 - 0x02810080, 729 729 - 0xbd0002f6, 730 730 - 0x0000d204, 731 731 - 0x25f08000, 732 732 - 0x88008002, 733 733 - 0x0002f602, 734 734 - 0x100104bd, 735 735 - 0xf0020042, 736 736 - 0x12fa0223, 737 737 - 0xbd03f805, 738 738 - 0x0899f094, 739 739 - 0x02170080, 740 740 - 0xbd0009f6, 741 741 - 0x81019804, 742 742 - 0x981814b6, 743 743 - 0x25b68002, 744 744 - 0x0512fd08, 745 745 - 0xbd1601b5, 746 746 - 0x0999f094, 747 747 - 0x02370080, 748 748 - 0xbd0009f6, 749 749 - 0x81008004, 750 750 - 0x0001f602, 751 751 - 0x010204bd, 752 752 - 0x02880080, 753 753 - 0xbd0002f6, 754 754 - 0x01004104, 755 755 - 0xfa0613f0, 756 756 - 0x03f80501, 661 661 + 0x7e030f04, 662 662 + 0x4b0002f8, 663 663 + 0xbfb20100, 664 664 + 0x4001448e, 665 665 + 0x00008f7e, 666 666 + /* 0x0674: ih_no_fwmthd */ 667 667 + 0xbd05044b, 668 668 + 0xb4abffb0, 669 669 + 0x800c0bf4, 670 670 + 0xf6030700, 671 671 + 0x04bd000b, 672 672 + /* 0x0688: ih_no_other */ 673 673 + 0xf6010040, 674 674 + 0x04bd000a, 675 675 + 0xe0fcf0fc, 676 676 + 0xb0fcd0fc, 677 677 + 0x90fca0fc, 678 678 + 0x88fe80fc, 679 679 + 0xf480fc00, 680 680 + 0x01f80032, 681 681 + /* 0x06a8: ctx_4170s */ 682 682 + 0xb210f5f0, 683 683 + 0x41708eff, 684 684 + 0x008f7e40, 685 685 + /* 0x06b7: ctx_4170w */ 686 686 + 0x8e00f800, 687 687 + 0x7e404170, 688 688 + 0xb2000065, 689 689 + 0x10f4f0ff, 690 690 + 0xf8f31bf4, 691 691 + /* 0x06c9: ctx_redswitch */ 692 692 + 0x02004e00, 693 693 + 0xf040e5f0, 694 694 + 0xe5f020e5, 695 695 + 0x85008010, 696 696 + 0x000ef601, 697 697 + 0x080f04bd, 698 698 + /* 0x06e0: ctx_redswitch_delay */ 699 699 + 0xf401f2b6, 700 700 + 0xe5f1fd1b, 701 701 + 0xe5f10400, 702 702 + 0x00800100, 703 703 + 0x0ef60185, 704 704 + 0xf804bd00, 705 705 + /* 0x06f9: ctx_86c */ 706 706 + 0x23008000, 707 707 + 0x000ff602, 708 708 + 0xffb204bd, 709 709 + 0x408a148e, 710 710 + 0x00008f7e, 711 711 + 0x8c8effb2, 712 712 + 0x8f7e41a8, 713 713 + 0x00f80000, 714 714 + /* 0x0718: ctx_mem */ 715 715 + 0x02840080, 716 716 + 0xbd000ff6, 717 717 + /* 0x0721: ctx_mem_wait */ 718 718 + 0x84008f04, 719 719 + 0x00ffcf02, 720 720 + 0xf405fffd, 721 721 + 0x00f8f61b, 722 722 + /* 0x0730: ctx_load */ 757 723 0x99f094bd, 758 758 - 0x17008009, 724 724 + 0x37008005, 759 725 0x0009f602, 760 760 - 0x94bd04bd, 761 761 - 0x800599f0, 726 726 + 0x0c0a04bd, 727 727 + 0x0000b87e, 728 728 + 0x0080f4bd, 729 729 + 0x0ff60289, 730 730 + 0x8004bd00, 731 731 + 0xf602c100, 732 732 + 0x04bd0002, 733 733 + 0x02830080, 734 734 + 0xbd0002f6, 735 735 + 0x7e070f04, 736 736 + 0x80000718, 737 737 + 0xf602c000, 738 738 + 0x04bd0002, 739 739 + 0xf0000bfe, 740 740 + 0x24b61f2a, 741 741 + 0x0220b604, 742 742 + 0x99f094bd, 743 743 + 0x37008008, 744 744 + 0x0009f602, 745 745 + 0x008004bd, 746 746 + 0x02f60281, 747 747 + 0xd204bd00, 748 748 + 0x80000000, 749 749 + 0x800225f0, 750 750 + 0xf6028800, 751 751 + 0x04bd0002, 752 752 + 0x00421001, 753 753 + 0x0223f002, 754 754 + 0xf80512fa, 755 755 + 0xf094bd03, 756 756 + 0x00800899, 757 757 + 0x09f60217, 758 758 + 0x9804bd00, 759 759 + 0x14b68101, 760 760 + 0x80029818, 761 761 + 0xfd0825b6, 762 762 + 0x01b50512, 763 763 + 0xf094bd16, 764 764 + 0x00800999, 765 765 + 0x09f60237, 766 766 + 0x8004bd00, 767 767 + 0xf6028100, 768 768 + 0x04bd0001, 769 769 + 0x00800102, 770 770 + 0x02f60288, 771 771 + 0x4104bd00, 772 772 + 0x13f00100, 773 773 + 0x0501fa06, 774 774 + 0x94bd03f8, 775 775 + 0x800999f0, 762 776 0xf6021700, 763 777 0x04bd0009, 764 764 - /* 0x07d6: ctx_chan */ 765 765 - 0xea7e00f8, 766 766 - 0x0c0a0006, 767 767 - 0x0000b87e, 768 768 - 0xd27e050f, 769 769 - 0x00f80006, 770 770 - /* 0x07e8: ctx_mmio_exec */ 771 771 - 0x80410398, 778 778 + 0x99f094bd, 779 779 + 0x17008005, 780 780 + 0x0009f602, 781 781 + 0x00f804bd, 782 782 + /* 0x081c: ctx_chan */ 783 783 + 0x0007307e, 784 784 + 0xb87e0c0a, 785 785 + 0x050f0000, 786 786 + 0x0007187e, 787 787 + /* 0x082e: ctx_mmio_exec */ 788 788 + 0x039800f8, 789 789 + 0x81008041, 790 790 + 0x0003f602, 791 791 + 0x34bd04bd, 792 792 + /* 0x083c: ctx_mmio_loop */ 793 793 + 0xf4ff34c4, 794 794 + 0x00450e1b, 795 795 + 0x0653f002, 796 796 + 0xf80535fa, 797 797 + /* 0x084d: ctx_mmio_pull */ 798 798 + 0x804e9803, 799 799 + 0x7e814f98, 800 800 + 0xb600008f, 801 801 + 0x12b60830, 802 802 + 0xdf1bf401, 803 803 + /* 0x0860: ctx_mmio_done */ 804 804 + 0x80160398, 772 805 0xf6028100, 773 806 0x04bd0003, 774 774 - /* 0x07f6: ctx_mmio_loop */ 775 775 - 0x34c434bd, 776 776 - 0x0e1bf4ff, 777 777 - 0xf0020045, 778 778 - 0x35fa0653, 779 779 - /* 0x0807: ctx_mmio_pull */ 780 780 - 0x9803f805, 781 781 - 0x4f98804e, 782 782 - 0x008f7e81, 783 783 - 0x0830b600, 784 784 - 0xf40112b6, 785 785 - /* 0x081a: ctx_mmio_done */ 786 786 - 0x0398df1b, 787 787 - 0x81008016, 788 788 - 0x0003f602, 789 789 - 0x00b504bd, 790 790 - 0x01004140, 791 791 - 0xfa0613f0, 792 792 - 0x03f80601, 793 793 - /* 0x0836: ctx_xfer */ 794 794 - 0x040e00f8, 795 795 - 0x03020080, 796 796 - 0xbd000ef6, 797 797 - /* 0x0841: ctx_xfer_idle */ 798 798 - 0x00008e04, 799 799 - 0x00eecf03, 800 800 - 0x2000e4f1, 801 801 - 0xf4f51bf4, 802 802 - 0x02f40611, 803 803 - /* 0x0855: ctx_xfer_pre */ 804 804 - 0x7e100f0c, 805 805 - 0xf40006b3, 806 806 - /* 0x085e: ctx_xfer_pre_load */ 807 807 - 0x020f1b11, 808 808 - 0x0006627e, 809 809 - 0x0006717e, 810 810 - 0x0006837e, 811 811 - 0x627ef4bd, 812 812 - 0xea7e0006, 813 813 - /* 0x0876: ctx_xfer_exec */ 814 814 - 0x01980006, 815 815 - 0x8024bd16, 816 816 - 0xf6010500, 817 817 - 0x04bd0002, 818 818 - 0x008e1fb2, 819 819 - 0x8f7e41a5, 820 820 - 0xfcf00000, 821 821 - 0x022cf001, 822 822 - 0xfd0124b6, 823 823 - 0xffb205f2, 824 824 - 0x41a5048e, 825 825 - 0x00008f7e, 826 826 - 0x0002167e, 827 827 - 0xfc8024bd, 828 828 - 0x02f60247, 829 829 - 0xf004bd00, 830 830 - 0x20b6012c, 831 831 - 0x4afc8003, 832 832 - 0x0002f602, 833 833 - 0xacf004bd, 834 834 - 0x06a5f001, 835 835 - 0x0c98000b, 836 836 - 0x010d9800, 837 837 - 0x3d7e000e, 838 838 - 0x080a0001, 839 839 - 0x0000ec7e, 840 840 - 0x00020a7e, 841 841 - 0x0a1201f4, 842 842 - 0x00b87e0c, 843 843 - 0x7e050f00, 844 844 - 0xf40006d2, 845 845 - /* 0x08f2: ctx_xfer_post */ 846 846 - 0x020f2d02, 847 847 - 0x0006627e, 848 848 - 0xb37ef4bd, 849 849 - 0x277e0006, 850 850 - 0x717e0002, 807 807 + 0x414000b5, 808 808 + 0x13f00100, 809 809 + 0x0601fa06, 810 810 + 0x00f803f8, 811 811 + /* 0x087c: ctx_xfer */ 812 812 + 0x0080040e, 813 813 + 0x0ef60302, 814 814 + /* 0x0887: ctx_xfer_idle */ 815 815 + 0x8e04bd00, 816 816 + 0xcf030000, 817 817 + 0xe4f100ee, 818 818 + 0x1bf42000, 819 819 + 0x0611f4f5, 820 820 + /* 0x089b: ctx_xfer_pre */ 821 821 + 0x0f0c02f4, 822 822 + 0x06f97e10, 823 823 + 0x1b11f400, 824 824 + /* 0x08a4: ctx_xfer_pre_load */ 825 825 + 0xa87e020f, 826 826 + 0xb77e0006, 827 827 + 0xc97e0006, 851 828 0xf4bd0006, 852 852 - 0x0006627e, 853 853 - 0x981011f4, 854 854 - 0x11fd4001, 855 855 - 0x070bf405, 856 856 - 0x0007e87e, 857 857 - /* 0x091c: ctx_xfer_no_post_mmio */ 858 858 - /* 0x091c: ctx_xfer_done */ 859 859 - 0x000000f8, 860 860 - 0x00000000, 861 861 - 0x00000000, 862 862 - 0x00000000, 863 863 - 0x00000000, 864 864 - 0x00000000, 865 865 - 0x00000000, 866 866 - 0x00000000, 867 867 - 0x00000000, 868 868 - 0x00000000, 869 869 - 0x00000000, 870 870 - 0x00000000, 871 871 - 0x00000000, 872 872 - 0x00000000, 873 873 - 0x00000000, 874 874 - 0x00000000, 875 875 - 0x00000000, 876 876 - 0x00000000, 829 829 + 0x0006a87e, 830 830 + 0x0007307e, 831 831 + /* 0x08bc: ctx_xfer_exec */ 832 832 + 0xbd160198, 833 833 + 0x05008024, 834 834 + 0x0002f601, 835 835 + 0x1fb204bd, 836 836 + 0x41a5008e, 837 837 + 0x00008f7e, 838 838 + 0xf001fcf0, 839 839 + 0x24b6022c, 840 840 + 0x05f2fd01, 841 841 + 0x048effb2, 842 842 + 0x8f7e41a5, 843 843 + 0x167e0000, 844 844 + 0x24bd0002, 845 845 + 0x0247fc80, 846 846 + 0xbd0002f6, 847 847 + 0x012cf004, 848 848 + 0x800320b6, 849 849 + 0xf6024afc, 850 850 + 0x04bd0002, 851 851 + 0xf001acf0, 852 852 + 0x000b06a5, 853 853 + 0x98000c98, 854 854 + 0x000e010d, 855 855 + 0x00013d7e, 856 856 + 0xec7e080a, 857 857 + 0x0a7e0000, 858 858 + 0x01f40002, 859 859 + 0x7e0c0a12, 860 860 + 0x0f0000b8, 861 861 + 0x07187e05, 862 862 + 0x2d02f400, 863 863 + /* 0x0938: ctx_xfer_post */ 864 864 + 0xa87e020f, 865 865 + 0xf4bd0006, 866 866 + 0x0006f97e, 867 867 + 0x0002277e, 868 868 + 0x0006b77e, 869 869 + 0xa87ef4bd, 870 870 + 0x11f40006, 871 871 + 0x40019810, 872 872 + 0xf40511fd, 873 873 + 0x2e7e070b, 874 874 + /* 0x0962: ctx_xfer_no_post_mmio */ 875 875 + /* 0x0962: ctx_xfer_done */ 876 876 + 0x00f80008, 877 877 0x00000000, 878 878 0x00000000, 879 879 0x00000000,

+233 -233

drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h

reviewed

··· 478 478 0x01040080, 479 479 0xbd0001f6, 480 480 0x01004104, 481 481 - 0x627e020f, 482 482 - 0x717e0006, 481 481 + 0xa87e020f, 482 482 + 0xb77e0006, 483 483 0x100f0006, 484 484 - 0x0006b37e, 484 484 + 0x0006f97e, 485 485 0x98000e98, 486 486 0x207e010f, 487 487 0x14950001, ··· 523 523 0x800040b7, 524 524 0xf40132b6, 525 525 0x000fb41b, 526 526 - 0x0006b37e, 527 527 - 0x627e000f, 526 526 + 0x0006f97e, 527 527 + 0xa87e000f, 528 528 0x00800006, 529 529 0x01f60201, 530 530 0xbd04bd00, ··· 554 554 0x0009f602, 555 555 0x32f404bd, 556 556 0x0231f401, 557 557 - 0x0008367e, 557 557 + 0x00087c7e, 558 558 0x99f094bd, 559 559 0x17008007, 560 560 0x0009f602, ··· 563 563 0x37008006, 564 564 0x0009f602, 565 565 0x31f404bd, 566 566 - 0x08367e01, 566 566 + 0x087c7e01, 567 567 0xf094bd00, 568 568 0x00800699, 569 569 0x09f60217, ··· 572 572 0x20f92f0e, 573 573 0x32f412b2, 574 574 0x0232f401, 575 575 - 0x0008367e, 575 575 + 0x00087c7e, 576 576 0x008020fc, 577 577 0x02f602c0, 578 578 0xf404bd00, ··· 580 580 0x23c8130e, 581 581 0x0d0bf41f, 582 582 0xf40131f4, 583 583 - 0x367e0232, 583 583 + 0x7c7e0232, 584 584 /* 0x054e: chsw_done */ 585 585 0x01020008, 586 586 0x02c30080, ··· 593 593 0xb0ff2a0e, 594 594 0x1bf401e4, 595 595 0x7ef2b20c, 596 596 - 0xf40007d6, 596 596 + 0xf400081c, 597 597 /* 0x057a: main_not_ctx_chan */ 598 598 0xe4b0400e, 599 599 0x2c1bf402, ··· 602 602 0x0009f602, 603 603 0x32f404bd, 604 604 0x0232f401, 605 605 - 0x0008367e, 605 605 + 0x00087c7e, 606 606 0x99f094bd, 607 607 0x17008007, 608 608 0x0009f602, ··· 642 642 /* 0x061a: ih_no_ctxsw */ 643 643 0xabe40000, 644 644 0x0bf40400, 645 645 - 0x01004b10, 646 646 - 0x448ebfb2, 647 647 - 0x8f7e4001, 648 648 - /* 0x062e: ih_no_fwmthd */ 649 649 - 0x044b0000, 650 650 - 0xffb0bd01, 651 651 - 0x0bf4b4ab, 652 652 - 0x0700800c, 653 653 - 0x000bf603, 654 654 - /* 0x0642: ih_no_other */ 655 655 - 0x004004bd, 656 656 - 0x000af601, 657 657 - 0xf0fc04bd, 658 658 - 0xd0fce0fc, 659 659 - 0xa0fcb0fc, 660 660 - 0x80fc90fc, 661 661 - 0xfc0088fe, 662 662 - 0x0032f480, 663 663 - /* 0x0662: ctx_4170s */ 664 664 - 0xf5f001f8, 665 665 - 0x8effb210, 666 666 - 0x7e404170, 667 667 - 0xf800008f, 668 668 - /* 0x0671: ctx_4170w */ 669 669 - 0x41708e00, 645 645 + 0x07088e56, 670 646 0x00657e40, 671 671 - 0xf0ffb200, 672 672 - 0x1bf410f4, 673 673 - /* 0x0683: ctx_redswitch */ 674 674 - 0x4e00f8f3, 675 675 - 0xe5f00200, 676 676 - 0x20e5f040, 677 677 - 0x8010e5f0, 678 678 - 0xf6018500, 679 679 - 0x04bd000e, 680 680 - /* 0x069a: ctx_redswitch_delay */ 681 681 - 0xf2b6080f, 682 682 - 0xfd1bf401, 683 683 - 0x0400e5f1, 684 684 - 0x0100e5f1, 685 685 - 0x01850080, 686 686 - 0xbd000ef6, 687 687 - /* 0x06b3: ctx_86c */ 688 688 - 0x8000f804, 689 689 - 0xf6022300, 647 647 + 0x80ffb200, 648 648 + 0xf6020400, 690 649 0x04bd000f, 691 691 - 0x148effb2, 692 692 - 0x8f7e408a, 693 693 - 0xffb20000, 694 694 - 0x41a88c8e, 695 695 - 0x00008f7e, 696 696 - /* 0x06d2: ctx_mem */ 697 697 - 0x008000f8, 698 698 - 0x0ff60284, 699 699 - /* 0x06db: ctx_mem_wait */ 700 700 - 0x8f04bd00, 701 701 - 0xcf028400, 702 702 - 0xfffd00ff, 703 703 - 0xf61bf405, 704 704 - /* 0x06ea: ctx_load */ 705 705 - 0x94bd00f8, 706 706 - 0x800599f0, 707 707 - 0xf6023700, 708 708 - 0x04bd0009, 709 709 - 0xb87e0c0a, 710 710 - 0xf4bd0000, 711 711 - 0x02890080, 650 650 + 0x4007048e, 651 651 + 0x0000657e, 652 652 + 0x0080ffb2, 653 653 + 0x0ff60203, 654 654 + 0xc704bd00, 655 655 + 0xee9450fe, 656 656 + 0x07008f02, 657 657 + 0x00efbb40, 658 658 + 0x0000657e, 659 659 + 0x02020080, 712 660 0xbd000ff6, 713 713 - 0xc1008004, 714 714 - 0x0002f602, 715 715 - 0x008004bd, 716 716 - 0x02f60283, 717 717 - 0x0f04bd00, 718 718 - 0x06d27e07, 719 719 - 0xc0008000, 720 720 - 0x0002f602, 721 721 - 0x0bfe04bd, 722 722 - 0x1f2af000, 723 723 - 0xb60424b6, 724 724 - 0x94bd0220, 725 725 - 0x800899f0, 726 726 - 0xf6023700, 727 727 - 0x04bd0009, 728 728 - 0x02810080, 729 729 - 0xbd0002f6, 730 730 - 0x0000d204, 731 731 - 0x25f08000, 732 732 - 0x88008002, 733 733 - 0x0002f602, 734 734 - 0x100104bd, 735 735 - 0xf0020042, 736 736 - 0x12fa0223, 737 737 - 0xbd03f805, 738 738 - 0x0899f094, 739 739 - 0x02170080, 740 740 - 0xbd0009f6, 741 741 - 0x81019804, 742 742 - 0x981814b6, 743 743 - 0x25b68002, 744 744 - 0x0512fd08, 745 745 - 0xbd1601b5, 746 746 - 0x0999f094, 747 747 - 0x02370080, 748 748 - 0xbd0009f6, 749 749 - 0x81008004, 750 750 - 0x0001f602, 751 751 - 0x010204bd, 752 752 - 0x02880080, 753 753 - 0xbd0002f6, 754 754 - 0x01004104, 755 755 - 0xfa0613f0, 756 756 - 0x03f80501, 661 661 + 0x7e030f04, 662 662 + 0x4b0002f8, 663 663 + 0xbfb20100, 664 664 + 0x4001448e, 665 665 + 0x00008f7e, 666 666 + /* 0x0674: ih_no_fwmthd */ 667 667 + 0xbd05044b, 668 668 + 0xb4abffb0, 669 669 + 0x800c0bf4, 670 670 + 0xf6030700, 671 671 + 0x04bd000b, 672 672 + /* 0x0688: ih_no_other */ 673 673 + 0xf6010040, 674 674 + 0x04bd000a, 675 675 + 0xe0fcf0fc, 676 676 + 0xb0fcd0fc, 677 677 + 0x90fca0fc, 678 678 + 0x88fe80fc, 679 679 + 0xf480fc00, 680 680 + 0x01f80032, 681 681 + /* 0x06a8: ctx_4170s */ 682 682 + 0xb210f5f0, 683 683 + 0x41708eff, 684 684 + 0x008f7e40, 685 685 + /* 0x06b7: ctx_4170w */ 686 686 + 0x8e00f800, 687 687 + 0x7e404170, 688 688 + 0xb2000065, 689 689 + 0x10f4f0ff, 690 690 + 0xf8f31bf4, 691 691 + /* 0x06c9: ctx_redswitch */ 692 692 + 0x02004e00, 693 693 + 0xf040e5f0, 694 694 + 0xe5f020e5, 695 695 + 0x85008010, 696 696 + 0x000ef601, 697 697 + 0x080f04bd, 698 698 + /* 0x06e0: ctx_redswitch_delay */ 699 699 + 0xf401f2b6, 700 700 + 0xe5f1fd1b, 701 701 + 0xe5f10400, 702 702 + 0x00800100, 703 703 + 0x0ef60185, 704 704 + 0xf804bd00, 705 705 + /* 0x06f9: ctx_86c */ 706 706 + 0x23008000, 707 707 + 0x000ff602, 708 708 + 0xffb204bd, 709 709 + 0x408a148e, 710 710 + 0x00008f7e, 711 711 + 0x8c8effb2, 712 712 + 0x8f7e41a8, 713 713 + 0x00f80000, 714 714 + /* 0x0718: ctx_mem */ 715 715 + 0x02840080, 716 716 + 0xbd000ff6, 717 717 + /* 0x0721: ctx_mem_wait */ 718 718 + 0x84008f04, 719 719 + 0x00ffcf02, 720 720 + 0xf405fffd, 721 721 + 0x00f8f61b, 722 722 + /* 0x0730: ctx_load */ 757 723 0x99f094bd, 758 758 - 0x17008009, 724 724 + 0x37008005, 759 725 0x0009f602, 760 760 - 0x94bd04bd, 761 761 - 0x800599f0, 726 726 + 0x0c0a04bd, 727 727 + 0x0000b87e, 728 728 + 0x0080f4bd, 729 729 + 0x0ff60289, 730 730 + 0x8004bd00, 731 731 + 0xf602c100, 732 732 + 0x04bd0002, 733 733 + 0x02830080, 734 734 + 0xbd0002f6, 735 735 + 0x7e070f04, 736 736 + 0x80000718, 737 737 + 0xf602c000, 738 738 + 0x04bd0002, 739 739 + 0xf0000bfe, 740 740 + 0x24b61f2a, 741 741 + 0x0220b604, 742 742 + 0x99f094bd, 743 743 + 0x37008008, 744 744 + 0x0009f602, 745 745 + 0x008004bd, 746 746 + 0x02f60281, 747 747 + 0xd204bd00, 748 748 + 0x80000000, 749 749 + 0x800225f0, 750 750 + 0xf6028800, 751 751 + 0x04bd0002, 752 752 + 0x00421001, 753 753 + 0x0223f002, 754 754 + 0xf80512fa, 755 755 + 0xf094bd03, 756 756 + 0x00800899, 757 757 + 0x09f60217, 758 758 + 0x9804bd00, 759 759 + 0x14b68101, 760 760 + 0x80029818, 761 761 + 0xfd0825b6, 762 762 + 0x01b50512, 763 763 + 0xf094bd16, 764 764 + 0x00800999, 765 765 + 0x09f60237, 766 766 + 0x8004bd00, 767 767 + 0xf6028100, 768 768 + 0x04bd0001, 769 769 + 0x00800102, 770 770 + 0x02f60288, 771 771 + 0x4104bd00, 772 772 + 0x13f00100, 773 773 + 0x0501fa06, 774 774 + 0x94bd03f8, 775 775 + 0x800999f0, 762 776 0xf6021700, 763 777 0x04bd0009, 764 764 - /* 0x07d6: ctx_chan */ 765 765 - 0xea7e00f8, 766 766 - 0x0c0a0006, 767 767 - 0x0000b87e, 768 768 - 0xd27e050f, 769 769 - 0x00f80006, 770 770 - /* 0x07e8: ctx_mmio_exec */ 771 771 - 0x80410398, 778 778 + 0x99f094bd, 779 779 + 0x17008005, 780 780 + 0x0009f602, 781 781 + 0x00f804bd, 782 782 + /* 0x081c: ctx_chan */ 783 783 + 0x0007307e, 784 784 + 0xb87e0c0a, 785 785 + 0x050f0000, 786 786 + 0x0007187e, 787 787 + /* 0x082e: ctx_mmio_exec */ 788 788 + 0x039800f8, 789 789 + 0x81008041, 790 790 + 0x0003f602, 791 791 + 0x34bd04bd, 792 792 + /* 0x083c: ctx_mmio_loop */ 793 793 + 0xf4ff34c4, 794 794 + 0x00450e1b, 795 795 + 0x0653f002, 796 796 + 0xf80535fa, 797 797 + /* 0x084d: ctx_mmio_pull */ 798 798 + 0x804e9803, 799 799 + 0x7e814f98, 800 800 + 0xb600008f, 801 801 + 0x12b60830, 802 802 + 0xdf1bf401, 803 803 + /* 0x0860: ctx_mmio_done */ 804 804 + 0x80160398, 772 805 0xf6028100, 773 806 0x04bd0003, 774 774 - /* 0x07f6: ctx_mmio_loop */ 775 775 - 0x34c434bd, 776 776 - 0x0e1bf4ff, 777 777 - 0xf0020045, 778 778 - 0x35fa0653, 779 779 - /* 0x0807: ctx_mmio_pull */ 780 780 - 0x9803f805, 781 781 - 0x4f98804e, 782 782 - 0x008f7e81, 783 783 - 0x0830b600, 784 784 - 0xf40112b6, 785 785 - /* 0x081a: ctx_mmio_done */ 786 786 - 0x0398df1b, 787 787 - 0x81008016, 788 788 - 0x0003f602, 789 789 - 0x00b504bd, 790 790 - 0x01004140, 791 791 - 0xfa0613f0, 792 792 - 0x03f80601, 793 793 - /* 0x0836: ctx_xfer */ 794 794 - 0x040e00f8, 795 795 - 0x03020080, 796 796 - 0xbd000ef6, 797 797 - /* 0x0841: ctx_xfer_idle */ 798 798 - 0x00008e04, 799 799 - 0x00eecf03, 800 800 - 0x2000e4f1, 801 801 - 0xf4f51bf4, 802 802 - 0x02f40611, 803 803 - /* 0x0855: ctx_xfer_pre */ 804 804 - 0x7e100f0c, 805 805 - 0xf40006b3, 806 806 - /* 0x085e: ctx_xfer_pre_load */ 807 807 - 0x020f1b11, 808 808 - 0x0006627e, 809 809 - 0x0006717e, 810 810 - 0x0006837e, 811 811 - 0x627ef4bd, 812 812 - 0xea7e0006, 813 813 - /* 0x0876: ctx_xfer_exec */ 814 814 - 0x01980006, 815 815 - 0x8024bd16, 816 816 - 0xf6010500, 817 817 - 0x04bd0002, 818 818 - 0x008e1fb2, 819 819 - 0x8f7e41a5, 820 820 - 0xfcf00000, 821 821 - 0x022cf001, 822 822 - 0xfd0124b6, 823 823 - 0xffb205f2, 824 824 - 0x41a5048e, 825 825 - 0x00008f7e, 826 826 - 0x0002167e, 827 827 - 0xfc8024bd, 828 828 - 0x02f60247, 829 829 - 0xf004bd00, 830 830 - 0x20b6012c, 831 831 - 0x4afc8003, 832 832 - 0x0002f602, 833 833 - 0xacf004bd, 834 834 - 0x06a5f001, 835 835 - 0x0c98000b, 836 836 - 0x010d9800, 837 837 - 0x3d7e000e, 838 838 - 0x080a0001, 839 839 - 0x0000ec7e, 840 840 - 0x00020a7e, 841 841 - 0x0a1201f4, 842 842 - 0x00b87e0c, 843 843 - 0x7e050f00, 844 844 - 0xf40006d2, 845 845 - /* 0x08f2: ctx_xfer_post */ 846 846 - 0x020f2d02, 847 847 - 0x0006627e, 848 848 - 0xb37ef4bd, 849 849 - 0x277e0006, 850 850 - 0x717e0002, 807 807 + 0x414000b5, 808 808 + 0x13f00100, 809 809 + 0x0601fa06, 810 810 + 0x00f803f8, 811 811 + /* 0x087c: ctx_xfer */ 812 812 + 0x0080040e, 813 813 + 0x0ef60302, 814 814 + /* 0x0887: ctx_xfer_idle */ 815 815 + 0x8e04bd00, 816 816 + 0xcf030000, 817 817 + 0xe4f100ee, 818 818 + 0x1bf42000, 819 819 + 0x0611f4f5, 820 820 + /* 0x089b: ctx_xfer_pre */ 821 821 + 0x0f0c02f4, 822 822 + 0x06f97e10, 823 823 + 0x1b11f400, 824 824 + /* 0x08a4: ctx_xfer_pre_load */ 825 825 + 0xa87e020f, 826 826 + 0xb77e0006, 827 827 + 0xc97e0006, 851 828 0xf4bd0006, 852 852 - 0x0006627e, 853 853 - 0x981011f4, 854 854 - 0x11fd4001, 855 855 - 0x070bf405, 856 856 - 0x0007e87e, 857 857 - /* 0x091c: ctx_xfer_no_post_mmio */ 858 858 - /* 0x091c: ctx_xfer_done */ 859 859 - 0x000000f8, 860 860 - 0x00000000, 861 861 - 0x00000000, 862 862 - 0x00000000, 863 863 - 0x00000000, 864 864 - 0x00000000, 865 865 - 0x00000000, 866 866 - 0x00000000, 867 867 - 0x00000000, 868 868 - 0x00000000, 869 869 - 0x00000000, 870 870 - 0x00000000, 871 871 - 0x00000000, 872 872 - 0x00000000, 873 873 - 0x00000000, 874 874 - 0x00000000, 875 875 - 0x00000000, 876 876 - 0x00000000, 829 829 + 0x0006a87e, 830 830 + 0x0007307e, 831 831 + /* 0x08bc: ctx_xfer_exec */ 832 832 + 0xbd160198, 833 833 + 0x05008024, 834 834 + 0x0002f601, 835 835 + 0x1fb204bd, 836 836 + 0x41a5008e, 837 837 + 0x00008f7e, 838 838 + 0xf001fcf0, 839 839 + 0x24b6022c, 840 840 + 0x05f2fd01, 841 841 + 0x048effb2, 842 842 + 0x8f7e41a5, 843 843 + 0x167e0000, 844 844 + 0x24bd0002, 845 845 + 0x0247fc80, 846 846 + 0xbd0002f6, 847 847 + 0x012cf004, 848 848 + 0x800320b6, 849 849 + 0xf6024afc, 850 850 + 0x04bd0002, 851 851 + 0xf001acf0, 852 852 + 0x000b06a5, 853 853 + 0x98000c98, 854 854 + 0x000e010d, 855 855 + 0x00013d7e, 856 856 + 0xec7e080a, 857 857 + 0x0a7e0000, 858 858 + 0x01f40002, 859 859 + 0x7e0c0a12, 860 860 + 0x0f0000b8, 861 861 + 0x07187e05, 862 862 + 0x2d02f400, 863 863 + /* 0x0938: ctx_xfer_post */ 864 864 + 0xa87e020f, 865 865 + 0xf4bd0006, 866 866 + 0x0006f97e, 867 867 + 0x0002277e, 868 868 + 0x0006b77e, 869 869 + 0xa87ef4bd, 870 870 + 0x11f40006, 871 871 + 0x40019810, 872 872 + 0xf40511fd, 873 873 + 0x2e7e070b, 874 874 + /* 0x0962: ctx_xfer_no_post_mmio */ 875 875 + /* 0x0962: ctx_xfer_done */ 876 876 + 0x00f80008, 877 877 0x00000000, 878 878 0x00000000, 879 879 0x00000000,

+126 -62

drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h

reviewed

··· 528 528 0x0001d001, 529 529 0x17f104bd, 530 530 0xf7f00100, 531 531 - 0xb521f502, 532 532 - 0xc721f507, 533 533 - 0x10f7f007, 534 534 - 0x081421f5, 531 531 + 0x0d21f502, 532 532 + 0x1f21f508, 533 533 + 0x10f7f008, 534 534 + 0x086c21f5, 535 535 0x98000e98, 536 536 0x21f5010f, 537 537 0x14950150, ··· 574 574 0xb6800040, 575 575 0x1bf40132, 576 576 0x00f7f0be, 577 577 - 0x081421f5, 577 577 + 0x086c21f5, 578 578 0xf500f7f0, 579 579 - 0xf107b521, 579 579 + 0xf1080d21, 580 580 0xf0010007, 581 581 0x01d00203, 582 582 0xbd04bd00, ··· 610 610 0x09d00203, 611 611 0xf404bd00, 612 612 0x31f40132, 613 613 - 0xe821f502, 614 614 - 0xf094bd09, 613 613 + 0x4021f502, 614 614 + 0xf094bd0a, 615 615 0x07f10799, 616 616 0x03f01700, 617 617 0x0009d002, ··· 621 621 0x0203f00f, 622 622 0xbd0009d0, 623 623 0x0131f404, 624 624 - 0x09e821f5, 624 624 + 0x0a4021f5, 625 625 0x99f094bd, 626 626 0x0007f106, 627 627 0x0203f017, ··· 631 631 0x12b920f9, 632 632 0x0132f402, 633 633 0xf50232f4, 634 634 - 0xfc09e821, 634 634 + 0xfc0a4021, 635 635 0x0007f120, 636 636 0x0203f0c0, 637 637 0xbd0002d0, ··· 640 640 0xf41f23c8, 641 641 0x31f40d0b, 642 642 0x0232f401, 643 643 - 0x09e821f5, 643 643 + 0x0a4021f5, 644 644 /* 0x063c: chsw_done */ 645 645 0xf10127f0, 646 646 0xf0c30007, ··· 654 654 /* 0x0660: main_not_ctx_switch */ 655 655 0xf401e4b0, 656 656 0xf2b90d1b, 657 657 - 0x7821f502, 657 657 + 0xd021f502, 658 658 0x460ef409, 659 659 /* 0x0670: main_not_ctx_chan */ 660 660 0xf402e4b0, ··· 664 664 0x09d00203, 665 665 0xf404bd00, 666 666 0x32f40132, 667 667 - 0xe821f502, 668 668 - 0xf094bd09, 667 667 + 0x4021f502, 668 668 + 0xf094bd0a, 669 669 0x07f10799, 670 670 0x03f01700, 671 671 0x0009d002, ··· 710 710 /* 0x072b: ih_no_ctxsw */ 711 711 0xe40421f4, 712 712 0xf40400ab, 713 713 - 0xb7f1140b, 713 713 + 0xe7f16c0b, 714 714 + 0xe3f00708, 715 715 + 0x6821f440, 716 716 + 0xf102ffb9, 717 717 + 0xf0040007, 718 718 + 0x0fd00203, 719 719 + 0xf104bd00, 720 720 + 0xf00704e7, 721 721 + 0x21f440e3, 722 722 + 0x02ffb968, 723 723 + 0x030007f1, 724 724 + 0xd00203f0, 725 725 + 0x04bd000f, 726 726 + 0x9450fec7, 727 727 + 0xf7f102ee, 728 728 + 0xf3f00700, 729 729 + 0x00efbb40, 730 730 + 0xf16821f4, 731 731 + 0xf0020007, 732 732 + 0x0fd00203, 733 733 + 0xf004bd00, 734 734 + 0x21f503f7, 735 735 + 0xb7f1037e, 714 736 0xbfb90100, 715 737 0x44e7f102, 716 738 0x40e3f001, 717 717 - /* 0x0743: ih_no_fwmthd */ 739 739 + /* 0x079b: ih_no_fwmthd */ 718 740 0xf19d21f4, 719 719 - 0xbd0104b7, 741 741 + 0xbd0504b7, 720 742 0xb4abffb0, 721 743 0xf10f0bf4, 722 744 0xf0070007, 723 745 0x0bd00303, 724 724 - /* 0x075b: ih_no_other */ 746 746 + /* 0x07b3: ih_no_other */ 725 747 0xf104bd00, 726 748 0xf0010007, 727 749 0x0ad00003, ··· 753 731 0xfc90fca0, 754 732 0x0088fe80, 755 733 0x32f480fc, 756 756 - /* 0x077f: ctx_4160s */ 734 734 + /* 0x07d7: ctx_4160s */ 757 735 0xf001f800, 758 736 0xffb901f7, 759 737 0x60e7f102, 760 738 0x40e3f041, 761 761 - /* 0x078f: ctx_4160s_wait */ 739 739 + /* 0x07e7: ctx_4160s_wait */ 762 740 0xf19d21f4, 763 741 0xf04160e7, 764 742 0x21f440e3, 765 743 0x02ffb968, 766 744 0xf404ffc8, 767 745 0x00f8f00b, 768 768 - /* 0x07a4: ctx_4160c */ 746 746 + /* 0x07fc: ctx_4160c */ 769 747 0xffb9f4bd, 770 748 0x60e7f102, 771 749 0x40e3f041, 772 750 0xf89d21f4, 773 773 - /* 0x07b5: ctx_4170s */ 751 751 + /* 0x080d: ctx_4170s */ 774 752 0x10f5f000, 775 753 0xf102ffb9, 776 754 0xf04170e7, 777 755 0x21f440e3, 778 778 - /* 0x07c7: ctx_4170w */ 756 756 + /* 0x081f: ctx_4170w */ 779 757 0xf100f89d, 780 758 0xf04170e7, 781 759 0x21f440e3, 782 760 0x02ffb968, 783 761 0xf410f4f0, 784 762 0x00f8f01b, 785 785 - /* 0x07dc: ctx_redswitch */ 763 763 + /* 0x0834: ctx_redswitch */ 786 764 0x0200e7f1, 787 765 0xf040e5f0, 788 766 0xe5f020e5, ··· 790 768 0x0103f085, 791 769 0xbd000ed0, 792 770 0x08f7f004, 793 793 - /* 0x07f8: ctx_redswitch_delay */ 771 771 + /* 0x0850: ctx_redswitch_delay */ 794 772 0xf401f2b6, 795 773 0xe5f1fd1b, 796 774 0xe5f10400, ··· 798 776 0x03f08500, 799 777 0x000ed001, 800 778 0x00f804bd, 801 801 - /* 0x0814: ctx_86c */ 779 779 + /* 0x086c: ctx_86c */ 802 780 0x1b0007f1, 803 781 0xd00203f0, 804 782 0x04bd000f, ··· 809 787 0xa86ce7f1, 810 788 0xf441e3f0, 811 789 0x00f89d21, 812 812 - /* 0x083c: ctx_mem */ 790 790 + /* 0x0894: ctx_mem */ 813 791 0x840007f1, 814 792 0xd00203f0, 815 793 0x04bd000f, 816 816 - /* 0x0848: ctx_mem_wait */ 794 794 + /* 0x08a0: ctx_mem_wait */ 817 795 0x8400f7f1, 818 796 0xcf02f3f0, 819 797 0xfffd00ff, 820 798 0xf31bf405, 821 821 - /* 0x085a: ctx_load */ 799 799 + /* 0x08b2: ctx_load */ 822 800 0x94bd00f8, 823 801 0xf10599f0, 824 802 0xf00f0007, ··· 836 814 0x02d00203, 837 815 0xf004bd00, 838 816 0x21f507f7, 839 839 - 0x07f1083c, 817 817 + 0x07f10894, 840 818 0x03f0c000, 841 819 0x0002d002, 842 820 0x0bfe04bd, ··· 891 869 0x03f01700, 892 870 0x0009d002, 893 871 0x00f804bd, 894 894 - /* 0x0978: ctx_chan */ 895 895 - 0x077f21f5, 896 896 - 0x085a21f5, 872 872 + /* 0x09d0: ctx_chan */ 873 873 + 0x07d721f5, 874 874 + 0x08b221f5, 897 875 0xf40ca7f0, 898 876 0xf7f0d021, 899 899 - 0x3c21f505, 900 900 - 0xa421f508, 901 901 - /* 0x0993: ctx_mmio_exec */ 877 877 + 0x9421f505, 878 878 + 0xfc21f508, 879 879 + /* 0x09eb: ctx_mmio_exec */ 902 880 0x9800f807, 903 881 0x07f14103, 904 882 0x03f08100, 905 883 0x0003d002, 906 884 0x34bd04bd, 907 907 - /* 0x09a4: ctx_mmio_loop */ 885 885 + /* 0x09fc: ctx_mmio_loop */ 908 886 0xf4ff34c4, 909 887 0x57f10f1b, 910 888 0x53f00200, 911 889 0x0535fa06, 912 912 - /* 0x09b6: ctx_mmio_pull */ 890 890 + /* 0x0a0e: ctx_mmio_pull */ 913 891 0x4e9803f8, 914 892 0x814f9880, 915 893 0xb69d21f4, 916 894 0x12b60830, 917 895 0xdf1bf401, 918 918 - /* 0x09c8: ctx_mmio_done */ 896 896 + /* 0x0a20: ctx_mmio_done */ 919 897 0xf1160398, 920 898 0xf0810007, 921 899 0x03d00203, ··· 924 902 0x13f00100, 925 903 0x0601fa06, 926 904 0x00f803f8, 927 927 - /* 0x09e8: ctx_xfer */ 905 905 + /* 0x0a40: ctx_xfer */ 928 906 0xf104e7f0, 929 907 0xf0020007, 930 908 0x0ed00303, 931 931 - /* 0x09f7: ctx_xfer_idle */ 909 909 + /* 0x0a4f: ctx_xfer_idle */ 932 910 0xf104bd00, 933 911 0xf00000e7, 934 912 0xeecf03e3, 935 913 0x00e4f100, 936 914 0xf21bf420, 937 915 0xf40611f4, 938 938 - /* 0x0a0e: ctx_xfer_pre */ 916 916 + /* 0x0a66: ctx_xfer_pre */ 939 917 0xf7f01102, 940 940 - 0x1421f510, 941 941 - 0x7f21f508, 918 918 + 0x6c21f510, 919 919 + 0xd721f508, 942 920 0x1c11f407, 943 943 - /* 0x0a1c: ctx_xfer_pre_load */ 921 921 + /* 0x0a74: ctx_xfer_pre_load */ 944 922 0xf502f7f0, 945 945 - 0xf507b521, 946 946 - 0xf507c721, 947 947 - 0xbd07dc21, 948 948 - 0xb521f5f4, 949 949 - 0x5a21f507, 950 950 - /* 0x0a35: ctx_xfer_exec */ 923 923 + 0xf5080d21, 924 924 + 0xf5081f21, 925 925 + 0xbd083421, 926 926 + 0x0d21f5f4, 927 927 + 0xb221f508, 928 928 + /* 0x0a8d: ctx_xfer_exec */ 951 929 0x16019808, 952 930 0x07f124bd, 953 931 0x03f00500, ··· 982 960 0x1301f402, 983 961 0xf40ca7f0, 984 962 0xf7f0d021, 985 985 - 0x3c21f505, 963 963 + 0x9421f505, 986 964 0x3202f408, 987 987 - /* 0x0ac4: ctx_xfer_post */ 965 965 + /* 0x0b1c: ctx_xfer_post */ 988 966 0xf502f7f0, 989 989 - 0xbd07b521, 990 990 - 0x1421f5f4, 967 967 + 0xbd080d21, 968 968 + 0x6c21f5f4, 991 969 0x7f21f508, 992 992 - 0xc721f502, 993 993 - 0xf5f4bd07, 994 994 - 0xf407b521, 970 970 + 0x1f21f502, 971 971 + 0xf5f4bd08, 972 972 + 0xf4080d21, 995 973 0x01981011, 996 974 0x0511fd40, 997 975 0xf5070bf4, 998 998 - /* 0x0aef: ctx_xfer_no_post_mmio */ 999 999 - 0xf5099321, 1000 1000 - /* 0x0af3: ctx_xfer_done */ 1001 1001 - 0xf807a421, 976 976 + /* 0x0b47: ctx_xfer_no_post_mmio */ 977 977 + 0xf509eb21, 978 978 + /* 0x0b4b: ctx_xfer_done */ 979 979 + 0xf807fc21, 980 980 + 0x00000000, 981 981 + 0x00000000, 982 982 + 0x00000000, 983 983 + 0x00000000, 984 984 + 0x00000000, 985 985 + 0x00000000, 986 986 + 0x00000000, 987 987 + 0x00000000, 988 988 + 0x00000000, 989 989 + 0x00000000, 990 990 + 0x00000000, 991 991 + 0x00000000, 992 992 + 0x00000000, 993 993 + 0x00000000, 994 994 + 0x00000000, 995 995 + 0x00000000, 996 996 + 0x00000000, 997 997 + 0x00000000, 998 998 + 0x00000000, 999 999 + 0x00000000, 1000 1000 + 0x00000000, 1001 1001 + 0x00000000, 1002 1002 + 0x00000000, 1003 1003 + 0x00000000, 1004 1004 + 0x00000000, 1005 1005 + 0x00000000, 1006 1006 + 0x00000000, 1007 1007 + 0x00000000, 1008 1008 + 0x00000000, 1009 1009 + 0x00000000, 1010 1010 + 0x00000000, 1011 1011 + 0x00000000, 1012 1012 + 0x00000000, 1013 1013 + 0x00000000, 1014 1014 + 0x00000000, 1015 1015 + 0x00000000, 1016 1016 + 0x00000000, 1017 1017 + 0x00000000, 1018 1018 + 0x00000000, 1019 1019 + 0x00000000, 1020 1020 + 0x00000000, 1021 1021 + 0x00000000, 1002 1022 0x00000000, 1003 1023 0x00000000, 1004 1024 0x00000000,

+126 -62

drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h

reviewed

··· 528 528 0x0001d001, 529 529 0x17f104bd, 530 530 0xf7f00100, 531 531 - 0xb521f502, 532 532 - 0xc721f507, 533 533 - 0x10f7f007, 534 534 - 0x081421f5, 531 531 + 0x0d21f502, 532 532 + 0x1f21f508, 533 533 + 0x10f7f008, 534 534 + 0x086c21f5, 535 535 0x98000e98, 536 536 0x21f5010f, 537 537 0x14950150, ··· 574 574 0xb6800040, 575 575 0x1bf40132, 576 576 0x00f7f0be, 577 577 - 0x081421f5, 577 577 + 0x086c21f5, 578 578 0xf500f7f0, 579 579 - 0xf107b521, 579 579 + 0xf1080d21, 580 580 0xf0010007, 581 581 0x01d00203, 582 582 0xbd04bd00, ··· 610 610 0x09d00203, 611 611 0xf404bd00, 612 612 0x31f40132, 613 613 - 0xe821f502, 614 614 - 0xf094bd09, 613 613 + 0x4021f502, 614 614 + 0xf094bd0a, 615 615 0x07f10799, 616 616 0x03f01700, 617 617 0x0009d002, ··· 621 621 0x0203f00f, 622 622 0xbd0009d0, 623 623 0x0131f404, 624 624 - 0x09e821f5, 624 624 + 0x0a4021f5, 625 625 0x99f094bd, 626 626 0x0007f106, 627 627 0x0203f017, ··· 631 631 0x12b920f9, 632 632 0x0132f402, 633 633 0xf50232f4, 634 634 - 0xfc09e821, 634 634 + 0xfc0a4021, 635 635 0x0007f120, 636 636 0x0203f0c0, 637 637 0xbd0002d0, ··· 640 640 0xf41f23c8, 641 641 0x31f40d0b, 642 642 0x0232f401, 643 643 - 0x09e821f5, 643 643 + 0x0a4021f5, 644 644 /* 0x063c: chsw_done */ 645 645 0xf10127f0, 646 646 0xf0c30007, ··· 654 654 /* 0x0660: main_not_ctx_switch */ 655 655 0xf401e4b0, 656 656 0xf2b90d1b, 657 657 - 0x7821f502, 657 657 + 0xd021f502, 658 658 0x460ef409, 659 659 /* 0x0670: main_not_ctx_chan */ 660 660 0xf402e4b0, ··· 664 664 0x09d00203, 665 665 0xf404bd00, 666 666 0x32f40132, 667 667 - 0xe821f502, 668 668 - 0xf094bd09, 667 667 + 0x4021f502, 668 668 + 0xf094bd0a, 669 669 0x07f10799, 670 670 0x03f01700, 671 671 0x0009d002, ··· 710 710 /* 0x072b: ih_no_ctxsw */ 711 711 0xe40421f4, 712 712 0xf40400ab, 713 713 - 0xb7f1140b, 713 713 + 0xe7f16c0b, 714 714 + 0xe3f00708, 715 715 + 0x6821f440, 716 716 + 0xf102ffb9, 717 717 + 0xf0040007, 718 718 + 0x0fd00203, 719 719 + 0xf104bd00, 720 720 + 0xf00704e7, 721 721 + 0x21f440e3, 722 722 + 0x02ffb968, 723 723 + 0x030007f1, 724 724 + 0xd00203f0, 725 725 + 0x04bd000f, 726 726 + 0x9450fec7, 727 727 + 0xf7f102ee, 728 728 + 0xf3f00700, 729 729 + 0x00efbb40, 730 730 + 0xf16821f4, 731 731 + 0xf0020007, 732 732 + 0x0fd00203, 733 733 + 0xf004bd00, 734 734 + 0x21f503f7, 735 735 + 0xb7f1037e, 714 736 0xbfb90100, 715 737 0x44e7f102, 716 738 0x40e3f001, 717 717 - /* 0x0743: ih_no_fwmthd */ 739 739 + /* 0x079b: ih_no_fwmthd */ 718 740 0xf19d21f4, 719 719 - 0xbd0104b7, 741 741 + 0xbd0504b7, 720 742 0xb4abffb0, 721 743 0xf10f0bf4, 722 744 0xf0070007, 723 745 0x0bd00303, 724 724 - /* 0x075b: ih_no_other */ 746 746 + /* 0x07b3: ih_no_other */ 725 747 0xf104bd00, 726 748 0xf0010007, 727 749 0x0ad00003, ··· 753 731 0xfc90fca0, 754 732 0x0088fe80, 755 733 0x32f480fc, 756 756 - /* 0x077f: ctx_4160s */ 734 734 + /* 0x07d7: ctx_4160s */ 757 735 0xf001f800, 758 736 0xffb901f7, 759 737 0x60e7f102, 760 738 0x40e3f041, 761 761 - /* 0x078f: ctx_4160s_wait */ 739 739 + /* 0x07e7: ctx_4160s_wait */ 762 740 0xf19d21f4, 763 741 0xf04160e7, 764 742 0x21f440e3, 765 743 0x02ffb968, 766 744 0xf404ffc8, 767 745 0x00f8f00b, 768 768 - /* 0x07a4: ctx_4160c */ 746 746 + /* 0x07fc: ctx_4160c */ 769 747 0xffb9f4bd, 770 748 0x60e7f102, 771 749 0x40e3f041, 772 750 0xf89d21f4, 773 773 - /* 0x07b5: ctx_4170s */ 751 751 + /* 0x080d: ctx_4170s */ 774 752 0x10f5f000, 775 753 0xf102ffb9, 776 754 0xf04170e7, 777 755 0x21f440e3, 778 778 - /* 0x07c7: ctx_4170w */ 756 756 + /* 0x081f: ctx_4170w */ 779 757 0xf100f89d, 780 758 0xf04170e7, 781 759 0x21f440e3, 782 760 0x02ffb968, 783 761 0xf410f4f0, 784 762 0x00f8f01b, 785 785 - /* 0x07dc: ctx_redswitch */ 763 763 + /* 0x0834: ctx_redswitch */ 786 764 0x0200e7f1, 787 765 0xf040e5f0, 788 766 0xe5f020e5, ··· 790 768 0x0103f085, 791 769 0xbd000ed0, 792 770 0x08f7f004, 793 793 - /* 0x07f8: ctx_redswitch_delay */ 771 771 + /* 0x0850: ctx_redswitch_delay */ 794 772 0xf401f2b6, 795 773 0xe5f1fd1b, 796 774 0xe5f10400, ··· 798 776 0x03f08500, 799 777 0x000ed001, 800 778 0x00f804bd, 801 801 - /* 0x0814: ctx_86c */ 779 779 + /* 0x086c: ctx_86c */ 802 780 0x1b0007f1, 803 781 0xd00203f0, 804 782 0x04bd000f, ··· 809 787 0xa86ce7f1, 810 788 0xf441e3f0, 811 789 0x00f89d21, 812 812 - /* 0x083c: ctx_mem */ 790 790 + /* 0x0894: ctx_mem */ 813 791 0x840007f1, 814 792 0xd00203f0, 815 793 0x04bd000f, 816 816 - /* 0x0848: ctx_mem_wait */ 794 794 + /* 0x08a0: ctx_mem_wait */ 817 795 0x8400f7f1, 818 796 0xcf02f3f0, 819 797 0xfffd00ff, 820 798 0xf31bf405, 821 821 - /* 0x085a: ctx_load */ 799 799 + /* 0x08b2: ctx_load */ 822 800 0x94bd00f8, 823 801 0xf10599f0, 824 802 0xf00f0007, ··· 836 814 0x02d00203, 837 815 0xf004bd00, 838 816 0x21f507f7, 839 839 - 0x07f1083c, 817 817 + 0x07f10894, 840 818 0x03f0c000, 841 819 0x0002d002, 842 820 0x0bfe04bd, ··· 891 869 0x03f01700, 892 870 0x0009d002, 893 871 0x00f804bd, 894 894 - /* 0x0978: ctx_chan */ 895 895 - 0x077f21f5, 896 896 - 0x085a21f5, 872 872 + /* 0x09d0: ctx_chan */ 873 873 + 0x07d721f5, 874 874 + 0x08b221f5, 897 875 0xf40ca7f0, 898 876 0xf7f0d021, 899 899 - 0x3c21f505, 900 900 - 0xa421f508, 901 901 - /* 0x0993: ctx_mmio_exec */ 877 877 + 0x9421f505, 878 878 + 0xfc21f508, 879 879 + /* 0x09eb: ctx_mmio_exec */ 902 880 0x9800f807, 903 881 0x07f14103, 904 882 0x03f08100, 905 883 0x0003d002, 906 884 0x34bd04bd, 907 907 - /* 0x09a4: ctx_mmio_loop */ 885 885 + /* 0x09fc: ctx_mmio_loop */ 908 886 0xf4ff34c4, 909 887 0x57f10f1b, 910 888 0x53f00200, 911 889 0x0535fa06, 912 912 - /* 0x09b6: ctx_mmio_pull */ 890 890 + /* 0x0a0e: ctx_mmio_pull */ 913 891 0x4e9803f8, 914 892 0x814f9880, 915 893 0xb69d21f4, 916 894 0x12b60830, 917 895 0xdf1bf401, 918 918 - /* 0x09c8: ctx_mmio_done */ 896 896 + /* 0x0a20: ctx_mmio_done */ 919 897 0xf1160398, 920 898 0xf0810007, 921 899 0x03d00203, ··· 924 902 0x13f00100, 925 903 0x0601fa06, 926 904 0x00f803f8, 927 927 - /* 0x09e8: ctx_xfer */ 905 905 + /* 0x0a40: ctx_xfer */ 928 906 0xf104e7f0, 929 907 0xf0020007, 930 908 0x0ed00303, 931 931 - /* 0x09f7: ctx_xfer_idle */ 909 909 + /* 0x0a4f: ctx_xfer_idle */ 932 910 0xf104bd00, 933 911 0xf00000e7, 934 912 0xeecf03e3, 935 913 0x00e4f100, 936 914 0xf21bf420, 937 915 0xf40611f4, 938 938 - /* 0x0a0e: ctx_xfer_pre */ 916 916 + /* 0x0a66: ctx_xfer_pre */ 939 917 0xf7f01102, 940 940 - 0x1421f510, 941 941 - 0x7f21f508, 918 918 + 0x6c21f510, 919 919 + 0xd721f508, 942 920 0x1c11f407, 943 943 - /* 0x0a1c: ctx_xfer_pre_load */ 921 921 + /* 0x0a74: ctx_xfer_pre_load */ 944 922 0xf502f7f0, 945 945 - 0xf507b521, 946 946 - 0xf507c721, 947 947 - 0xbd07dc21, 948 948 - 0xb521f5f4, 949 949 - 0x5a21f507, 950 950 - /* 0x0a35: ctx_xfer_exec */ 923 923 + 0xf5080d21, 924 924 + 0xf5081f21, 925 925 + 0xbd083421, 926 926 + 0x0d21f5f4, 927 927 + 0xb221f508, 928 928 + /* 0x0a8d: ctx_xfer_exec */ 951 929 0x16019808, 952 930 0x07f124bd, 953 931 0x03f00500, ··· 982 960 0x1301f402, 983 961 0xf40ca7f0, 984 962 0xf7f0d021, 985 985 - 0x3c21f505, 963 963 + 0x9421f505, 986 964 0x3202f408, 987 987 - /* 0x0ac4: ctx_xfer_post */ 965 965 + /* 0x0b1c: ctx_xfer_post */ 988 966 0xf502f7f0, 989 989 - 0xbd07b521, 990 990 - 0x1421f5f4, 967 967 + 0xbd080d21, 968 968 + 0x6c21f5f4, 991 969 0x7f21f508, 992 992 - 0xc721f502, 993 993 - 0xf5f4bd07, 994 994 - 0xf407b521, 970 970 + 0x1f21f502, 971 971 + 0xf5f4bd08, 972 972 + 0xf4080d21, 995 973 0x01981011, 996 974 0x0511fd40, 997 975 0xf5070bf4, 998 998 - /* 0x0aef: ctx_xfer_no_post_mmio */ 999 999 - 0xf5099321, 1000 1000 - /* 0x0af3: ctx_xfer_done */ 1001 1001 - 0xf807a421, 976 976 + /* 0x0b47: ctx_xfer_no_post_mmio */ 977 977 + 0xf509eb21, 978 978 + /* 0x0b4b: ctx_xfer_done */ 979 979 + 0xf807fc21, 980 980 + 0x00000000, 981 981 + 0x00000000, 982 982 + 0x00000000, 983 983 + 0x00000000, 984 984 + 0x00000000, 985 985 + 0x00000000, 986 986 + 0x00000000, 987 987 + 0x00000000, 988 988 + 0x00000000, 989 989 + 0x00000000, 990 990 + 0x00000000, 991 991 + 0x00000000, 992 992 + 0x00000000, 993 993 + 0x00000000, 994 994 + 0x00000000, 995 995 + 0x00000000, 996 996 + 0x00000000, 997 997 + 0x00000000, 998 998 + 0x00000000, 999 999 + 0x00000000, 1000 1000 + 0x00000000, 1001 1001 + 0x00000000, 1002 1002 + 0x00000000, 1003 1003 + 0x00000000, 1004 1004 + 0x00000000, 1005 1005 + 0x00000000, 1006 1006 + 0x00000000, 1007 1007 + 0x00000000, 1008 1008 + 0x00000000, 1009 1009 + 0x00000000, 1010 1010 + 0x00000000, 1011 1011 + 0x00000000, 1012 1012 + 0x00000000, 1013 1013 + 0x00000000, 1014 1014 + 0x00000000, 1015 1015 + 0x00000000, 1016 1016 + 0x00000000, 1017 1017 + 0x00000000, 1018 1018 + 0x00000000, 1019 1019 + 0x00000000, 1020 1020 + 0x00000000, 1021 1021 + 0x00000000, 1002 1022 0x00000000, 1003 1023 0x00000000, 1004 1024 0x00000000,

+117 -53

drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h

reviewed

··· 528 528 0x0001d001, 529 529 0x17f104bd, 530 530 0xf7f00100, 531 531 - 0x7f21f502, 532 532 - 0x9121f507, 531 531 + 0xd721f502, 532 532 + 0xe921f507, 533 533 0x10f7f007, 534 534 - 0x07de21f5, 534 534 + 0x083621f5, 535 535 0x98000e98, 536 536 0x21f5010f, 537 537 0x14950150, ··· 574 574 0xb6800040, 575 575 0x1bf40132, 576 576 0x00f7f0be, 577 577 - 0x07de21f5, 577 577 + 0x083621f5, 578 578 0xf500f7f0, 579 579 - 0xf1077f21, 579 579 + 0xf107d721, 580 580 0xf0010007, 581 581 0x01d00203, 582 582 0xbd04bd00, ··· 610 610 0x09d00203, 611 611 0xf404bd00, 612 612 0x31f40132, 613 613 - 0xaa21f502, 614 614 - 0xf094bd09, 613 613 + 0x0221f502, 614 614 + 0xf094bd0a, 615 615 0x07f10799, 616 616 0x03f01700, 617 617 0x0009d002, ··· 621 621 0x0203f00f, 622 622 0xbd0009d0, 623 623 0x0131f404, 624 624 - 0x09aa21f5, 624 624 + 0x0a0221f5, 625 625 0x99f094bd, 626 626 0x0007f106, 627 627 0x0203f017, ··· 631 631 0x12b920f9, 632 632 0x0132f402, 633 633 0xf50232f4, 634 634 - 0xfc09aa21, 634 634 + 0xfc0a0221, 635 635 0x0007f120, 636 636 0x0203f0c0, 637 637 0xbd0002d0, ··· 640 640 0xf41f23c8, 641 641 0x31f40d0b, 642 642 0x0232f401, 643 643 - 0x09aa21f5, 643 643 + 0x0a0221f5, 644 644 /* 0x063c: chsw_done */ 645 645 0xf10127f0, 646 646 0xf0c30007, ··· 654 654 /* 0x0660: main_not_ctx_switch */ 655 655 0xf401e4b0, 656 656 0xf2b90d1b, 657 657 - 0x4221f502, 657 657 + 0x9a21f502, 658 658 0x460ef409, 659 659 /* 0x0670: main_not_ctx_chan */ 660 660 0xf402e4b0, ··· 664 664 0x09d00203, 665 665 0xf404bd00, 666 666 0x32f40132, 667 667 - 0xaa21f502, 668 668 - 0xf094bd09, 667 667 + 0x0221f502, 668 668 + 0xf094bd0a, 669 669 0x07f10799, 670 670 0x03f01700, 671 671 0x0009d002, ··· 710 710 /* 0x072b: ih_no_ctxsw */ 711 711 0xe40421f4, 712 712 0xf40400ab, 713 713 - 0xb7f1140b, 713 713 + 0xe7f16c0b, 714 714 + 0xe3f00708, 715 715 + 0x6821f440, 716 716 + 0xf102ffb9, 717 717 + 0xf0040007, 718 718 + 0x0fd00203, 719 719 + 0xf104bd00, 720 720 + 0xf00704e7, 721 721 + 0x21f440e3, 722 722 + 0x02ffb968, 723 723 + 0x030007f1, 724 724 + 0xd00203f0, 725 725 + 0x04bd000f, 726 726 + 0x9450fec7, 727 727 + 0xf7f102ee, 728 728 + 0xf3f00700, 729 729 + 0x00efbb40, 730 730 + 0xf16821f4, 731 731 + 0xf0020007, 732 732 + 0x0fd00203, 733 733 + 0xf004bd00, 734 734 + 0x21f503f7, 735 735 + 0xb7f1037e, 714 736 0xbfb90100, 715 737 0x44e7f102, 716 738 0x40e3f001, 717 717 - /* 0x0743: ih_no_fwmthd */ 739 739 + /* 0x079b: ih_no_fwmthd */ 718 740 0xf19d21f4, 719 719 - 0xbd0104b7, 741 741 + 0xbd0504b7, 720 742 0xb4abffb0, 721 743 0xf10f0bf4, 722 744 0xf0070007, 723 745 0x0bd00303, 724 724 - /* 0x075b: ih_no_other */ 746 746 + /* 0x07b3: ih_no_other */ 725 747 0xf104bd00, 726 748 0xf0010007, 727 749 0x0ad00003, ··· 753 731 0xfc90fca0, 754 732 0x0088fe80, 755 733 0x32f480fc, 756 756 - /* 0x077f: ctx_4170s */ 734 734 + /* 0x07d7: ctx_4170s */ 757 735 0xf001f800, 758 736 0xffb910f5, 759 737 0x70e7f102, 760 738 0x40e3f041, 761 739 0xf89d21f4, 762 762 - /* 0x0791: ctx_4170w */ 740 740 + /* 0x07e9: ctx_4170w */ 763 741 0x70e7f100, 764 742 0x40e3f041, 765 743 0xb96821f4, 766 744 0xf4f002ff, 767 745 0xf01bf410, 768 768 - /* 0x07a6: ctx_redswitch */ 746 746 + /* 0x07fe: ctx_redswitch */ 769 747 0xe7f100f8, 770 748 0xe5f00200, 771 749 0x20e5f040, ··· 773 751 0xf0850007, 774 752 0x0ed00103, 775 753 0xf004bd00, 776 776 - /* 0x07c2: ctx_redswitch_delay */ 754 754 + /* 0x081a: ctx_redswitch_delay */ 777 755 0xf2b608f7, 778 756 0xfd1bf401, 779 757 0x0400e5f1, ··· 781 759 0x850007f1, 782 760 0xd00103f0, 783 761 0x04bd000e, 784 784 - /* 0x07de: ctx_86c */ 762 762 + /* 0x0836: ctx_86c */ 785 763 0x07f100f8, 786 764 0x03f01b00, 787 765 0x000fd002, ··· 792 770 0xe7f102ff, 793 771 0xe3f0a86c, 794 772 0x9d21f441, 795 795 - /* 0x0806: ctx_mem */ 773 773 + /* 0x085e: ctx_mem */ 796 774 0x07f100f8, 797 775 0x03f08400, 798 776 0x000fd002, 799 799 - /* 0x0812: ctx_mem_wait */ 777 777 + /* 0x086a: ctx_mem_wait */ 800 778 0xf7f104bd, 801 779 0xf3f08400, 802 780 0x00ffcf02, 803 781 0xf405fffd, 804 782 0x00f8f31b, 805 805 - /* 0x0824: ctx_load */ 783 783 + /* 0x087c: ctx_load */ 806 784 0x99f094bd, 807 785 0x0007f105, 808 786 0x0203f00f, ··· 819 797 0x0203f083, 820 798 0xbd0002d0, 821 799 0x07f7f004, 822 822 - 0x080621f5, 800 800 + 0x085e21f5, 823 801 0xc00007f1, 824 802 0xd00203f0, 825 803 0x04bd0002, ··· 874 852 0x170007f1, 875 853 0xd00203f0, 876 854 0x04bd0009, 877 877 - /* 0x0942: ctx_chan */ 855 855 + /* 0x099a: ctx_chan */ 878 856 0x21f500f8, 879 879 - 0xa7f00824, 857 857 + 0xa7f0087c, 880 858 0xd021f40c, 881 859 0xf505f7f0, 882 882 - 0xf8080621, 883 883 - /* 0x0955: ctx_mmio_exec */ 860 860 + 0xf8085e21, 861 861 + /* 0x09ad: ctx_mmio_exec */ 884 862 0x41039800, 885 863 0x810007f1, 886 864 0xd00203f0, 887 865 0x04bd0003, 888 888 - /* 0x0966: ctx_mmio_loop */ 866 866 + /* 0x09be: ctx_mmio_loop */ 889 867 0x34c434bd, 890 868 0x0f1bf4ff, 891 869 0x020057f1, 892 870 0xfa0653f0, 893 871 0x03f80535, 894 894 - /* 0x0978: ctx_mmio_pull */ 872 872 + /* 0x09d0: ctx_mmio_pull */ 895 873 0x98804e98, 896 874 0x21f4814f, 897 875 0x0830b69d, 898 876 0xf40112b6, 899 899 - /* 0x098a: ctx_mmio_done */ 877 877 + /* 0x09e2: ctx_mmio_done */ 900 878 0x0398df1b, 901 879 0x0007f116, 902 880 0x0203f081, ··· 905 883 0x010017f1, 906 884 0xfa0613f0, 907 885 0x03f80601, 908 908 - /* 0x09aa: ctx_xfer */ 886 886 + /* 0x0a02: ctx_xfer */ 909 887 0xe7f000f8, 910 888 0x0007f104, 911 889 0x0303f002, 912 890 0xbd000ed0, 913 913 - /* 0x09b9: ctx_xfer_idle */ 891 891 + /* 0x0a11: ctx_xfer_idle */ 914 892 0x00e7f104, 915 893 0x03e3f000, 916 894 0xf100eecf, 917 895 0xf42000e4, 918 896 0x11f4f21b, 919 897 0x0d02f406, 920 920 - /* 0x09d0: ctx_xfer_pre */ 898 898 + /* 0x0a28: ctx_xfer_pre */ 921 899 0xf510f7f0, 922 922 - 0xf407de21, 923 923 - /* 0x09da: ctx_xfer_pre_load */ 900 900 + 0xf4083621, 901 901 + /* 0x0a32: ctx_xfer_pre_load */ 924 902 0xf7f01c11, 925 925 - 0x7f21f502, 926 926 - 0x9121f507, 927 927 - 0xa621f507, 903 903 + 0xd721f502, 904 904 + 0xe921f507, 905 905 + 0xfe21f507, 928 906 0xf5f4bd07, 929 929 - 0xf5077f21, 930 930 - /* 0x09f3: ctx_xfer_exec */ 931 931 - 0x98082421, 907 907 + 0xf507d721, 908 908 + /* 0x0a4b: ctx_xfer_exec */ 909 909 + 0x98087c21, 932 910 0x24bd1601, 933 911 0x050007f1, 934 912 0xd00103f0, ··· 963 941 0xa7f01301, 964 942 0xd021f40c, 965 943 0xf505f7f0, 966 966 - 0xf4080621, 967 967 - /* 0x0a82: ctx_xfer_post */ 944 944 + 0xf4085e21, 945 945 + /* 0x0ada: ctx_xfer_post */ 968 946 0xf7f02e02, 969 969 - 0x7f21f502, 947 947 + 0xd721f502, 970 948 0xf5f4bd07, 971 971 - 0xf507de21, 949 949 + 0xf5083621, 972 950 0xf5027f21, 973 973 - 0xbd079121, 974 974 - 0x7f21f5f4, 951 951 + 0xbd07e921, 952 952 + 0xd721f5f4, 975 953 0x1011f407, 976 954 0xfd400198, 977 955 0x0bf40511, 978 978 - 0x5521f507, 979 979 - /* 0x0aad: ctx_xfer_no_post_mmio */ 980 980 - /* 0x0aad: ctx_xfer_done */ 956 956 + 0xad21f507, 957 957 + /* 0x0b05: ctx_xfer_no_post_mmio */ 958 958 + /* 0x0b05: ctx_xfer_done */ 981 959 0x0000f809, 960 960 + 0x00000000, 961 961 + 0x00000000, 962 962 + 0x00000000, 963 963 + 0x00000000, 964 964 + 0x00000000, 965 965 + 0x00000000, 966 966 + 0x00000000, 967 967 + 0x00000000, 968 968 + 0x00000000, 969 969 + 0x00000000, 970 970 + 0x00000000, 971 971 + 0x00000000, 972 972 + 0x00000000, 973 973 + 0x00000000, 974 974 + 0x00000000, 975 975 + 0x00000000, 976 976 + 0x00000000, 977 977 + 0x00000000, 978 978 + 0x00000000, 979 979 + 0x00000000, 980 980 + 0x00000000, 981 981 + 0x00000000, 982 982 + 0x00000000, 983 983 + 0x00000000, 984 984 + 0x00000000, 985 985 + 0x00000000, 986 986 + 0x00000000, 987 987 + 0x00000000, 988 988 + 0x00000000, 989 989 + 0x00000000, 990 990 + 0x00000000, 991 991 + 0x00000000, 992 992 + 0x00000000, 993 993 + 0x00000000, 994 994 + 0x00000000, 995 995 + 0x00000000, 996 996 + 0x00000000, 997 997 + 0x00000000, 998 998 + 0x00000000, 999 999 + 0x00000000, 1000 1000 + 0x00000000, 1001 1001 + 0x00000000, 982 1002 0x00000000, 983 1003 0x00000000, 984 1004 0x00000000,

+117 -53

drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h

reviewed

··· 528 528 0x0001d001, 529 529 0x17f104bd, 530 530 0xf7f00100, 531 531 - 0x7f21f502, 532 532 - 0x9121f507, 531 531 + 0xd721f502, 532 532 + 0xe921f507, 533 533 0x10f7f007, 534 534 - 0x07de21f5, 534 534 + 0x083621f5, 535 535 0x98000e98, 536 536 0x21f5010f, 537 537 0x14950150, ··· 574 574 0xb6800040, 575 575 0x1bf40132, 576 576 0x00f7f0be, 577 577 - 0x07de21f5, 577 577 + 0x083621f5, 578 578 0xf500f7f0, 579 579 - 0xf1077f21, 579 579 + 0xf107d721, 580 580 0xf0010007, 581 581 0x01d00203, 582 582 0xbd04bd00, ··· 610 610 0x09d00203, 611 611 0xf404bd00, 612 612 0x31f40132, 613 613 - 0xaa21f502, 614 614 - 0xf094bd09, 613 613 + 0x0221f502, 614 614 + 0xf094bd0a, 615 615 0x07f10799, 616 616 0x03f01700, 617 617 0x0009d002, ··· 621 621 0x0203f037, 622 622 0xbd0009d0, 623 623 0x0131f404, 624 624 - 0x09aa21f5, 624 624 + 0x0a0221f5, 625 625 0x99f094bd, 626 626 0x0007f106, 627 627 0x0203f017, ··· 631 631 0x12b920f9, 632 632 0x0132f402, 633 633 0xf50232f4, 634 634 - 0xfc09aa21, 634 634 + 0xfc0a0221, 635 635 0x0007f120, 636 636 0x0203f0c0, 637 637 0xbd0002d0, ··· 640 640 0xf41f23c8, 641 641 0x31f40d0b, 642 642 0x0232f401, 643 643 - 0x09aa21f5, 643 643 + 0x0a0221f5, 644 644 /* 0x063c: chsw_done */ 645 645 0xf10127f0, 646 646 0xf0c30007, ··· 654 654 /* 0x0660: main_not_ctx_switch */ 655 655 0xf401e4b0, 656 656 0xf2b90d1b, 657 657 - 0x4221f502, 657 657 + 0x9a21f502, 658 658 0x460ef409, 659 659 /* 0x0670: main_not_ctx_chan */ 660 660 0xf402e4b0, ··· 664 664 0x09d00203, 665 665 0xf404bd00, 666 666 0x32f40132, 667 667 - 0xaa21f502, 668 668 - 0xf094bd09, 667 667 + 0x0221f502, 668 668 + 0xf094bd0a, 669 669 0x07f10799, 670 670 0x03f01700, 671 671 0x0009d002, ··· 710 710 /* 0x072b: ih_no_ctxsw */ 711 711 0xe40421f4, 712 712 0xf40400ab, 713 713 - 0xb7f1140b, 713 713 + 0xe7f16c0b, 714 714 + 0xe3f00708, 715 715 + 0x6821f440, 716 716 + 0xf102ffb9, 717 717 + 0xf0040007, 718 718 + 0x0fd00203, 719 719 + 0xf104bd00, 720 720 + 0xf00704e7, 721 721 + 0x21f440e3, 722 722 + 0x02ffb968, 723 723 + 0x030007f1, 724 724 + 0xd00203f0, 725 725 + 0x04bd000f, 726 726 + 0x9450fec7, 727 727 + 0xf7f102ee, 728 728 + 0xf3f00700, 729 729 + 0x00efbb40, 730 730 + 0xf16821f4, 731 731 + 0xf0020007, 732 732 + 0x0fd00203, 733 733 + 0xf004bd00, 734 734 + 0x21f503f7, 735 735 + 0xb7f1037e, 714 736 0xbfb90100, 715 737 0x44e7f102, 716 738 0x40e3f001, 717 717 - /* 0x0743: ih_no_fwmthd */ 739 739 + /* 0x079b: ih_no_fwmthd */ 718 740 0xf19d21f4, 719 719 - 0xbd0104b7, 741 741 + 0xbd0504b7, 720 742 0xb4abffb0, 721 743 0xf10f0bf4, 722 744 0xf0070007, 723 745 0x0bd00303, 724 724 - /* 0x075b: ih_no_other */ 746 746 + /* 0x07b3: ih_no_other */ 725 747 0xf104bd00, 726 748 0xf0010007, 727 749 0x0ad00003, ··· 753 731 0xfc90fca0, 754 732 0x0088fe80, 755 733 0x32f480fc, 756 756 - /* 0x077f: ctx_4170s */ 734 734 + /* 0x07d7: ctx_4170s */ 757 735 0xf001f800, 758 736 0xffb910f5, 759 737 0x70e7f102, 760 738 0x40e3f041, 761 739 0xf89d21f4, 762 762 - /* 0x0791: ctx_4170w */ 740 740 + /* 0x07e9: ctx_4170w */ 763 741 0x70e7f100, 764 742 0x40e3f041, 765 743 0xb96821f4, 766 744 0xf4f002ff, 767 745 0xf01bf410, 768 768 - /* 0x07a6: ctx_redswitch */ 746 746 + /* 0x07fe: ctx_redswitch */ 769 747 0xe7f100f8, 770 748 0xe5f00200, 771 749 0x20e5f040, ··· 773 751 0xf0850007, 774 752 0x0ed00103, 775 753 0xf004bd00, 776 776 - /* 0x07c2: ctx_redswitch_delay */ 754 754 + /* 0x081a: ctx_redswitch_delay */ 777 755 0xf2b608f7, 778 756 0xfd1bf401, 779 757 0x0400e5f1, ··· 781 759 0x850007f1, 782 760 0xd00103f0, 783 761 0x04bd000e, 784 784 - /* 0x07de: ctx_86c */ 762 762 + /* 0x0836: ctx_86c */ 785 763 0x07f100f8, 786 764 0x03f02300, 787 765 0x000fd002, ··· 792 770 0xe7f102ff, 793 771 0xe3f0a88c, 794 772 0x9d21f441, 795 795 - /* 0x0806: ctx_mem */ 773 773 + /* 0x085e: ctx_mem */ 796 774 0x07f100f8, 797 775 0x03f08400, 798 776 0x000fd002, 799 799 - /* 0x0812: ctx_mem_wait */ 777 777 + /* 0x086a: ctx_mem_wait */ 800 778 0xf7f104bd, 801 779 0xf3f08400, 802 780 0x00ffcf02, 803 781 0xf405fffd, 804 782 0x00f8f31b, 805 805 - /* 0x0824: ctx_load */ 783 783 + /* 0x087c: ctx_load */ 806 784 0x99f094bd, 807 785 0x0007f105, 808 786 0x0203f037, ··· 819 797 0x0203f083, 820 798 0xbd0002d0, 821 799 0x07f7f004, 822 822 - 0x080621f5, 800 800 + 0x085e21f5, 823 801 0xc00007f1, 824 802 0xd00203f0, 825 803 0x04bd0002, ··· 874 852 0x170007f1, 875 853 0xd00203f0, 876 854 0x04bd0009, 877 877 - /* 0x0942: ctx_chan */ 855 855 + /* 0x099a: ctx_chan */ 878 856 0x21f500f8, 879 879 - 0xa7f00824, 857 857 + 0xa7f0087c, 880 858 0xd021f40c, 881 859 0xf505f7f0, 882 882 - 0xf8080621, 883 883 - /* 0x0955: ctx_mmio_exec */ 860 860 + 0xf8085e21, 861 861 + /* 0x09ad: ctx_mmio_exec */ 884 862 0x41039800, 885 863 0x810007f1, 886 864 0xd00203f0, 887 865 0x04bd0003, 888 888 - /* 0x0966: ctx_mmio_loop */ 866 866 + /* 0x09be: ctx_mmio_loop */ 889 867 0x34c434bd, 890 868 0x0f1bf4ff, 891 869 0x020057f1, 892 870 0xfa0653f0, 893 871 0x03f80535, 894 894 - /* 0x0978: ctx_mmio_pull */ 872 872 + /* 0x09d0: ctx_mmio_pull */ 895 873 0x98804e98, 896 874 0x21f4814f, 897 875 0x0830b69d, 898 876 0xf40112b6, 899 899 - /* 0x098a: ctx_mmio_done */ 877 877 + /* 0x09e2: ctx_mmio_done */ 900 878 0x0398df1b, 901 879 0x0007f116, 902 880 0x0203f081, ··· 905 883 0x010017f1, 906 884 0xfa0613f0, 907 885 0x03f80601, 908 908 - /* 0x09aa: ctx_xfer */ 886 886 + /* 0x0a02: ctx_xfer */ 909 887 0xe7f000f8, 910 888 0x0007f104, 911 889 0x0303f002, 912 890 0xbd000ed0, 913 913 - /* 0x09b9: ctx_xfer_idle */ 891 891 + /* 0x0a11: ctx_xfer_idle */ 914 892 0x00e7f104, 915 893 0x03e3f000, 916 894 0xf100eecf, 917 895 0xf42000e4, 918 896 0x11f4f21b, 919 897 0x0d02f406, 920 920 - /* 0x09d0: ctx_xfer_pre */ 898 898 + /* 0x0a28: ctx_xfer_pre */ 921 899 0xf510f7f0, 922 922 - 0xf407de21, 923 923 - /* 0x09da: ctx_xfer_pre_load */ 900 900 + 0xf4083621, 901 901 + /* 0x0a32: ctx_xfer_pre_load */ 924 902 0xf7f01c11, 925 925 - 0x7f21f502, 926 926 - 0x9121f507, 927 927 - 0xa621f507, 903 903 + 0xd721f502, 904 904 + 0xe921f507, 905 905 + 0xfe21f507, 928 906 0xf5f4bd07, 929 929 - 0xf5077f21, 930 930 - /* 0x09f3: ctx_xfer_exec */ 931 931 - 0x98082421, 907 907 + 0xf507d721, 908 908 + /* 0x0a4b: ctx_xfer_exec */ 909 909 + 0x98087c21, 932 910 0x24bd1601, 933 911 0x050007f1, 934 912 0xd00103f0, ··· 963 941 0xa7f01301, 964 942 0xd021f40c, 965 943 0xf505f7f0, 966 966 - 0xf4080621, 967 967 - /* 0x0a82: ctx_xfer_post */ 944 944 + 0xf4085e21, 945 945 + /* 0x0ada: ctx_xfer_post */ 968 946 0xf7f02e02, 969 969 - 0x7f21f502, 947 947 + 0xd721f502, 970 948 0xf5f4bd07, 971 971 - 0xf507de21, 949 949 + 0xf5083621, 972 950 0xf5027f21, 973 973 - 0xbd079121, 974 974 - 0x7f21f5f4, 951 951 + 0xbd07e921, 952 952 + 0xd721f5f4, 975 953 0x1011f407, 976 954 0xfd400198, 977 955 0x0bf40511, 978 978 - 0x5521f507, 979 979 - /* 0x0aad: ctx_xfer_no_post_mmio */ 980 980 - /* 0x0aad: ctx_xfer_done */ 956 956 + 0xad21f507, 957 957 + /* 0x0b05: ctx_xfer_no_post_mmio */ 958 958 + /* 0x0b05: ctx_xfer_done */ 981 959 0x0000f809, 960 960 + 0x00000000, 961 961 + 0x00000000, 962 962 + 0x00000000, 963 963 + 0x00000000, 964 964 + 0x00000000, 965 965 + 0x00000000, 966 966 + 0x00000000, 967 967 + 0x00000000, 968 968 + 0x00000000, 969 969 + 0x00000000, 970 970 + 0x00000000, 971 971 + 0x00000000, 972 972 + 0x00000000, 973 973 + 0x00000000, 974 974 + 0x00000000, 975 975 + 0x00000000, 976 976 + 0x00000000, 977 977 + 0x00000000, 978 978 + 0x00000000, 979 979 + 0x00000000, 980 980 + 0x00000000, 981 981 + 0x00000000, 982 982 + 0x00000000, 983 983 + 0x00000000, 984 984 + 0x00000000, 985 985 + 0x00000000, 986 986 + 0x00000000, 987 987 + 0x00000000, 988 988 + 0x00000000, 989 989 + 0x00000000, 990 990 + 0x00000000, 991 991 + 0x00000000, 992 992 + 0x00000000, 993 993 + 0x00000000, 994 994 + 0x00000000, 995 995 + 0x00000000, 996 996 + 0x00000000, 997 997 + 0x00000000, 998 998 + 0x00000000, 999 999 + 0x00000000, 1000 1000 + 0x00000000, 1001 1001 + 0x00000000, 982 1002 0x00000000, 983 1003 0x00000000, 984 1004 0x00000000,

+6

drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc

reviewed

··· 30 30 #define GK110 0xf0 31 31 #define GK208 0x108 32 32 33 33 + #define NV_PGRAPH_TRAPPED_ADDR 0x400704 34 34 + #define NV_PGRAPH_TRAPPED_DATA_LO 0x400708 35 35 + #define NV_PGRAPH_TRAPPED_DATA_HI 0x40070c 36 36 + 37 37 + #define NV_PGRAPH_FE_OBJECT_TABLE(n) ((n) * 4 + 0x400700) 38 38 + 33 39 #define NV_PGRAPH_FECS_INTR_ACK 0x409004 34 40 #define NV_PGRAPH_FECS_INTR 0x409008 35 41 #define NV_PGRAPH_FECS_INTR_FWMTHD 0x00000400

+1

drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h

reviewed

··· 3 3 4 4 #define E_BAD_COMMAND 0x00000001 5 5 #define E_CMD_OVERFLOW 0x00000002 6 6 + #define E_BAD_FWMTHD 0x00000003 6 7 7 8 #endif

+4 -5

drivers/gpu/drm/nouveau/core/engine/graph/nv50.c

reviewed

··· 976 976 break; 977 977 case 0xa0: 978 978 default: 979 979 - nv_wr32(priv, 0x402cc0, 0x00000000); 980 979 if (nv_device(priv)->chipset == 0xa0 || 981 980 nv_device(priv)->chipset == 0xaa || 982 981 nv_device(priv)->chipset == 0xac) { ··· 990 991 991 992 /* zero out zcull regions */ 992 993 for (i = 0; i < 8; i++) { 993 993 - nv_wr32(priv, 0x402c20 + (i * 8), 0x00000000); 994 994 - nv_wr32(priv, 0x402c24 + (i * 8), 0x00000000); 995 995 - nv_wr32(priv, 0x402c28 + (i * 8), 0x00000000); 996 996 - nv_wr32(priv, 0x402c2c + (i * 8), 0x00000000); 994 994 + nv_wr32(priv, 0x402c20 + (i * 0x10), 0x00000000); 995 995 + nv_wr32(priv, 0x402c24 + (i * 0x10), 0x00000000); 996 996 + nv_wr32(priv, 0x402c28 + (i * 0x10), 0x00000000); 997 997 + nv_wr32(priv, 0x402c2c + (i * 0x10), 0x00000000); 997 998 } 998 999 return 0; 999 1000 }

+32 -9

drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c

reviewed

··· 789 789 static void 790 790 nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv) 791 791 { 792 792 - u32 ustat = nv_rd32(priv, 0x409c18); 792 792 + u32 stat = nv_rd32(priv, 0x409c18); 793 793 794 794 - if (ustat & 0x00000001) 795 795 - nv_error(priv, "CTXCTL ucode error\n"); 796 796 - if (ustat & 0x00080000) 797 797 - nv_error(priv, "CTXCTL watchdog timeout\n"); 798 798 - if (ustat & ~0x00080001) 799 799 - nv_error(priv, "CTXCTL 0x%08x\n", ustat); 794 794 + if (stat & 0x00000001) { 795 795 + u32 code = nv_rd32(priv, 0x409814); 796 796 + if (code == E_BAD_FWMTHD) { 797 797 + u32 class = nv_rd32(priv, 0x409808); 798 798 + u32 addr = nv_rd32(priv, 0x40980c); 799 799 + u32 subc = (addr & 0x00070000) >> 16; 800 800 + u32 mthd = (addr & 0x00003ffc); 801 801 + u32 data = nv_rd32(priv, 0x409810); 800 802 801 801 - nvc0_graph_ctxctl_debug(priv); 802 802 - nv_wr32(priv, 0x409c20, ustat); 803 803 + nv_error(priv, "FECS MTHD subc %d class 0x%04x " 804 804 + "mthd 0x%04x data 0x%08x\n", 805 805 + subc, class, mthd, data); 806 806 + 807 807 + nv_wr32(priv, 0x409c20, 0x00000001); 808 808 + stat &= ~0x00000001; 809 809 + } else { 810 810 + nv_error(priv, "FECS ucode error %d\n", code); 811 811 + } 812 812 + } 813 813 + 814 814 + if (stat & 0x00080000) { 815 815 + nv_error(priv, "FECS watchdog timeout\n"); 816 816 + nvc0_graph_ctxctl_debug(priv); 817 817 + nv_wr32(priv, 0x409c20, 0x00080000); 818 818 + stat &= ~0x00080000; 819 819 + } 820 820 + 821 821 + if (stat) { 822 822 + nv_error(priv, "FECS 0x%08x\n", stat); 823 823 + nvc0_graph_ctxctl_debug(priv); 824 824 + nv_wr32(priv, 0x409c20, stat); 825 825 + } 803 826 } 804 827 805 828 static void

+2

drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h

reviewed

··· 38 38 #include <engine/fifo.h> 39 39 #include <engine/graph.h> 40 40 41 41 + #include "fuc/os.h" 42 42 + 41 43 #define GPC_MAX 32 42 44 #define TPC_MAX (GPC_MAX * 8) 43 45

+1

drivers/gpu/drm/nouveau/core/include/subdev/i2c.h

reviewed

··· 84 84 extern struct nouveau_oclass *nv50_i2c_oclass; 85 85 extern struct nouveau_oclass *nv94_i2c_oclass; 86 86 extern struct nouveau_oclass *nvd0_i2c_oclass; 87 87 + extern struct nouveau_oclass *gf117_i2c_oclass; 87 88 extern struct nouveau_oclass *nve0_i2c_oclass; 88 89 89 90 static inline int

+5 -3

drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c

reviewed

··· 307 307 info->dsrc = src0; 308 308 if (div0) { 309 309 info->ddiv |= 0x80000000; 310 310 - info->ddiv |= div0 << 8; 311 310 info->ddiv |= div0; 312 311 } 313 312 if (div1D) { ··· 351 352 { 352 353 struct nve0_clock_info *info = &priv->eng[clk]; 353 354 if (!info->ssel) { 354 354 - nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv); 355 355 + nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x8000003f, info->ddiv); 355 356 nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); 356 357 } 357 358 } ··· 388 389 nve0_clock_prog_3(struct nve0_clock_priv *priv, int clk) 389 390 { 390 391 struct nve0_clock_info *info = &priv->eng[clk]; 391 391 - nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv); 392 392 + if (info->ssel) 393 393 + nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f00, info->mdiv); 394 394 + else 395 395 + nv_mask(priv, 0x137250 + (clk * 0x04), 0x0000003f, info->mdiv); 392 396 } 393 397 394 398 static void

+38 -38

drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c

reviewed

··· 262 262 struct nve0_ram *ram = (void *)pfb->ram; 263 263 struct nve0_ramfuc *fuc = &ram->fuc; 264 264 struct nouveau_ram_data *next = ram->base.next; 265 265 - int vc = !(next->bios.ramcfg_11_02_08); 266 266 - int mv = !(next->bios.ramcfg_11_02_04); 265 265 + int vc = !next->bios.ramcfg_11_02_08; 266 266 + int mv = !next->bios.ramcfg_11_02_04; 267 267 u32 mask, data; 268 268 269 269 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); ··· 370 370 } 371 371 } 372 372 373 373 - if ( (next->bios.ramcfg_11_02_40) || 374 374 - (next->bios.ramcfg_11_07_10)) { 373 373 + if (next->bios.ramcfg_11_02_40 || 374 374 + next->bios.ramcfg_11_07_10) { 375 375 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); 376 376 ram_nsec(fuc, 20000); 377 377 } ··· 417 417 ram_mask(fuc, 0x10f694, 0xff00ff00, data); 418 418 } 419 419 420 420 - if (ram->mode == 2 && (next->bios.ramcfg_11_08_10)) 420 420 + if (ram->mode == 2 && next->bios.ramcfg_11_08_10) 421 421 data = 0x00000080; 422 422 else 423 423 data = 0x00000000; ··· 425 425 426 426 mask = 0x00070000; 427 427 data = 0x00000000; 428 428 - if (!(next->bios.ramcfg_11_02_80)) 428 428 + if (!next->bios.ramcfg_11_02_80) 429 429 data |= 0x03000000; 430 430 - if (!(next->bios.ramcfg_11_02_40)) 430 430 + if (!next->bios.ramcfg_11_02_40) 431 431 data |= 0x00002000; 432 432 - if (!(next->bios.ramcfg_11_07_10)) 432 432 + if (!next->bios.ramcfg_11_07_10) 433 433 data |= 0x00004000; 434 434 - if (!(next->bios.ramcfg_11_07_08)) 434 434 + if (!next->bios.ramcfg_11_07_08) 435 435 data |= 0x00000003; 436 436 else 437 437 data |= 0x74000000; ··· 486 486 487 487 data = mask = 0x00000000; 488 488 if (NOTE00(ramcfg_02_03 != 0)) { 489 489 - data |= (next->bios.ramcfg_11_02_03) << 8; 489 489 + data |= next->bios.ramcfg_11_02_03 << 8; 490 490 mask |= 0x00000300; 491 491 } 492 492 if (NOTE00(ramcfg_01_10)) { ··· 498 498 499 499 data = mask = 0x00000000; 500 500 if (NOTE00(timing_30_07 != 0)) { 501 501 - data |= (next->bios.timing_20_30_07) << 28; 501 501 + data |= next->bios.timing_20_30_07 << 28; 502 502 mask |= 0x70000000; 503 503 } 504 504 if (NOTE00(ramcfg_01_01)) { ··· 510 510 511 511 data = mask = 0x00000000; 512 512 if (NOTE00(timing_30_07 != 0)) { 513 513 - data |= (next->bios.timing_20_30_07) << 28; 513 513 + data |= next->bios.timing_20_30_07 << 28; 514 514 mask |= 0x70000000; 515 515 } 516 516 if (NOTE00(ramcfg_01_02)) { ··· 522 522 523 523 mask = 0x33f00000; 524 524 data = 0x00000000; 525 525 - if (!(next->bios.ramcfg_11_01_04)) 525 525 + if (!next->bios.ramcfg_11_01_04) 526 526 data |= 0x20200000; 527 527 - if (!(next->bios.ramcfg_11_07_80)) 527 527 + if (!next->bios.ramcfg_11_07_80) 528 528 data |= 0x12800000; 529 529 /*XXX: see note above about there probably being some condition 530 530 * for the 10f824 stuff that uses ramcfg 3... 531 531 */ 532 532 - if ( (next->bios.ramcfg_11_03_f0)) { 532 532 + if (next->bios.ramcfg_11_03_f0) { 533 533 if (next->bios.rammap_11_08_0c) { 534 534 - if (!(next->bios.ramcfg_11_07_80)) 534 534 + if (!next->bios.ramcfg_11_07_80) 535 535 mask |= 0x00000020; 536 536 else 537 537 data |= 0x00000020; ··· 563 563 ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000); 564 564 } 565 565 566 566 - data = (next->bios.timing_20_30_07) << 8; 566 566 + data = next->bios.timing_20_30_07 << 8; 567 567 if (next->bios.ramcfg_11_01_01) 568 568 data |= 0x80000000; 569 569 ram_mask(fuc, 0x100778, 0x00000700, data); ··· 588 588 ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ 589 589 ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */ 590 590 591 591 - if ((next->bios.ramcfg_11_08_10) && (ram->mode == 2) /*XXX*/) { 591 591 + if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) { 592 592 u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000); 593 593 nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/ 594 594 ram_nsec(fuc, 1000); ··· 621 621 data = ram_rd32(fuc, 0x10f978); 622 622 data &= ~0x00046144; 623 623 data |= 0x0000000b; 624 624 - if (!(next->bios.ramcfg_11_07_08)) { 625 625 - if (!(next->bios.ramcfg_11_07_04)) 624 624 + if (!next->bios.ramcfg_11_07_08) { 625 625 + if (!next->bios.ramcfg_11_07_04) 626 626 data |= 0x0000200c; 627 627 else 628 628 data |= 0x00000000; ··· 636 636 ram_wr32(fuc, 0x10f830, data); 637 637 } 638 638 639 639 - if (!(next->bios.ramcfg_11_07_08)) { 639 639 + if (!next->bios.ramcfg_11_07_08) { 640 640 data = 0x88020000; 641 641 - if ( (next->bios.ramcfg_11_07_04)) 641 641 + if ( next->bios.ramcfg_11_07_04) 642 642 data |= 0x10000000; 643 643 - if (!(next->bios.rammap_11_08_10)) 643 643 + if (!next->bios.rammap_11_08_10) 644 644 data |= 0x00080000; 645 645 } else { 646 646 data = 0xa40e0000; ··· 689 689 const u32 runk0 = ram->fN1 << 16; 690 690 const u32 runk1 = ram->fN1; 691 691 struct nouveau_ram_data *next = ram->base.next; 692 692 - int vc = !(next->bios.ramcfg_11_02_08); 693 693 - int mv = !(next->bios.ramcfg_11_02_04); 692 692 + int vc = !next->bios.ramcfg_11_02_08; 693 693 + int mv = !next->bios.ramcfg_11_02_04; 694 694 u32 mask, data; 695 695 696 696 ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); ··· 705 705 } 706 706 707 707 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); 708 708 - if ((next->bios.ramcfg_11_03_f0)) 708 708 + if (next->bios.ramcfg_11_03_f0) 709 709 ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000); 710 710 711 711 ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ ··· 761 761 762 762 ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010); 763 763 data = ram_rd32(fuc, 0x1373ec) & ~0x00030000; 764 764 - data |= (next->bios.ramcfg_11_03_30) << 12; 764 764 + data |= next->bios.ramcfg_11_03_30 << 16; 765 765 ram_wr32(fuc, 0x1373ec, data); 766 766 ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000); 767 767 ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000); ··· 793 793 } 794 794 } 795 795 796 796 - if ( (next->bios.ramcfg_11_02_40) || 797 797 - (next->bios.ramcfg_11_07_10)) { 796 796 + if (next->bios.ramcfg_11_02_40 || 797 797 + next->bios.ramcfg_11_07_10) { 798 798 ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); 799 799 ram_nsec(fuc, 20000); 800 800 } ··· 810 810 811 811 mask = 0x00010000; 812 812 data = 0x00000000; 813 813 - if (!(next->bios.ramcfg_11_02_80)) 813 813 + if (!next->bios.ramcfg_11_02_80) 814 814 data |= 0x03000000; 815 815 - if (!(next->bios.ramcfg_11_02_40)) 815 815 + if (!next->bios.ramcfg_11_02_40) 816 816 data |= 0x00002000; 817 817 - if (!(next->bios.ramcfg_11_07_10)) 817 817 + if (!next->bios.ramcfg_11_07_10) 818 818 data |= 0x00004000; 819 819 - if (!(next->bios.ramcfg_11_07_08)) 819 819 + if (!next->bios.ramcfg_11_07_08) 820 820 data |= 0x00000003; 821 821 else 822 822 data |= 0x14000000; ··· 844 844 845 845 mask = 0x33f00000; 846 846 data = 0x00000000; 847 847 - if (!(next->bios.ramcfg_11_01_04)) 847 847 + if (!next->bios.ramcfg_11_01_04) 848 848 data |= 0x20200000; 849 849 - if (!(next->bios.ramcfg_11_07_80)) 849 849 + if (!next->bios.ramcfg_11_07_80) 850 850 data |= 0x12800000; 851 851 /*XXX: see note above about there probably being some condition 852 852 * for the 10f824 stuff that uses ramcfg 3... 853 853 */ 854 854 - if ( (next->bios.ramcfg_11_03_f0)) { 854 854 + if (next->bios.ramcfg_11_03_f0) { 855 855 if (next->bios.rammap_11_08_0c) { 856 856 - if (!(next->bios.ramcfg_11_07_80)) 856 856 + if (!next->bios.ramcfg_11_07_80) 857 857 mask |= 0x00000020; 858 858 else 859 859 data |= 0x00000020; ··· 876 876 data = next->bios.timing_20_2c_1fc0; 877 877 ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); 878 878 879 879 - ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8); 879 879 + ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16); 880 880 881 881 ram_wr32(fuc, 0x10f090, 0x4000007f); 882 882 ram_nsec(fuc, 1000);

+39

drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c

reviewed

··· 1 1 + /* 2 2 + * Copyright 2012 Red Hat Inc. 3 3 + * 4 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 5 + * copy of this software and associated documentation files (the "Software"), 6 6 + * to deal in the Software without restriction, including without limitation 7 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 9 + * Software is furnished to do so, subject to the following conditions: 10 10 + * 11 11 + * The above copyright notice and this permission notice shall be included in 12 12 + * all copies or substantial portions of the Software. 13 13 + * 14 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 21 + * 22 22 + * Authors: Ben Skeggs 23 23 + */ 24 24 + 25 25 + #include "nv50.h" 26 26 + 27 27 + struct nouveau_oclass * 28 28 + gf117_i2c_oclass = &(struct nouveau_i2c_impl) { 29 29 + .base.handle = NV_SUBDEV(I2C, 0xd7), 30 30 + .base.ofuncs = &(struct nouveau_ofuncs) { 31 31 + .ctor = _nouveau_i2c_ctor, 32 32 + .dtor = _nouveau_i2c_dtor, 33 33 + .init = _nouveau_i2c_init, 34 34 + .fini = _nouveau_i2c_fini, 35 35 + }, 36 36 + .sclass = nvd0_i2c_sclass, 37 37 + .pad_x = &nv04_i2c_pad_oclass, 38 38 + .pad_s = &nv04_i2c_pad_oclass, 39 39 + }.base;

+18 -1

drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c

reviewed

··· 95 95 } 96 96 97 97 static int 98 98 + nve0_ibus_init(struct nouveau_object *object) 99 99 + { 100 100 + struct nve0_ibus_priv *priv = (void *)object; 101 101 + int ret = nouveau_ibus_init(&priv->base); 102 102 + if (ret == 0) { 103 103 + nv_mask(priv, 0x122318, 0x0003ffff, 0x00001000); 104 104 + nv_mask(priv, 0x12231c, 0x0003ffff, 0x00000200); 105 105 + nv_mask(priv, 0x122310, 0x0003ffff, 0x00000800); 106 106 + nv_mask(priv, 0x122348, 0x0003ffff, 0x00000100); 107 107 + nv_mask(priv, 0x1223b0, 0x0003ffff, 0x00000fff); 108 108 + nv_mask(priv, 0x122348, 0x0003ffff, 0x00000200); 109 109 + nv_mask(priv, 0x122358, 0x0003ffff, 0x00002880); 110 110 + } 111 111 + return ret; 112 112 + } 113 113 + 114 114 + static int 98 115 nve0_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 99 116 struct nouveau_oclass *oclass, void *data, u32 size, 100 117 struct nouveau_object **pobject) ··· 134 117 .ofuncs = &(struct nouveau_ofuncs) { 135 118 .ctor = nve0_ibus_ctor, 136 119 .dtor = _nouveau_ibus_dtor, 137 137 - .init = _nouveau_ibus_init, 120 120 + .init = nve0_ibus_init, 138 121 .fini = _nouveau_ibus_fini, 139 122 }, 140 123 };

+1 -1

drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc

reviewed

··· 83 83 // increment GET 84 84 add b32 $r1 0x1 85 85 and $r14 $r1 #fifo_qmaskf 86 86 - nv_iowr(NV_PPWR_FIFO_GET(0), $r1) 86 86 + nv_iowr(NV_PPWR_FIFO_GET(0), $r14) 87 87 bra #host_send 88 88 host_send_done: 89 89 ret

+1 -1

drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h

reviewed

··· 1018 1018 0xb600023f, 1019 1019 0x1ec40110, 1020 1020 0x04b0400f, 1021 1021 - 0xbd0001f6, 1021 1021 + 0xbd000ef6, 1022 1022 0xc70ef404, 1023 1023 /* 0x0328: host_send_done */ 1024 1024 /* 0x032a: host_recv */

+1 -1

drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h

reviewed

··· 1124 1124 0x0f1ec401, 1125 1125 0x04b007f1, 1126 1126 0xd00604b6, 1127 1127 - 0x04bd0001, 1127 1127 + 0x04bd000e, 1128 1128 /* 0x03cb: host_send_done */ 1129 1129 0xf8ba0ef4, 1130 1130 /* 0x03cd: host_recv */

+1 -1

drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h

reviewed

··· 1124 1124 0x0f1ec401, 1125 1125 0x04b007f1, 1126 1126 0xd00604b6, 1127 1127 - 0x04bd0001, 1127 1127 + 0x04bd000e, 1128 1128 /* 0x03cb: host_send_done */ 1129 1129 0xf8ba0ef4, 1130 1130 /* 0x03cd: host_recv */

+1 -1

drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h

reviewed

··· 1033 1033 0xb6026b21, 1034 1034 0x1ec40110, 1035 1035 0xb007f10f, 1036 1036 - 0x0001d004, 1036 1036 + 0x000ed004, 1037 1037 0x0ef404bd, 1038 1038 /* 0x0365: host_send_done */ 1039 1039 /* 0x0367: host_recv */

+7

drivers/gpu/drm/nouveau/nouveau_display.c

reviewed

··· 736 736 fb->bits_per_pixel, fb->pitches[0], crtc->x, crtc->y, 737 737 new_bo->bo.offset }; 738 738 739 739 + /* Keep vblanks on during flip, for the target crtc of this flip */ 740 740 + drm_vblank_get(dev, nouveau_crtc(crtc)->index); 741 741 + 739 742 /* Emit a page flip */ 740 743 if (nv_device(drm->device)->card_type >= NV_50) { 741 744 ret = nv50_display_flip_next(crtc, fb, chan, swap_interval); ··· 782 779 return 0; 783 780 784 781 fail_unreserve: 782 782 + drm_vblank_put(dev, nouveau_crtc(crtc)->index); 785 783 ttm_bo_unreserve(&old_bo->bo); 786 784 fail_unpin: 787 785 mutex_unlock(&chan->cli->mutex); ··· 820 816 821 817 drm_send_vblank_event(dev, crtcid, s->event); 822 818 } 819 819 + 820 820 + /* Give up ownership of vblank for page-flipped crtc */ 821 821 + drm_vblank_put(dev, s->crtc); 823 822 824 823 list_del(&s->head); 825 824 if (ps)

+101 -17

drivers/gpu/drm/radeon/atombios_crtc.c

reviewed

··· 1052 1052 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 1053 1053 1054 1054 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */ 1055 1055 - if (ASIC_IS_DCE5(rdev) && !ASIC_IS_DCE8(rdev) && 1055 1055 + if (ASIC_IS_DCE5(rdev) && 1056 1056 (encoder_mode == ATOM_ENCODER_MODE_HDMI) && 1057 1057 (radeon_crtc->bpc > 8)) 1058 1058 clock = radeon_crtc->adjusted_clock; ··· 1136 1136 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 1137 1137 u32 tmp, viewport_w, viewport_h; 1138 1138 int r; 1139 1139 + bool bypass_lut = false; 1139 1140 1140 1141 /* no fb bound */ 1141 1142 if (!atomic && !crtc->primary->fb) { ··· 1175 1174 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1176 1175 radeon_bo_unreserve(rbo); 1177 1176 1178 1178 - switch (target_fb->bits_per_pixel) { 1179 1179 - case 8: 1177 1177 + switch (target_fb->pixel_format) { 1178 1178 + case DRM_FORMAT_C8: 1180 1179 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | 1181 1180 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 1182 1181 break; 1183 1183 - case 15: 1182 1182 + case DRM_FORMAT_XRGB4444: 1183 1183 + case DRM_FORMAT_ARGB4444: 1184 1184 + fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1185 1185 + EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444)); 1186 1186 + #ifdef __BIG_ENDIAN 1187 1187 + fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1188 1188 + #endif 1189 1189 + break; 1190 1190 + case DRM_FORMAT_XRGB1555: 1191 1191 + case DRM_FORMAT_ARGB1555: 1184 1192 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1185 1193 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 1194 1194 + #ifdef __BIG_ENDIAN 1195 1195 + fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1196 1196 + #endif 1186 1197 break; 1187 1187 - case 16: 1198 1198 + case DRM_FORMAT_BGRX5551: 1199 1199 + case DRM_FORMAT_BGRA5551: 1200 1200 + fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1201 1201 + EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551)); 1202 1202 + #ifdef __BIG_ENDIAN 1203 1203 + fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1204 1204 + #endif 1205 1205 + break; 1206 1206 + case DRM_FORMAT_RGB565: 1188 1207 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1189 1208 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 1190 1209 #ifdef __BIG_ENDIAN 1191 1210 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1192 1211 #endif 1193 1212 break; 1194 1194 - case 24: 1195 1195 - case 32: 1213 1213 + case DRM_FORMAT_XRGB8888: 1214 1214 + case DRM_FORMAT_ARGB8888: 1196 1215 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1197 1216 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 1198 1217 #ifdef __BIG_ENDIAN 1199 1218 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1200 1219 #endif 1201 1220 break; 1221 1221 + case DRM_FORMAT_XRGB2101010: 1222 1222 + case DRM_FORMAT_ARGB2101010: 1223 1223 + fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1224 1224 + EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010)); 1225 1225 + #ifdef __BIG_ENDIAN 1226 1226 + fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1227 1227 + #endif 1228 1228 + /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1229 1229 + bypass_lut = true; 1230 1230 + break; 1231 1231 + case DRM_FORMAT_BGRX1010102: 1232 1232 + case DRM_FORMAT_BGRA1010102: 1233 1233 + fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1234 1234 + EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102)); 1235 1235 + #ifdef __BIG_ENDIAN 1236 1236 + fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1237 1237 + #endif 1238 1238 + /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1239 1239 + bypass_lut = true; 1240 1240 + break; 1202 1241 default: 1203 1203 - DRM_ERROR("Unsupported screen depth %d\n", 1204 1204 - target_fb->bits_per_pixel); 1242 1242 + DRM_ERROR("Unsupported screen format %s\n", 1243 1243 + drm_get_format_name(target_fb->pixel_format)); 1205 1244 return -EINVAL; 1206 1245 } 1207 1246 ··· 1370 1329 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1371 1330 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1372 1331 1332 1332 + /* 1333 1333 + * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 1334 1334 + * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 1335 1335 + * retain the full precision throughout the pipeline. 1336 1336 + */ 1337 1337 + WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset, 1338 1338 + (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0), 1339 1339 + ~EVERGREEN_LUT_10BIT_BYPASS_EN); 1340 1340 + 1341 1341 + if (bypass_lut) 1342 1342 + DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 1343 1343 + 1373 1344 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1374 1345 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1375 1346 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); ··· 1449 1396 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; 1450 1397 u32 tmp, viewport_w, viewport_h; 1451 1398 int r; 1399 1399 + bool bypass_lut = false; 1452 1400 1453 1401 /* no fb bound */ 1454 1402 if (!atomic && !crtc->primary->fb) { ··· 1487 1433 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1488 1434 radeon_bo_unreserve(rbo); 1489 1435 1490 1490 - switch (target_fb->bits_per_pixel) { 1491 1491 - case 8: 1436 1436 + switch (target_fb->pixel_format) { 1437 1437 + case DRM_FORMAT_C8: 1492 1438 fb_format = 1493 1439 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | 1494 1440 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; 1495 1441 break; 1496 1496 - case 15: 1442 1442 + case DRM_FORMAT_XRGB4444: 1443 1443 + case DRM_FORMAT_ARGB4444: 1444 1444 + fb_format = 1445 1445 + AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1446 1446 + AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444; 1447 1447 + #ifdef __BIG_ENDIAN 1448 1448 + fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1449 1449 + #endif 1450 1450 + break; 1451 1451 + case DRM_FORMAT_XRGB1555: 1497 1452 fb_format = 1498 1453 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1499 1454 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; 1455 1455 + #ifdef __BIG_ENDIAN 1456 1456 + fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1457 1457 + #endif 1500 1458 break; 1501 1501 - case 16: 1459 1459 + case DRM_FORMAT_RGB565: 1502 1460 fb_format = 1503 1461 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1504 1462 AVIVO_D1GRPH_CONTROL_16BPP_RGB565; ··· 1518 1452 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1519 1453 #endif 1520 1454 break; 1521 1521 - case 24: 1522 1522 - case 32: 1455 1455 + case DRM_FORMAT_XRGB8888: 1456 1456 + case DRM_FORMAT_ARGB8888: 1523 1457 fb_format = 1524 1458 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1525 1459 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; ··· 1527 1461 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1528 1462 #endif 1529 1463 break; 1464 1464 + case DRM_FORMAT_XRGB2101010: 1465 1465 + case DRM_FORMAT_ARGB2101010: 1466 1466 + fb_format = 1467 1467 + AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1468 1468 + AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010; 1469 1469 + #ifdef __BIG_ENDIAN 1470 1470 + fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1471 1471 + #endif 1472 1472 + /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1473 1473 + bypass_lut = true; 1474 1474 + break; 1530 1475 default: 1531 1531 - DRM_ERROR("Unsupported screen depth %d\n", 1532 1532 - target_fb->bits_per_pixel); 1476 1476 + DRM_ERROR("Unsupported screen format %s\n", 1477 1477 + drm_get_format_name(target_fb->pixel_format)); 1533 1478 return -EINVAL; 1534 1479 } 1535 1480 ··· 1578 1501 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1579 1502 if (rdev->family >= CHIP_R600) 1580 1503 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1504 1504 + 1505 1505 + /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */ 1506 1506 + WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, 1507 1507 + (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN); 1508 1508 + 1509 1509 + if (bypass_lut) 1510 1510 + DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 1581 1511 1582 1512 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1583 1513 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);

+2

drivers/gpu/drm/radeon/evergreen_reg.h

reviewed

··· 116 116 # define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED 1 117 117 # define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1 2 118 118 # define EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1 4 119 119 + #define EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL 0x6808 120 120 + # define EVERGREEN_LUT_10BIT_BYPASS_EN (1 << 8) 119 121 #define EVERGREEN_GRPH_SWAP_CONTROL 0x680c 120 122 # define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) 121 123 # define EVERGREEN_GRPH_ENDIAN_NONE 0

+1

drivers/gpu/drm/radeon/r500_reg.h

reviewed

··· 402 402 * block and vice versa. This applies to GRPH, CUR, etc. 403 403 */ 404 404 #define AVIVO_D1GRPH_LUT_SEL 0x6108 405 405 + # define AVIVO_LUT_10BIT_BYPASS_EN (1 << 8) 405 406 #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 406 407 #define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 407 408 #define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114

+22 -13

drivers/gpu/drm/radeon/radeon_connectors.c

reviewed

··· 1288 1288 (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1289 1289 (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) 1290 1290 return MODE_OK; 1291 1291 - else if (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_A) { 1292 1292 - if (ASIC_IS_DCE6(rdev)) { 1293 1293 - /* HDMI 1.3+ supports max clock of 340 Mhz */ 1294 1294 - if (mode->clock > 340000) 1295 1295 - return MODE_CLOCK_HIGH; 1296 1296 - else 1297 1297 - return MODE_OK; 1298 1298 - } else 1291 1291 + else if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector->edid)) { 1292 1292 + /* HDMI 1.3+ supports max clock of 340 Mhz */ 1293 1293 + if (mode->clock > 340000) 1299 1294 return MODE_CLOCK_HIGH; 1300 1300 - } else 1295 1295 + else 1296 1296 + return MODE_OK; 1297 1297 + } else { 1301 1298 return MODE_CLOCK_HIGH; 1299 1299 + } 1302 1300 } 1303 1301 1304 1302 /* check against the max pixel clock */ ··· 1547 1549 static int radeon_dp_mode_valid(struct drm_connector *connector, 1548 1550 struct drm_display_mode *mode) 1549 1551 { 1552 1552 + struct drm_device *dev = connector->dev; 1553 1553 + struct radeon_device *rdev = dev->dev_private; 1550 1554 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1551 1555 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; 1552 1556 ··· 1579 1579 return MODE_PANEL; 1580 1580 } 1581 1581 } 1582 1582 - return MODE_OK; 1583 1582 } else { 1584 1583 if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1585 1585 - (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 1584 1584 + (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1586 1585 return radeon_dp_mode_valid_helper(connector, mode); 1587 1587 - else 1588 1588 - return MODE_OK; 1586 1586 + } else { 1587 1587 + if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector->edid)) { 1588 1588 + /* HDMI 1.3+ supports max clock of 340 Mhz */ 1589 1589 + if (mode->clock > 340000) 1590 1590 + return MODE_CLOCK_HIGH; 1591 1591 + } else { 1592 1592 + if (mode->clock > 165000) 1593 1593 + return MODE_CLOCK_HIGH; 1594 1594 + } 1595 1595 + } 1589 1596 } 1597 1597 + 1598 1598 + return MODE_OK; 1590 1599 } 1591 1600 1592 1601 static const struct drm_connector_helper_funcs radeon_dp_connector_helper_funcs = {

+20 -2

drivers/gpu/drm/radeon/radeon_display.c

reviewed

··· 66 66 (radeon_crtc->lut_b[i] << 0)); 67 67 } 68 68 69 69 - WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); 69 69 + /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ 70 70 + WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); 70 71 } 71 72 72 73 static void dce4_crtc_load_lut(struct drm_crtc *crtc) ··· 358 357 359 358 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); 360 359 360 360 + drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id); 361 361 radeon_fence_unref(&work->fence); 362 362 - radeon_irq_kms_pflip_irq_get(rdev, work->crtc_id); 362 362 + radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); 363 363 queue_work(radeon_crtc->flip_queue, &work->unpin_work); 364 364 } 365 365 ··· 461 459 base &= ~7; 462 460 } 463 461 462 462 + r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id); 463 463 + if (r) { 464 464 + DRM_ERROR("failed to get vblank before flip\n"); 465 465 + goto pflip_cleanup; 466 466 + } 467 467 + 464 468 /* We borrow the event spin lock for protecting flip_work */ 465 469 spin_lock_irqsave(&crtc->dev->event_lock, flags); 466 470 ··· 480 472 up_read(&rdev->exclusive_lock); 481 473 482 474 return; 475 475 + 476 476 + pflip_cleanup: 477 477 + if (unlikely(radeon_bo_reserve(work->new_rbo, false) != 0)) { 478 478 + DRM_ERROR("failed to reserve new rbo in error path\n"); 479 479 + goto cleanup; 480 480 + } 481 481 + if (unlikely(radeon_bo_unpin(work->new_rbo) != 0)) { 482 482 + DRM_ERROR("failed to unpin new rbo in error path\n"); 483 483 + } 484 484 + radeon_bo_unreserve(work->new_rbo); 483 485 484 486 cleanup: 485 487 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);

+14 -10

drivers/tty/vt/vt.c

reviewed

··· 3226 3226 for (i = 0; i < MAX_NR_CON_DRIVER; i++) { 3227 3227 con_back = &registered_con_driver[i]; 3228 3228 3229 3229 - if (con_back->con && 3230 3230 - !(con_back->flag & CON_DRIVER_FLAG_MODULE)) { 3229 3229 + if (con_back->con && con_back->con != csw) { 3231 3230 defcsw = con_back->con; 3232 3231 retval = 0; 3233 3232 break; ··· 3331 3332 { 3332 3333 const struct consw *csw = NULL; 3333 3334 int i, more = 1, first = -1, last = -1, deflt = 0; 3335 3335 + int ret; 3334 3336 3335 3337 if (!con->con || !(con->flag & CON_DRIVER_FLAG_MODULE) || 3336 3338 con_is_graphics(con->con, con->first, con->last)) ··· 3357 3357 3358 3358 if (first != -1) { 3359 3359 console_lock(); 3360 3360 - do_unbind_con_driver(csw, first, last, deflt); 3360 3360 + ret = do_unbind_con_driver(csw, first, last, deflt); 3361 3361 console_unlock(); 3362 3362 + if (ret != 0) 3363 3363 + return ret; 3362 3364 } 3363 3365 3364 3366 first = -1; ··· 3647 3645 */ 3648 3646 int do_unregister_con_driver(const struct consw *csw) 3649 3647 { 3650 3650 - int i, retval = -ENODEV; 3648 3648 + int i; 3651 3649 3652 3650 /* cannot unregister a bound driver */ 3653 3651 if (con_is_bound(csw)) 3654 3654 - goto err; 3652 3652 + return -EBUSY; 3653 3653 + 3654 3654 + if (csw == conswitchp) 3655 3655 + return -EINVAL; 3655 3656 3656 3657 for (i = 0; i < MAX_NR_CON_DRIVER; i++) { 3657 3658 struct con_driver *con_driver = &registered_con_driver[i]; 3658 3659 3659 3660 if (con_driver->con == csw && 3660 3660 - con_driver->flag & CON_DRIVER_FLAG_MODULE) { 3661 3661 + con_driver->flag & CON_DRIVER_FLAG_INIT) { 3661 3662 vtconsole_deinit_device(con_driver); 3662 3663 device_destroy(vtconsole_class, 3663 3664 MKDEV(0, con_driver->node)); ··· 3671 3666 con_driver->flag = 0; 3672 3667 con_driver->first = 0; 3673 3668 con_driver->last = 0; 3674 3674 - retval = 0; 3675 3675 - break; 3669 3669 + return 0; 3676 3670 } 3677 3671 } 3678 3678 - err: 3679 3679 - return retval; 3672 3672 + 3673 3673 + return -ENODEV; 3680 3674 } 3681 3675 EXPORT_SYMBOL_GPL(do_unregister_con_driver); 3682 3676

+1

drivers/video/console/dummycon.c

reviewed

··· 77 77 .con_set_palette = DUMMY, 78 78 .con_scrolldelta = DUMMY, 79 79 }; 80 80 + EXPORT_SYMBOL_GPL(dummy_con);

+1

drivers/video/console/vgacon.c

reviewed

··· 1441 1441 .con_build_attr = vgacon_build_attr, 1442 1442 .con_invert_region = vgacon_invert_region, 1443 1443 }; 1444 1444 + EXPORT_SYMBOL(vga_con); 1444 1445 1445 1446 MODULE_LICENSE("GPL");