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net: stmmac: stm32: convert to use phy_interface

dwmac-stm32 supports MII, RMII, GMII and RGMII interface modes,
selecting the dwmac core interface mode via bits 23:21 of the
SYSCFG register. The bit combinations are identical to the
dwmac phy_intf_sel_i signals.

None of the DTS files set "mac-mode", so mac_interface will be
identical to phy_interface.

Convert dwmac-stm32 to use phy_interface when determining the
interface mode rather than mac_interface.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1uytpf-00000006H2c-3hiU@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Russell King (Oracle) and committed by
Jakub Kicinski 0ca60c26 6cb2b69c

+13 -13
+13 -13
drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
··· 171 171 { 172 172 struct stm32_dwmac *dwmac = plat_dat->bsp_priv; 173 173 174 - switch (plat_dat->mac_interface) { 174 + switch (plat_dat->phy_interface) { 175 175 case PHY_INTERFACE_MODE_MII: 176 176 dwmac->enable_eth_ck = dwmac->ext_phyclk; 177 177 return 0; ··· 193 193 default: 194 194 dwmac->enable_eth_ck = false; 195 195 dev_err(dwmac->dev, "Mode %s not supported", 196 - phy_modes(plat_dat->mac_interface)); 196 + phy_modes(plat_dat->phy_interface)); 197 197 return -EINVAL; 198 198 } 199 199 } ··· 206 206 if (!dwmac->enable_eth_ck) 207 207 return 0; 208 208 209 - switch (plat_dat->mac_interface) { 209 + switch (plat_dat->phy_interface) { 210 210 case PHY_INTERFACE_MODE_MII: 211 211 case PHY_INTERFACE_MODE_GMII: 212 212 if (clk_rate == ETH_CK_F_25M) ··· 228 228 } 229 229 230 230 dev_err(dwmac->dev, "Mode %s does not match eth-ck frequency %d Hz", 231 - phy_modes(plat_dat->mac_interface), clk_rate); 231 + phy_modes(plat_dat->phy_interface), clk_rate); 232 232 return -EINVAL; 233 233 } 234 234 ··· 238 238 u32 reg = dwmac->mode_reg; 239 239 int val = 0; 240 240 241 - switch (plat_dat->mac_interface) { 241 + switch (plat_dat->phy_interface) { 242 242 case PHY_INTERFACE_MODE_MII: 243 243 /* 244 244 * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only. ··· 269 269 break; 270 270 default: 271 271 dev_err(dwmac->dev, "Mode %s not supported", 272 - phy_modes(plat_dat->mac_interface)); 272 + phy_modes(plat_dat->phy_interface)); 273 273 /* Do not manage others interfaces */ 274 274 return -EINVAL; 275 275 } 276 276 277 - dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); 277 + dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->phy_interface)); 278 278 279 279 /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */ 280 280 val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK); ··· 294 294 u32 reg = dwmac->mode_reg; 295 295 int val = 0; 296 296 297 - switch (plat_dat->mac_interface) { 297 + switch (plat_dat->phy_interface) { 298 298 case PHY_INTERFACE_MODE_MII: 299 299 /* ETH_REF_CLK_SEL bit in SYSCFG register is not applicable in MII mode */ 300 300 break; ··· 319 319 break; 320 320 default: 321 321 dev_err(dwmac->dev, "Mode %s not supported", 322 - phy_modes(plat_dat->mac_interface)); 322 + phy_modes(plat_dat->phy_interface)); 323 323 /* Do not manage others interfaces */ 324 324 return -EINVAL; 325 325 } 326 326 327 - dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); 327 + dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->phy_interface)); 328 328 329 329 /* Select PTP (IEEE1588) clock selection from RCC (ck_ker_ethxptp) */ 330 330 val |= SYSCFG_ETHCR_ETH_PTP_CLK_SEL; ··· 359 359 u32 reg = dwmac->mode_reg; 360 360 int val; 361 361 362 - switch (plat_dat->mac_interface) { 362 + switch (plat_dat->phy_interface) { 363 363 case PHY_INTERFACE_MODE_MII: 364 364 val = SYSCFG_MCU_ETH_SEL_MII; 365 365 break; ··· 368 368 break; 369 369 default: 370 370 dev_err(dwmac->dev, "Mode %s not supported", 371 - phy_modes(plat_dat->mac_interface)); 371 + phy_modes(plat_dat->phy_interface)); 372 372 /* Do not manage others interfaces */ 373 373 return -EINVAL; 374 374 } 375 375 376 - dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); 376 + dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->phy_interface)); 377 377 378 378 return regmap_update_bits(dwmac->regmap, reg, 379 379 SYSCFG_MCU_ETH_MASK, val << 23);