Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-for-v4.9-rc8' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"A pretty small pull request: a couple of AMD powerxpress regression
fixes and a power management fix, a couple of i915 fixes and one hdlcd
fix, along with one core don't oops because of incorrect API usage fix"
* tag 'drm-fixes-for-v4.9-rc8' of git://people.freedesktop.org/~airlied/linux:
drm/i915: drop the struct_mutex when wedged or trying to reset
drm/i915: Don't touch NULL sg on i915_gem_object_get_pages_gtt() error
drm: Don't call drm_for_each_crtc with a non-KMS driver
drm/radeon: fix check for port PM availability
drm/amdgpu: fix check for port PM availability
drm/amd/powerplay: initialize the soft_regs offset in struct smu7_hwmgr
drm: hdlcd: Fix cleanup order
+34
-13
+9
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+9
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
···
485
485
*/
486
486
static bool amdgpu_atpx_pci_probe_handle(struct pci_dev *pdev)
487
487
{
488
-
struct pci_dev *parent_pdev = pci_upstream_bridge(pdev);
489
488
acpi_handle dhandle, atpx_handle;
490
489
acpi_status status;
491
490
···
499
500
}
500
501
amdgpu_atpx_priv.dhandle = dhandle;
501
502
amdgpu_atpx_priv.atpx.handle = atpx_handle;
502
-
amdgpu_atpx_priv.bridge_pm_usable = parent_pdev && parent_pdev->bridge_d3;
503
503
return true;
504
504
}
505
505
···
560
562
struct pci_dev *pdev = NULL;
561
563
bool has_atpx = false;
562
564
int vga_count = 0;
565
+
bool d3_supported = false;
566
+
struct pci_dev *parent_pdev;
563
567
564
568
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
565
569
vga_count++;
566
570
567
571
has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
572
+
573
+
parent_pdev = pci_upstream_bridge(pdev);
574
+
d3_supported |= parent_pdev && parent_pdev->bridge_d3;
568
575
}
569
576
570
577
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
571
578
vga_count++;
572
579
573
580
has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
581
+
582
+
parent_pdev = pci_upstream_bridge(pdev);
583
+
d3_supported |= parent_pdev && parent_pdev->bridge_d3;
574
584
}
575
585
576
586
if (has_atpx && vga_count == 2) {
···
586
580
printk(KERN_INFO "vga_switcheroo: detected switching method %s handle\n",
587
581
acpi_method_name);
588
582
amdgpu_atpx_priv.atpx_detected = true;
583
+
amdgpu_atpx_priv.bridge_pm_usable = d3_supported;
589
584
amdgpu_atpx_init();
590
585
return true;
591
586
}
+4
-1
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
+4
-1
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
···
2214
2214
int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
2215
2215
{
2216
2216
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
2217
+
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2217
2218
uint32_t tmp;
2218
2219
int result;
2219
2220
bool error = false;
···
2234
2233
offsetof(SMU74_Firmware_Header, SoftRegisters),
2235
2234
&tmp, SMC_RAM_END);
2236
2235
2237
-
if (!result)
2236
+
if (!result) {
2237
+
data->soft_regs_start = tmp;
2238
2238
smu_data->smu7_data.soft_regs_start = tmp;
2239
+
}
2239
2240
2240
2241
error |= (0 != result);
2241
2242
+1
-1
drivers/gpu/drm/arm/hdlcd_drv.c
+1
-1
drivers/gpu/drm/arm/hdlcd_drv.c
···
375
375
376
376
err_fbdev:
377
377
drm_kms_helper_poll_fini(drm);
378
-
drm_mode_config_cleanup(drm);
379
378
drm_vblank_cleanup(drm);
380
379
err_vblank:
381
380
pm_runtime_disable(drm->dev);
···
386
387
drm_irq_uninstall(drm);
387
388
of_reserved_mem_device_release(drm->dev);
388
389
err_free:
390
+
drm_mode_config_cleanup(drm);
389
391
dev_set_drvdata(dev, NULL);
390
392
drm_dev_unref(drm);
391
393
+6
-4
drivers/gpu/drm/drm_ioctl.c
+6
-4
drivers/gpu/drm/drm_ioctl.c
···
254
254
req->value = dev->mode_config.async_page_flip;
255
255
break;
256
256
case DRM_CAP_PAGE_FLIP_TARGET:
257
-
req->value = 1;
258
-
drm_for_each_crtc(crtc, dev) {
259
-
if (!crtc->funcs->page_flip_target)
260
-
req->value = 0;
257
+
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
258
+
req->value = 1;
259
+
drm_for_each_crtc(crtc, dev) {
260
+
if (!crtc->funcs->page_flip_target)
261
+
req->value = 0;
262
+
}
261
263
}
262
264
break;
263
265
case DRM_CAP_CURSOR_WIDTH:
+3
-2
drivers/gpu/drm/i915/i915_gem.c
+3
-2
drivers/gpu/drm/i915/i915_gem.c
···
2268
2268
page = shmem_read_mapping_page(mapping, i);
2269
2269
if (IS_ERR(page)) {
2270
2270
ret = PTR_ERR(page);
2271
-
goto err_pages;
2271
+
goto err_sg;
2272
2272
}
2273
2273
}
2274
2274
#ifdef CONFIG_SWIOTLB
···
2311
2311
2312
2312
return 0;
2313
2313
2314
-
err_pages:
2314
+
err_sg:
2315
2315
sg_mark_end(sg);
2316
+
err_pages:
2316
2317
for_each_sgt_page(page, sgt_iter, st)
2317
2318
put_page(page);
2318
2319
sg_free_table(st);
+2
-1
drivers/gpu/drm/i915/intel_display.c
+2
-1
drivers/gpu/drm/i915/intel_display.c
···
12260
12260
intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12261
12261
if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
12262
12262
ret = -EIO;
12263
-
goto cleanup;
12263
+
goto unlock;
12264
12264
}
12265
12265
12266
12266
atomic_inc(&intel_crtc->unpin_work_count);
···
12352
12352
intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12353
12353
cleanup_pending:
12354
12354
atomic_dec(&intel_crtc->unpin_work_count);
12355
+
unlock:
12355
12356
mutex_unlock(&dev->struct_mutex);
12356
12357
cleanup:
12357
12358
crtc->primary->fb = old_fb;
+9
-2
drivers/gpu/drm/radeon/radeon_atpx_handler.c
+9
-2
drivers/gpu/drm/radeon/radeon_atpx_handler.c
···
479
479
*/
480
480
static bool radeon_atpx_pci_probe_handle(struct pci_dev *pdev)
481
481
{
482
-
struct pci_dev *parent_pdev = pci_upstream_bridge(pdev);
483
482
acpi_handle dhandle, atpx_handle;
484
483
acpi_status status;
485
484
···
492
493
493
494
radeon_atpx_priv.dhandle = dhandle;
494
495
radeon_atpx_priv.atpx.handle = atpx_handle;
495
-
radeon_atpx_priv.bridge_pm_usable = parent_pdev && parent_pdev->bridge_d3;
496
496
return true;
497
497
}
498
498
···
553
555
struct pci_dev *pdev = NULL;
554
556
bool has_atpx = false;
555
557
int vga_count = 0;
558
+
bool d3_supported = false;
559
+
struct pci_dev *parent_pdev;
556
560
557
561
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
558
562
vga_count++;
559
563
560
564
has_atpx |= (radeon_atpx_pci_probe_handle(pdev) == true);
565
+
566
+
parent_pdev = pci_upstream_bridge(pdev);
567
+
d3_supported |= parent_pdev && parent_pdev->bridge_d3;
561
568
}
562
569
563
570
/* some newer PX laptops mark the dGPU as a non-VGA display device */
···
570
567
vga_count++;
571
568
572
569
has_atpx |= (radeon_atpx_pci_probe_handle(pdev) == true);
570
+
571
+
parent_pdev = pci_upstream_bridge(pdev);
572
+
d3_supported |= parent_pdev && parent_pdev->bridge_d3;
573
573
}
574
574
575
575
if (has_atpx && vga_count == 2) {
···
580
574
printk(KERN_INFO "vga_switcheroo: detected switching method %s handle\n",
581
575
acpi_method_name);
582
576
radeon_atpx_priv.atpx_detected = true;
577
+
radeon_atpx_priv.bridge_pm_usable = d3_supported;
583
578
radeon_atpx_init();
584
579
return true;
585
580
}