Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
iio: adc: ad4030: add driver for ad4030-24
This adds a new driver for the Analog Devices INC. AD4030-24 ADC.
The driver implements basic support for the AD4030-24 1 channel
differential ADC with hardware gain and offset control.
Signed-off-by: Esteban Blanc <eblanc@baylibre.com>
Link: https://patch.msgid.link/20250214-eblanc-ad4630_v1-v4-2-135dd66cab6a@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
authored by
Esteban Blanc
and committed by
Jonathan Cameron
0cb8b324
8de148c0
+938
+1
MAINTAINERS
+1
MAINTAINERS
···
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S: Supported
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W: https://ez.analog.com/linux-software-drivers
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F: Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml
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F: drivers/iio/adc/ad4030.c
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ANALOG DEVICES INC AD4130 DRIVER
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M: Cosmin Tanislav <cosmin.tanislav@analog.com>
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drivers/iio/adc/Kconfig
+14
drivers/iio/adc/Kconfig
···
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To compile this driver as a module, choose M here: the module will be
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called ad4000.
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config AD4030
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tristate "Analog Devices AD4030 ADC Driver"
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depends on SPI
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depends on GPIOLIB
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select REGMAP
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select IIO_BUFFER
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select IIO_TRIGGERED_BUFFER
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help
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Say yes here to build support for Analog Devices AD4030 and AD4630 high speed
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SPI analog to digital converters (ADC).
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To compile this driver as a module, choose M here: the module will be
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called ad4030.
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config AD4130
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tristate "Analog Device AD4130 ADC Driver"
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depends on SPI
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drivers/iio/adc/Makefile
+1
drivers/iio/adc/Makefile
+922
drivers/iio/adc/ad4030.c
+922
drivers/iio/adc/ad4030.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Analog Devices AD4030 and AD4630 ADC family driver.
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*
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* Copyright 2024 Analog Devices, Inc.
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* Copyright 2024 BayLibre, SAS
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*
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* based on code from:
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* Analog Devices, Inc.
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* Sergiu Cuciurean <sergiu.cuciurean@analog.com>
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* Nuno Sa <nuno.sa@analog.com>
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* Marcelo Schmitt <marcelo.schmitt@analog.com>
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* Liviu Adace <liviu.adace@analog.com>
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*/
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+
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/spi/spi.h>
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#include <linux/unaligned.h>
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#include <linux/units.h>
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+
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#define AD4030_REG_INTERFACE_CONFIG_A 0x00
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#define AD4030_REG_INTERFACE_CONFIG_A_SW_RESET (BIT(0) | BIT(7))
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#define AD4030_REG_INTERFACE_CONFIG_B 0x01
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#define AD4030_REG_DEVICE_CONFIG 0x02
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#define AD4030_REG_CHIP_TYPE 0x03
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#define AD4030_REG_PRODUCT_ID_L 0x04
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#define AD4030_REG_PRODUCT_ID_H 0x05
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#define AD4030_REG_CHIP_GRADE 0x06
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#define AD4030_REG_CHIP_GRADE_AD4030_24_GRADE 0x10
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#define AD4030_REG_CHIP_GRADE_MASK_CHIP_GRADE GENMASK(7, 3)
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#define AD4030_REG_SCRATCH_PAD 0x0A
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#define AD4030_REG_SPI_REVISION 0x0B
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#define AD4030_REG_VENDOR_L 0x0C
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#define AD4030_REG_VENDOR_H 0x0D
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#define AD4030_REG_STREAM_MODE 0x0E
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#define AD4030_REG_INTERFACE_CONFIG_C 0x10
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#define AD4030_REG_INTERFACE_STATUS_A 0x11
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#define AD4030_REG_EXIT_CFG_MODE 0x14
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#define AD4030_REG_EXIT_CFG_MODE_EXIT_MSK BIT(0)
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#define AD4030_REG_AVG 0x15
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#define AD4030_REG_AVG_MASK_AVG_SYNC BIT(7)
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#define AD4030_REG_AVG_MASK_AVG_VAL GENMASK(4, 0)
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#define AD4030_REG_OFFSET_X0_0 0x16
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#define AD4030_REG_OFFSET_X0_1 0x17
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#define AD4030_REG_OFFSET_X0_2 0x18
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#define AD4030_REG_OFFSET_X1_0 0x19
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#define AD4030_REG_OFFSET_X1_1 0x1A
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#define AD4030_REG_OFFSET_X1_2 0x1B
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#define AD4030_REG_OFFSET_BYTES_NB 3
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#define AD4030_REG_OFFSET_CHAN(ch) \
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(AD4030_REG_OFFSET_X0_2 + (AD4030_REG_OFFSET_BYTES_NB * (ch)))
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#define AD4030_REG_GAIN_X0_LSB 0x1C
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#define AD4030_REG_GAIN_X0_MSB 0x1D
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#define AD4030_REG_GAIN_X1_LSB 0x1E
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#define AD4030_REG_GAIN_X1_MSB 0x1F
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#define AD4030_REG_GAIN_MAX_GAIN 1999970
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#define AD4030_REG_GAIN_BYTES_NB 2
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#define AD4030_REG_GAIN_CHAN(ch) \
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(AD4030_REG_GAIN_X0_MSB + (AD4030_REG_GAIN_BYTES_NB * (ch)))
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#define AD4030_REG_MODES 0x20
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#define AD4030_REG_MODES_MASK_OUT_DATA_MODE GENMASK(2, 0)
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#define AD4030_REG_MODES_MASK_LANE_MODE GENMASK(7, 6)
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#define AD4030_REG_OSCILATOR 0x21
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#define AD4030_REG_IO 0x22
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#define AD4030_REG_IO_MASK_IO2X BIT(1)
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#define AD4030_REG_PAT0 0x23
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#define AD4030_REG_PAT1 0x24
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#define AD4030_REG_PAT2 0x25
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#define AD4030_REG_PAT3 0x26
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#define AD4030_REG_DIG_DIAG 0x34
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#define AD4030_REG_DIG_ERR 0x35
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+
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/* Sequence starting with "1 0 1" to enable reg access */
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#define AD4030_REG_ACCESS 0xA0
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#define AD4030_MAX_IIO_SAMPLE_SIZE_BUFFERED BITS_TO_BYTES(64)
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#define AD4030_MAX_HARDWARE_CHANNEL_NB 2
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#define AD4030_MAX_IIO_CHANNEL_NB 5
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#define AD4030_SINGLE_COMMON_BYTE_CHANNELS_MASK 0b10
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#define AD4030_GAIN_MIDLE_POINT 0x8000
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/*
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* This accounts for 1 sample per channel plus one s64 for the timestamp,
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* aligned on a s64 boundary
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*/
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#define AD4030_MAXIMUM_RX_BUFFER_SIZE \
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(ALIGN(AD4030_MAX_IIO_SAMPLE_SIZE_BUFFERED * \
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AD4030_MAX_HARDWARE_CHANNEL_NB, \
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sizeof(s64)) + sizeof(s64))
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+
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#define AD4030_VREF_MIN_UV (4096 * MILLI)
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#define AD4030_VREF_MAX_UV (5000 * MILLI)
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#define AD4030_VIO_THRESHOLD_UV (1400 * MILLI)
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#define AD4030_SPI_MAX_XFER_LEN 8
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#define AD4030_SPI_MAX_REG_XFER_SPEED (80 * MEGA)
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#define AD4030_TCNVH_NS 10
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#define AD4030_TCNVL_NS 20
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#define AD4030_TCYC_NS 500
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#define AD4030_TCYC_ADJUSTED_NS (AD4030_TCYC_NS - AD4030_TCNVL_NS)
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#define AD4030_TRESET_PW_NS 50
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+
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enum ad4030_out_mode {
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AD4030_OUT_DATA_MD_DIFF,
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AD4030_OUT_DATA_MD_16_DIFF_8_COM,
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AD4030_OUT_DATA_MD_24_DIFF_8_COM,
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AD4030_OUT_DATA_MD_30_AVERAGED_DIFF,
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AD4030_OUT_DATA_MD_32_PATTERN,
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};
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+
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struct ad4030_chip_info {
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const char *name;
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const unsigned long *available_masks;
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const struct iio_chan_spec channels[AD4030_MAX_IIO_CHANNEL_NB];
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u8 grade;
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u8 precision_bits;
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/* Number of hardware channels */
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int num_voltage_inputs;
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unsigned int tcyc_ns;
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};
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+
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struct ad4030_state {
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struct spi_device *spi;
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struct regmap *regmap;
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const struct ad4030_chip_info *chip;
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struct gpio_desc *cnv_gpio;
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int vref_uv;
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int vio_uv;
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int offset_avail[3];
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enum ad4030_out_mode mode;
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+
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/*
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* DMA (thus cache coherency maintenance) requires the transfer buffers
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* to live in their own cache lines.
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*/
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u8 tx_data[AD4030_SPI_MAX_XFER_LEN] __aligned(IIO_DMA_MINALIGN);
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union {
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u8 raw[AD4030_MAXIMUM_RX_BUFFER_SIZE];
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struct {
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s32 diff;
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u8 common;
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};
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} rx_data;
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};
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/*
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* For a chip with 2 hardware channel this will be used to create 2 common-mode
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* channels:
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* - voltage4
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* - voltage5
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* As the common-mode channels are after the differential ones, we compute the
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* channel number like this:
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* - _idx is the scan_index (the order in the output buffer)
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* - _ch is the hardware channel number this common-mode channel is related
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* - _idx - _ch gives us the number of channel in the chip
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* - _idx - _ch * 2 is the starting number of the common-mode channels, since
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* for each differential channel there is a common-mode channel
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* - _idx - _ch * 2 + _ch gives the channel number for this specific common-mode
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* channel
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*/
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#define AD4030_CHAN_CMO(_idx, _ch) { \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_SCALE), \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.address = (_ch), \
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.channel = ((_idx) - (_ch)) * 2 + (_ch), \
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.scan_index = (_idx), \
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.scan_type = { \
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.sign = 'u', \
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.storagebits = 8, \
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.realbits = 8, \
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.endianness = IIO_BE, \
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}, \
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}
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+
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/*
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* For a chip with 2 hardware channel this will be used to create 2 differential
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* channels:
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* - voltage0-voltage1
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* - voltage2-voltage3
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*/
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#define AD4030_CHAN_DIFF(_idx, _storage, _real, _shift) { \
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.info_mask_separate = BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_CALIBSCALE) | \
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BIT(IIO_CHAN_INFO_CALIBBIAS) | \
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BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_separate_available = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
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BIT(IIO_CHAN_INFO_CALIBSCALE), \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.address = (_idx), \
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.channel = (_idx) * 2, \
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.channel2 = (_idx) * 2 + 1, \
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.scan_index = (_idx), \
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.differential = true, \
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.scan_type = { \
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.sign = 's', \
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.storagebits = _storage, \
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.realbits = _real, \
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.shift = _shift, \
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.endianness = IIO_BE, \
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}, \
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}
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static int ad4030_enter_config_mode(struct ad4030_state *st)
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{
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st->tx_data[0] = AD4030_REG_ACCESS;
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+
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struct spi_transfer xfer = {
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.tx_buf = st->tx_data,
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.bits_per_word = 8,
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.len = 1,
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.speed_hz = AD4030_SPI_MAX_REG_XFER_SPEED,
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};
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return spi_sync_transfer(st->spi, &xfer, 1);
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}
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static int ad4030_exit_config_mode(struct ad4030_state *st)
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{
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st->tx_data[0] = 0;
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st->tx_data[1] = AD4030_REG_EXIT_CFG_MODE;
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st->tx_data[2] = AD4030_REG_EXIT_CFG_MODE_EXIT_MSK;
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+
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struct spi_transfer xfer = {
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.tx_buf = st->tx_data,
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.bits_per_word = 8,
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.len = 3,
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.speed_hz = AD4030_SPI_MAX_REG_XFER_SPEED,
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};
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return spi_sync_transfer(st->spi, &xfer, 1);
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}
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static int ad4030_spi_read(void *context, const void *reg, size_t reg_size,
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void *val, size_t val_size)
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{
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int ret;
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struct ad4030_state *st = context;
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struct spi_transfer xfer = {
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.tx_buf = st->tx_data,
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.rx_buf = st->rx_data.raw,
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.bits_per_word = 8,
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.len = reg_size + val_size,
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.speed_hz = AD4030_SPI_MAX_REG_XFER_SPEED,
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};
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+
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if (xfer.len > sizeof(st->tx_data) ||
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xfer.len > sizeof(st->rx_data.raw))
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return -EINVAL;
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+
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ret = ad4030_enter_config_mode(st);
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if (ret)
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return ret;
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+
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memset(st->tx_data, 0, sizeof(st->tx_data));
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memcpy(st->tx_data, reg, reg_size);
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+
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ret = spi_sync_transfer(st->spi, &xfer, 1);
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if (ret)
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return ret;
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+
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memcpy(val, &st->rx_data.raw[reg_size], val_size);
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+
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return ad4030_exit_config_mode(st);
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}
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+
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static int ad4030_spi_write(void *context, const void *data, size_t count)
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{
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int ret;
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struct ad4030_state *st = context;
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bool is_reset = count >= 3 &&
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((u8 *)data)[0] == 0 &&
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((u8 *)data)[1] == 0 &&
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((u8 *)data)[2] == 0x81;
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struct spi_transfer xfer = {
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.tx_buf = st->tx_data,
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.bits_per_word = 8,
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.len = count,
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.speed_hz = AD4030_SPI_MAX_REG_XFER_SPEED,
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};
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+
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if (count > sizeof(st->tx_data))
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return -EINVAL;
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+
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ret = ad4030_enter_config_mode(st);
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if (ret)
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return ret;
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+
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memcpy(st->tx_data, data, count);
296
+
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ret = spi_sync_transfer(st->spi, &xfer, 1);
298
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if (ret)
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return ret;
300
+
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/*
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* From datasheet: "After a [...] reset, no SPI commands or conversions
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* can be started for 750us"
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* After a reset we are in conversion mode, no need to exit config mode
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*/
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if (is_reset) {
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fsleep(750);
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return 0;
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}
310
+
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return ad4030_exit_config_mode(st);
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}
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+
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static const struct regmap_bus ad4030_regmap_bus = {
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.read = ad4030_spi_read,
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.write = ad4030_spi_write,
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.reg_format_endian_default = REGMAP_ENDIAN_BIG,
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};
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+
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static const struct regmap_range ad4030_regmap_rd_range[] = {
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regmap_reg_range(AD4030_REG_INTERFACE_CONFIG_A, AD4030_REG_CHIP_GRADE),
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regmap_reg_range(AD4030_REG_SCRATCH_PAD, AD4030_REG_STREAM_MODE),
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regmap_reg_range(AD4030_REG_INTERFACE_CONFIG_C,
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AD4030_REG_INTERFACE_STATUS_A),
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regmap_reg_range(AD4030_REG_EXIT_CFG_MODE, AD4030_REG_PAT3),
326
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regmap_reg_range(AD4030_REG_DIG_DIAG, AD4030_REG_DIG_ERR),
327
+
};
328
+
329
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static const struct regmap_range ad4030_regmap_wr_range[] = {
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regmap_reg_range(AD4030_REG_CHIP_TYPE, AD4030_REG_CHIP_GRADE),
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regmap_reg_range(AD4030_REG_SPI_REVISION, AD4030_REG_VENDOR_H),
332
+
};
333
+
334
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static const struct regmap_access_table ad4030_regmap_rd_table = {
335
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.yes_ranges = ad4030_regmap_rd_range,
336
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.n_yes_ranges = ARRAY_SIZE(ad4030_regmap_rd_range),
337
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};
338
+
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static const struct regmap_access_table ad4030_regmap_wr_table = {
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.no_ranges = ad4030_regmap_wr_range,
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.n_no_ranges = ARRAY_SIZE(ad4030_regmap_wr_range),
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+
};
343
+
344
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static const struct regmap_config ad4030_regmap_config = {
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.reg_bits = 16,
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.val_bits = 8,
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.read_flag_mask = 0x80,
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.rd_table = &ad4030_regmap_rd_table,
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.wr_table = &ad4030_regmap_wr_table,
350
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.max_register = AD4030_REG_DIG_ERR,
351
+
};
352
+
353
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static int ad4030_get_chan_scale(struct iio_dev *indio_dev,
354
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struct iio_chan_spec const *chan,
355
+
int *val,
356
+
int *val2)
357
+
{
358
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struct ad4030_state *st = iio_priv(indio_dev);
359
+
360
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if (chan->differential) {
361
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*val = (st->vref_uv * 2) / MILLI;
362
+
*val2 = chan->scan_type.realbits;
363
+
return IIO_VAL_FRACTIONAL_LOG2;
364
+
}
365
+
366
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*val = st->vref_uv / MILLI;
367
+
*val2 = chan->scan_type.realbits;
368
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return IIO_VAL_FRACTIONAL_LOG2;
369
+
}
370
+
371
+
static int ad4030_get_chan_calibscale(struct iio_dev *indio_dev,
372
+
struct iio_chan_spec const *chan,
373
+
int *val,
374
+
int *val2)
375
+
{
376
+
struct ad4030_state *st = iio_priv(indio_dev);
377
+
u16 gain;
378
+
int ret;
379
+
380
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ret = regmap_bulk_read(st->regmap, AD4030_REG_GAIN_CHAN(chan->address),
381
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st->rx_data.raw, AD4030_REG_GAIN_BYTES_NB);
382
+
if (ret)
383
+
return ret;
384
+
385
+
gain = get_unaligned_be16(st->rx_data.raw);
386
+
387
+
/* From datasheet: multiplied output = input × gain word/0x8000 */
388
+
*val = gain / AD4030_GAIN_MIDLE_POINT;
389
+
*val2 = mul_u64_u32_div(gain % AD4030_GAIN_MIDLE_POINT, NANO,
390
+
AD4030_GAIN_MIDLE_POINT);
391
+
392
+
return IIO_VAL_INT_PLUS_NANO;
393
+
}
394
+
395
+
/* Returns the offset where 1 LSB = (VREF/2^precision_bits - 1)/gain */
396
+
static int ad4030_get_chan_calibbias(struct iio_dev *indio_dev,
397
+
struct iio_chan_spec const *chan,
398
+
int *val)
399
+
{
400
+
struct ad4030_state *st = iio_priv(indio_dev);
401
+
int ret;
402
+
403
+
ret = regmap_bulk_read(st->regmap,
404
+
AD4030_REG_OFFSET_CHAN(chan->address),
405
+
st->rx_data.raw, AD4030_REG_OFFSET_BYTES_NB);
406
+
if (ret)
407
+
return ret;
408
+
409
+
switch (st->chip->precision_bits) {
410
+
case 16:
411
+
*val = sign_extend32(get_unaligned_be16(st->rx_data.raw), 15);
412
+
return IIO_VAL_INT;
413
+
414
+
case 24:
415
+
*val = sign_extend32(get_unaligned_be24(st->rx_data.raw), 23);
416
+
return IIO_VAL_INT;
417
+
418
+
default:
419
+
return -EINVAL;
420
+
}
421
+
}
422
+
423
+
static int ad4030_set_chan_calibscale(struct iio_dev *indio_dev,
424
+
struct iio_chan_spec const *chan,
425
+
int gain_int,
426
+
int gain_frac)
427
+
{
428
+
struct ad4030_state *st = iio_priv(indio_dev);
429
+
u64 gain;
430
+
431
+
if (gain_int < 0 || gain_frac < 0)
432
+
return -EINVAL;
433
+
434
+
gain = mul_u32_u32(gain_int, MICRO) + gain_frac;
435
+
436
+
if (gain > AD4030_REG_GAIN_MAX_GAIN)
437
+
return -EINVAL;
438
+
439
+
put_unaligned_be16(DIV_ROUND_CLOSEST_ULL(gain * AD4030_GAIN_MIDLE_POINT,
440
+
MICRO),
441
+
st->tx_data);
442
+
443
+
return regmap_bulk_write(st->regmap,
444
+
AD4030_REG_GAIN_CHAN(chan->address),
445
+
st->tx_data, AD4030_REG_GAIN_BYTES_NB);
446
+
}
447
+
448
+
static int ad4030_set_chan_calibbias(struct iio_dev *indio_dev,
449
+
struct iio_chan_spec const *chan,
450
+
int offset)
451
+
{
452
+
struct ad4030_state *st = iio_priv(indio_dev);
453
+
454
+
if (offset < st->offset_avail[0] || offset > st->offset_avail[2])
455
+
return -EINVAL;
456
+
457
+
st->tx_data[2] = 0;
458
+
459
+
switch (st->chip->precision_bits) {
460
+
case 16:
461
+
put_unaligned_be16(offset, st->tx_data);
462
+
break;
463
+
464
+
case 24:
465
+
put_unaligned_be24(offset, st->tx_data);
466
+
break;
467
+
468
+
default:
469
+
return -EINVAL;
470
+
}
471
+
472
+
return regmap_bulk_write(st->regmap,
473
+
AD4030_REG_OFFSET_CHAN(chan->address),
474
+
st->tx_data, AD4030_REG_OFFSET_BYTES_NB);
475
+
}
476
+
477
+
static bool ad4030_is_common_byte_asked(struct ad4030_state *st,
478
+
unsigned int mask)
479
+
{
480
+
return mask & AD4030_SINGLE_COMMON_BYTE_CHANNELS_MASK;
481
+
}
482
+
483
+
static int ad4030_set_mode(struct iio_dev *indio_dev, unsigned long mask)
484
+
{
485
+
struct ad4030_state *st = iio_priv(indio_dev);
486
+
487
+
if (ad4030_is_common_byte_asked(st, mask))
488
+
st->mode = AD4030_OUT_DATA_MD_24_DIFF_8_COM;
489
+
else
490
+
st->mode = AD4030_OUT_DATA_MD_DIFF;
491
+
492
+
return regmap_update_bits(st->regmap, AD4030_REG_MODES,
493
+
AD4030_REG_MODES_MASK_OUT_DATA_MODE,
494
+
st->mode);
495
+
}
496
+
497
+
static int ad4030_conversion(struct iio_dev *indio_dev)
498
+
{
499
+
struct ad4030_state *st = iio_priv(indio_dev);
500
+
const struct iio_scan_type scan_type = indio_dev->channels->scan_type;
501
+
unsigned char diff_realbytes = BITS_TO_BYTES(scan_type.realbits);
502
+
unsigned int bytes_to_read;
503
+
int ret;
504
+
505
+
/* Number of bytes for one differential channel */
506
+
bytes_to_read = diff_realbytes;
507
+
/* Add one byte if we are using a differential + common byte mode */
508
+
bytes_to_read += (st->mode == AD4030_OUT_DATA_MD_24_DIFF_8_COM ||
509
+
st->mode == AD4030_OUT_DATA_MD_16_DIFF_8_COM) ? 1 : 0;
510
+
/* Mulitiply by the number of hardware channels */
511
+
bytes_to_read *= st->chip->num_voltage_inputs;
512
+
513
+
gpiod_set_value_cansleep(st->cnv_gpio, 1);
514
+
ndelay(AD4030_TCNVH_NS);
515
+
gpiod_set_value_cansleep(st->cnv_gpio, 0);
516
+
ndelay(st->chip->tcyc_ns);
517
+
518
+
ret = spi_read(st->spi, st->rx_data.raw, bytes_to_read);
519
+
if (ret)
520
+
return ret;
521
+
522
+
if (st->mode != AD4030_OUT_DATA_MD_24_DIFF_8_COM)
523
+
return 0;
524
+
525
+
st->rx_data.common = st->rx_data.raw[diff_realbytes];
526
+
527
+
return 0;
528
+
}
529
+
530
+
static int ad4030_single_conversion(struct iio_dev *indio_dev,
531
+
const struct iio_chan_spec *chan, int *val)
532
+
{
533
+
struct ad4030_state *st = iio_priv(indio_dev);
534
+
int ret;
535
+
536
+
ret = ad4030_set_mode(indio_dev, BIT(chan->scan_index));
537
+
if (ret)
538
+
return ret;
539
+
540
+
ret = ad4030_conversion(indio_dev);
541
+
if (ret)
542
+
return ret;
543
+
544
+
if (chan->differential)
545
+
*val = st->rx_data.diff;
546
+
else
547
+
*val = st->rx_data.common;
548
+
549
+
return IIO_VAL_INT;
550
+
}
551
+
552
+
static irqreturn_t ad4030_trigger_handler(int irq, void *p)
553
+
{
554
+
struct iio_poll_func *pf = p;
555
+
struct iio_dev *indio_dev = pf->indio_dev;
556
+
struct ad4030_state *st = iio_priv(indio_dev);
557
+
int ret;
558
+
559
+
ret = ad4030_conversion(indio_dev);
560
+
if (ret)
561
+
goto out;
562
+
563
+
iio_push_to_buffers_with_timestamp(indio_dev, st->rx_data.raw,
564
+
pf->timestamp);
565
+
566
+
out:
567
+
iio_trigger_notify_done(indio_dev->trig);
568
+
569
+
return IRQ_HANDLED;
570
+
}
571
+
572
+
static const int ad4030_gain_avail[3][2] = {
573
+
{ 0, 0 },
574
+
{ 0, 30518 },
575
+
{ 1, 999969482 },
576
+
};
577
+
578
+
static int ad4030_read_avail(struct iio_dev *indio_dev,
579
+
struct iio_chan_spec const *channel,
580
+
const int **vals, int *type,
581
+
int *length, long mask)
582
+
{
583
+
struct ad4030_state *st = iio_priv(indio_dev);
584
+
585
+
switch (mask) {
586
+
case IIO_CHAN_INFO_CALIBBIAS:
587
+
*vals = st->offset_avail;
588
+
*type = IIO_VAL_INT;
589
+
return IIO_AVAIL_RANGE;
590
+
591
+
case IIO_CHAN_INFO_CALIBSCALE:
592
+
*vals = (void *)ad4030_gain_avail;
593
+
*type = IIO_VAL_INT_PLUS_NANO;
594
+
return IIO_AVAIL_RANGE;
595
+
596
+
default:
597
+
return -EINVAL;
598
+
}
599
+
}
600
+
601
+
static int ad4030_read_raw_dispatch(struct iio_dev *indio_dev,
602
+
struct iio_chan_spec const *chan, int *val,
603
+
int *val2, long info)
604
+
{
605
+
switch (info) {
606
+
case IIO_CHAN_INFO_RAW:
607
+
return ad4030_single_conversion(indio_dev, chan, val);
608
+
609
+
case IIO_CHAN_INFO_CALIBSCALE:
610
+
return ad4030_get_chan_calibscale(indio_dev, chan, val, val2);
611
+
612
+
case IIO_CHAN_INFO_CALIBBIAS:
613
+
return ad4030_get_chan_calibbias(indio_dev, chan, val);
614
+
615
+
default:
616
+
return -EINVAL;
617
+
}
618
+
}
619
+
620
+
static int ad4030_read_raw(struct iio_dev *indio_dev,
621
+
struct iio_chan_spec const *chan, int *val,
622
+
int *val2, long info)
623
+
{
624
+
int ret;
625
+
626
+
if (info == IIO_CHAN_INFO_SCALE)
627
+
return ad4030_get_chan_scale(indio_dev, chan, val, val2);
628
+
629
+
ret = iio_device_claim_direct_mode(indio_dev);
630
+
if (ret)
631
+
return ret;
632
+
633
+
ret = ad4030_read_raw_dispatch(indio_dev, chan, val, val2, info);
634
+
635
+
iio_device_release_direct_mode(indio_dev);
636
+
637
+
return ret;
638
+
}
639
+
640
+
static int ad4030_write_raw_dispatch(struct iio_dev *indio_dev,
641
+
struct iio_chan_spec const *chan, int val,
642
+
int val2, long info)
643
+
{
644
+
switch (info) {
645
+
case IIO_CHAN_INFO_CALIBSCALE:
646
+
return ad4030_set_chan_calibscale(indio_dev, chan, val, val2);
647
+
648
+
case IIO_CHAN_INFO_CALIBBIAS:
649
+
if (val2 != 0)
650
+
return -EINVAL;
651
+
return ad4030_set_chan_calibbias(indio_dev, chan, val);
652
+
653
+
default:
654
+
return -EINVAL;
655
+
}
656
+
}
657
+
658
+
static int ad4030_write_raw(struct iio_dev *indio_dev,
659
+
struct iio_chan_spec const *chan, int val,
660
+
int val2, long info)
661
+
{
662
+
int ret;
663
+
664
+
ret = iio_device_claim_direct_mode(indio_dev);
665
+
if (ret)
666
+
return ret;
667
+
668
+
ret = ad4030_write_raw_dispatch(indio_dev, chan, val, val2, info);
669
+
670
+
iio_device_release_direct_mode(indio_dev);
671
+
672
+
return ret;
673
+
}
674
+
675
+
static int ad4030_reg_access(struct iio_dev *indio_dev, unsigned int reg,
676
+
unsigned int writeval, unsigned int *readval)
677
+
{
678
+
const struct ad4030_state *st = iio_priv(indio_dev);
679
+
int ret;
680
+
681
+
ret = iio_device_claim_direct_mode(indio_dev);
682
+
if (ret)
683
+
return ret;
684
+
685
+
if (readval)
686
+
ret = regmap_read(st->regmap, reg, readval);
687
+
else
688
+
ret = regmap_write(st->regmap, reg, writeval);
689
+
690
+
iio_device_release_direct_mode(indio_dev);
691
+
692
+
return ret;
693
+
}
694
+
695
+
static int ad4030_read_label(struct iio_dev *indio_dev,
696
+
struct iio_chan_spec const *chan,
697
+
char *label)
698
+
{
699
+
if (chan->differential)
700
+
return sprintf(label, "differential%lu\n", chan->address);
701
+
return sprintf(label, "common-mode%lu\n", chan->address);
702
+
}
703
+
704
+
static const struct iio_info ad4030_iio_info = {
705
+
.read_avail = ad4030_read_avail,
706
+
.read_raw = ad4030_read_raw,
707
+
.write_raw = ad4030_write_raw,
708
+
.debugfs_reg_access = ad4030_reg_access,
709
+
.read_label = ad4030_read_label,
710
+
};
711
+
712
+
static int ad4030_buffer_preenable(struct iio_dev *indio_dev)
713
+
{
714
+
return ad4030_set_mode(indio_dev, *indio_dev->active_scan_mask);
715
+
}
716
+
717
+
static const struct iio_buffer_setup_ops ad4030_buffer_setup_ops = {
718
+
.preenable = ad4030_buffer_preenable,
719
+
};
720
+
721
+
static int ad4030_regulators_get(struct ad4030_state *st)
722
+
{
723
+
struct device *dev = &st->spi->dev;
724
+
static const char * const ids[] = { "vdd-5v", "vdd-1v8" };
725
+
int ret;
726
+
727
+
ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ids), ids);
728
+
if (ret)
729
+
return dev_err_probe(dev, ret, "Failed to enable regulators\n");
730
+
731
+
st->vio_uv = devm_regulator_get_enable_read_voltage(dev, "vio");
732
+
if (st->vio_uv < 0)
733
+
return dev_err_probe(dev, st->vio_uv,
734
+
"Failed to enable and read vio voltage\n");
735
+
736
+
st->vref_uv = devm_regulator_get_enable_read_voltage(dev, "ref");
737
+
if (st->vref_uv < 0) {
738
+
if (st->vref_uv != -ENODEV)
739
+
return dev_err_probe(dev, st->vref_uv,
740
+
"Failed to read ref voltage\n");
741
+
742
+
/* if not using optional REF, the REFIN must be used */
743
+
st->vref_uv = devm_regulator_get_enable_read_voltage(dev,
744
+
"refin");
745
+
if (st->vref_uv < 0)
746
+
return dev_err_probe(dev, st->vref_uv,
747
+
"Failed to read refin voltage\n");
748
+
}
749
+
750
+
return 0;
751
+
}
752
+
753
+
static int ad4030_reset(struct ad4030_state *st)
754
+
{
755
+
struct device *dev = &st->spi->dev;
756
+
struct gpio_desc *reset;
757
+
758
+
reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
759
+
if (IS_ERR(reset))
760
+
return dev_err_probe(dev, PTR_ERR(reset),
761
+
"Failed to get reset GPIO\n");
762
+
763
+
if (reset) {
764
+
ndelay(50);
765
+
gpiod_set_value_cansleep(reset, 0);
766
+
return 0;
767
+
}
768
+
769
+
return regmap_write(st->regmap, AD4030_REG_INTERFACE_CONFIG_A,
770
+
AD4030_REG_INTERFACE_CONFIG_A_SW_RESET);
771
+
}
772
+
773
+
static int ad4030_detect_chip_info(const struct ad4030_state *st)
774
+
{
775
+
unsigned int grade;
776
+
int ret;
777
+
778
+
ret = regmap_read(st->regmap, AD4030_REG_CHIP_GRADE, &grade);
779
+
if (ret)
780
+
return ret;
781
+
782
+
grade = FIELD_GET(AD4030_REG_CHIP_GRADE_MASK_CHIP_GRADE, grade);
783
+
if (grade != st->chip->grade)
784
+
dev_warn(&st->spi->dev, "Unknown grade(0x%x) for %s\n", grade,
785
+
st->chip->name);
786
+
787
+
return 0;
788
+
}
789
+
790
+
static int ad4030_config(struct ad4030_state *st)
791
+
{
792
+
st->offset_avail[0] = (int)BIT(st->chip->precision_bits - 1) * -1;
793
+
st->offset_avail[1] = 1;
794
+
st->offset_avail[2] = BIT(st->chip->precision_bits - 1) - 1;
795
+
796
+
if (st->vio_uv < AD4030_VIO_THRESHOLD_UV)
797
+
return regmap_write(st->regmap, AD4030_REG_IO,
798
+
AD4030_REG_IO_MASK_IO2X);
799
+
800
+
return 0;
801
+
}
802
+
803
+
static int ad4030_probe(struct spi_device *spi)
804
+
{
805
+
struct device *dev = &spi->dev;
806
+
struct iio_dev *indio_dev;
807
+
struct ad4030_state *st;
808
+
int ret;
809
+
810
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
811
+
if (!indio_dev)
812
+
return -ENOMEM;
813
+
814
+
st = iio_priv(indio_dev);
815
+
st->spi = spi;
816
+
817
+
st->regmap = devm_regmap_init(dev, &ad4030_regmap_bus, st,
818
+
&ad4030_regmap_config);
819
+
if (IS_ERR(st->regmap))
820
+
dev_err_probe(dev, PTR_ERR(st->regmap),
821
+
"Failed to initialize regmap\n");
822
+
823
+
st->chip = spi_get_device_match_data(spi);
824
+
if (!st->chip)
825
+
return -EINVAL;
826
+
827
+
ret = ad4030_regulators_get(st);
828
+
if (ret)
829
+
return ret;
830
+
831
+
/*
832
+
* From datasheet: "Perform a reset no sooner than 3ms after the power
833
+
* supplies are valid and stable"
834
+
*/
835
+
fsleep(3000);
836
+
837
+
ret = ad4030_reset(st);
838
+
if (ret)
839
+
return ret;
840
+
841
+
ret = ad4030_detect_chip_info(st);
842
+
if (ret)
843
+
return ret;
844
+
845
+
ret = ad4030_config(st);
846
+
if (ret)
847
+
return ret;
848
+
849
+
st->cnv_gpio = devm_gpiod_get(dev, "cnv", GPIOD_OUT_LOW);
850
+
if (IS_ERR(st->cnv_gpio))
851
+
return dev_err_probe(dev, PTR_ERR(st->cnv_gpio),
852
+
"Failed to get cnv gpio\n");
853
+
854
+
/*
855
+
* One hardware channel is split in two software channels when using
856
+
* common byte mode. Add one more channel for the timestamp.
857
+
*/
858
+
indio_dev->num_channels = 2 * st->chip->num_voltage_inputs + 1;
859
+
indio_dev->name = st->chip->name;
860
+
indio_dev->modes = INDIO_DIRECT_MODE;
861
+
indio_dev->info = &ad4030_iio_info;
862
+
indio_dev->channels = st->chip->channels;
863
+
indio_dev->available_scan_masks = st->chip->available_masks;
864
+
865
+
ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
866
+
iio_pollfunc_store_time,
867
+
ad4030_trigger_handler,
868
+
&ad4030_buffer_setup_ops);
869
+
if (ret)
870
+
return dev_err_probe(dev, ret,
871
+
"Failed to setup triggered buffer\n");
872
+
873
+
return devm_iio_device_register(dev, indio_dev);
874
+
}
875
+
876
+
static const unsigned long ad4030_channel_masks[] = {
877
+
/* Differential only */
878
+
BIT(0),
879
+
/* Differential and common-mode voltage */
880
+
GENMASK(1, 0),
881
+
0,
882
+
};
883
+
884
+
static const struct ad4030_chip_info ad4030_24_chip_info = {
885
+
.name = "ad4030-24",
886
+
.available_masks = ad4030_channel_masks,
887
+
.channels = {
888
+
AD4030_CHAN_DIFF(0, 32, 24, 8),
889
+
AD4030_CHAN_CMO(1, 0),
890
+
IIO_CHAN_SOFT_TIMESTAMP(2),
891
+
},
892
+
.grade = AD4030_REG_CHIP_GRADE_AD4030_24_GRADE,
893
+
.precision_bits = 24,
894
+
.num_voltage_inputs = 1,
895
+
.tcyc_ns = AD4030_TCYC_ADJUSTED_NS,
896
+
};
897
+
898
+
static const struct spi_device_id ad4030_id_table[] = {
899
+
{ "ad4030-24", (kernel_ulong_t)&ad4030_24_chip_info },
900
+
{ }
901
+
};
902
+
MODULE_DEVICE_TABLE(spi, ad4030_id_table);
903
+
904
+
static const struct of_device_id ad4030_of_match[] = {
905
+
{ .compatible = "adi,ad4030-24", .data = &ad4030_24_chip_info },
906
+
{ }
907
+
};
908
+
MODULE_DEVICE_TABLE(of, ad4030_of_match);
909
+
910
+
static struct spi_driver ad4030_driver = {
911
+
.driver = {
912
+
.name = "ad4030",
913
+
.of_match_table = ad4030_of_match,
914
+
},
915
+
.probe = ad4030_probe,
916
+
.id_table = ad4030_id_table,
917
+
};
918
+
module_spi_driver(ad4030_driver);
919
+
920
+
MODULE_AUTHOR("Esteban Blanc <eblanc@baylibre.com>");
921
+
MODULE_DESCRIPTION("Analog Devices AD4630 ADC family driver");
922
+
MODULE_LICENSE("GPL");