tjh.dev / kernel
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drm/amdgpu: add support for NBIO IP version 7.11.4

This initializes NBIO IP version 7.11.4.

Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Tim Huang <tim.huang@amd.com>
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Tim Huang and committed by
Alex Deucher 0cc0c5e7 ab90fd05

+66 -10
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
··· 3065 3065 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 3066 3066 break; 3067 3067 case IP_VERSION(6, 3, 1): 3068 + case IP_VERSION(7, 11, 4): 3068 3069 adev->nbio.funcs = &nbif_v6_3_1_funcs; 3069 3070 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 3070 3071 break;
+63 -10
drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
··· 30 30 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 31 31 #include <uapi/linux/kfd_ioctl.h> 32 32 33 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10 0x4f0aeb 34 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10_BASE_IDX 3 35 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_nbif_4_10 0x4f0aec 36 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_nbif_4_10_BASE_IDX 3 37 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10 0x4f0aed 38 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10_BASE_IDX 3 39 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_nbif_4_10 0x4f0aee 40 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_nbif_4_10_BASE_IDX 3 41 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10 0x4f0aef 42 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10_BASE_IDX 3 43 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_nbif_4_10 0x4f0af0 44 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_nbif_4_10_BASE_IDX 3 45 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10 0x4f0af1 46 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10_BASE_IDX 3 47 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_nbif_4_10 0x4f0af2 48 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_nbif_4_10_BASE_IDX 3 49 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10 0x4f0af3 50 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10_BASE_IDX 3 51 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_nbif_4_10 0x4f0af4 52 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_nbif_4_10_BASE_IDX 3 53 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10 0x4f0af5 54 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10_BASE_IDX 3 55 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_nbif_4_10 0x4f0af6 56 + #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_nbif_4_10_BASE_IDX 3 57 + 33 58 static void nbif_v6_3_1_remap_hdp_registers(struct amdgpu_device *adev) 34 59 { 35 60 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, ··· 123 98 S2A_DOORBELL_PORT2_RANGE_SIZE, 124 99 0); 125 100 126 - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, doorbell_range); 101 + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { 102 + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10, doorbell_range); 103 + } else { 104 + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, doorbell_range); 105 + } 127 106 } 128 107 } 129 108 ··· 169 140 S2A_DOORBELL_PORT4_RANGE_SIZE, 170 141 0); 171 142 172 - if (instance) 173 - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); 174 - else 175 - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range); 143 + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { 144 + if (instance) 145 + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10, doorbell_range); 146 + else 147 + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10, doorbell_range); 148 + } else { 149 + if (instance) 150 + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); 151 + else 152 + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range); 153 + } 176 154 } 177 155 178 156 static void nbif_v6_3_1_gc_doorbell_init(struct amdgpu_device *adev) 179 157 { 180 - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007); 181 - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d); 158 + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { 159 + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10, 0x30000007); 160 + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10, 0x3000000d); 161 + } else { 162 + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007); 163 + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d); 164 + } 182 165 } 183 166 184 167 static void nbif_v6_3_1_enable_doorbell_aperture(struct amdgpu_device *adev, ··· 255 214 S2A_DOORBELL_PORT1_RANGE_SIZE, 256 215 0); 257 216 258 - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range); 217 + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { 218 + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10, ih_doorbell_range); 219 + } else { 220 + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range); 221 + } 259 222 } 260 223 261 224 static void nbif_v6_3_1_ih_control(struct amdgpu_device *adev) ··· 314 269 315 270 static u32 nbif_v6_3_1_get_pcie_index_offset(struct amdgpu_device *adev) 316 271 { 317 - return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); 272 + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { 273 + return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX); 274 + } 275 + else { 276 + return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); 277 + } 318 278 } 319 279 320 280 static u32 nbif_v6_3_1_get_pcie_data_offset(struct amdgpu_device *adev) 321 281 { 322 - return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); 282 + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) 283 + return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA); 284 + else 285 + return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); 323 286 } 324 287 325 288 const struct nbio_hdp_flush_reg nbif_v6_3_1_hdp_flush_reg = {
+1
drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c
··· 279 279 case IP_VERSION(7, 11, 1): 280 280 case IP_VERSION(7, 11, 2): 281 281 case IP_VERSION(7, 11, 3): 282 + case IP_VERSION(7, 11, 4): 282 283 data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23); 283 284 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4, data); 284 285 break;
+1
drivers/gpu/drm/amd/amdgpu/soc21.c
··· 965 965 case IP_VERSION(7, 11, 1): 966 966 case IP_VERSION(7, 11, 2): 967 967 case IP_VERSION(7, 11, 3): 968 + case IP_VERSION(7, 11, 4): 968 969 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 969 970 state == AMD_CG_STATE_GATE); 970 971 adev->nbio.funcs->update_medium_grain_light_sleep(adev,