Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2022-12-09' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Last set of fixes for final, scattered bunch of fixes, two amdgpu, one
vmwgfx, and some misc others.
amdgpu:
- S0ix fix
- DCN 3.2 array out of bounds fix
shmem:
- Fixes to shmem-helper error paths
bridge:
- Fix polarity bug in bridge/ti-sn65dsi86
dw-hdmi:
- Prefer 8-bit RGB fallback before any YUV mode in dw-hdmi, since
some panels lie about YUV support
vmwgfx:
- Stop using screen objects when SEV is active"
* tag 'drm-fixes-2022-12-09' of git://anongit.freedesktop.org/drm/drm:
drm/amd/display: fix array index out of bound error in DCN32 DML
drm/amdgpu/sdma_v4_0: turn off SDMA ring buffer in the s2idle suspend
drm/vmwgfx: Don't use screen objects when SEV is active
drm/shmem-helper: Avoid vm_open error paths
drm/shmem-helper: Remove errant put in error path
drm: bridge: dw_hdmi: fix preference of RGB modes over YUV420
drm/bridge: ti-sn65dsi86: Fix output polarity setting bug
drm/vmwgfx: Fix race issue calling pin_user_pages
+40
-24
+15
-9
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+15
-9
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
···
907
907
908
908
909
909
/**
910
-
* sdma_v4_0_gfx_stop - stop the gfx async dma engines
910
+
* sdma_v4_0_gfx_enable - enable the gfx async dma engines
911
911
*
912
912
* @adev: amdgpu_device pointer
913
-
*
914
-
* Stop the gfx async dma ring buffers (VEGA10).
913
+
* @enable: enable SDMA RB/IB
914
+
* control the gfx async dma ring buffers (VEGA10).
915
915
*/
916
-
static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
916
+
static void sdma_v4_0_gfx_enable(struct amdgpu_device *adev, bool enable)
917
917
{
918
918
u32 rb_cntl, ib_cntl;
919
919
int i;
···
922
922
923
923
for (i = 0; i < adev->sdma.num_instances; i++) {
924
924
rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
925
-
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
925
+
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, enable ? 1 : 0);
926
926
WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
927
927
ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
928
-
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
928
+
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, enable ? 1 : 0);
929
929
WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
930
930
}
931
931
}
···
1044
1044
int i;
1045
1045
1046
1046
if (!enable) {
1047
-
sdma_v4_0_gfx_stop(adev);
1047
+
sdma_v4_0_gfx_enable(adev, enable);
1048
1048
sdma_v4_0_rlc_stop(adev);
1049
1049
if (adev->sdma.has_page_queue)
1050
1050
sdma_v4_0_page_stop(adev);
···
1960
1960
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1961
1961
1962
1962
/* SMU saves SDMA state for us */
1963
-
if (adev->in_s0ix)
1963
+
if (adev->in_s0ix) {
1964
+
sdma_v4_0_gfx_enable(adev, false);
1964
1965
return 0;
1966
+
}
1965
1967
1966
1968
return sdma_v4_0_hw_fini(adev);
1967
1969
}
···
1973
1971
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1974
1972
1975
1973
/* SMU restores SDMA state for us */
1976
-
if (adev->in_s0ix)
1974
+
if (adev->in_s0ix) {
1975
+
sdma_v4_0_enable(adev, true);
1976
+
sdma_v4_0_gfx_enable(adev, true);
1977
+
amdgpu_ttm_set_buffer_funcs_status(adev, true);
1977
1978
return 0;
1979
+
}
1978
1980
1979
1981
return sdma_v4_0_hw_init(adev);
1980
1982
}
+1
-1
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+1
-1
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
···
1153
1153
double UrgBurstFactorLumaPre[DC__NUM_DPP__MAX];
1154
1154
double UrgBurstFactorChromaPre[DC__NUM_DPP__MAX];
1155
1155
bool NotUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
1156
-
bool LinkCapacitySupport[DC__NUM_DPP__MAX];
1156
+
bool LinkCapacitySupport[DC__VOLTAGE_STATES];
1157
1157
bool VREADY_AT_OR_AFTER_VSYNC[DC__NUM_DPP__MAX];
1158
1158
unsigned int MIN_DST_Y_NEXT_START[DC__NUM_DPP__MAX];
1159
1159
unsigned int VFrontPorch[DC__NUM_DPP__MAX];
+3
-3
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+3
-3
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
···
2720
2720
* if supported. In any case the default RGB888 format is added
2721
2721
*/
2722
2722
2723
+
/* Default 8bit RGB fallback */
2724
+
output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2725
+
2723
2726
if (max_bpc >= 16 && info->bpc == 16) {
2724
2727
if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
2725
2728
output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
···
2755
2752
2756
2753
if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
2757
2754
output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2758
-
2759
-
/* Default 8bit RGB fallback */
2760
-
output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2761
2755
2762
2756
*num_output_fmts = i;
2763
2757
+2
-2
drivers/gpu/drm/bridge/ti-sn65dsi86.c
+2
-2
drivers/gpu/drm/bridge/ti-sn65dsi86.c
···
931
931
&pdata->bridge.encoder->crtc->state->adjusted_mode;
932
932
u8 hsync_polarity = 0, vsync_polarity = 0;
933
933
934
-
if (mode->flags & DRM_MODE_FLAG_PHSYNC)
934
+
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
935
935
hsync_polarity = CHA_HSYNC_POLARITY;
936
-
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
936
+
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
937
937
vsync_polarity = CHA_VSYNC_POLARITY;
938
938
939
939
ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
+12
-6
drivers/gpu/drm/drm_gem_shmem_helper.c
+12
-6
drivers/gpu/drm/drm_gem_shmem_helper.c
···
571
571
{
572
572
struct drm_gem_object *obj = vma->vm_private_data;
573
573
struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj);
574
-
int ret;
575
574
576
575
WARN_ON(shmem->base.import_attach);
577
576
578
-
ret = drm_gem_shmem_get_pages(shmem);
579
-
WARN_ON_ONCE(ret != 0);
577
+
mutex_lock(&shmem->pages_lock);
578
+
579
+
/*
580
+
* We should have already pinned the pages when the buffer was first
581
+
* mmap'd, vm_open() just grabs an additional reference for the new
582
+
* mm the vma is getting copied into (ie. on fork()).
583
+
*/
584
+
if (!WARN_ON_ONCE(!shmem->pages_use_count))
585
+
shmem->pages_use_count++;
586
+
587
+
mutex_unlock(&shmem->pages_lock);
580
588
581
589
drm_gem_vm_open(vma);
582
590
}
···
630
622
}
631
623
632
624
ret = drm_gem_shmem_get_pages(shmem);
633
-
if (ret) {
634
-
drm_gem_vm_close(vma);
625
+
if (ret)
635
626
return ret;
636
-
}
637
627
638
628
vma->vm_flags |= VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP;
639
629
vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
+3
-3
drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
+3
-3
drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
···
1085
1085
reset_ppn_array(pdesc->strsPPNs, ARRAY_SIZE(pdesc->strsPPNs));
1086
1086
1087
1087
/* Pin mksGuestStat user pages and store those in the instance descriptor */
1088
-
nr_pinned_stat = pin_user_pages(arg->stat, num_pages_stat, FOLL_LONGTERM, pages_stat, NULL);
1088
+
nr_pinned_stat = pin_user_pages_fast(arg->stat, num_pages_stat, FOLL_LONGTERM, pages_stat);
1089
1089
if (num_pages_stat != nr_pinned_stat)
1090
1090
goto err_pin_stat;
1091
1091
1092
1092
for (i = 0; i < num_pages_stat; ++i)
1093
1093
pdesc->statPPNs[i] = page_to_pfn(pages_stat[i]);
1094
1094
1095
-
nr_pinned_info = pin_user_pages(arg->info, num_pages_info, FOLL_LONGTERM, pages_info, NULL);
1095
+
nr_pinned_info = pin_user_pages_fast(arg->info, num_pages_info, FOLL_LONGTERM, pages_info);
1096
1096
if (num_pages_info != nr_pinned_info)
1097
1097
goto err_pin_info;
1098
1098
1099
1099
for (i = 0; i < num_pages_info; ++i)
1100
1100
pdesc->infoPPNs[i] = page_to_pfn(pages_info[i]);
1101
1101
1102
-
nr_pinned_strs = pin_user_pages(arg->strs, num_pages_strs, FOLL_LONGTERM, pages_strs, NULL);
1102
+
nr_pinned_strs = pin_user_pages_fast(arg->strs, num_pages_strs, FOLL_LONGTERM, pages_strs);
1103
1103
if (num_pages_strs != nr_pinned_strs)
1104
1104
goto err_pin_strs;
1105
1105
+4
drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
+4
drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
···
949
949
struct drm_device *dev = &dev_priv->drm;
950
950
int i, ret;
951
951
952
+
/* Screen objects won't work if GMR's aren't available */
953
+
if (!dev_priv->has_gmr)
954
+
return -ENOSYS;
955
+
952
956
if (!(dev_priv->capabilities & SVGA_CAP_SCREEN_OBJECT_2)) {
953
957
return -ENOSYS;
954
958
}