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Merge tag 'devicetree-fixes-for-5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree fixes from Rob Herring:

- Two fixes due to DT node name changes on Arm, Ltd. boards

- Treewide rename of Ingenic CGU headers

- Update ST email addresses

- Remove Netlogic DT bindings

- Dropping few more cases of redundant 'maxItems' in schemas

- Convert toshiba,tc358767 bridge binding to schema

* tag 'devicetree-fixes-for-5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
dt-bindings: watchdog: sunxi: fix error in schema
bindings: media: venus: Drop redundant maxItems for power-domain-names
dt-bindings: Remove Netlogic bindings
clk: versatile: clk-icst: Ensure clock names are unique
of: Support using 'mask' in making device bus id
dt-bindings: treewide: Update @st.com email address to @foss.st.com
dt-bindings: media: Update maintainers for st,stm32-hwspinlock.yaml
dt-bindings: media: Update maintainers for st,stm32-cec.yaml
dt-bindings: mfd: timers: Update maintainers for st,stm32-timers
dt-bindings: timer: Update maintainers for st,stm32-timer
dt-bindings: i2c: imx: hardware do not restrict clock-frequency to only 100 and 400 kHz
dt-bindings: display: bridge: Convert toshiba,tc358767.txt to yaml
dt-bindings: Rename Ingenic CGU headers to ingenic,*.h

Linus Torvalds 0d1503d8 622c72b6

+277 -277
+1 -1
Documentation/devicetree/bindings/arm/sti.yaml
··· 7 7 title: ST STi Platforms Device Tree Bindings 8 8 9 9 maintainers: 10 - - Patrice Chotard <patrice.chotard@st.com> 10 + - Patrice Chotard <patrice.chotard@foss.st.com> 11 11 12 12 properties: 13 13 $nodename:
+2 -2
Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml
··· 7 7 title: STMicroelectronics STM32 ML-AHB interconnect bindings 8 8 9 9 maintainers: 10 - - Fabien Dessenne <fabien.dessenne@st.com> 11 - - Arnaud Pouliquen <arnaud.pouliquen@st.com> 10 + - Fabien Dessenne <fabien.dessenne@foss.st.com> 11 + - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> 12 12 13 13 description: | 14 14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
+2 -2
Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
··· 7 7 title: STMicroelectronics STM32 Platforms System Controller bindings 8 8 9 9 maintainers: 10 - - Alexandre Torgue <alexandre.torgue@st.com> 11 - - Christophe Roullier <christophe.roullier@st.com> 10 + - Alexandre Torgue <alexandre.torgue@foss.st.com> 11 + - Christophe Roullier <christophe.roullier@foss.st.com> 12 12 13 13 properties: 14 14 compatible:
+1 -1
Documentation/devicetree/bindings/arm/stm32/stm32.yaml
··· 7 7 title: STMicroelectronics STM32 Platforms Device Tree Bindings 8 8 9 9 maintainers: 10 - - Alexandre Torgue <alexandre.torgue@st.com> 10 + - Alexandre Torgue <alexandre.torgue@foss.st.com> 11 11 12 12 properties: 13 13 $nodename:
+1 -1
Documentation/devicetree/bindings/clock/ingenic,cgu.yaml
··· 104 104 105 105 examples: 106 106 - | 107 - #include <dt-bindings/clock/jz4770-cgu.h> 107 + #include <dt-bindings/clock/ingenic,jz4770-cgu.h> 108 108 cgu: clock-controller@10000000 { 109 109 compatible = "ingenic,jz4770-cgu", "simple-mfd"; 110 110 reg = <0x10000000 0x100>;
+1 -1
Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
··· 7 7 title: Reset Clock Controller Binding 8 8 9 9 maintainers: 10 - - Gabriel Fernandez <gabriel.fernandez@st.com> 10 + - Gabriel Fernandez <gabriel.fernandez@foss.st.com> 11 11 12 12 description: | 13 13 The RCC IP is both a reset and a clock controller.
+1 -1
Documentation/devicetree/bindings/crypto/st,stm32-crc.yaml
··· 7 7 title: STMicroelectronics STM32 CRC bindings 8 8 9 9 maintainers: 10 - - Lionel Debieve <lionel.debieve@st.com> 10 + - Lionel Debieve <lionel.debieve@foss.st.com> 11 11 12 12 properties: 13 13 compatible:
+1 -1
Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml
··· 7 7 title: STMicroelectronics STM32 CRYP bindings 8 8 9 9 maintainers: 10 - - Lionel Debieve <lionel.debieve@st.com> 10 + - Lionel Debieve <lionel.debieve@foss.st.com> 11 11 12 12 properties: 13 13 compatible:
+1 -1
Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
··· 7 7 title: STMicroelectronics STM32 HASH bindings 8 8 9 9 maintainers: 10 - - Lionel Debieve <lionel.debieve@st.com> 10 + - Lionel Debieve <lionel.debieve@foss.st.com> 11 11 12 12 properties: 13 13 compatible:
+1 -1
Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml
··· 7 7 title: Synopsys DesignWare MIPI DSI host controller 8 8 9 9 maintainers: 10 - - Philippe CORNU <philippe.cornu@st.com> 10 + - Philippe CORNU <philippe.cornu@foss.st.com> 11 11 12 12 description: | 13 13 This document defines device tree properties for the Synopsys DesignWare MIPI
-54
Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.txt
··· 1 - Toshiba TC358767 eDP bridge bindings 2 - 3 - Required properties: 4 - - compatible: "toshiba,tc358767" 5 - - reg: i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins 6 - - clock-names: should be "ref" 7 - - clocks: OF device-tree clock specification for refclk input. The reference 8 - clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz. 9 - 10 - Optional properties: 11 - - shutdown-gpios: OF device-tree gpio specification for SD pin 12 - (active high shutdown input) 13 - - reset-gpios: OF device-tree gpio specification for RSTX pin 14 - (active low system reset) 15 - - toshiba,hpd-pin: TC358767 GPIO pin number to which HPD is connected to (0 or 1) 16 - - ports: the ports node can contain video interface port nodes to connect 17 - to a DPI/DSI source and to an eDP/DP sink according to [1][2]: 18 - - port@0: DSI input port 19 - - port@1: DPI input port 20 - - port@2: eDP/DP output port 21 - 22 - [1]: Documentation/devicetree/bindings/graph.txt 23 - [2]: Documentation/devicetree/bindings/media/video-interfaces.txt 24 - 25 - Example: 26 - edp-bridge@68 { 27 - compatible = "toshiba,tc358767"; 28 - reg = <0x68>; 29 - shutdown-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; 30 - reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; 31 - clock-names = "ref"; 32 - clocks = <&edp_refclk>; 33 - 34 - ports { 35 - #address-cells = <1>; 36 - #size-cells = <0>; 37 - 38 - port@1 { 39 - reg = <1>; 40 - 41 - bridge_in: endpoint { 42 - remote-endpoint = <&dpi_out>; 43 - }; 44 - }; 45 - 46 - port@2 { 47 - reg = <2>; 48 - 49 - bridge_out: endpoint { 50 - remote-endpoint = <&panel_in>; 51 - }; 52 - }; 53 - }; 54 - };
+158
Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/display/bridge/toshiba,tc358767.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Toshiba TC358767 eDP bridge bindings 8 + 9 + maintainers: 10 + - Andrey Gusakov <andrey.gusakov@cogentembedded.com> 11 + 12 + description: The TC358767 is bridge device which converts DSI/DPI to eDP/DP 13 + 14 + properties: 15 + compatible: 16 + const: toshiba,tc358767 17 + 18 + reg: 19 + enum: 20 + - 0x68 21 + - 0x0f 22 + description: | 23 + i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins 24 + 25 + clock-names: 26 + const: "ref" 27 + 28 + clocks: 29 + maxItems: 1 30 + description: | 31 + OF device-tree clock specification for refclk input. The reference. 32 + clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz. 33 + 34 + shutdown-gpios: 35 + maxItems: 1 36 + description: | 37 + OF device-tree gpio specification for SD pin(active high shutdown input) 38 + 39 + reset-gpios: 40 + maxItems: 1 41 + description: | 42 + OF device-tree gpio specification for RSTX pin(active low system reset) 43 + 44 + toshiba,hpd-pin: 45 + $ref: /schemas/types.yaml#/definitions/uint32 46 + enum: 47 + - 0 48 + - 1 49 + description: TC358767 GPIO pin number to which HPD is connected to (0 or 1) 50 + 51 + ports: 52 + $ref: /schemas/graph.yaml#/properties/ports 53 + 54 + properties: 55 + port@0: 56 + $ref: /schemas/graph.yaml#/properties/port 57 + description: | 58 + DSI input port. The remote endpoint phandle should be a 59 + reference to a valid DSI output endpoint node 60 + 61 + port@1: 62 + $ref: /schemas/graph.yaml#/properties/port 63 + description: | 64 + DPI input port. The remote endpoint phandle should be a 65 + reference to a valid DPI output endpoint node 66 + 67 + port@2: 68 + $ref: /schemas/graph.yaml#/properties/port 69 + description: | 70 + eDP/DP output port. The remote endpoint phandle should be a 71 + reference to a valid eDP panel input endpoint node. This port is 72 + optional, treated as DP panel if not defined 73 + 74 + oneOf: 75 + - required: 76 + - port@0 77 + - required: 78 + - port@1 79 + 80 + 81 + required: 82 + - compatible 83 + - reg 84 + - clock-names 85 + - clocks 86 + - ports 87 + 88 + additionalProperties: false 89 + 90 + examples: 91 + - | 92 + #include <dt-bindings/gpio/gpio.h> 93 + 94 + /* DPI input and eDP output */ 95 + 96 + i2c { 97 + #address-cells = <1>; 98 + #size-cells = <0>; 99 + 100 + edp-bridge@68 { 101 + compatible = "toshiba,tc358767"; 102 + reg = <0x68>; 103 + shutdown-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; 104 + reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; 105 + clock-names = "ref"; 106 + clocks = <&edp_refclk>; 107 + 108 + ports { 109 + #address-cells = <1>; 110 + #size-cells = <0>; 111 + 112 + port@1 { 113 + reg = <1>; 114 + 115 + bridge_in_0: endpoint { 116 + remote-endpoint = <&dpi_out>; 117 + }; 118 + }; 119 + 120 + port@2 { 121 + reg = <2>; 122 + 123 + bridge_out: endpoint { 124 + remote-endpoint = <&panel_in>; 125 + }; 126 + }; 127 + }; 128 + }; 129 + }; 130 + - | 131 + /* DPI input and DP output */ 132 + 133 + i2c { 134 + #address-cells = <1>; 135 + #size-cells = <0>; 136 + 137 + edp-bridge@68 { 138 + compatible = "toshiba,tc358767"; 139 + reg = <0x68>; 140 + shutdown-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; 141 + reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; 142 + clock-names = "ref"; 143 + clocks = <&edp_refclk>; 144 + 145 + ports { 146 + #address-cells = <1>; 147 + #size-cells = <0>; 148 + 149 + port@1 { 150 + reg = <1>; 151 + 152 + bridge_in_1: endpoint { 153 + remote-endpoint = <&dpi_out>; 154 + }; 155 + }; 156 + }; 157 + }; 158 + };
+1 -1
Documentation/devicetree/bindings/display/ingenic,ipu.yaml
··· 45 45 46 46 examples: 47 47 - | 48 - #include <dt-bindings/clock/jz4770-cgu.h> 48 + #include <dt-bindings/clock/ingenic,jz4770-cgu.h> 49 49 ipu@13080000 { 50 50 compatible = "ingenic,jz4770-ipu", "ingenic,jz4760-ipu"; 51 51 reg = <0x13080000 0x800>;
+2 -2
Documentation/devicetree/bindings/display/ingenic,lcd.yaml
··· 88 88 89 89 examples: 90 90 - | 91 - #include <dt-bindings/clock/jz4740-cgu.h> 91 + #include <dt-bindings/clock/ingenic,jz4740-cgu.h> 92 92 lcd-controller@13050000 { 93 93 compatible = "ingenic,jz4740-lcd"; 94 94 reg = <0x13050000 0x1000>; ··· 107 107 }; 108 108 109 109 - | 110 - #include <dt-bindings/clock/jz4725b-cgu.h> 110 + #include <dt-bindings/clock/ingenic,jz4725b-cgu.h> 111 111 lcd-controller@13050000 { 112 112 compatible = "ingenic,jz4725b-lcd"; 113 113 reg = <0x13050000 0x1000>;
+1 -1
Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.yaml
··· 7 7 title: Orise Tech OTM8009A 3.97" 480x800 TFT LCD panel (MIPI-DSI video mode) 8 8 9 9 maintainers: 10 - - Philippe CORNU <philippe.cornu@st.com> 10 + - Philippe CORNU <philippe.cornu@foss.st.com> 11 11 12 12 description: | 13 13 The Orise Tech OTM8009A is a 3.97" 480x800 TFT LCD panel connected using
+1 -1
Documentation/devicetree/bindings/display/panel/raydium,rm68200.yaml
··· 7 7 title: Raydium Semiconductor Corporation RM68200 5.5" 720p MIPI-DSI TFT LCD panel 8 8 9 9 maintainers: 10 - - Philippe CORNU <philippe.cornu@st.com> 10 + - Philippe CORNU <philippe.cornu@foss.st.com> 11 11 12 12 description: | 13 13 The Raydium Semiconductor Corporation RM68200 is a 5.5" 720x1280 TFT LCD
+2 -2
Documentation/devicetree/bindings/display/st,stm32-dsi.yaml
··· 7 7 title: STMicroelectronics STM32 DSI host controller 8 8 9 9 maintainers: 10 - - Philippe Cornu <philippe.cornu@st.com> 11 - - Yannick Fertre <yannick.fertre@st.com> 10 + - Philippe Cornu <philippe.cornu@foss.st.com> 11 + - Yannick Fertre <yannick.fertre@foss.st.com> 12 12 13 13 description: 14 14 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
+2 -2
Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml
··· 7 7 title: STMicroelectronics STM32 lcd-tft display controller 8 8 9 9 maintainers: 10 - - Philippe Cornu <philippe.cornu@st.com> 11 - - Yannick Fertre <yannick.fertre@st.com> 10 + - Philippe Cornu <philippe.cornu@foss.st.com> 11 + - Yannick Fertre <yannick.fertre@foss.st.com> 12 12 13 13 properties: 14 14 compatible:
+1 -1
Documentation/devicetree/bindings/dma/ingenic,dma.yaml
··· 68 68 69 69 examples: 70 70 - | 71 - #include <dt-bindings/clock/jz4780-cgu.h> 71 + #include <dt-bindings/clock/ingenic,jz4780-cgu.h> 72 72 dma: dma-controller@13420000 { 73 73 compatible = "ingenic,jz4780-dma"; 74 74 reg = <0x13420000 0x400>, <0x13421000 0x40>;
+1 -1
Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
··· 50 50 51 51 52 52 maintainers: 53 - - Amelie Delaunay <amelie.delaunay@st.com> 53 + - Amelie Delaunay <amelie.delaunay@foss.st.com> 54 54 55 55 allOf: 56 56 - $ref: "dma-controller.yaml#"
+1 -1
Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
··· 7 7 title: STMicroelectronics STM32 DMA MUX (DMA request router) bindings 8 8 9 9 maintainers: 10 - - Amelie Delaunay <amelie.delaunay@st.com> 10 + - Amelie Delaunay <amelie.delaunay@foss.st.com> 11 11 12 12 allOf: 13 13 - $ref: "dma-router.yaml#"
+1 -1
Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml
··· 50 50 if no HW ack signal is used by the MDMA client 51 51 52 52 maintainers: 53 - - Amelie Delaunay <amelie.delaunay@st.com> 53 + - Amelie Delaunay <amelie.delaunay@foss.st.com> 54 54 55 55 allOf: 56 56 - $ref: "dma-controller.yaml#"
-49
Documentation/devicetree/bindings/gpio/gpio-xlp.txt
··· 1 - Netlogic XLP Family GPIO 2 - ======================== 3 - 4 - This GPIO driver is used for following Netlogic XLP SoCs: 5 - XLP832, XLP316, XLP208, XLP980, XLP532 6 - This GPIO driver is also compatible with GPIO controller found on 7 - Broadcom Vulcan ARM64. 8 - 9 - Required properties: 10 - ------------------- 11 - 12 - - compatible: Should be one of the following: 13 - - "netlogic,xlp832-gpio": For Netlogic XLP832 14 - - "netlogic,xlp316-gpio": For Netlogic XLP316 15 - - "netlogic,xlp208-gpio": For Netlogic XLP208 16 - - "netlogic,xlp980-gpio": For Netlogic XLP980 17 - - "netlogic,xlp532-gpio": For Netlogic XLP532 18 - - "brcm,vulcan-gpio": For Broadcom Vulcan ARM64 19 - - reg: Physical base address and length of the controller's registers. 20 - - #gpio-cells: Should be two. The first cell is the pin number and the second 21 - cell is used to specify optional parameters (currently unused). 22 - - gpio-controller: Marks the device node as a GPIO controller. 23 - - nr-gpios: Number of GPIO pins supported by the controller. 24 - - interrupt-cells: Should be two. The first cell is the GPIO Number. The 25 - second cell is used to specify flags. The following subset of flags is 26 - supported: 27 - - trigger type: 28 - 1 = low to high edge triggered. 29 - 2 = high to low edge triggered. 30 - 4 = active high level-sensitive. 31 - 8 = active low level-sensitive. 32 - - interrupts: Interrupt number for this device. 33 - - interrupt-controller: Identifies the node as an interrupt controller. 34 - 35 - Example: 36 - 37 - gpio: xlp_gpio@34000 { 38 - compatible = "netlogic,xlp316-gpio"; 39 - reg = <0 0x34100 0x1000 40 - 0 0x35100 0x1000>; 41 - #gpio-cells = <2>; 42 - gpio-controller; 43 - nr-gpios = <57>; 44 - 45 - #interrupt-cells = <2>; 46 - interrupt-parent = <&pic>; 47 - interrupts = <39>; 48 - interrupt-controller; 49 - };
+1 -2
Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.yaml
··· 7 7 title: STMicroelectronics STM32 Hardware Spinlock bindings 8 8 9 9 maintainers: 10 - - Benjamin Gaignard <benjamin.gaignard@st.com> 11 - - Fabien Dessenne <fabien.dessenne@st.com> 10 + - Fabien Dessenne <fabien.dessenne@foss.st.com> 12 11 13 12 properties: 14 13 "#hwlock-cells":
+3 -1
Documentation/devicetree/bindings/i2c/i2c-imx.yaml
··· 57 57 const: ipg 58 58 59 59 clock-frequency: 60 - enum: [ 100000, 400000 ] 60 + minimum: 1 61 + default: 100000 62 + maximum: 400000 61 63 62 64 dmas: 63 65 items:
-22
Documentation/devicetree/bindings/i2c/i2c-xlp9xx.txt
··· 1 - Device tree configuration for the I2C controller on the XLP9xx/5xx SoC 2 - 3 - Required properties: 4 - - compatible : should be "netlogic,xlp980-i2c" 5 - - reg : bus address start and address range size of device 6 - - interrupts : interrupt number 7 - 8 - Optional properties: 9 - - clock-frequency : frequency of bus clock in Hz 10 - Defaults to 100 KHz when the property is not specified 11 - 12 - Example: 13 - 14 - i2c0: i2c@113100 { 15 - compatible = "netlogic,xlp980-i2c"; 16 - #address-cells = <1>; 17 - #size-cells = <0>; 18 - reg = <0 0x113100 0x100>; 19 - clock-frequency = <400000>; 20 - interrupts = <30>; 21 - interrupt-parent = <&pic>; 22 - };
+1 -1
Documentation/devicetree/bindings/i2c/ingenic,i2c.yaml
··· 60 60 61 61 examples: 62 62 - | 63 - #include <dt-bindings/clock/jz4780-cgu.h> 63 + #include <dt-bindings/clock/ingenic,jz4780-cgu.h> 64 64 #include <dt-bindings/dma/jz4780-dma.h> 65 65 #include <dt-bindings/interrupt-controller/irq.h> 66 66 i2c@10054000 {
+1 -1
Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
··· 7 7 title: I2C controller embedded in STMicroelectronics STM32 I2C platform 8 8 9 9 maintainers: 10 - - Pierre-Yves MORDRET <pierre-yves.mordret@st.com> 10 + - Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com> 11 11 12 12 allOf: 13 13 - $ref: /schemas/i2c/i2c-controller.yaml#
+1 -1
Documentation/devicetree/bindings/iio/adc/ingenic,adc.yaml
··· 74 74 75 75 examples: 76 76 - | 77 - #include <dt-bindings/clock/jz4740-cgu.h> 77 + #include <dt-bindings/clock/ingenic,jz4740-cgu.h> 78 78 #include <dt-bindings/iio/adc/ingenic,adc.h> 79 79 80 80 adc@10070000 {
+1 -1
Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.yaml
··· 7 7 title: Device-Tree bindings for sigma delta modulator 8 8 9 9 maintainers: 10 - - Arnaud Pouliquen <arnaud.pouliquen@st.com> 10 + - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> 11 11 12 12 properties: 13 13 compatible:
+1 -1
Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
··· 19 19 Each STM32 ADC block can have up to 3 ADC instances. 20 20 21 21 maintainers: 22 - - Fabrice Gasnier <fabrice.gasnier@st.com> 22 + - Fabrice Gasnier <fabrice.gasnier@foss.st.com> 23 23 24 24 properties: 25 25 compatible:
+2 -2
Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
··· 7 7 title: STMicroelectronics STM32 DFSDM ADC device driver 8 8 9 9 maintainers: 10 - - Fabrice Gasnier <fabrice.gasnier@st.com> 11 - - Olivier Moysan <olivier.moysan@st.com> 10 + - Fabrice Gasnier <fabrice.gasnier@foss.st.com> 11 + - Olivier Moysan <olivier.moysan@foss.st.com> 12 12 13 13 description: | 14 14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
+1 -1
Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
··· 15 15 current. 16 16 17 17 maintainers: 18 - - Fabrice Gasnier <fabrice.gasnier@st.com> 18 + - Fabrice Gasnier <fabrice.gasnier@foss.st.com> 19 19 20 20 properties: 21 21 compatible:
+2 -2
Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml
··· 7 7 title: STM32 External Interrupt Controller Device Tree Bindings 8 8 9 9 maintainers: 10 - - Alexandre Torgue <alexandre.torgue@st.com> 11 - - Ludovic Barre <ludovic.barre@st.com> 10 + - Alexandre Torgue <alexandre.torgue@foss.st.com> 11 + - Ludovic Barre <ludovic.barre@foss.st.com> 12 12 13 13 properties: 14 14 compatible:
+2 -2
Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml
··· 13 13 channels (N) can be read from a dedicated register. 14 14 15 15 maintainers: 16 - - Fabien Dessenne <fabien.dessenne@st.com> 17 - - Arnaud Pouliquen <arnaud.pouliquen@st.com> 16 + - Fabien Dessenne <fabien.dessenne@foss.st.com> 17 + - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> 18 18 19 19 properties: 20 20 compatible:
-1
Documentation/devicetree/bindings/media/qcom,sc7280-venus.yaml
··· 30 30 31 31 power-domain-names: 32 32 minItems: 2 33 - maxItems: 3 34 33 items: 35 34 - const: venus 36 35 - const: vcodec0
+1 -2
Documentation/devicetree/bindings/media/st,stm32-cec.yaml
··· 7 7 title: STMicroelectronics STM32 CEC bindings 8 8 9 9 maintainers: 10 - - Benjamin Gaignard <benjamin.gaignard@st.com> 11 - - Yannick Fertre <yannick.fertre@st.com> 10 + - Yannick Fertre <yannick.fertre@foss.st.com> 12 11 13 12 properties: 14 13 compatible:
+1 -1
Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
··· 7 7 title: STMicroelectronics STM32 Digital Camera Memory Interface (DCMI) binding 8 8 9 9 maintainers: 10 - - Hugues Fruchet <hugues.fruchet@st.com> 10 + - Hugues Fruchet <hugues.fruchet@foss.st.com> 11 11 12 12 properties: 13 13 compatible:
+1 -1
Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml
··· 84 84 85 85 examples: 86 86 - | 87 - #include <dt-bindings/clock/jz4780-cgu.h> 87 + #include <dt-bindings/clock/ingenic,jz4780-cgu.h> 88 88 #include <dt-bindings/gpio/gpio.h> 89 89 nemc: memory-controller@13410000 { 90 90 compatible = "ingenic,jz4780-nemc";
+1 -1
Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
··· 19 19 Select. The FMC2 performs only one access at a time to an external device. 20 20 21 21 maintainers: 22 - - Christophe Kerello <christophe.kerello@st.com> 22 + - Christophe Kerello <christophe.kerello@foss.st.com> 23 23 24 24 properties: 25 25 compatible:
+1 -1
Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
··· 17 17 - simple counter from IN1 input signal. 18 18 19 19 maintainers: 20 - - Fabrice Gasnier <fabrice.gasnier@st.com> 20 + - Fabrice Gasnier <fabrice.gasnier@foss.st.com> 21 21 22 22 properties: 23 23 compatible:
+1 -2
Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
··· 17 17 programmable prescaler. 18 18 19 19 maintainers: 20 - - Benjamin Gaignard <benjamin.gaignard@st.com> 21 - - Fabrice Gasnier <fabrice.gasnier@st.com> 20 + - Fabrice Gasnier <fabrice.gasnier@foss.st.com> 22 21 23 22 properties: 24 23 compatible:
+1 -1
Documentation/devicetree/bindings/mfd/st,stmfx.yaml
··· 12 12 through VDD) and resistive touchscreen controller. 13 13 14 14 maintainers: 15 - - Amelie Delaunay <amelie.delaunay@st.com> 15 + - Amelie Delaunay <amelie.delaunay@foss.st.com> 16 16 17 17 properties: 18 18 compatible:
+1 -1
Documentation/devicetree/bindings/mfd/st,stpmic1.yaml
··· 9 9 description: STMicroelectronics STPMIC1 Power Management IC 10 10 11 11 maintainers: 12 - - pascal Paillet <p.paillet@st.com> 12 + - pascal Paillet <p.paillet@foss.st.com> 13 13 14 14 properties: 15 15 compatible:
+1 -1
Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
··· 44 44 45 45 examples: 46 46 - | 47 - #include <dt-bindings/clock/jz4780-cgu.h> 47 + #include <dt-bindings/clock/ingenic,jz4780-cgu.h> 48 48 49 49 cpus { 50 50 #address-cells = <1>;
+1 -1
Documentation/devicetree/bindings/mmc/ingenic,mmc.yaml
··· 61 61 62 62 examples: 63 63 - | 64 - #include <dt-bindings/clock/jz4780-cgu.h> 64 + #include <dt-bindings/clock/ingenic,jz4780-cgu.h> 65 65 #include <dt-bindings/dma/jz4780-dma.h> 66 66 mmc0: mmc@13450000 { 67 67 compatible = "ingenic,jz4780-mmc";
+1 -1
Documentation/devicetree/bindings/mtd/ingenic,nand.yaml
··· 55 55 56 56 examples: 57 57 - | 58 - #include <dt-bindings/clock/jz4780-cgu.h> 58 + #include <dt-bindings/clock/ingenic,jz4780-cgu.h> 59 59 memory-controller@13410000 { 60 60 compatible = "ingenic,jz4780-nemc"; 61 61 reg = <0x13410000 0x10000>;
+1 -1
Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml
··· 7 7 title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings 8 8 9 9 maintainers: 10 - - Christophe Kerello <christophe.kerello@st.com> 10 + - Christophe Kerello <christophe.kerello@foss.st.com> 11 11 12 12 properties: 13 13 compatible:
+1 -1
Documentation/devicetree/bindings/net/ingenic,mac.yaml
··· 58 58 59 59 examples: 60 60 - | 61 - #include <dt-bindings/clock/x1000-cgu.h> 61 + #include <dt-bindings/clock/ingenic,x1000-cgu.h> 62 62 63 63 mac: ethernet@134b0000 { 64 64 compatible = "ingenic,x1000-mac";
+1 -1
Documentation/devicetree/bindings/net/snps,dwmac.yaml
··· 7 7 title: Synopsys DesignWare MAC Device Tree Bindings 8 8 9 9 maintainers: 10 - - Alexandre Torgue <alexandre.torgue@st.com> 10 + - Alexandre Torgue <alexandre.torgue@foss.st.com> 11 11 - Giuseppe Cavallaro <peppe.cavallaro@st.com> 12 12 - Jose Abreu <joabreu@synopsys.com> 13 13
+2 -2
Documentation/devicetree/bindings/net/stm32-dwmac.yaml
··· 8 8 title: STMicroelectronics STM32 / MCU DWMAC glue layer controller 9 9 10 10 maintainers: 11 - - Alexandre Torgue <alexandre.torgue@st.com> 12 - - Christophe Roullier <christophe.roullier@st.com> 11 + - Alexandre Torgue <alexandre.torgue@foss.st.com> 12 + - Christophe Roullier <christophe.roullier@foss.st.com> 13 13 14 14 description: 15 15 This file documents platform glue layer for stmmac.
+1 -1
Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
··· 33 33 34 34 examples: 35 35 - | 36 - #include <dt-bindings/clock/jz4780-cgu.h> 36 + #include <dt-bindings/clock/ingenic,jz4780-cgu.h> 37 37 38 38 efuse@134100d0 { 39 39 compatible = "ingenic,jz4780-efuse";
+1 -1
Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml
··· 13 13 internal vref (VREFIN_CAL), unique device ID... 14 14 15 15 maintainers: 16 - - Fabrice Gasnier <fabrice.gasnier@st.com> 16 + - Fabrice Gasnier <fabrice.gasnier@foss.st.com> 17 17 18 18 allOf: 19 19 - $ref: "nvmem.yaml#"
+1 -1
Documentation/devicetree/bindings/phy/ingenic,phy-usb.yaml
··· 46 46 47 47 examples: 48 48 - | 49 - #include <dt-bindings/clock/jz4770-cgu.h> 49 + #include <dt-bindings/clock/ingenic,jz4770-cgu.h> 50 50 otg_phy: usb-phy@3c { 51 51 compatible = "ingenic,jz4770-phy"; 52 52 reg = <0x3c 0x10>;
+1 -1
Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
··· 24 24 |_ UTMI switch_______| OTG controller 25 25 26 26 maintainers: 27 - - Amelie Delaunay <amelie.delaunay@st.com> 27 + - Amelie Delaunay <amelie.delaunay@foss.st.com> 28 28 29 29 properties: 30 30 compatible:
+1 -1
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
··· 8 8 title: STM32 GPIO and Pin Mux/Config controller 9 9 10 10 maintainers: 11 - - Alexandre TORGUE <alexandre.torgue@st.com> 11 + - Alexandre TORGUE <alexandre.torgue@foss.st.com> 12 12 13 13 description: | 14 14 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
+1 -1
Documentation/devicetree/bindings/regulator/st,stm32-booster.yaml
··· 7 7 title: STMicroelectronics STM32 booster for ADC analog input switches bindings 8 8 9 9 maintainers: 10 - - Fabrice Gasnier <fabrice.gasnier@st.com> 10 + - Fabrice Gasnier <fabrice.gasnier@foss.st.com> 11 11 12 12 description: | 13 13 Some STM32 devices embed a 3.3V booster supplied by Vdda, that can be used
+1 -1
Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
··· 12 12 components through the dedicated VREF+ pin. 13 13 14 14 maintainers: 15 - - Fabrice Gasnier <fabrice.gasnier@st.com> 15 + - Fabrice Gasnier <fabrice.gasnier@foss.st.com> 16 16 17 17 allOf: 18 18 - $ref: "regulator.yaml#"
+1 -1
Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.yaml
··· 7 7 title: STM32MP1 PWR voltage regulators 8 8 9 9 maintainers: 10 - - Pascal Paillet <p.paillet@st.com> 10 + - Pascal Paillet <p.paillet@foss.st.com> 11 11 12 12 properties: 13 13 compatible:
+1 -1
Documentation/devicetree/bindings/remoteproc/ingenic,vpu.yaml
··· 58 58 59 59 examples: 60 60 - | 61 - #include <dt-bindings/clock/jz4770-cgu.h> 61 + #include <dt-bindings/clock/ingenic,jz4770-cgu.h> 62 62 63 63 vpu: video-decoder@132a0000 { 64 64 compatible = "ingenic,jz4770-vpu-rproc";
+2 -2
Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml
··· 11 11 boots firmwares on the ST32MP family chipset. 12 12 13 13 maintainers: 14 - - Fabien Dessenne <fabien.dessenne@st.com> 15 - - Arnaud Pouliquen <arnaud.pouliquen@st.com> 14 + - Fabien Dessenne <fabien.dessenne@foss.st.com> 15 + - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> 16 16 17 17 properties: 18 18 compatible:
+1 -1
Documentation/devicetree/bindings/rng/ingenic,trng.yaml
··· 32 32 33 33 examples: 34 34 - | 35 - #include <dt-bindings/clock/x1830-cgu.h> 35 + #include <dt-bindings/clock/ingenic,x1830-cgu.h> 36 36 37 37 dtrng: trng@10072000 { 38 38 compatible = "ingenic,x1830-dtrng";
+1 -1
Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
··· 11 11 IP and is fully separated from other crypto functions. 12 12 13 13 maintainers: 14 - - Lionel Debieve <lionel.debieve@st.com> 14 + - Lionel Debieve <lionel.debieve@foss.st.com> 15 15 16 16 properties: 17 17 compatible:
+1 -1
Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml
··· 72 72 73 73 examples: 74 74 - | 75 - #include <dt-bindings/clock/jz4740-cgu.h> 75 + #include <dt-bindings/clock/ingenic,jz4740-cgu.h> 76 76 rtc_dev: rtc@10003000 { 77 77 compatible = "ingenic,jz4740-rtc"; 78 78 reg = <0x10003000 0x40>;
+1 -1
Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml
··· 7 7 title: STMicroelectronics STM32 Real Time Clock Bindings 8 8 9 9 maintainers: 10 - - Gabriel Fernandez <gabriel.fernandez@st.com> 10 + - Gabriel Fernandez <gabriel.fernandez@foss.st.com> 11 11 12 12 properties: 13 13 compatible:
+1 -1
Documentation/devicetree/bindings/serial/ingenic,uart.yaml
··· 71 71 72 72 examples: 73 73 - | 74 - #include <dt-bindings/clock/jz4780-cgu.h> 74 + #include <dt-bindings/clock/ingenic,jz4780-cgu.h> 75 75 #include <dt-bindings/dma/jz4780-dma.h> 76 76 #include <dt-bindings/gpio/gpio.h> 77 77 serial@10032000 {
+1 -1
Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
··· 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 maintainers: 8 - - Erwan Le Ray <erwan.leray@st.com> 8 + - Erwan Le Ray <erwan.leray@foss.st.com> 9 9 10 10 title: STMicroelectronics STM32 USART bindings 11 11
+1 -1
Documentation/devicetree/bindings/sound/cirrus,cs42l51.yaml
··· 7 7 title: CS42L51 audio codec DT bindings 8 8 9 9 maintainers: 10 - - Olivier Moysan <olivier.moysan@st.com> 10 + - Olivier Moysan <olivier.moysan@foss.st.com> 11 11 12 12 properties: 13 13 compatible:
+1 -1
Documentation/devicetree/bindings/sound/ingenic,aic.yaml
··· 71 71 72 72 examples: 73 73 - | 74 - #include <dt-bindings/clock/jz4740-cgu.h> 74 + #include <dt-bindings/clock/ingenic,jz4740-cgu.h> 75 75 aic: audio-controller@10020000 { 76 76 compatible = "ingenic,jz4740-i2s"; 77 77 reg = <0x10020000 0x38>;
+1 -1
Documentation/devicetree/bindings/sound/ingenic,codec.yaml
··· 48 48 49 49 examples: 50 50 - | 51 - #include <dt-bindings/clock/jz4740-cgu.h> 51 + #include <dt-bindings/clock/ingenic,jz4740-cgu.h> 52 52 codec: audio-codec@10020080 { 53 53 compatible = "ingenic,jz4740-codec"; 54 54 reg = <0x10020080 0x8>;
+1 -1
Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml
··· 7 7 title: STMicroelectronics STM32 SPI/I2S Controller 8 8 9 9 maintainers: 10 - - Olivier Moysan <olivier.moysan@st.com> 10 + - Olivier Moysan <olivier.moysan@foss.st.com> 11 11 12 12 description: 13 13 The SPI/I2S block supports I2S/PCM protocols when configured on I2S mode.
+1 -1
Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
··· 7 7 title: STMicroelectronics STM32 Serial Audio Interface (SAI) 8 8 9 9 maintainers: 10 - - Olivier Moysan <olivier.moysan@st.com> 10 + - Olivier Moysan <olivier.moysan@foss.st.com> 11 11 12 12 description: 13 13 The SAI interface (Serial Audio Interface) offers a wide set of audio
+1 -1
Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml
··· 7 7 title: STMicroelectronics STM32 S/PDIF receiver (SPDIFRX) 8 8 9 9 maintainers: 10 - - Olivier Moysan <olivier.moysan@st.com> 10 + - Olivier Moysan <olivier.moysan@foss.st.com> 11 11 12 12 description: | 13 13 The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with
+1 -1
Documentation/devicetree/bindings/spi/ingenic,spi.yaml
··· 55 55 56 56 examples: 57 57 - | 58 - #include <dt-bindings/clock/jz4770-cgu.h> 58 + #include <dt-bindings/clock/ingenic,jz4770-cgu.h> 59 59 spi@10043000 { 60 60 compatible = "ingenic,jz4770-spi", "ingenic,jz4750-spi"; 61 61 reg = <0x10043000 0x1c>;
-38
Documentation/devicetree/bindings/spi/spi-xlp.txt
··· 1 - SPI Master controller for Netlogic XLP MIPS64 SOCs 2 - ================================================== 3 - 4 - Currently this SPI controller driver is supported for the following 5 - Netlogic XLP SoCs: 6 - XLP832, XLP316, XLP208, XLP980, XLP532 7 - 8 - Required properties: 9 - - compatible : Should be "netlogic,xlp832-spi". 10 - - #address-cells : Number of cells required to define a chip select address 11 - on the SPI bus. 12 - - #size-cells : Should be zero. 13 - - reg : Should contain register location and length. 14 - - clocks : Phandle of the spi clock 15 - - interrupts : Interrupt number used by this controller. 16 - 17 - SPI slave nodes must be children of the SPI master node and can contain 18 - properties described in Documentation/devicetree/bindings/spi/spi-bus.txt. 19 - 20 - Example: 21 - 22 - spi: xlp_spi@3a100 { 23 - compatible = "netlogic,xlp832-spi"; 24 - #address-cells = <1>; 25 - #size-cells = <0>; 26 - reg = <0 0x3a100 0x100>; 27 - clocks = <&spi_clk>; 28 - interrupts = <34>; 29 - interrupt-parent = <&pic>; 30 - 31 - spi_nor@1 { 32 - compatible = "spansion,s25sl12801"; 33 - #address-cells = <1>; 34 - #size-cells = <1>; 35 - reg = <1>; /* Chip Select */ 36 - spi-max-frequency = <40000000>; 37 - }; 38 - };
+2 -2
Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
··· 7 7 title: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI) bindings 8 8 9 9 maintainers: 10 - - Christophe Kerello <christophe.kerello@st.com> 11 - - Patrice Chotard <patrice.chotard@st.com> 10 + - Christophe Kerello <christophe.kerello@foss.st.com> 11 + - Patrice Chotard <patrice.chotard@foss.st.com> 12 12 13 13 allOf: 14 14 - $ref: "spi-controller.yaml#"
+2 -2
Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
··· 13 13 from 4 to 32-bit data size. 14 14 15 15 maintainers: 16 - - Erwan Leray <erwan.leray@st.com> 17 - - Fabrice Gasnier <fabrice.gasnier@st.com> 16 + - Erwan Leray <erwan.leray@foss.st.com> 17 + - Fabrice Gasnier <fabrice.gasnier@foss.st.com> 18 18 19 19 allOf: 20 20 - $ref: "spi-controller.yaml#"
+1 -1
Documentation/devicetree/bindings/thermal/st,stm32-thermal.yaml
··· 7 7 title: STMicroelectronics STM32 digital thermal sensor (DTS) binding 8 8 9 9 maintainers: 10 - - David Hernandez Sanchez <david.hernandezsanchez@st.com> 10 + - Pascal Paillet <p.paillet@foss.st.com> 11 11 12 12 properties: 13 13 compatible:
+1 -1
Documentation/devicetree/bindings/timer/ingenic,sysost.yaml
··· 46 46 47 47 examples: 48 48 - | 49 - #include <dt-bindings/clock/x1000-cgu.h> 49 + #include <dt-bindings/clock/ingenic,x1000-cgu.h> 50 50 51 51 ost: timer@12000000 { 52 52 compatible = "ingenic,x1000-ost";
+1 -1
Documentation/devicetree/bindings/timer/ingenic,tcu.yaml
··· 237 237 238 238 examples: 239 239 - | 240 - #include <dt-bindings/clock/jz4770-cgu.h> 240 + #include <dt-bindings/clock/ingenic,jz4770-cgu.h> 241 241 #include <dt-bindings/clock/ingenic,tcu.h> 242 242 tcu: timer@10002000 { 243 243 compatible = "ingenic,jz4770-tcu", "ingenic,jz4760-tcu", "simple-mfd";
+2 -1
Documentation/devicetree/bindings/timer/st,stm32-timer.yaml
··· 7 7 title: STMicroelectronics STM32 general-purpose 16 and 32 bits timers bindings 8 8 9 9 maintainers: 10 - - Benjamin Gaignard <benjamin.gaignard@st.com> 10 + - Fabrice Gasnier <fabrice.gasnier@foss.st.com> 11 + - Patrice Chotard <patrice.chotard@foss.st.com> 11 12 12 13 properties: 13 14 compatible:
+1 -1
Documentation/devicetree/bindings/usb/ingenic,musb.yaml
··· 58 58 59 59 examples: 60 60 - | 61 - #include <dt-bindings/clock/jz4740-cgu.h> 61 + #include <dt-bindings/clock/ingenic,jz4740-cgu.h> 62 62 usb_phy: usb-phy { 63 63 compatible = "usb-nop-xceiv"; 64 64 #phy-cells = <0>;
+1 -1
Documentation/devicetree/bindings/usb/st,stusb160x.yaml
··· 7 7 title: STMicroelectronics STUSB160x Type-C controller bindings 8 8 9 9 maintainers: 10 - - Amelie Delaunay <amelie.delaunay@st.com> 10 + - Amelie Delaunay <amelie.delaunay@foss.st.com> 11 11 12 12 properties: 13 13 compatible:
-2
Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
··· 40 40 41 41 clocks: 42 42 minItems: 1 43 - maxItems: 2 44 43 items: 45 44 - description: High-frequency oscillator input, divided internally 46 45 - description: Low-frequency oscillator input, only found on some variants 47 46 48 47 clock-names: 49 48 minItems: 1 50 - maxItems: 2 51 49 items: 52 50 - const: hosc 53 51 - const: losc
+2 -2
Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml
··· 7 7 title: STMicroelectronics STM32 Independent WatchDoG (IWDG) bindings 8 8 9 9 maintainers: 10 - - Yannick Fertre <yannick.fertre@st.com> 11 - - Christophe Roullier <christophe.roullier@st.com> 10 + - Yannick Fertre <yannick.fertre@foss.st.com> 11 + - Christophe Roullier <christophe.roullier@foss.st.com> 12 12 13 13 allOf: 14 14 - $ref: "watchdog.yaml#"
+1 -1
arch/mips/boot/dts/ingenic/jz4725b.dtsi
··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 - #include <dt-bindings/clock/jz4725b-cgu.h> 2 + #include <dt-bindings/clock/ingenic,jz4725b-cgu.h> 3 3 #include <dt-bindings/clock/ingenic,tcu.h> 4 4 5 5 / {
+1 -1
arch/mips/boot/dts/ingenic/jz4740.dtsi
··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 - #include <dt-bindings/clock/jz4740-cgu.h> 2 + #include <dt-bindings/clock/ingenic,jz4740-cgu.h> 3 3 #include <dt-bindings/clock/ingenic,tcu.h> 4 4 5 5 / {
+1 -1
arch/mips/boot/dts/ingenic/jz4770.dtsi
··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 - #include <dt-bindings/clock/jz4770-cgu.h> 2 + #include <dt-bindings/clock/ingenic,jz4770-cgu.h> 3 3 #include <dt-bindings/clock/ingenic,tcu.h> 4 4 5 5 / {
+1 -1
arch/mips/boot/dts/ingenic/jz4780.dtsi
··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 - #include <dt-bindings/clock/jz4780-cgu.h> 2 + #include <dt-bindings/clock/ingenic,jz4780-cgu.h> 3 3 #include <dt-bindings/clock/ingenic,tcu.h> 4 4 #include <dt-bindings/dma/jz4780-dma.h> 5 5
+1 -1
arch/mips/boot/dts/ingenic/x1000.dtsi
··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 #include <dt-bindings/clock/ingenic,tcu.h> 3 - #include <dt-bindings/clock/x1000-cgu.h> 3 + #include <dt-bindings/clock/ingenic,x1000-cgu.h> 4 4 #include <dt-bindings/dma/x1000-dma.h> 5 5 6 6 / {
+1 -1
arch/mips/boot/dts/ingenic/x1830.dtsi
··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 #include <dt-bindings/clock/ingenic,tcu.h> 3 - #include <dt-bindings/clock/x1830-cgu.h> 3 + #include <dt-bindings/clock/ingenic,x1830-cgu.h> 4 4 #include <dt-bindings/dma/x1830-dma.h> 5 5 6 6 / {
+1 -1
drivers/clk/ingenic/jz4725b-cgu.c
··· 10 10 #include <linux/delay.h> 11 11 #include <linux/of.h> 12 12 13 - #include <dt-bindings/clock/jz4725b-cgu.h> 13 + #include <dt-bindings/clock/ingenic,jz4725b-cgu.h> 14 14 15 15 #include "cgu.h" 16 16 #include "pm.h"
+1 -1
drivers/clk/ingenic/jz4740-cgu.c
··· 11 11 #include <linux/io.h> 12 12 #include <linux/of.h> 13 13 14 - #include <dt-bindings/clock/jz4740-cgu.h> 14 + #include <dt-bindings/clock/ingenic,jz4740-cgu.h> 15 15 16 16 #include "cgu.h" 17 17 #include "pm.h"
+1 -1
drivers/clk/ingenic/jz4760-cgu.c
··· 12 12 13 13 #include <linux/clk.h> 14 14 15 - #include <dt-bindings/clock/jz4760-cgu.h> 15 + #include <dt-bindings/clock/ingenic,jz4760-cgu.h> 16 16 17 17 #include "cgu.h" 18 18 #include "pm.h"
+1 -1
drivers/clk/ingenic/jz4770-cgu.c
··· 10 10 #include <linux/io.h> 11 11 #include <linux/of.h> 12 12 13 - #include <dt-bindings/clock/jz4770-cgu.h> 13 + #include <dt-bindings/clock/ingenic,jz4770-cgu.h> 14 14 15 15 #include "cgu.h" 16 16 #include "pm.h"
+1 -1
drivers/clk/ingenic/jz4780-cgu.c
··· 13 13 #include <linux/iopoll.h> 14 14 #include <linux/of.h> 15 15 16 - #include <dt-bindings/clock/jz4780-cgu.h> 16 + #include <dt-bindings/clock/ingenic,jz4780-cgu.h> 17 17 18 18 #include "cgu.h" 19 19 #include "pm.h"
+1 -1
drivers/clk/ingenic/x1000-cgu.c
··· 9 9 #include <linux/io.h> 10 10 #include <linux/of.h> 11 11 12 - #include <dt-bindings/clock/x1000-cgu.h> 12 + #include <dt-bindings/clock/ingenic,x1000-cgu.h> 13 13 14 14 #include "cgu.h" 15 15 #include "pm.h"
+1 -1
drivers/clk/ingenic/x1830-cgu.c
··· 9 9 #include <linux/io.h> 10 10 #include <linux/of.h> 11 11 12 - #include <dt-bindings/clock/x1830-cgu.h> 12 + #include <dt-bindings/clock/ingenic,x1830-cgu.h> 13 13 14 14 #include "cgu.h" 15 15 #include "pm.h"
+4 -2
drivers/clk/versatile/clk-icst.c
··· 484 484 struct device_node *parent; 485 485 struct regmap *map; 486 486 struct clk_icst_desc icst_desc; 487 - const char *name = np->name; 487 + const char *name; 488 488 const char *parent_name; 489 489 struct clk *regclk; 490 490 enum icst_control_type ctype; ··· 533 533 icst_desc.params = &icst525_apcp_cm_params; 534 534 ctype = ICST_INTEGRATOR_CP_CM_MEM; 535 535 } else { 536 - pr_err("unknown ICST clock %s\n", name); 536 + pr_err("unknown ICST clock %pOF\n", np); 537 537 return; 538 538 } 539 539 540 540 /* Parent clock name is not the same as node parent */ 541 541 parent_name = of_clk_get_parent_name(np, 0); 542 + name = kasprintf(GFP_KERNEL, "%pOFP", np); 542 543 543 544 regclk = icst_clk_setup(NULL, &icst_desc, name, parent_name, map, ctype); 544 545 if (IS_ERR(regclk)) { 546 + kfree(name); 545 547 pr_err("error setting up syscon ICST clock %s\n", name); 546 548 return; 547 549 }
+8 -2
drivers/of/platform.c
··· 76 76 struct device_node *node = dev->of_node; 77 77 const __be32 *reg; 78 78 u64 addr; 79 + u32 mask; 79 80 80 81 /* Construct the name, using parent nodes if necessary to ensure uniqueness */ 81 82 while (node->parent) { ··· 86 85 */ 87 86 reg = of_get_property(node, "reg", NULL); 88 87 if (reg && (addr = of_translate_address(node, reg)) != OF_BAD_ADDR) { 89 - dev_set_name(dev, dev_name(dev) ? "%llx.%pOFn:%s" : "%llx.%pOFn", 90 - addr, node, dev_name(dev)); 88 + if (!of_property_read_u32(node, "mask", &mask)) 89 + dev_set_name(dev, dev_name(dev) ? "%llx.%x.%pOFn:%s" : "%llx.%x.%pOFn", 90 + addr, ffs(mask) - 1, node, dev_name(dev)); 91 + 92 + else 93 + dev_set_name(dev, dev_name(dev) ? "%llx.%pOFn:%s" : "%llx.%pOFn", 94 + addr, node, dev_name(dev)); 91 95 return; 92 96 } 93 97
include/dt-bindings/clock/jz4725b-cgu.h include/dt-bindings/clock/ingenic,jz4725b-cgu.h
include/dt-bindings/clock/jz4740-cgu.h include/dt-bindings/clock/ingenic,jz4740-cgu.h
include/dt-bindings/clock/jz4760-cgu.h include/dt-bindings/clock/ingenic,jz4760-cgu.h
include/dt-bindings/clock/jz4770-cgu.h include/dt-bindings/clock/ingenic,jz4770-cgu.h
include/dt-bindings/clock/jz4780-cgu.h include/dt-bindings/clock/ingenic,jz4780-cgu.h
include/dt-bindings/clock/x1000-cgu.h include/dt-bindings/clock/ingenic,x1000-cgu.h
include/dt-bindings/clock/x1830-cgu.h include/dt-bindings/clock/ingenic,x1830-cgu.h