+1

Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml

reviewed

··· 33 33 - enum: 34 34 - mediatek,mt2712-disp-aal 35 35 - mediatek,mt6795-disp-aal 36 36 + - mediatek,mt8167-disp-aal 36 37 - const: mediatek,mt8173-disp-aal 37 38 - items: 38 39 - enum:

+3 -1

Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml

reviewed

··· 25 25 - mediatek,mt8183-disp-ccorr 26 26 - mediatek,mt8192-disp-ccorr 27 27 - items: 28 28 - - const: mediatek,mt8365-disp-ccorr 28 28 + - enum: 29 29 + - mediatek,mt8167-disp-ccorr 30 30 + - mediatek,mt8365-disp-ccorr 29 31 - const: mediatek,mt8183-disp-ccorr 30 32 - items: 31 33 - enum:

+1

Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml

reviewed

··· 26 26 - mediatek,mt8183-disp-dither 27 27 - items: 28 28 - enum: 29 29 + - mediatek,mt8167-disp-dither 29 30 - mediatek,mt8186-disp-dither 30 31 - mediatek,mt8188-disp-dither 31 32 - mediatek,mt8192-disp-dither

+1

Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml

reviewed

··· 28 28 - items: 29 29 - enum: 30 30 - mediatek,mt6795-disp-gamma 31 31 + - mediatek,mt8167-disp-gamma 31 32 - const: mediatek,mt8173-disp-gamma 32 33 - items: 33 34 - enum:

+1

Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml

reviewed

··· 23 23 oneOf: 24 24 - enum: 25 25 - mediatek,mt2701-disp-ovl 26 26 + - mediatek,mt8167-disp-ovl 26 27 - mediatek,mt8173-disp-ovl 27 28 - mediatek,mt8183-disp-ovl 28 29 - mediatek,mt8192-disp-ovl

+1

Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml

reviewed

··· 36 36 - enum: 37 37 - mediatek,mt7623-disp-rdma 38 38 - mediatek,mt2712-disp-rdma 39 39 + - mediatek,mt8167-disp-rdma 39 40 - const: mediatek,mt2701-disp-rdma 40 41 - items: 41 42 - enum:

+3 -1

Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml

reviewed

··· 24 24 - enum: 25 25 - mediatek,mt8173-disp-wdma 26 26 - items: 27 27 - - const: mediatek,mt6795-disp-wdma 27 27 + - enum: 28 28 + - mediatek,mt6795-disp-wdma 29 29 + - mediatek,mt8167-disp-wdma 28 30 - const: mediatek,mt8173-disp-wdma 29 31 30 32 reg:

+1

Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml

reviewed

··· 23 23 - items: 24 24 - enum: 25 25 - mediatek,mt7623-mipi-tx 26 26 + - mediatek,mt8167-mipi-tx 26 27 - const: mediatek,mt2701-mipi-tx 27 28 - items: 28 29 - enum:

+12

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

reviewed

··· 671 671 .num_formats = ARRAY_SIZE(mt8173_formats), 672 672 }; 673 673 674 674 + static const struct mtk_disp_ovl_data mt8167_ovl_driver_data = { 675 675 + .addr = DISP_REG_OVL_ADDR_MT8173, 676 676 + .gmc_bits = 8, 677 677 + .layer_nr = 4, 678 678 + .fmt_rgb565_is_0 = true, 679 679 + .smi_id_en = true, 680 680 + .formats = mt8173_formats, 681 681 + .num_formats = ARRAY_SIZE(mt8173_formats), 682 682 + }; 683 683 + 674 684 static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { 675 685 .addr = DISP_REG_OVL_ADDR_MT8173, 676 686 .gmc_bits = 8, ··· 752 742 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { 753 743 { .compatible = "mediatek,mt2701-disp-ovl", 754 744 .data = &mt2701_ovl_driver_data}, 745 745 + { .compatible = "mediatek,mt8167-disp-ovl", 746 746 + .data = &mt8167_ovl_driver_data}, 755 747 { .compatible = "mediatek,mt8173-disp-ovl", 756 748 .data = &mt8173_ovl_driver_data}, 757 749 { .compatible = "mediatek,mt8183-disp-ovl",

+5

drivers/gpu/drm/mediatek/mtk_drm_drv.c

reviewed

··· 4 4 * Author: YT SHEN <yt.shen@mediatek.com> 5 5 */ 6 6 7 7 + #include <linux/aperture.h> 7 8 #include <linux/component.h> 8 9 #include <linux/module.h> 9 10 #include <linux/of.h> ··· 655 654 ret = mtk_drm_kms_init(drm); 656 655 if (ret < 0) 657 656 goto err_free; 657 657 + 658 658 + ret = aperture_remove_all_conflicting_devices(DRIVER_NAME); 659 659 + if (ret < 0) 660 660 + dev_err(dev, "Error %d while removing conflicting aperture devices", ret); 658 661 659 662 ret = drm_dev_register(drm, 0); 660 663 if (ret < 0)

+17 -18

drivers/gpu/drm/mediatek/mtk_dsi.c

reviewed

··· 673 673 } 674 674 } 675 675 676 676 + static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) 677 677 + { 678 678 + if (!dsi->lanes_ready) { 679 679 + dsi->lanes_ready = true; 680 680 + mtk_dsi_rxtx_control(dsi); 681 681 + usleep_range(30, 100); 682 682 + mtk_dsi_reset_dphy(dsi); 683 683 + mtk_dsi_clk_ulp_mode_leave(dsi); 684 684 + mtk_dsi_lane0_ulp_mode_leave(dsi); 685 685 + mtk_dsi_clk_hs_mode(dsi, 0); 686 686 + usleep_range(1000, 3000); 687 687 + /* The reaction time after pulling up the mipi signal for dsi_rx */ 688 688 + } 689 689 + } 690 690 + 676 691 static int mtk_dsi_poweron(struct mtk_dsi *dsi) 677 692 { 678 693 struct device *dev = dsi->host.dev; ··· 740 725 mtk_dsi_set_vm_cmd(dsi); 741 726 mtk_dsi_config_vdo_timing(dsi); 742 727 mtk_dsi_set_interrupt_enable(dsi); 728 728 + mtk_dsi_lane_ready(dsi); 729 729 + mtk_dsi_clk_hs_mode(dsi, 1); 743 730 744 731 return 0; 745 732 err_disable_engine_clk: ··· 787 770 dsi->lanes_ready = false; 788 771 } 789 772 790 790 - static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) 791 791 - { 792 792 - if (!dsi->lanes_ready) { 793 793 - dsi->lanes_ready = true; 794 794 - mtk_dsi_rxtx_control(dsi); 795 795 - usleep_range(30, 100); 796 796 - mtk_dsi_reset_dphy(dsi); 797 797 - mtk_dsi_clk_ulp_mode_leave(dsi); 798 798 - mtk_dsi_lane0_ulp_mode_leave(dsi); 799 799 - mtk_dsi_clk_hs_mode(dsi, 0); 800 800 - usleep_range(1000, 3000); 801 801 - /* The reaction time after pulling up the mipi signal for dsi_rx */ 802 802 - } 803 803 - } 804 804 - 805 773 static void mtk_output_dsi_enable(struct mtk_dsi *dsi) 806 774 { 807 775 if (dsi->enabled) 808 776 return; 809 777 810 810 - mtk_dsi_lane_ready(dsi); 811 778 mtk_dsi_set_mode(dsi); 812 812 - mtk_dsi_clk_hs_mode(dsi, 1); 813 813 - 814 779 mtk_dsi_start(dsi); 815 780 816 781 dsi->enabled = true;