+7 -6

drivers/usb/atm/cxacru.c

reviewed

··· 1131 1131 struct cxacru_data *instance; 1132 1132 struct usb_device *usb_dev = interface_to_usbdev(intf); 1133 1133 struct usb_host_endpoint *cmd_ep = usb_dev->ep_in[CXACRU_EP_CMD]; 1134 1134 - struct usb_endpoint_descriptor *in, *out; 1134 1134 + static const u8 ep_addrs[] = { 1135 1135 + CXACRU_EP_CMD + USB_DIR_IN, 1136 1136 + CXACRU_EP_CMD + USB_DIR_OUT, 1137 1137 + 0}; 1135 1138 int ret; 1136 1139 1137 1140 /* instance init */ ··· 1182 1179 } 1183 1180 1184 1181 if (usb_endpoint_xfer_int(&cmd_ep->desc)) 1185 1185 - ret = usb_find_common_endpoints(intf->cur_altsetting, 1186 1186 - NULL, NULL, &in, &out); 1182 1182 + ret = usb_check_int_endpoints(intf, ep_addrs); 1187 1183 else 1188 1188 - ret = usb_find_common_endpoints(intf->cur_altsetting, 1189 1189 - &in, &out, NULL, NULL); 1184 1184 + ret = usb_check_bulk_endpoints(intf, ep_addrs); 1190 1185 1191 1191 - if (ret) { 1186 1186 + if (!ret) { 1192 1187 usb_err(usbatm_instance, "cxacru_bind: interface has incorrect endpoints\n"); 1193 1188 ret = -ENODEV; 1194 1189 goto fail;

+33

drivers/usb/core/hub.c

reviewed

··· 6066 6066 } /* usb_hub_cleanup() */ 6067 6067 6068 6068 /** 6069 6069 + * hub_hc_release_resources - clear resources used by host controller 6070 6070 + * @udev: pointer to device being released 6071 6071 + * 6072 6072 + * Context: task context, might sleep 6073 6073 + * 6074 6074 + * Function releases the host controller resources in correct order before 6075 6075 + * making any operation on resuming usb device. The host controller resources 6076 6076 + * allocated for devices in tree should be released starting from the last 6077 6077 + * usb device in tree toward the root hub. This function is used only during 6078 6078 + * resuming device when usb device require reinitialization – that is, when 6079 6079 + * flag udev->reset_resume is set. 6080 6080 + * 6081 6081 + * This call is synchronous, and may not be used in an interrupt context. 6082 6082 + */ 6083 6083 + static void hub_hc_release_resources(struct usb_device *udev) 6084 6084 + { 6085 6085 + struct usb_hub *hub = usb_hub_to_struct_hub(udev); 6086 6086 + struct usb_hcd *hcd = bus_to_hcd(udev->bus); 6087 6087 + int i; 6088 6088 + 6089 6089 + /* Release up resources for all children before this device */ 6090 6090 + for (i = 0; i < udev->maxchild; i++) 6091 6091 + if (hub->ports[i]->child) 6092 6092 + hub_hc_release_resources(hub->ports[i]->child); 6093 6093 + 6094 6094 + if (hcd->driver->reset_device) 6095 6095 + hcd->driver->reset_device(hcd, udev); 6096 6096 + } 6097 6097 + 6098 6098 + /** 6069 6099 * usb_reset_and_verify_device - perform a USB port reset to reinitialize a device 6070 6100 * @udev: device to reset (not in SUSPENDED or NOTATTACHED state) 6071 6101 * ··· 6158 6128 6159 6129 bos = udev->bos; 6160 6130 udev->bos = NULL; 6131 6131 + 6132 6132 + if (udev->reset_resume) 6133 6133 + hub_hc_release_resources(udev); 6161 6134 6162 6135 mutex_lock(hcd->address0_mutex); 6163 6136

+4

drivers/usb/core/quirks.c

reviewed

··· 341 341 { USB_DEVICE(0x0638, 0x0a13), .driver_info = 342 342 USB_QUIRK_STRING_FETCH_255 }, 343 343 344 344 + /* Prolific Single-LUN Mass Storage Card Reader */ 345 345 + { USB_DEVICE(0x067b, 0x2731), .driver_info = USB_QUIRK_DELAY_INIT | 346 346 + USB_QUIRK_NO_LPM }, 347 347 + 344 348 /* Saitek Cyborg Gold Joystick */ 345 349 { USB_DEVICE(0x06a3, 0x0006), .driver_info = 346 350 USB_QUIRK_CONFIG_INTF_STRINGS },

+48 -37

drivers/usb/dwc3/core.c

reviewed

··· 131 131 } 132 132 } 133 133 134 134 - void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 134 134 + void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy) 135 135 { 136 136 + unsigned int hw_mode; 136 137 u32 reg; 137 138 138 139 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 140 140 + 141 141 + /* 142 142 + * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE and 143 143 + * GUSB2PHYCFG.SUSPHY should be cleared during mode switching, 144 144 + * and they can be set after core initialization. 145 145 + */ 146 146 + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 147 147 + if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && !ignore_susphy) { 148 148 + if (DWC3_GCTL_PRTCAP(reg) != mode) 149 149 + dwc3_enable_susphy(dwc, false); 150 150 + } 151 151 + 139 152 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 140 153 reg |= DWC3_GCTL_PRTCAPDIR(mode); 141 154 dwc3_writel(dwc->regs, DWC3_GCTL, reg); ··· 229 216 230 217 spin_lock_irqsave(&dwc->lock, flags); 231 218 232 232 - dwc3_set_prtcap(dwc, desired_dr_role); 219 219 + dwc3_set_prtcap(dwc, desired_dr_role, false); 233 220 234 221 spin_unlock_irqrestore(&dwc->lock, flags); 235 222 ··· 671 658 */ 672 659 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 673 660 674 674 - /* 675 675 - * Above DWC_usb3.0 1.94a, it is recommended to set 676 676 - * DWC3_GUSB3PIPECTL_SUSPHY to '0' during coreConsultant configuration. 677 677 - * So default value will be '0' when the core is reset. Application 678 678 - * needs to set it to '1' after the core initialization is completed. 679 679 - * 680 680 - * Similarly for DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be 681 681 - * cleared after power-on reset, and it can be set after core 682 682 - * initialization. 683 683 - */ 661 661 + /* Ensure the GUSB3PIPECTL.SUSPENDENABLE is cleared prior to phy init. */ 684 662 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 685 663 686 664 if (dwc->u2ss_inp3_quirk) ··· 751 747 break; 752 748 } 753 749 754 754 - /* 755 755 - * Above DWC_usb3.0 1.94a, it is recommended to set 756 756 - * DWC3_GUSB2PHYCFG_SUSPHY to '0' during coreConsultant configuration. 757 757 - * So default value will be '0' when the core is reset. Application 758 758 - * needs to set it to '1' after the core initialization is completed. 759 759 - * 760 760 - * Similarly for DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared 761 761 - * after power-on reset, and it can be set after core initialization. 762 762 - */ 750 750 + /* Ensure the GUSB2PHYCFG.SUSPHY is cleared prior to phy init. */ 763 751 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 764 752 765 753 if (dwc->dis_enblslpm_quirk) ··· 825 829 if (ret < 0) 826 830 goto err_exit_usb3_phy; 827 831 } 832 832 + 833 833 + /* 834 834 + * Above DWC_usb3.0 1.94a, it is recommended to set 835 835 + * DWC3_GUSB3PIPECTL_SUSPHY and DWC3_GUSB2PHYCFG_SUSPHY to '0' during 836 836 + * coreConsultant configuration. So default value will be '0' when the 837 837 + * core is reset. Application needs to set it to '1' after the core 838 838 + * initialization is completed. 839 839 + * 840 840 + * Certain phy requires to be in P0 power state during initialization. 841 841 + * Make sure GUSB3PIPECTL.SUSPENDENABLE and GUSB2PHYCFG.SUSPHY are clear 842 842 + * prior to phy init to maintain in the P0 state. 843 843 + * 844 844 + * After phy initialization, some phy operations can only be executed 845 845 + * while in lower P states. Ensure GUSB3PIPECTL.SUSPENDENABLE and 846 846 + * GUSB2PHYCFG.SUSPHY are set soon after initialization to avoid 847 847 + * blocking phy ops. 848 848 + */ 849 849 + if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 850 850 + dwc3_enable_susphy(dwc, true); 828 851 829 852 return 0; 830 853 ··· 1603 1588 1604 1589 switch (dwc->dr_mode) { 1605 1590 case USB_DR_MODE_PERIPHERAL: 1606 1606 - dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1591 1591 + dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, false); 1607 1592 1608 1593 if (dwc->usb2_phy) 1609 1594 otg_set_vbus(dwc->usb2_phy->otg, false); ··· 1615 1600 return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 1616 1601 break; 1617 1602 case USB_DR_MODE_HOST: 1618 1618 - dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1603 1603 + dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST, false); 1619 1604 1620 1605 if (dwc->usb2_phy) 1621 1606 otg_set_vbus(dwc->usb2_phy->otg, true); ··· 1660 1645 } 1661 1646 1662 1647 /* de-assert DRVVBUS for HOST and OTG mode */ 1663 1663 - dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1648 1648 + dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, true); 1664 1649 } 1665 1650 1666 1651 static void dwc3_get_software_properties(struct dwc3 *dwc) ··· 1850 1835 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1851 1836 dwc->tx_max_burst_prd = tx_max_burst_prd; 1852 1837 1853 1853 - dwc->imod_interval = 0; 1854 1854 - 1855 1838 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1856 1839 } 1857 1840 ··· 1867 1854 unsigned int hwparam_gen = 1868 1855 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 1869 1856 1870 1870 - /* Check for proper value of imod_interval */ 1871 1871 - if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1872 1872 - dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1873 1873 - dwc->imod_interval = 0; 1874 1874 - } 1875 1875 - 1876 1857 /* 1858 1858 + * Enable IMOD for all supporting controllers. 1859 1859 + * 1860 1860 + * Particularly, DWC_usb3 v3.00a must enable this feature for 1861 1861 + * the following reason: 1862 1862 + * 1877 1863 * Workaround for STAR 9000961433 which affects only version 1878 1864 * 3.00a of the DWC_usb3 core. This prevents the controller 1879 1865 * interrupt from being masked while handling events. IMOD 1880 1866 * allows us to work around this issue. Enable it for the 1881 1867 * affected version. 1882 1868 */ 1883 1883 - if (!dwc->imod_interval && 1884 1884 - DWC3_VER_IS(DWC3, 300A)) 1869 1869 + if (dwc3_has_imod((dwc))) 1885 1870 dwc->imod_interval = 1; 1886 1871 1887 1872 /* Check the maximum_speed parameter */ ··· 2468 2457 if (ret) 2469 2458 return ret; 2470 2459 2471 2471 - dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 2460 2460 + dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, true); 2472 2461 dwc3_gadget_resume(dwc); 2473 2462 break; 2474 2463 case DWC3_GCTL_PRTCAP_HOST: ··· 2476 2465 ret = dwc3_core_init_for_resume(dwc); 2477 2466 if (ret) 2478 2467 return ret; 2479 2479 - dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 2468 2468 + dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST, true); 2480 2469 break; 2481 2470 } 2482 2471 /* Restore GUSB2PHYCFG bits that were modified in suspend */ ··· 2505 2494 if (ret) 2506 2495 return ret; 2507 2496 2508 2508 - dwc3_set_prtcap(dwc, dwc->current_dr_role); 2497 2497 + dwc3_set_prtcap(dwc, dwc->current_dr_role, true); 2509 2498 2510 2499 dwc3_otg_init(dwc); 2511 2500 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {

+1 -1

drivers/usb/dwc3/core.h

reviewed

··· 1558 1558 #define DWC3_HAS_OTG BIT(3) 1559 1559 1560 1560 /* prototypes */ 1561 1561 - void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode); 1561 1561 + void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy); 1562 1562 void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 1563 1563 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type); 1564 1564

+2 -2

drivers/usb/dwc3/drd.c

reviewed

··· 173 173 * block "Initialize GCTL for OTG operation". 174 174 */ 175 175 /* GCTL.PrtCapDir=2'b11 */ 176 176 - dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_OTG); 176 176 + dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_OTG, true); 177 177 /* GUSB2PHYCFG0.SusPHY=0 */ 178 178 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 179 179 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; ··· 556 556 557 557 dwc3_drd_update(dwc); 558 558 } else { 559 559 - dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_OTG); 559 559 + dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_OTG, true); 560 560 561 561 /* use OTG block to get ID event */ 562 562 irq = dwc3_otg_get_irq(dwc);

+7 -3

drivers/usb/dwc3/gadget.c

reviewed

··· 4501 4501 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 4502 4502 DWC3_GEVNTSIZ_SIZE(evt->length)); 4503 4503 4504 4504 + evt->flags &= ~DWC3_EVENT_PENDING; 4505 4505 + /* 4506 4506 + * Add an explicit write memory barrier to make sure that the update of 4507 4507 + * clearing DWC3_EVENT_PENDING is observed in dwc3_check_event_buf() 4508 4508 + */ 4509 4509 + wmb(); 4510 4510 + 4504 4511 if (dwc->imod_interval) { 4505 4512 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); 4506 4513 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); 4507 4514 } 4508 4508 - 4509 4509 - /* Keep the clearing of DWC3_EVENT_PENDING at the end */ 4510 4510 - evt->flags &= ~DWC3_EVENT_PENDING; 4511 4515 4512 4516 return ret; 4513 4517 }

+12 -5

drivers/usb/gadget/composite.c

reviewed

··· 1050 1050 else 1051 1051 usb_gadget_set_remote_wakeup(gadget, 0); 1052 1052 done: 1053 1053 - if (power <= USB_SELF_POWER_VBUS_MAX_DRAW) 1054 1054 - usb_gadget_set_selfpowered(gadget); 1055 1055 - else 1053 1053 + if (power > USB_SELF_POWER_VBUS_MAX_DRAW || 1054 1054 + (c && !(c->bmAttributes & USB_CONFIG_ATT_SELFPOWER))) 1056 1055 usb_gadget_clear_selfpowered(gadget); 1056 1056 + else 1057 1057 + usb_gadget_set_selfpowered(gadget); 1057 1058 1058 1059 usb_gadget_vbus_draw(gadget, power); 1059 1060 if (result >= 0 && cdev->delayed_status) ··· 2616 2615 2617 2616 cdev->suspended = 1; 2618 2617 2619 2619 - usb_gadget_set_selfpowered(gadget); 2618 2618 + if (cdev->config && 2619 2619 + cdev->config->bmAttributes & USB_CONFIG_ATT_SELFPOWER) 2620 2620 + usb_gadget_set_selfpowered(gadget); 2621 2621 + 2620 2622 usb_gadget_vbus_draw(gadget, 2); 2621 2623 } 2622 2624 ··· 2653 2649 else 2654 2650 maxpower = min(maxpower, 900U); 2655 2651 2656 2656 - if (maxpower > USB_SELF_POWER_VBUS_MAX_DRAW) 2652 2652 + if (maxpower > USB_SELF_POWER_VBUS_MAX_DRAW || 2653 2653 + !(cdev->config->bmAttributes & USB_CONFIG_ATT_SELFPOWER)) 2657 2654 usb_gadget_clear_selfpowered(gadget); 2655 2655 + else 2656 2656 + usb_gadget_set_selfpowered(gadget); 2658 2657 2659 2658 usb_gadget_vbus_draw(gadget, maxpower); 2660 2659 } else {

+2 -2

drivers/usb/gadget/function/u_ether.c

reviewed

··· 1052 1052 * There is a transfer in progress. So we trigger a remote 1053 1053 * wakeup to inform the host. 1054 1054 */ 1055 1055 - ether_wakeup_host(dev->port_usb); 1056 1056 - return; 1055 1055 + if (!ether_wakeup_host(dev->port_usb)) 1056 1056 + return; 1057 1057 } 1058 1058 spin_lock_irqsave(&dev->lock, flags); 1059 1059 link->is_suspend = true;

+8

drivers/usb/host/xhci-hub.c

reviewed

··· 12 12 #include <linux/slab.h> 13 13 #include <linux/unaligned.h> 14 14 #include <linux/bitfield.h> 15 15 + #include <linux/pci.h> 15 16 16 17 #include "xhci.h" 17 18 #include "xhci-trace.h" ··· 771 770 enum usb_link_tunnel_mode xhci_port_is_tunneled(struct xhci_hcd *xhci, 772 771 struct xhci_port *port) 773 772 { 773 773 + struct usb_hcd *hcd; 774 774 void __iomem *base; 775 775 u32 offset; 776 776 + 777 777 + /* Don't try and probe this capability for non-Intel hosts */ 778 778 + hcd = xhci_to_hcd(xhci); 779 779 + if (!dev_is_pci(hcd->self.controller) || 780 780 + to_pci_dev(hcd->self.controller)->vendor != PCI_VENDOR_ID_INTEL) 781 781 + return USB_LINK_UNKNOWN; 776 782 777 783 base = &xhci->cap_regs->hc_capbase; 778 784 offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_INTEL_SPR_SHADOW);

+2 -1

drivers/usb/host/xhci-mem.c

reviewed

··· 2437 2437 * and our use of dma addresses in the trb_address_map radix tree needs 2438 2438 * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need. 2439 2439 */ 2440 2440 - if (xhci->quirks & XHCI_ZHAOXIN_TRB_FETCH) 2440 2440 + if (xhci->quirks & XHCI_TRB_OVERFETCH) 2441 2441 + /* Buggy HC prefetches beyond segment bounds - allocate dummy space at the end */ 2441 2442 xhci->segment_pool = dma_pool_create("xHCI ring segments", dev, 2442 2443 TRB_SEGMENT_SIZE * 2, TRB_SEGMENT_SIZE * 2, xhci->page_size * 2); 2443 2444 else

+7 -3

drivers/usb/host/xhci-pci.c

reviewed

··· 38 38 #define PCI_DEVICE_ID_ETRON_EJ168 0x7023 39 39 #define PCI_DEVICE_ID_ETRON_EJ188 0x7052 40 40 41 41 + #define PCI_DEVICE_ID_VIA_VL805 0x3483 42 42 + 41 43 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 42 44 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 43 45 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 ··· 420 418 pdev->device == 0x3432) 421 419 xhci->quirks |= XHCI_BROKEN_STREAMS; 422 420 423 423 - if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) 421 421 + if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == PCI_DEVICE_ID_VIA_VL805) { 424 422 xhci->quirks |= XHCI_LPM_SUPPORT; 423 423 + xhci->quirks |= XHCI_TRB_OVERFETCH; 424 424 + } 425 425 426 426 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && 427 427 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) { ··· 471 467 472 468 if (pdev->device == 0x9202) { 473 469 xhci->quirks |= XHCI_RESET_ON_RESUME; 474 474 - xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 470 470 + xhci->quirks |= XHCI_TRB_OVERFETCH; 475 471 } 476 472 477 473 if (pdev->device == 0x9203) 478 478 - xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH; 474 474 + xhci->quirks |= XHCI_TRB_OVERFETCH; 479 475 } 480 476 481 477 if (pdev->vendor == PCI_VENDOR_ID_CDNS &&

+5 -1

drivers/usb/host/xhci.c

reviewed

··· 780 780 struct xhci_segment *seg; 781 781 782 782 ring = xhci->cmd_ring; 783 783 - xhci_for_each_ring_seg(ring->first_seg, seg) 783 783 + xhci_for_each_ring_seg(ring->first_seg, seg) { 784 784 + /* erase all TRBs before the link */ 784 785 memset(seg->trbs, 0, sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1)); 786 786 + /* clear link cycle bit */ 787 787 + seg->trbs[TRBS_PER_SEGMENT - 1].link.control &= cpu_to_le32(~TRB_CYCLE); 788 788 + } 785 789 786 790 xhci_initialize_ring_info(ring); 787 791 /*

+1 -1

drivers/usb/host/xhci.h

reviewed

··· 1632 1632 #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) 1633 1633 #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) 1634 1634 #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) 1635 1635 - #define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45) 1635 1635 + #define XHCI_TRB_OVERFETCH BIT_ULL(45) 1636 1636 #define XHCI_ZHAOXIN_HOST BIT_ULL(46) 1637 1637 #define XHCI_WRITE_64_HI_LO BIT_ULL(47) 1638 1638 #define XHCI_CDNS_SCTX_QUIRK BIT_ULL(48)

+5 -1

drivers/usb/renesas_usbhs/common.c

reviewed

··· 312 312 priv->clks[1] = of_clk_get(dev_of_node(dev), 1); 313 313 if (PTR_ERR(priv->clks[1]) == -ENOENT) 314 314 priv->clks[1] = NULL; 315 315 - else if (IS_ERR(priv->clks[1])) 315 315 + else if (IS_ERR(priv->clks[1])) { 316 316 + clk_put(priv->clks[0]); 316 317 return PTR_ERR(priv->clks[1]); 318 318 + } 317 319 318 320 return 0; 319 321 } ··· 780 778 struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev); 781 779 782 780 dev_dbg(&pdev->dev, "usb remove\n"); 781 781 + 782 782 + flush_delayed_work(&priv->notify_hotplug_work); 783 783 784 784 /* power off */ 785 785 if (!usbhs_get_dparam(priv, runtime_pwctrl))

+1 -1

drivers/usb/renesas_usbhs/mod_gadget.c

reviewed

··· 1094 1094 goto usbhs_mod_gadget_probe_err_gpriv; 1095 1095 } 1096 1096 1097 1097 - gpriv->transceiver = usb_get_phy(USB_PHY_TYPE_UNDEFINED); 1097 1097 + gpriv->transceiver = devm_usb_get_phy(dev, USB_PHY_TYPE_UNDEFINED); 1098 1098 dev_info(dev, "%stransceiver found\n", 1099 1099 !IS_ERR(gpriv->transceiver) ? "" : "no "); 1100 1100

+11

drivers/usb/typec/tcpm/tcpci_rt1711h.c

reviewed

··· 334 334 { 335 335 int ret; 336 336 struct rt1711h_chip *chip; 337 337 + const u16 alert_mask = TCPC_ALERT_TX_SUCCESS | TCPC_ALERT_TX_DISCARDED | 338 338 + TCPC_ALERT_TX_FAILED | TCPC_ALERT_RX_HARD_RST | 339 339 + TCPC_ALERT_RX_STATUS | TCPC_ALERT_POWER_STATUS | 340 340 + TCPC_ALERT_CC_STATUS | TCPC_ALERT_RX_BUF_OVF | 341 341 + TCPC_ALERT_FAULT; 337 342 338 343 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); 339 344 if (!chip) ··· 387 382 dev_name(chip->dev), chip); 388 383 if (ret < 0) 389 384 return ret; 385 385 + 386 386 + /* Enable alert interrupts */ 387 387 + ret = rt1711h_write16(chip, TCPC_ALERT_MASK, alert_mask); 388 388 + if (ret < 0) 389 389 + return ret; 390 390 + 390 391 enable_irq_wake(client->irq); 391 392 392 393 return 0;

+13 -12

drivers/usb/typec/ucsi/ucsi.c

reviewed

··· 25 25 * difficult to estimate the time it takes for the system to process the command 26 26 * before it is actually passed to the PPM. 27 27 */ 28 28 - #define UCSI_TIMEOUT_MS 5000 28 28 + #define UCSI_TIMEOUT_MS 10000 29 29 30 30 /* 31 31 * UCSI_SWAP_TIMEOUT_MS - Timeout for role swap requests ··· 1346 1346 1347 1347 mutex_lock(&ucsi->ppm_lock); 1348 1348 1349 1349 - ret = ucsi->ops->read_cci(ucsi, &cci); 1349 1349 + ret = ucsi->ops->poll_cci(ucsi, &cci); 1350 1350 if (ret < 0) 1351 1351 goto out; 1352 1352 ··· 1364 1364 1365 1365 tmo = jiffies + msecs_to_jiffies(UCSI_TIMEOUT_MS); 1366 1366 do { 1367 1367 - ret = ucsi->ops->read_cci(ucsi, &cci); 1367 1367 + ret = ucsi->ops->poll_cci(ucsi, &cci); 1368 1368 if (ret < 0) 1369 1369 goto out; 1370 1370 if (cci & UCSI_CCI_COMMAND_COMPLETE) ··· 1393 1393 /* Give the PPM time to process a reset before reading CCI */ 1394 1394 msleep(20); 1395 1395 1396 1396 - ret = ucsi->ops->read_cci(ucsi, &cci); 1396 1396 + ret = ucsi->ops->poll_cci(ucsi, &cci); 1397 1397 if (ret) 1398 1398 goto out; 1399 1399 ··· 1825 1825 1826 1826 err_unregister: 1827 1827 for (con = connector; con->port; con++) { 1828 1828 + if (con->wq) 1829 1829 + destroy_workqueue(con->wq); 1828 1830 ucsi_unregister_partner(con); 1829 1831 ucsi_unregister_altmodes(con, UCSI_RECIPIENT_CON); 1830 1832 ucsi_unregister_port_psy(con); 1831 1831 - if (con->wq) 1832 1832 - destroy_workqueue(con->wq); 1833 1833 1834 1834 usb_power_delivery_unregister_capabilities(con->port_sink_caps); 1835 1835 con->port_sink_caps = NULL; ··· 1929 1929 struct ucsi *ucsi; 1930 1930 1931 1931 if (!ops || 1932 1932 - !ops->read_version || !ops->read_cci || !ops->read_message_in || 1933 1933 - !ops->sync_control || !ops->async_control) 1932 1932 + !ops->read_version || !ops->read_cci || !ops->poll_cci || 1933 1933 + !ops->read_message_in || !ops->sync_control || !ops->async_control) 1934 1934 return ERR_PTR(-EINVAL); 1935 1935 1936 1936 ucsi = kzalloc(sizeof(*ucsi), GFP_KERNEL); ··· 2013 2013 2014 2014 for (i = 0; i < ucsi->cap.num_connectors; i++) { 2015 2015 cancel_work_sync(&ucsi->connector[i].work); 2016 2016 - ucsi_unregister_partner(&ucsi->connector[i]); 2017 2017 - ucsi_unregister_altmodes(&ucsi->connector[i], 2018 2018 - UCSI_RECIPIENT_CON); 2019 2019 - ucsi_unregister_port_psy(&ucsi->connector[i]); 2020 2016 2021 2017 if (ucsi->connector[i].wq) { 2022 2018 struct ucsi_work *uwork; ··· 2027 2031 mutex_unlock(&ucsi->connector[i].lock); 2028 2032 destroy_workqueue(ucsi->connector[i].wq); 2029 2033 } 2034 2034 + 2035 2035 + ucsi_unregister_partner(&ucsi->connector[i]); 2036 2036 + ucsi_unregister_altmodes(&ucsi->connector[i], 2037 2037 + UCSI_RECIPIENT_CON); 2038 2038 + ucsi_unregister_port_psy(&ucsi->connector[i]); 2030 2039 2031 2040 usb_power_delivery_unregister_capabilities(ucsi->connector[i].port_sink_caps); 2032 2041 ucsi->connector[i].port_sink_caps = NULL;

+2

drivers/usb/typec/ucsi/ucsi.h

reviewed

··· 62 62 * struct ucsi_operations - UCSI I/O operations 63 63 * @read_version: Read implemented UCSI version 64 64 * @read_cci: Read CCI register 65 65 + * @poll_cci: Read CCI register while polling with notifications disabled 65 66 * @read_message_in: Read message data from UCSI 66 67 * @sync_control: Blocking control operation 67 68 * @async_control: Non-blocking control operation ··· 77 76 struct ucsi_operations { 78 77 int (*read_version)(struct ucsi *ucsi, u16 *version); 79 78 int (*read_cci)(struct ucsi *ucsi, u32 *cci); 79 79 + int (*poll_cci)(struct ucsi *ucsi, u32 *cci); 80 80 int (*read_message_in)(struct ucsi *ucsi, void *val, size_t val_len); 81 81 int (*sync_control)(struct ucsi *ucsi, u64 command); 82 82 int (*async_control)(struct ucsi *ucsi, u64 command);

+14 -7

drivers/usb/typec/ucsi/ucsi_acpi.c

reviewed

··· 59 59 static int ucsi_acpi_read_cci(struct ucsi *ucsi, u32 *cci) 60 60 { 61 61 struct ucsi_acpi *ua = ucsi_get_drvdata(ucsi); 62 62 - int ret; 63 63 - 64 64 - if (UCSI_COMMAND(ua->cmd) == UCSI_PPM_RESET) { 65 65 - ret = ucsi_acpi_dsm(ua, UCSI_DSM_FUNC_READ); 66 66 - if (ret) 67 67 - return ret; 68 68 - } 69 62 70 63 memcpy(cci, ua->base + UCSI_CCI, sizeof(*cci)); 71 64 72 65 return 0; 66 66 + } 67 67 + 68 68 + static int ucsi_acpi_poll_cci(struct ucsi *ucsi, u32 *cci) 69 69 + { 70 70 + struct ucsi_acpi *ua = ucsi_get_drvdata(ucsi); 71 71 + int ret; 72 72 + 73 73 + ret = ucsi_acpi_dsm(ua, UCSI_DSM_FUNC_READ); 74 74 + if (ret) 75 75 + return ret; 76 76 + 77 77 + return ucsi_acpi_read_cci(ucsi, cci); 73 78 } 74 79 75 80 static int ucsi_acpi_read_message_in(struct ucsi *ucsi, void *val, size_t val_len) ··· 99 94 static const struct ucsi_operations ucsi_acpi_ops = { 100 95 .read_version = ucsi_acpi_read_version, 101 96 .read_cci = ucsi_acpi_read_cci, 97 97 + .poll_cci = ucsi_acpi_poll_cci, 102 98 .read_message_in = ucsi_acpi_read_message_in, 103 99 .sync_control = ucsi_sync_control_common, 104 100 .async_control = ucsi_acpi_async_control ··· 148 142 static const struct ucsi_operations ucsi_gram_ops = { 149 143 .read_version = ucsi_acpi_read_version, 150 144 .read_cci = ucsi_acpi_read_cci, 145 145 + .poll_cci = ucsi_acpi_poll_cci, 151 146 .read_message_in = ucsi_gram_read_message_in, 152 147 .sync_control = ucsi_gram_sync_control, 153 148 .async_control = ucsi_acpi_async_control

+1

drivers/usb/typec/ucsi/ucsi_ccg.c

reviewed

··· 664 664 static const struct ucsi_operations ucsi_ccg_ops = { 665 665 .read_version = ucsi_ccg_read_version, 666 666 .read_cci = ucsi_ccg_read_cci, 667 667 + .poll_cci = ucsi_ccg_read_cci, 667 668 .read_message_in = ucsi_ccg_read_message_in, 668 669 .sync_control = ucsi_ccg_sync_control, 669 670 .async_control = ucsi_ccg_async_control,

+1

drivers/usb/typec/ucsi/ucsi_glink.c

reviewed

··· 206 206 static const struct ucsi_operations pmic_glink_ucsi_ops = { 207 207 .read_version = pmic_glink_ucsi_read_version, 208 208 .read_cci = pmic_glink_ucsi_read_cci, 209 209 + .poll_cci = pmic_glink_ucsi_read_cci, 209 210 .read_message_in = pmic_glink_ucsi_read_message_in, 210 211 .sync_control = ucsi_sync_control_common, 211 212 .async_control = pmic_glink_ucsi_async_control,

+1

drivers/usb/typec/ucsi/ucsi_stm32g0.c

reviewed

··· 424 424 static const struct ucsi_operations ucsi_stm32g0_ops = { 425 425 .read_version = ucsi_stm32g0_read_version, 426 426 .read_cci = ucsi_stm32g0_read_cci, 427 427 + .poll_cci = ucsi_stm32g0_read_cci, 427 428 .read_message_in = ucsi_stm32g0_read_message_in, 428 429 .sync_control = ucsi_sync_control_common, 429 430 .async_control = ucsi_stm32g0_async_control,

+1

drivers/usb/typec/ucsi/ucsi_yoga_c630.c

reviewed

··· 74 74 static const struct ucsi_operations yoga_c630_ucsi_ops = { 75 75 .read_version = yoga_c630_ucsi_read_version, 76 76 .read_cci = yoga_c630_ucsi_read_cci, 77 77 + .poll_cci = yoga_c630_ucsi_read_cci, 77 78 .read_message_in = yoga_c630_ucsi_read_message_in, 78 79 .sync_control = ucsi_sync_control_common, 79 80 .async_control = yoga_c630_ucsi_async_control,