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Merge tag 'renesas-dts-for-v6.17-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v6.17

- Add SPI FLASH, camera, and Ethernet support on the RZ/G3E SoC and/or
the RZ/G3E SoM and SMARC Carrier-II EVK development board,
- Add Ethernet, USB2, and PMIC support on the RZ/V2H and RZ/V2N SoCs
and EVK boards,
- Add timer, I2C, watchdog, and GPU support on the RZ/V2N SoC and the
RZ/V2N EVK board,
- Add debug LED support for the RZN1D-DB development board,
- Improve PCIe clock description on the Retronix Sparrow Hawk board,
- Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v6.17-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (34 commits)
arm64: dts: renesas: r9a09g047: Add GBETH nodes
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Rename fixed regulator node names
arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add RAA215300 PMIC
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add RAA215300 PMIC
arm64: dts: renesas: rcar-gen3: Add bootph-all to sysinfo EEPROMs
arm64: dts: renesas: sparrow-hawk: Describe split PCIe clock
arm64: dts: renesas: r8a779g0: Describe PCIe root ports
arm64: dts: renesas: ebisu: Add CAN0 support
ARM: dts: renesas: r9a06g032: Add second clock input to RTC
arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable USB2.0 support
arm64: dts: renesas: r9a09g056: Add USB2.0 support
arm64: dts: renesas: r8a779g3-sparrow-hawk: Sort DTS
ARM: dts: renesas: r9a06g032-rzn1d400-db: Describe debug LEDs
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB2.0 support
PCI/pwrctrl: Add optional slot clock for PCI slots
arm64: dts: renesas: r9a09g057: Add USB2.0 support
arm64: dts: renesas: r9a09g047e57-smarc: Enable CRU, CSI support
arm64: dts: renesas: renesas-smarc2: Enable I2C0 node
arm64: dts: renesas: r9a09g047e57-smarc: Add I2C0 pincontrol
arm64: dts: renesas: r9a09g047: Add CRU, CSI2 nodes
...

Link: https://lore.kernel.org/r/cover.1751026664.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann 0dc89a25 3e0111b6

+1912 -19
+64
arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
··· 10 10 11 11 #include <dt-bindings/gpio/gpio.h> 12 12 #include <dt-bindings/input/input.h> 13 + #include <dt-bindings/leds/common.h> 13 14 #include <dt-bindings/net/pcs-rzn1-miic.h> 14 15 #include <dt-bindings/pinctrl/rzn1-pinctrl.h> 15 16 ··· 87 86 debounce-interval = <20>; 88 87 gpios = <&pca9698 15 GPIO_ACTIVE_LOW>; 89 88 }; 89 + }; 90 90 91 + leds { 92 + compatible = "gpio-leds"; 93 + 94 + led-dbg0 { 95 + gpios = <&pca9698 0 GPIO_ACTIVE_HIGH>; 96 + color = <LED_COLOR_ID_GREEN>; 97 + function = LED_FUNCTION_DEBUG; 98 + function-enumerator = <0>; 99 + }; 100 + 101 + led-dbg1 { 102 + gpios = <&pca9698 1 GPIO_ACTIVE_HIGH>; 103 + color = <LED_COLOR_ID_GREEN>; 104 + function = LED_FUNCTION_DEBUG; 105 + function-enumerator = <1>; 106 + }; 107 + 108 + led-dbg2 { 109 + gpios = <&pca9698 2 GPIO_ACTIVE_HIGH>; 110 + color = <LED_COLOR_ID_GREEN>; 111 + function = LED_FUNCTION_DEBUG; 112 + function-enumerator = <2>; 113 + }; 114 + 115 + led-dbg3 { 116 + gpios = <&pca9698 3 GPIO_ACTIVE_HIGH>; 117 + color = <LED_COLOR_ID_GREEN>; 118 + function = LED_FUNCTION_DEBUG; 119 + function-enumerator = <3>; 120 + }; 121 + 122 + led-dbg4 { 123 + gpios = <&pca9698 4 GPIO_ACTIVE_HIGH>; 124 + color = <LED_COLOR_ID_GREEN>; 125 + function = LED_FUNCTION_DEBUG; 126 + function-enumerator = <4>; 127 + }; 128 + 129 + led-dbg5 { 130 + gpios = <&pca9698 5 GPIO_ACTIVE_HIGH>; 131 + color = <LED_COLOR_ID_GREEN>; 132 + function = LED_FUNCTION_DEBUG; 133 + function-enumerator = <5>; 134 + }; 135 + 136 + led-dbg6 { 137 + gpios = <&pca9698 6 GPIO_ACTIVE_HIGH>; 138 + color = <LED_COLOR_ID_GREEN>; 139 + function = LED_FUNCTION_DEBUG; 140 + function-enumerator = <6>; 141 + }; 142 + 143 + led-dbg7 { 144 + gpios = <&pca9698 7 GPIO_ACTIVE_HIGH>; 145 + color = <LED_COLOR_ID_GREEN>; 146 + function = LED_FUNCTION_DEBUG; 147 + function-enumerator = <7>; 148 + }; 91 149 }; 92 150 }; 93 151 ··· 169 109 &eth_miic { 170 110 status = "okay"; 171 111 renesas,miic-switch-portin = <MIIC_GMAC2_PORT>; 112 + }; 113 + 114 + &ext_rtc_clk { 115 + clock-frequency = <32768>; 172 116 }; 173 117 174 118 &gmac2 {
+2 -2
arch/arm/boot/dts/renesas/r9a06g032.dtsi
··· 73 73 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, 74 74 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 75 75 interrupt-names = "alarm", "timer", "pps"; 76 - clocks = <&sysctrl R9A06G032_HCLK_RTC>; 77 - clock-names = "hclk"; 76 + clocks = <&sysctrl R9A06G032_HCLK_RTC>, <&ext_rtc_clk>; 77 + clock-names = "hclk", "xtal"; 78 78 power-domains = <&sysctrl>; 79 79 status = "disabled"; 80 80 };
+3
arch/arm64/boot/dts/renesas/Makefile
··· 156 156 dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb 157 157 158 158 dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb 159 + dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc-cru-csi-ov5645.dtbo 160 + r9a09g047e57-smarc-cru-csi-ov5645-dtbs := r9a09g047e57-smarc.dtb r9a09g047e57-smarc-cru-csi-ov5645.dtbo 161 + dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc-cru-csi-ov5645.dtb 159 162 160 163 dtb-$(CONFIG_ARCH_R9A09G056) += r9a09g056n48-rzv2n-evk.dtb 161 164
+2
arch/arm64/boot/dts/renesas/condor-common.dtsi
··· 174 174 &i2c0 { 175 175 pinctrl-0 = <&i2c0_pins>; 176 176 pinctrl-names = "default"; 177 + bootph-all; 177 178 178 179 status = "okay"; 179 180 clock-frequency = <400000>; ··· 231 230 compatible = "rohm,br24t01", "atmel,24c01"; 232 231 reg = <0x50>; 233 232 pagesize = <8>; 233 + bootph-all; 234 234 }; 235 235 }; 236 236
+2
arch/arm64/boot/dts/renesas/draak.dtsi
··· 308 308 &i2c0 { 309 309 pinctrl-0 = <&i2c0_pins>; 310 310 pinctrl-names = "default"; 311 + bootph-all; 311 312 status = "okay"; 312 313 313 314 ak4613: codec@10 { ··· 450 449 compatible = "rohm,br24t01", "atmel,24c01"; 451 450 reg = <0x50>; 452 451 pagesize = <8>; 452 + bootph-all; 453 453 }; 454 454 }; 455 455
+16
arch/arm64/boot/dts/renesas/ebisu.dtsi
··· 327 327 }; 328 328 }; 329 329 330 + &can0 { 331 + pinctrl-0 = <&can0_pins>; 332 + pinctrl-names = "default"; 333 + 334 + /* Please only enable canfd or can0 */ 335 + /* status = "okay"; */ 336 + }; 337 + 330 338 &canfd { 331 339 pinctrl-0 = <&canfd0_pins>; 332 340 pinctrl-names = "default"; 341 + /* Please only enable canfd or can0 */ 333 342 status = "okay"; 334 343 335 344 channel0 { ··· 512 503 }; 513 504 514 505 &i2c_dvfs { 506 + bootph-all; 515 507 status = "okay"; 516 508 517 509 clock-frequency = <400000>; ··· 536 526 compatible = "rohm,br24t01", "atmel,24c01"; 537 527 reg = <0x50>; 538 528 pagesize = <8>; 529 + bootph-all; 539 530 }; 540 531 }; 541 532 ··· 588 577 avb_pins: avb { 589 578 groups = "avb_link", "avb_mii"; 590 579 function = "avb"; 580 + }; 581 + 582 + can0_pins: can0 { 583 + groups = "can0_data"; 584 + function = "can0"; 591 585 }; 592 586 593 587 canfd0_pins: canfd0 {
+20
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
··· 798 798 <0 0 0 4 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; 799 799 snps,enable-cdm-check; 800 800 status = "disabled"; 801 + 802 + /* PCIe bridge, Root Port */ 803 + pciec0_rp: pci@0,0 { 804 + #address-cells = <3>; 805 + #size-cells = <2>; 806 + reg = <0x0 0x0 0x0 0x0 0x0>; 807 + compatible = "pciclass,0604"; 808 + device_type = "pci"; 809 + ranges; 810 + }; 801 811 }; 802 812 803 813 pciec1: pcie@e65d8000 { ··· 845 835 <0 0 0 4 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>; 846 836 snps,enable-cdm-check; 847 837 status = "disabled"; 838 + 839 + /* PCIe bridge, Root Port */ 840 + pciec1_rp: pci@0,0 { 841 + #address-cells = <3>; 842 + #size-cells = <2>; 843 + reg = <0x0 0x0 0x0 0x0 0x0>; 844 + compatible = "pciclass,0604"; 845 + device_type = "pci"; 846 + ranges; 847 + }; 848 848 }; 849 849 850 850 pciec0_ep: pcie-ep@e65d0000 {
+42 -15
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts
··· 130 130 }; 131 131 }; 132 132 133 + /* Page 26 / PCIe.0/1 CLK */ 134 + pcie_refclk: clk-x8 { 135 + compatible = "fixed-clock"; 136 + #clock-cells = <0>; 137 + clock-frequency = <25000000>; 138 + }; 139 + 133 140 reg_1p2v: regulator-1p2v { 134 141 compatible = "regulator-fixed"; 135 142 regulator-name = "fixed-1.2V"; ··· 411 404 reg = <2>; 412 405 #address-cells = <1>; 413 406 #size-cells = <0>; 407 + 408 + /* Page 26 / PCIe.0/1 CLK */ 409 + pcie_clk: clk@68 { 410 + compatible = "renesas,9fgv0441"; 411 + reg = <0x68>; 412 + clocks = <&pcie_refclk>; 413 + #clock-cells = <1>; 414 + }; 414 415 }; 415 416 416 417 i2c0_mux3: i2c@3 { ··· 502 487 503 488 /* Page 26 / 2230 Key M M.2 */ 504 489 &pcie0_clkref { 505 - clock-frequency = <100000000>; 490 + status = "disabled"; 506 491 }; 507 492 508 493 &pciec0 { 494 + clocks = <&cpg CPG_MOD 624>, <&pcie_clk 0>; 509 495 reset-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 510 496 status = "okay"; 511 497 }; 512 498 499 + &pciec0_rp { 500 + clocks = <&pcie_clk 1>; 501 + vpcie3v3-supply = <&reg_3p3v>; 502 + }; 503 + 513 504 /* Page 25 / PCIe to USB */ 514 505 &pcie1_clkref { 515 - clock-frequency = <100000000>; 506 + status = "disabled"; 516 507 }; 517 508 518 509 &pciec1 { 510 + clocks = <&cpg CPG_MOD 625>, <&pcie_clk 2>; 519 511 /* uPD720201 is PCIe Gen2 x1 device */ 520 512 num-lanes = <1>; 521 513 reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 522 514 status = "okay"; 515 + }; 516 + 517 + &pciec1_rp { 518 + clocks = <&pcie_clk 3>; 519 + vpcie3v3-supply = <&reg_3p3v>; 523 520 }; 524 521 525 522 &pfc { ··· 706 679 }; 707 680 }; 708 681 709 - /* Page 30 / Audio_Codec */ 710 - &rcar_sound { 711 - pinctrl-0 = <&sound_clk_pins>; 712 - pinctrl-names = "default"; 713 - 714 - /* It is used for ADG output as DA7212_MCLK */ 715 - 716 - /* audio_clkout */ 717 - clock-frequency = <12288000>; /* 48 kHz groups */ 718 - 719 - status = "okay"; 720 - }; 721 - 722 682 /* Page 31 / FAN */ 723 683 &pwm0 { 724 684 pinctrl-0 = <&pwm0_pins>; ··· 731 717 &pwm7 { 732 718 pinctrl-0 = <&pwm7_pins>; 733 719 pinctrl-names = "default"; 720 + status = "okay"; 721 + }; 722 + 723 + /* Page 30 / Audio_Codec */ 724 + &rcar_sound { 725 + pinctrl-0 = <&sound_clk_pins>; 726 + pinctrl-names = "default"; 727 + 728 + /* It is used for ADG output as DA7212_MCLK */ 729 + 730 + /* audio_clkout */ 731 + clock-frequency = <12288000>; /* 48 kHz groups */ 732 + 734 733 status = "okay"; 735 734 }; 736 735
+299
arch/arm64/boot/dts/renesas/r9a09g047.dtsi
··· 280 280 resets = <&cpg 0x30>; 281 281 }; 282 282 283 + xspi: spi@11030000 { 284 + compatible = "renesas,r9a09g047-xspi"; 285 + reg = <0 0x11030000 0 0x10000>, 286 + <0 0x20000000 0 0x10000000>; 287 + reg-names = "regs", "dirmap"; 288 + interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 289 + <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; 290 + interrupt-names = "pulse", "err_pulse"; 291 + clocks = <&cpg CPG_MOD 0x9f>, 292 + <&cpg CPG_MOD 0xa0>, 293 + <&cpg CPG_CORE R9A09G047_SPI_CLK_SPI>, 294 + <&cpg CPG_MOD 0xa1>; 295 + clock-names = "ahb", "axi", "spi", "spix2"; 296 + resets = <&cpg 0xa3>, <&cpg 0xa4>; 297 + reset-names = "hresetn", "aresetn"; 298 + power-domains = <&cpg>; 299 + #address-cells = <1>; 300 + #size-cells = <0>; 301 + status = "disabled"; 302 + }; 303 + 283 304 scif0: serial@11c01400 { 284 305 compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057"; 285 306 reg = <0 0x11c01400 0 0x400>; ··· 690 669 status = "disabled"; 691 670 }; 692 671 }; 672 + 673 + eth0: ethernet@15c30000 { 674 + compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth", 675 + "snps,dwmac-5.20"; 676 + reg = <0 0x15c30000 0 0x10000>; 677 + clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 678 + <&cpg CPG_CORE R9A09G047_GBETH_0_CLK_PTP_REF_I>, 679 + <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 680 + <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 681 + clock-names = "stmmaceth", "pclk", "ptp_ref", 682 + "tx", "rx", "tx-180", "rx-180"; 683 + interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 684 + <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 685 + <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 686 + <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 687 + <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 688 + <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 689 + <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 690 + <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 691 + <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 692 + <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 693 + <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; 694 + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 695 + "rx-queue-0", "rx-queue-1", "rx-queue-2", 696 + "rx-queue-3", "tx-queue-0", "tx-queue-1", 697 + "tx-queue-2", "tx-queue-3"; 698 + resets = <&cpg 0xb0>; 699 + power-domains = <&cpg>; 700 + snps,multicast-filter-bins = <256>; 701 + snps,perfect-filter-entries = <128>; 702 + rx-fifo-depth = <8192>; 703 + tx-fifo-depth = <8192>; 704 + snps,fixed-burst; 705 + snps,no-pbl-x8; 706 + snps,force_thresh_dma_mode; 707 + snps,axi-config = <&stmmac_axi_setup>; 708 + snps,mtl-rx-config = <&mtl_rx_setup0>; 709 + snps,mtl-tx-config = <&mtl_tx_setup0>; 710 + snps,txpbl = <32>; 711 + snps,rxpbl = <32>; 712 + status = "disabled"; 713 + 714 + mdio0: mdio { 715 + compatible = "snps,dwmac-mdio"; 716 + #address-cells = <1>; 717 + #size-cells = <0>; 718 + }; 719 + 720 + mtl_rx_setup0: rx-queues-config { 721 + snps,rx-queues-to-use = <4>; 722 + snps,rx-sched-sp; 723 + 724 + queue0 { 725 + snps,dcb-algorithm; 726 + snps,priority = <0x1>; 727 + snps,map-to-dma-channel = <0>; 728 + }; 729 + 730 + queue1 { 731 + snps,dcb-algorithm; 732 + snps,priority = <0x2>; 733 + snps,map-to-dma-channel = <1>; 734 + }; 735 + 736 + queue2 { 737 + snps,dcb-algorithm; 738 + snps,priority = <0x4>; 739 + snps,map-to-dma-channel = <2>; 740 + }; 741 + 742 + queue3 { 743 + snps,dcb-algorithm; 744 + snps,priority = <0x8>; 745 + snps,map-to-dma-channel = <3>; 746 + }; 747 + }; 748 + 749 + mtl_tx_setup0: tx-queues-config { 750 + snps,tx-queues-to-use = <4>; 751 + 752 + queue0 { 753 + snps,dcb-algorithm; 754 + snps,priority = <0x1>; 755 + }; 756 + 757 + queue1 { 758 + snps,dcb-algorithm; 759 + snps,priority = <0x2>; 760 + }; 761 + 762 + queue2 { 763 + snps,dcb-algorithm; 764 + snps,priority = <0x4>; 765 + }; 766 + 767 + queue3 { 768 + snps,dcb-algorithm; 769 + snps,priority = <0x8>; 770 + }; 771 + }; 772 + }; 773 + 774 + eth1: ethernet@15c40000 { 775 + compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth", 776 + "snps,dwmac-5.20"; 777 + reg = <0 0x15c40000 0 0x10000>; 778 + clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 779 + <&cpg CPG_CORE R9A09G047_GBETH_1_CLK_PTP_REF_I>, 780 + <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 781 + <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 782 + clock-names = "stmmaceth", "pclk", "ptp_ref", 783 + "tx", "rx", "tx-180", "rx-180"; 784 + interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 785 + <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 786 + <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 787 + <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 788 + <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 789 + <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 790 + <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 791 + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 792 + <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 793 + <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 794 + <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>; 795 + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 796 + "rx-queue-0", "rx-queue-1", "rx-queue-2", 797 + "rx-queue-3", "tx-queue-0", "tx-queue-1", 798 + "tx-queue-2", "tx-queue-3"; 799 + resets = <&cpg 0xb1>; 800 + power-domains = <&cpg>; 801 + snps,multicast-filter-bins = <256>; 802 + snps,perfect-filter-entries = <128>; 803 + rx-fifo-depth = <8192>; 804 + tx-fifo-depth = <8192>; 805 + snps,fixed-burst; 806 + snps,no-pbl-x8; 807 + snps,force_thresh_dma_mode; 808 + snps,axi-config = <&stmmac_axi_setup>; 809 + snps,mtl-rx-config = <&mtl_rx_setup1>; 810 + snps,mtl-tx-config = <&mtl_tx_setup1>; 811 + snps,txpbl = <32>; 812 + snps,rxpbl = <32>; 813 + status = "disabled"; 814 + 815 + mdio1: mdio { 816 + compatible = "snps,dwmac-mdio"; 817 + #address-cells = <1>; 818 + #size-cells = <0>; 819 + }; 820 + 821 + mtl_rx_setup1: rx-queues-config { 822 + snps,rx-queues-to-use = <4>; 823 + snps,rx-sched-sp; 824 + 825 + queue0 { 826 + snps,dcb-algorithm; 827 + snps,priority = <0x1>; 828 + snps,map-to-dma-channel = <0>; 829 + }; 830 + 831 + queue1 { 832 + snps,dcb-algorithm; 833 + snps,priority = <0x2>; 834 + snps,map-to-dma-channel = <1>; 835 + }; 836 + 837 + queue2 { 838 + snps,dcb-algorithm; 839 + snps,priority = <0x4>; 840 + snps,map-to-dma-channel = <2>; 841 + }; 842 + 843 + queue3 { 844 + snps,dcb-algorithm; 845 + snps,priority = <0x8>; 846 + snps,map-to-dma-channel = <3>; 847 + }; 848 + }; 849 + 850 + mtl_tx_setup1: tx-queues-config { 851 + snps,tx-queues-to-use = <4>; 852 + 853 + queue0 { 854 + snps,dcb-algorithm; 855 + snps,priority = <0x1>; 856 + }; 857 + 858 + queue1 { 859 + snps,dcb-algorithm; 860 + snps,priority = <0x2>; 861 + }; 862 + 863 + queue2 { 864 + snps,dcb-algorithm; 865 + snps,priority = <0x4>; 866 + }; 867 + 868 + queue3 { 869 + snps,dcb-algorithm; 870 + snps,priority = <0x8>; 871 + }; 872 + }; 873 + }; 874 + 875 + cru: video@16000000 { 876 + compatible = "renesas,r9a09g047-cru"; 877 + reg = <0 0x16000000 0 0x400>; 878 + clocks = <&cpg CPG_MOD 0xd3>, 879 + <&cpg CPG_MOD 0xd4>, 880 + <&cpg CPG_MOD 0xd2>; 881 + clock-names = "video", "apb", "axi"; 882 + interrupts = <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 883 + <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 884 + <GIC_SPI 840 IRQ_TYPE_EDGE_RISING>, 885 + <GIC_SPI 841 IRQ_TYPE_EDGE_RISING>, 886 + <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>; 887 + interrupt-names = "image_conv", "axi_mst_err", 888 + "vd_addr_wend", "sd_addr_wend", 889 + "vsd_addr_wend"; 890 + resets = <&cpg 0xc5>, <&cpg 0xc6>; 891 + reset-names = "presetn", "aresetn"; 892 + power-domains = <&cpg>; 893 + status = "disabled"; 894 + 895 + ports { 896 + #address-cells = <1>; 897 + #size-cells = <0>; 898 + 899 + port@1 { 900 + #address-cells = <1>; 901 + #size-cells = <0>; 902 + 903 + reg = <1>; 904 + crucsi2: endpoint@0 { 905 + reg = <0>; 906 + remote-endpoint = <&csi2cru>; 907 + }; 908 + }; 909 + }; 910 + }; 911 + 912 + csi2: csi2@16000400 { 913 + compatible = "renesas,r9a09g047-csi2", "renesas,r9a09g057-csi2"; 914 + reg = <0 0x16000400 0 0xc00>; 915 + interrupts = <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>; 916 + clocks = <&cpg CPG_MOD 0xd3>, <&cpg CPG_MOD 0xd4>; 917 + clock-names = "video", "apb"; 918 + resets = <&cpg 0xc5>, <&cpg 0xc7>; 919 + reset-names = "presetn", "cmn-rstb"; 920 + power-domains = <&cpg>; 921 + status = "disabled"; 922 + 923 + ports { 924 + #address-cells = <1>; 925 + #size-cells = <0>; 926 + 927 + port@0 { 928 + reg = <0>; 929 + }; 930 + 931 + port@1 { 932 + #address-cells = <1>; 933 + #size-cells = <0>; 934 + reg = <1>; 935 + 936 + csi2cru: endpoint@0 { 937 + reg = <0>; 938 + remote-endpoint = <&crucsi2>; 939 + }; 940 + }; 941 + }; 942 + }; 943 + }; 944 + 945 + stmmac_axi_setup: stmmac-axi-config { 946 + snps,lpi_en; 947 + snps,wr_osr_lmt = <0xf>; 948 + snps,rd_osr_lmt = <0xf>; 949 + snps,blen = <16 8 4 0 0 0 0>; 693 950 }; 694 951 695 952 timer {
+21
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc-cru-csi-ov5645.dtso
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Device Tree overlay for the RZ/G3E SMARC EVK with OV5645 camera 4 + * connected to CSI and CRU enabled. 5 + * 6 + * Copyright (C) 2025 Renesas Electronics Corp. 7 + */ 8 + 9 + /dts-v1/; 10 + /plugin/; 11 + 12 + #include <dt-bindings/gpio/gpio.h> 13 + #include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h> 14 + 15 + #define OV5645_PARENT_I2C i2c0 16 + #include "rz-smarc-cru-csi-ov5645.dtsi" 17 + 18 + &ov5645 { 19 + enable-gpios = <&pinctrl RZG3E_GPIO(D, 6) GPIO_ACTIVE_HIGH>; 20 + reset-gpios = <&pinctrl RZG3E_GPIO(D, 7) GPIO_ACTIVE_LOW>; 21 + };
+10
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
··· 74 74 }; 75 75 #endif 76 76 77 + &i2c0 { 78 + pinctrl-0 = <&i2c0_pins>; 79 + pinctrl-names = "default"; 80 + }; 81 + 77 82 &pinctrl { 78 83 canfd_pins: canfd { 79 84 can1_pins: can1 { ··· 90 85 pinmux = <RZG3E_PORT_PINMUX(5, 2, 3)>, /* RX */ 91 86 <RZG3E_PORT_PINMUX(5, 3, 3)>; /* TX */ 92 87 }; 88 + }; 89 + 90 + i2c0_pins: i2c0 { 91 + pinmux = <RZG3E_PORT_PINMUX(D, 4, 4)>, /* SCL0 */ 92 + <RZG3E_PORT_PINMUX(D, 5, 4)>; /* SDA0 */ 93 93 }; 94 94 95 95 scif_pins: scif {
+635
arch/arm64/boot/dts/renesas/r9a09g056.dtsi
··· 123 123 }; 124 124 }; 125 125 126 + gpu_opp_table: opp-table-1 { 127 + compatible = "operating-points-v2"; 128 + 129 + opp-630000000 { 130 + opp-hz = /bits/ 64 <630000000>; 131 + opp-microvolt = <800000>; 132 + }; 133 + 134 + opp-315000000 { 135 + opp-hz = /bits/ 64 <315000000>; 136 + opp-microvolt = <800000>; 137 + }; 138 + 139 + opp-157500000 { 140 + opp-hz = /bits/ 64 <157500000>; 141 + opp-microvolt = <800000>; 142 + }; 143 + 144 + opp-78750000 { 145 + opp-hz = /bits/ 64 <78750000>; 146 + opp-microvolt = <800000>; 147 + }; 148 + 149 + opp-19687500 { 150 + opp-hz = /bits/ 64 <19687500>; 151 + opp-microvolt = <800000>; 152 + }; 153 + }; 154 + 126 155 psci { 127 156 compatible = "arm,psci-1.0", "arm,psci-0.2"; 128 157 method = "smc"; ··· 206 177 resets = <&cpg 0x30>; 207 178 }; 208 179 180 + ostm0: timer@11800000 { 181 + compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 182 + reg = <0x0 0x11800000 0x0 0x1000>; 183 + interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>; 184 + clocks = <&cpg CPG_MOD 0x43>; 185 + resets = <&cpg 0x6d>; 186 + power-domains = <&cpg>; 187 + status = "disabled"; 188 + }; 189 + 190 + ostm1: timer@11801000 { 191 + compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 192 + reg = <0x0 0x11801000 0x0 0x1000>; 193 + interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>; 194 + clocks = <&cpg CPG_MOD 0x44>; 195 + resets = <&cpg 0x6e>; 196 + power-domains = <&cpg>; 197 + status = "disabled"; 198 + }; 199 + 200 + ostm2: timer@14000000 { 201 + compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 202 + reg = <0x0 0x14000000 0x0 0x1000>; 203 + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; 204 + clocks = <&cpg CPG_MOD 0x45>; 205 + resets = <&cpg 0x6f>; 206 + power-domains = <&cpg>; 207 + status = "disabled"; 208 + }; 209 + 210 + ostm3: timer@14001000 { 211 + compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 212 + reg = <0x0 0x14001000 0x0 0x1000>; 213 + interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>; 214 + clocks = <&cpg CPG_MOD 0x46>; 215 + resets = <&cpg 0x70>; 216 + power-domains = <&cpg>; 217 + status = "disabled"; 218 + }; 219 + 220 + ostm4: timer@12c00000 { 221 + compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 222 + reg = <0x0 0x12c00000 0x0 0x1000>; 223 + interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 224 + clocks = <&cpg CPG_MOD 0x47>; 225 + resets = <&cpg 0x71>; 226 + power-domains = <&cpg>; 227 + status = "disabled"; 228 + }; 229 + 230 + ostm5: timer@12c01000 { 231 + compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 232 + reg = <0x0 0x12c01000 0x0 0x1000>; 233 + interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 234 + clocks = <&cpg CPG_MOD 0x48>; 235 + resets = <&cpg 0x72>; 236 + power-domains = <&cpg>; 237 + status = "disabled"; 238 + }; 239 + 240 + ostm6: timer@12c02000 { 241 + compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 242 + reg = <0x0 0x12c02000 0x0 0x1000>; 243 + interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 244 + clocks = <&cpg CPG_MOD 0x49>; 245 + resets = <&cpg 0x73>; 246 + power-domains = <&cpg>; 247 + status = "disabled"; 248 + }; 249 + 250 + ostm7: timer@12c03000 { 251 + compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 252 + reg = <0x0 0x12c03000 0x0 0x1000>; 253 + interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; 254 + clocks = <&cpg CPG_MOD 0x4a>; 255 + resets = <&cpg 0x74>; 256 + power-domains = <&cpg>; 257 + status = "disabled"; 258 + }; 259 + 260 + wdt0: watchdog@11c00400 { 261 + compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; 262 + reg = <0 0x11c00400 0 0x400>; 263 + clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>; 264 + clock-names = "pclk", "oscclk"; 265 + resets = <&cpg 0x75>; 266 + power-domains = <&cpg>; 267 + status = "disabled"; 268 + }; 269 + 270 + wdt1: watchdog@14400000 { 271 + compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; 272 + reg = <0 0x14400000 0 0x400>; 273 + clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; 274 + clock-names = "pclk", "oscclk"; 275 + resets = <&cpg 0x76>; 276 + power-domains = <&cpg>; 277 + status = "disabled"; 278 + }; 279 + 280 + wdt2: watchdog@13000000 { 281 + compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; 282 + reg = <0 0x13000000 0 0x400>; 283 + clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; 284 + clock-names = "pclk", "oscclk"; 285 + resets = <&cpg 0x77>; 286 + power-domains = <&cpg>; 287 + status = "disabled"; 288 + }; 289 + 290 + wdt3: watchdog@13000400 { 291 + compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; 292 + reg = <0 0x13000400 0 0x400>; 293 + clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; 294 + clock-names = "pclk", "oscclk"; 295 + resets = <&cpg 0x78>; 296 + power-domains = <&cpg>; 297 + status = "disabled"; 298 + }; 299 + 209 300 scif: serial@11c01400 { 210 301 compatible = "renesas,scif-r9a09g056", 211 302 "renesas,scif-r9a09g057"; ··· 348 199 status = "disabled"; 349 200 }; 350 201 202 + i2c0: i2c@14400400 { 203 + compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 204 + reg = <0 0x14400400 0 0x400>; 205 + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 206 + <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 207 + <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 208 + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 209 + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 210 + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 211 + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 212 + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 213 + interrupt-names = "tei", "ri", "ti", "spi", "sti", 214 + "naki", "ali", "tmoi"; 215 + clocks = <&cpg CPG_MOD 0x94>; 216 + resets = <&cpg 0x98>; 217 + power-domains = <&cpg>; 218 + #address-cells = <1>; 219 + #size-cells = <0>; 220 + status = "disabled"; 221 + }; 222 + 223 + i2c1: i2c@14400800 { 224 + compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 225 + reg = <0 0x14400800 0 0x400>; 226 + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 227 + <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 228 + <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 229 + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 230 + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 231 + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 232 + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 233 + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 234 + interrupt-names = "tei", "ri", "ti", "spi", "sti", 235 + "naki", "ali", "tmoi"; 236 + clocks = <&cpg CPG_MOD 0x95>; 237 + resets = <&cpg 0x99>; 238 + power-domains = <&cpg>; 239 + #address-cells = <1>; 240 + #size-cells = <0>; 241 + status = "disabled"; 242 + }; 243 + 244 + i2c2: i2c@14400c00 { 245 + compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 246 + reg = <0 0x14400c00 0 0x400>; 247 + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 248 + <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 249 + <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 250 + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 251 + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 252 + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 253 + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 254 + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 255 + interrupt-names = "tei", "ri", "ti", "spi", "sti", 256 + "naki", "ali", "tmoi"; 257 + clocks = <&cpg CPG_MOD 0x96>; 258 + resets = <&cpg 0x9a>; 259 + power-domains = <&cpg>; 260 + #address-cells = <1>; 261 + #size-cells = <0>; 262 + status = "disabled"; 263 + }; 264 + 265 + i2c3: i2c@14401000 { 266 + compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 267 + reg = <0 0x14401000 0 0x400>; 268 + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 269 + <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 270 + <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 271 + <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 272 + <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 273 + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 274 + <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 275 + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 276 + interrupt-names = "tei", "ri", "ti", "spi", "sti", 277 + "naki", "ali", "tmoi"; 278 + clocks = <&cpg CPG_MOD 0x97>; 279 + resets = <&cpg 0x9b>; 280 + power-domains = <&cpg>; 281 + #address-cells = <1>; 282 + #size-cells = <0>; 283 + status = "disabled"; 284 + }; 285 + 286 + i2c4: i2c@14401400 { 287 + compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 288 + reg = <0 0x14401400 0 0x400>; 289 + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 290 + <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 291 + <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 292 + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 293 + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 294 + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 295 + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 296 + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 297 + interrupt-names = "tei", "ri", "ti", "spi", "sti", 298 + "naki", "ali", "tmoi"; 299 + clocks = <&cpg CPG_MOD 0x98>; 300 + resets = <&cpg 0x9c>; 301 + power-domains = <&cpg>; 302 + #address-cells = <1>; 303 + #size-cells = <0>; 304 + status = "disabled"; 305 + }; 306 + 307 + i2c5: i2c@14401800 { 308 + compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 309 + reg = <0 0x14401800 0 0x400>; 310 + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 311 + <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 312 + <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 313 + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 314 + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 315 + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 316 + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 317 + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 318 + interrupt-names = "tei", "ri", "ti", "spi", "sti", 319 + "naki", "ali", "tmoi"; 320 + clocks = <&cpg CPG_MOD 0x99>; 321 + resets = <&cpg 0x9d>; 322 + power-domains = <&cpg>; 323 + #address-cells = <1>; 324 + #size-cells = <0>; 325 + status = "disabled"; 326 + }; 327 + 328 + i2c6: i2c@14401c00 { 329 + compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 330 + reg = <0 0x14401c00 0 0x400>; 331 + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 332 + <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 333 + <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 334 + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 335 + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 336 + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 337 + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 338 + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 339 + interrupt-names = "tei", "ri", "ti", "spi", "sti", 340 + "naki", "ali", "tmoi"; 341 + clocks = <&cpg CPG_MOD 0x9a>; 342 + resets = <&cpg 0x9e>; 343 + power-domains = <&cpg>; 344 + #address-cells = <1>; 345 + #size-cells = <0>; 346 + status = "disabled"; 347 + }; 348 + 349 + i2c7: i2c@14402000 { 350 + compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 351 + reg = <0 0x14402000 0 0x400>; 352 + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 353 + <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 354 + <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 355 + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 356 + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 357 + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 358 + <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 359 + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 360 + interrupt-names = "tei", "ri", "ti", "spi", "sti", 361 + "naki", "ali", "tmoi"; 362 + clocks = <&cpg CPG_MOD 0x9b>; 363 + resets = <&cpg 0x9f>; 364 + power-domains = <&cpg>; 365 + #address-cells = <1>; 366 + #size-cells = <0>; 367 + status = "disabled"; 368 + }; 369 + 370 + i2c8: i2c@11c01000 { 371 + compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 372 + reg = <0 0x11c01000 0 0x400>; 373 + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 374 + <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 375 + <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 376 + <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 377 + <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 378 + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 379 + <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 380 + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 381 + interrupt-names = "tei", "ri", "ti", "spi", "sti", 382 + "naki", "ali", "tmoi"; 383 + clocks = <&cpg CPG_MOD 0x93>; 384 + resets = <&cpg 0xa0>; 385 + power-domains = <&cpg>; 386 + #address-cells = <1>; 387 + #size-cells = <0>; 388 + status = "disabled"; 389 + }; 390 + 391 + gpu: gpu@14850000 { 392 + compatible = "renesas,r9a09g056-mali", 393 + "arm,mali-bifrost"; 394 + reg = <0x0 0x14850000 0x0 0x10000>; 395 + interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>, 396 + <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 397 + <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>, 398 + <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>; 399 + interrupt-names = "job", "mmu", "gpu", "event"; 400 + clocks = <&cpg CPG_MOD 0xf0>, 401 + <&cpg CPG_MOD 0xf1>, 402 + <&cpg CPG_MOD 0xf2>; 403 + clock-names = "gpu", "bus", "bus_ace"; 404 + resets = <&cpg 0xdd>, 405 + <&cpg 0xde>, 406 + <&cpg 0xdf>; 407 + reset-names = "rst", "axi_rst", "ace_rst"; 408 + power-domains = <&cpg>; 409 + operating-points-v2 = <&gpu_opp_table>; 410 + status = "disabled"; 411 + }; 412 + 351 413 gic: interrupt-controller@14900000 { 352 414 compatible = "arm,gic-v3"; 353 415 reg = <0x0 0x14900000 0 0x20000>, ··· 567 207 #address-cells = <0>; 568 208 interrupt-controller; 569 209 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 210 + }; 211 + 212 + ohci0: usb@15800000 { 213 + compatible = "generic-ohci"; 214 + reg = <0 0x15800000 0 0x100>; 215 + interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>; 216 + clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 217 + resets = <&usb20phyrst>, <&cpg 0xac>; 218 + phys = <&usb2_phy0 1>; 219 + phy-names = "usb"; 220 + power-domains = <&cpg>; 221 + status = "disabled"; 222 + }; 223 + 224 + ehci0: usb@15800100 { 225 + compatible = "generic-ehci"; 226 + reg = <0 0x15800100 0 0x100>; 227 + interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>; 228 + clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 229 + resets = <&usb20phyrst>, <&cpg 0xac>; 230 + phys = <&usb2_phy0 2>; 231 + phy-names = "usb"; 232 + companion = <&ohci0>; 233 + power-domains = <&cpg>; 234 + status = "disabled"; 235 + }; 236 + 237 + usb2_phy0: usb-phy@15800200 { 238 + compatible = "renesas,usb2-phy-r9a09g056", "renesas,usb2-phy-r9a09g057"; 239 + reg = <0 0x15800200 0 0x700>; 240 + interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>; 241 + clocks = <&cpg CPG_MOD 0xb3>, 242 + <&cpg CPG_CORE R9A09G056_USB2_0_CLK_CORE0>; 243 + clock-names = "fck", "usb_x1"; 244 + resets = <&usb20phyrst>; 245 + #phy-cells = <1>; 246 + power-domains = <&cpg>; 247 + status = "disabled"; 248 + }; 249 + 250 + hsusb: usb@15820000 { 251 + compatible = "renesas,usbhs-r9a09g056", 252 + "renesas,rzg2l-usbhs"; 253 + reg = <0 0x15820000 0 0x10000>; 254 + interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>, 255 + <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 256 + <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 257 + <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>; 258 + clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>; 259 + resets = <&usb20phyrst>, 260 + <&cpg 0xae>; 261 + phys = <&usb2_phy0 3>; 262 + phy-names = "usb"; 263 + power-domains = <&cpg>; 264 + status = "disabled"; 265 + }; 266 + 267 + usb20phyrst: usb20phy-reset@15830000 { 268 + compatible = "renesas,r9a09g056-usb2phy-reset", 269 + "renesas,r9a09g057-usb2phy-reset"; 270 + reg = <0 0x15830000 0 0x10000>; 271 + clocks = <&cpg CPG_MOD 0xb6>; 272 + resets = <&cpg 0xaf>; 273 + power-domains = <&cpg>; 274 + #reset-cells = <0>; 275 + status = "disabled"; 570 276 }; 571 277 572 278 sdhi0: mmc@15c00000 { ··· 694 268 status = "disabled"; 695 269 }; 696 270 }; 271 + 272 + eth0: ethernet@15c30000 { 273 + compatible = "renesas,r9a09g056-gbeth", "renesas,rzv2h-gbeth", 274 + "snps,dwmac-5.20"; 275 + reg = <0 0x15c30000 0 0x10000>; 276 + interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 277 + <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 278 + <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 279 + <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 280 + <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 281 + <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 282 + <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 283 + <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 284 + <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 285 + <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 286 + <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; 287 + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 288 + "rx-queue-0", "rx-queue-1", "rx-queue-2", 289 + "rx-queue-3", "tx-queue-0", "tx-queue-1", 290 + "tx-queue-2", "tx-queue-3"; 291 + clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 292 + <&cpg CPG_CORE R9A09G056_GBETH_0_CLK_PTP_REF_I>, 293 + <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 294 + <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 295 + clock-names = "stmmaceth", "pclk", "ptp_ref", 296 + "tx", "rx", "tx-180", "rx-180"; 297 + resets = <&cpg 0xb0>; 298 + power-domains = <&cpg>; 299 + snps,multicast-filter-bins = <256>; 300 + snps,perfect-filter-entries = <128>; 301 + rx-fifo-depth = <8192>; 302 + tx-fifo-depth = <8192>; 303 + snps,fixed-burst; 304 + snps,no-pbl-x8; 305 + snps,force_thresh_dma_mode; 306 + snps,axi-config = <&stmmac_axi_setup>; 307 + snps,mtl-rx-config = <&mtl_rx_setup0>; 308 + snps,mtl-tx-config = <&mtl_tx_setup0>; 309 + snps,txpbl = <32>; 310 + snps,rxpbl = <32>; 311 + status = "disabled"; 312 + 313 + mdio0: mdio { 314 + compatible = "snps,dwmac-mdio"; 315 + #address-cells = <1>; 316 + #size-cells = <0>; 317 + }; 318 + 319 + mtl_rx_setup0: rx-queues-config { 320 + snps,rx-queues-to-use = <4>; 321 + snps,rx-sched-sp; 322 + 323 + queue0 { 324 + snps,dcb-algorithm; 325 + snps,priority = <0x1>; 326 + snps,map-to-dma-channel = <0>; 327 + }; 328 + 329 + queue1 { 330 + snps,dcb-algorithm; 331 + snps,priority = <0x2>; 332 + snps,map-to-dma-channel = <1>; 333 + }; 334 + 335 + queue2 { 336 + snps,dcb-algorithm; 337 + snps,priority = <0x4>; 338 + snps,map-to-dma-channel = <2>; 339 + }; 340 + 341 + queue3 { 342 + snps,dcb-algorithm; 343 + snps,priority = <0x8>; 344 + snps,map-to-dma-channel = <3>; 345 + }; 346 + }; 347 + 348 + mtl_tx_setup0: tx-queues-config { 349 + snps,tx-queues-to-use = <4>; 350 + 351 + queue0 { 352 + snps,dcb-algorithm; 353 + snps,priority = <0x1>; 354 + }; 355 + 356 + queue1 { 357 + snps,dcb-algorithm; 358 + snps,priority = <0x2>; 359 + }; 360 + 361 + queue2 { 362 + snps,dcb-algorithm; 363 + snps,priority = <0x4>; 364 + }; 365 + 366 + queue3 { 367 + snps,dcb-algorithm; 368 + snps,priority = <0x8>; 369 + }; 370 + }; 371 + }; 372 + 373 + eth1: ethernet@15c40000 { 374 + compatible = "renesas,r9a09g056-gbeth", "renesas,rzv2h-gbeth", 375 + "snps,dwmac-5.20"; 376 + reg = <0 0x15c40000 0 0x10000>; 377 + interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 378 + <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 379 + <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 380 + <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 381 + <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 382 + <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 383 + <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 384 + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 385 + <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 386 + <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 387 + <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>; 388 + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 389 + "rx-queue-0", "rx-queue-1", "rx-queue-2", 390 + "rx-queue-3", "tx-queue-0", "tx-queue-1", 391 + "tx-queue-2", "tx-queue-3"; 392 + clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 393 + <&cpg CPG_CORE R9A09G056_GBETH_1_CLK_PTP_REF_I>, 394 + <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 395 + <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 396 + clock-names = "stmmaceth", "pclk", "ptp_ref", 397 + "tx", "rx", "tx-180", "rx-180"; 398 + resets = <&cpg 0xb1>; 399 + power-domains = <&cpg>; 400 + snps,multicast-filter-bins = <256>; 401 + snps,perfect-filter-entries = <128>; 402 + rx-fifo-depth = <8192>; 403 + tx-fifo-depth = <8192>; 404 + snps,fixed-burst; 405 + snps,no-pbl-x8; 406 + snps,force_thresh_dma_mode; 407 + snps,axi-config = <&stmmac_axi_setup>; 408 + snps,mtl-rx-config = <&mtl_rx_setup1>; 409 + snps,mtl-tx-config = <&mtl_tx_setup1>; 410 + snps,txpbl = <32>; 411 + snps,rxpbl = <32>; 412 + status = "disabled"; 413 + 414 + mdio1: mdio { 415 + compatible = "snps,dwmac-mdio"; 416 + #address-cells = <1>; 417 + #size-cells = <0>; 418 + }; 419 + 420 + mtl_rx_setup1: rx-queues-config { 421 + snps,rx-queues-to-use = <4>; 422 + snps,rx-sched-sp; 423 + 424 + queue0 { 425 + snps,dcb-algorithm; 426 + snps,priority = <0x1>; 427 + snps,map-to-dma-channel = <0>; 428 + }; 429 + 430 + queue1 { 431 + snps,dcb-algorithm; 432 + snps,priority = <0x2>; 433 + snps,map-to-dma-channel = <1>; 434 + }; 435 + 436 + queue2 { 437 + snps,dcb-algorithm; 438 + snps,priority = <0x4>; 439 + snps,map-to-dma-channel = <2>; 440 + }; 441 + 442 + queue3 { 443 + snps,dcb-algorithm; 444 + snps,priority = <0x8>; 445 + snps,map-to-dma-channel = <3>; 446 + }; 447 + }; 448 + 449 + mtl_tx_setup1: tx-queues-config { 450 + snps,tx-queues-to-use = <4>; 451 + 452 + queue0 { 453 + snps,dcb-algorithm; 454 + snps,priority = <0x1>; 455 + }; 456 + 457 + queue1 { 458 + snps,dcb-algorithm; 459 + snps,priority = <0x2>; 460 + }; 461 + 462 + queue2 { 463 + snps,dcb-algorithm; 464 + snps,priority = <0x4>; 465 + }; 466 + 467 + queue3 { 468 + snps,dcb-algorithm; 469 + snps,priority = <0x8>; 470 + }; 471 + }; 472 + }; 473 + }; 474 + 475 + stmmac_axi_setup: stmmac-axi-config { 476 + snps,lpi_en; 477 + snps,wr_osr_lmt = <0xf>; 478 + snps,rd_osr_lmt = <0xf>; 479 + snps,blen = <16 8 4 0 0 0 0>; 697 480 }; 698 481 699 482 timer {
+262
arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
··· 15 15 compatible = "renesas,rzv2n-evk", "renesas,r9a09g056n48", "renesas,r9a09g056"; 16 16 17 17 aliases { 18 + ethernet0 = &eth0; 19 + ethernet1 = &eth1; 20 + i2c0 = &i2c0; 21 + i2c1 = &i2c1; 22 + i2c2 = &i2c2; 23 + i2c3 = &i2c3; 24 + i2c6 = &i2c6; 25 + i2c7 = &i2c7; 26 + i2c8 = &i2c8; 18 27 mmc1 = &sdhi1; 19 28 serial0 = &scif; 20 29 }; ··· 37 28 device_type = "memory"; 38 29 /* first 128MB is reserved for secure area. */ 39 30 reg = <0x0 0x48000000 0x1 0xf8000000>; 31 + }; 32 + 33 + reg_0p8v: regulator-0p8v { 34 + compatible = "regulator-fixed"; 35 + regulator-name = "fixed-0.8V"; 36 + regulator-min-microvolt = <800000>; 37 + regulator-max-microvolt = <800000>; 38 + regulator-boot-on; 39 + regulator-always-on; 40 40 }; 41 41 42 42 reg_3p3v: regulator-3p3v { ··· 66 48 gpios-states = <0>; 67 49 states = <3300000 0>, <1800000 1>; 68 50 }; 51 + 52 + /* 32.768kHz crystal */ 53 + x6: x6-clock { 54 + compatible = "fixed-clock"; 55 + #clock-cells = <0>; 56 + clock-frequency = <32768>; 57 + }; 69 58 }; 70 59 71 60 &audio_extal_clk { 72 61 clock-frequency = <22579200>; 73 62 }; 74 63 64 + &ehci0 { 65 + dr_mode = "otg"; 66 + status = "okay"; 67 + }; 68 + 69 + &eth0 { 70 + pinctrl-0 = <&eth0_pins>; 71 + pinctrl-names = "default"; 72 + phy-handle = <&phy0>; 73 + phy-mode = "rgmii-id"; 74 + status = "okay"; 75 + }; 76 + 77 + &eth1 { 78 + pinctrl-0 = <&eth1_pins>; 79 + pinctrl-names = "default"; 80 + phy-handle = <&phy1>; 81 + phy-mode = "rgmii-id"; 82 + status = "okay"; 83 + }; 84 + 85 + &gpu { 86 + status = "okay"; 87 + mali-supply = <&reg_0p8v>; 88 + }; 89 + 90 + &hsusb { 91 + dr_mode = "otg"; 92 + status = "okay"; 93 + }; 94 + 95 + &i2c0 { 96 + pinctrl-0 = <&i2c0_pins>; 97 + pinctrl-names = "default"; 98 + clock-frequency = <400000>; 99 + status = "okay"; 100 + }; 101 + 102 + &i2c1 { 103 + pinctrl-0 = <&i2c1_pins>; 104 + pinctrl-names = "default"; 105 + clock-frequency = <400000>; 106 + status = "okay"; 107 + }; 108 + 109 + &i2c2 { 110 + pinctrl-0 = <&i2c2_pins>; 111 + pinctrl-names = "default"; 112 + clock-frequency = <400000>; 113 + status = "okay"; 114 + }; 115 + 116 + &i2c3 { 117 + pinctrl-0 = <&i2c3_pins>; 118 + pinctrl-names = "default"; 119 + clock-frequency = <400000>; 120 + status = "okay"; 121 + }; 122 + 123 + &i2c6 { 124 + pinctrl-0 = <&i2c6_pins>; 125 + pinctrl-names = "default"; 126 + clock-frequency = <400000>; 127 + status = "okay"; 128 + }; 129 + 130 + &i2c7 { 131 + pinctrl-0 = <&i2c7_pins>; 132 + pinctrl-names = "default"; 133 + clock-frequency = <400000>; 134 + status = "okay"; 135 + }; 136 + 137 + &i2c8 { 138 + pinctrl-0 = <&i2c8_pins>; 139 + pinctrl-names = "default"; 140 + clock-frequency = <400000>; 141 + status = "okay"; 142 + 143 + raa215300: pmic@12 { 144 + compatible = "renesas,raa215300"; 145 + reg = <0x12>, <0x6f>; 146 + reg-names = "main", "rtc"; 147 + clocks = <&x6>; 148 + clock-names = "xin"; 149 + }; 150 + }; 151 + 152 + &mdio0 { 153 + phy0: ethernet-phy@0 { 154 + compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; 155 + reg = <0>; 156 + rxc-skew-psec = <0>; 157 + txc-skew-psec = <0>; 158 + rxdv-skew-psec = <0>; 159 + txdv-skew-psec = <0>; 160 + rxd0-skew-psec = <0>; 161 + rxd1-skew-psec = <0>; 162 + rxd2-skew-psec = <0>; 163 + rxd3-skew-psec = <0>; 164 + txd0-skew-psec = <0>; 165 + txd1-skew-psec = <0>; 166 + txd2-skew-psec = <0>; 167 + txd3-skew-psec = <0>; 168 + }; 169 + }; 170 + 171 + &mdio1 { 172 + phy1: ethernet-phy@1 { 173 + compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; 174 + reg = <0>; 175 + rxc-skew-psec = <0>; 176 + txc-skew-psec = <0>; 177 + rxdv-skew-psec = <0>; 178 + txdv-skew-psec = <0>; 179 + rxd0-skew-psec = <0>; 180 + rxd1-skew-psec = <0>; 181 + rxd2-skew-psec = <0>; 182 + rxd3-skew-psec = <0>; 183 + txd0-skew-psec = <0>; 184 + txd1-skew-psec = <0>; 185 + txd2-skew-psec = <0>; 186 + txd3-skew-psec = <0>; 187 + }; 188 + }; 189 + 190 + &ohci0 { 191 + dr_mode = "otg"; 192 + status = "okay"; 193 + }; 194 + 195 + &ostm0 { 196 + status = "okay"; 197 + }; 198 + 199 + &ostm1 { 200 + status = "okay"; 201 + }; 202 + 203 + &ostm2 { 204 + status = "okay"; 205 + }; 206 + 207 + &ostm3 { 208 + status = "okay"; 209 + }; 210 + 211 + &ostm4 { 212 + status = "okay"; 213 + }; 214 + 215 + &ostm5 { 216 + status = "okay"; 217 + }; 218 + 219 + &ostm6 { 220 + status = "okay"; 221 + }; 222 + 223 + &ostm7 { 224 + status = "okay"; 225 + }; 226 + 75 227 &pinctrl { 228 + eth0_pins: eth0 { 229 + pins = "ET0_TXC_TXCLK"; 230 + output-enable; 231 + }; 232 + 233 + eth1_pins: eth0 { 234 + pins = "ET1_TXC_TXCLK"; 235 + output-enable; 236 + }; 237 + 238 + i2c0_pins: i2c0 { 239 + pinmux = <RZV2N_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */ 240 + <RZV2N_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */ 241 + }; 242 + 243 + i2c1_pins: i2c1 { 244 + pinmux = <RZV2N_PORT_PINMUX(3, 2, 1)>, /* I2C1_SDA */ 245 + <RZV2N_PORT_PINMUX(3, 3, 1)>; /* I2C1_SCL */ 246 + }; 247 + 248 + i2c2_pins: i2c2 { 249 + pinmux = <RZV2N_PORT_PINMUX(2, 0, 4)>, /* I2C2_SDA */ 250 + <RZV2N_PORT_PINMUX(2, 1, 4)>; /* I2C2_SCL */ 251 + }; 252 + 253 + i2c3_pins: i2c3 { 254 + pinmux = <RZV2N_PORT_PINMUX(3, 6, 1)>, /* I2C3_SDA */ 255 + <RZV2N_PORT_PINMUX(3, 7, 1)>; /* I2C3_SCL */ 256 + }; 257 + 258 + i2c6_pins: i2c6 { 259 + pinmux = <RZV2N_PORT_PINMUX(4, 4, 1)>, /* I2C6_SDA */ 260 + <RZV2N_PORT_PINMUX(4, 5, 1)>; /* I2C6_SCL */ 261 + /* There are no pull-up resistors on the EVK, so enable the internal pull-up */ 262 + bias-pull-up; 263 + }; 264 + 265 + i2c7_pins: i2c7 { 266 + pinmux = <RZV2N_PORT_PINMUX(4, 6, 1)>, /* I2C7_SDA */ 267 + <RZV2N_PORT_PINMUX(4, 7, 1)>; /* I2C7_SCL */ 268 + /* There are no pull-up resistors on the EVK, so enable the internal pull-up */ 269 + bias-pull-up; 270 + }; 271 + 272 + i2c8_pins: i2c8 { 273 + pinmux = <RZV2N_PORT_PINMUX(0, 6, 1)>, /* I2C8_SDA */ 274 + <RZV2N_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */ 275 + }; 276 + 76 277 scif_pins: scif { 77 278 pins = "SCIF_TXD", "SCIF_RXD"; 78 279 renesas,output-impedance = <1>; ··· 322 85 slew-rate = <0>; 323 86 }; 324 87 }; 88 + 89 + usb20_pins: usb20 { 90 + ovc { 91 + pinmux = <RZV2N_PORT_PINMUX(9, 6, 14)>; /* OVC */ 92 + }; 93 + 94 + vbus { 95 + pinmux = <RZV2N_PORT_PINMUX(9, 5, 14)>; /* VBUS */ 96 + }; 97 + }; 325 98 }; 326 99 327 100 &qextal_clk { ··· 357 110 bus-width = <4>; 358 111 sd-uhs-sdr50; 359 112 sd-uhs-sdr104; 113 + status = "okay"; 114 + }; 115 + 116 + &usb20phyrst { 117 + status = "okay"; 118 + }; 119 + 120 + &usb2_phy0 { 121 + pinctrl-0 = <&usb20_pins>; 122 + pinctrl-names = "default"; 123 + 124 + status = "okay"; 125 + }; 126 + 127 + &wdt1 { 360 128 status = "okay"; 361 129 };
+322
arch/arm64/boot/dts/renesas/r9a09g057.dtsi
··· 807 807 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 808 808 }; 809 809 810 + ohci0: usb@15800000 { 811 + compatible = "generic-ohci"; 812 + reg = <0 0x15800000 0 0x100>; 813 + interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>; 814 + clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 815 + resets = <&usb20phyrst>, <&cpg 0xac>; 816 + phys = <&usb2_phy0 1>; 817 + phy-names = "usb"; 818 + power-domains = <&cpg>; 819 + status = "disabled"; 820 + }; 821 + 822 + ohci1: usb@15810000 { 823 + compatible = "generic-ohci"; 824 + reg = <0 0x15810000 0 0x100>; 825 + interrupts = <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>; 826 + clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>; 827 + resets = <&usb21phyrst>, <&cpg 0xad>; 828 + phys = <&usb2_phy1 1>; 829 + phy-names = "usb"; 830 + power-domains = <&cpg>; 831 + status = "disabled"; 832 + }; 833 + 834 + ehci0: usb@15800100 { 835 + compatible = "generic-ehci"; 836 + reg = <0 0x15800100 0 0x100>; 837 + interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>; 838 + clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 839 + resets = <&usb20phyrst>, <&cpg 0xac>; 840 + phys = <&usb2_phy0 2>; 841 + phy-names = "usb"; 842 + companion = <&ohci0>; 843 + power-domains = <&cpg>; 844 + status = "disabled"; 845 + }; 846 + 847 + ehci1: usb@15810100 { 848 + compatible = "generic-ehci"; 849 + reg = <0 0x15810100 0 0x100>; 850 + interrupts = <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>; 851 + clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>; 852 + resets = <&usb21phyrst>, <&cpg 0xad>; 853 + phys = <&usb2_phy1 2>; 854 + phy-names = "usb"; 855 + companion = <&ohci1>; 856 + power-domains = <&cpg>; 857 + status = "disabled"; 858 + }; 859 + 860 + usb2_phy0: usb-phy@15800200 { 861 + compatible = "renesas,usb2-phy-r9a09g057"; 862 + reg = <0 0x15800200 0 0x700>; 863 + interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>; 864 + clocks = <&cpg CPG_MOD 0xb3>, 865 + <&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE0>; 866 + clock-names = "fck", "usb_x1"; 867 + resets = <&usb20phyrst>; 868 + #phy-cells = <1>; 869 + power-domains = <&cpg>; 870 + status = "disabled"; 871 + }; 872 + 873 + usb2_phy1: usb-phy@15810200 { 874 + compatible = "renesas,usb2-phy-r9a09g057"; 875 + reg = <0 0x15810200 0 0x700>; 876 + interrupts = <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>; 877 + clocks = <&cpg CPG_MOD 0xb4>, 878 + <&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE1>; 879 + clock-names = "fck", "usb_x1"; 880 + resets = <&usb21phyrst>; 881 + #phy-cells = <1>; 882 + power-domains = <&cpg>; 883 + status = "disabled"; 884 + }; 885 + 886 + hsusb: usb@15820000 { 887 + compatible = "renesas,usbhs-r9a09g057", 888 + "renesas,rzg2l-usbhs"; 889 + reg = <0 0x15820000 0 0x10000>; 890 + interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>, 891 + <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 892 + <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 893 + <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>; 894 + clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>; 895 + resets = <&usb20phyrst>, 896 + <&cpg 0xae>; 897 + phys = <&usb2_phy0 3>; 898 + phy-names = "usb"; 899 + power-domains = <&cpg>; 900 + status = "disabled"; 901 + }; 902 + 903 + usb20phyrst: usb20phy-reset@15830000 { 904 + compatible = "renesas,r9a09g057-usb2phy-reset"; 905 + reg = <0 0x15830000 0 0x10000>; 906 + clocks = <&cpg CPG_MOD 0xb6>; 907 + resets = <&cpg 0xaf>; 908 + power-domains = <&cpg>; 909 + #reset-cells = <0>; 910 + status = "disabled"; 911 + }; 912 + 913 + usb21phyrst: usb21phy-reset@15840000 { 914 + compatible = "renesas,r9a09g057-usb2phy-reset"; 915 + reg = <0 0x15840000 0 0x10000>; 916 + clocks = <&cpg CPG_MOD 0xb7>; 917 + resets = <&cpg 0xaf>; 918 + power-domains = <&cpg>; 919 + #reset-cells = <0>; 920 + status = "disabled"; 921 + }; 922 + 810 923 sdhi0: mmc@15c00000 { 811 924 compatible = "renesas,sdhi-r9a09g057"; 812 925 reg = <0x0 0x15c00000 0 0x10000>; ··· 979 866 status = "disabled"; 980 867 }; 981 868 }; 869 + 870 + eth0: ethernet@15c30000 { 871 + compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", 872 + "snps,dwmac-5.20"; 873 + reg = <0 0x15c30000 0 0x10000>; 874 + interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 875 + <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 876 + <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 877 + <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 878 + <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 879 + <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 880 + <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 881 + <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 882 + <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 883 + <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 884 + <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; 885 + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 886 + "rx-queue-0", "rx-queue-1", "rx-queue-2", 887 + "rx-queue-3", "tx-queue-0", "tx-queue-1", 888 + "tx-queue-2", "tx-queue-3"; 889 + clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 890 + <&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>, 891 + <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 892 + <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 893 + clock-names = "stmmaceth", "pclk", "ptp_ref", 894 + "tx", "rx", "tx-180", "rx-180"; 895 + resets = <&cpg 0xb0>; 896 + power-domains = <&cpg>; 897 + snps,multicast-filter-bins = <256>; 898 + snps,perfect-filter-entries = <128>; 899 + rx-fifo-depth = <8192>; 900 + tx-fifo-depth = <8192>; 901 + snps,fixed-burst; 902 + snps,no-pbl-x8; 903 + snps,force_thresh_dma_mode; 904 + snps,axi-config = <&stmmac_axi_setup>; 905 + snps,mtl-rx-config = <&mtl_rx_setup0>; 906 + snps,mtl-tx-config = <&mtl_tx_setup0>; 907 + snps,txpbl = <32>; 908 + snps,rxpbl = <32>; 909 + status = "disabled"; 910 + 911 + mdio0: mdio { 912 + compatible = "snps,dwmac-mdio"; 913 + #address-cells = <1>; 914 + #size-cells = <0>; 915 + }; 916 + 917 + mtl_rx_setup0: rx-queues-config { 918 + snps,rx-queues-to-use = <4>; 919 + snps,rx-sched-sp; 920 + 921 + queue0 { 922 + snps,dcb-algorithm; 923 + snps,priority = <0x1>; 924 + snps,map-to-dma-channel = <0>; 925 + }; 926 + 927 + queue1 { 928 + snps,dcb-algorithm; 929 + snps,priority = <0x2>; 930 + snps,map-to-dma-channel = <1>; 931 + }; 932 + 933 + queue2 { 934 + snps,dcb-algorithm; 935 + snps,priority = <0x4>; 936 + snps,map-to-dma-channel = <2>; 937 + }; 938 + 939 + queue3 { 940 + snps,dcb-algorithm; 941 + snps,priority = <0x8>; 942 + snps,map-to-dma-channel = <3>; 943 + }; 944 + }; 945 + 946 + mtl_tx_setup0: tx-queues-config { 947 + snps,tx-queues-to-use = <4>; 948 + 949 + queue0 { 950 + snps,dcb-algorithm; 951 + snps,priority = <0x1>; 952 + }; 953 + 954 + queue1 { 955 + snps,dcb-algorithm; 956 + snps,priority = <0x2>; 957 + }; 958 + 959 + queue2 { 960 + snps,dcb-algorithm; 961 + snps,priority = <0x4>; 962 + }; 963 + 964 + queue3 { 965 + snps,dcb-algorithm; 966 + snps,priority = <0x8>; 967 + }; 968 + }; 969 + }; 970 + 971 + eth1: ethernet@15c40000 { 972 + compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", 973 + "snps,dwmac-5.20"; 974 + reg = <0 0x15c40000 0 0x10000>; 975 + interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 976 + <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 977 + <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 978 + <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 979 + <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 980 + <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 981 + <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 982 + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 983 + <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 984 + <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 985 + <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>; 986 + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 987 + "rx-queue-0", "rx-queue-1", "rx-queue-2", 988 + "rx-queue-3", "tx-queue-0", "tx-queue-1", 989 + "tx-queue-2", "tx-queue-3"; 990 + clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 991 + <&cpg CPG_CORE R9A09G057_GBETH_1_CLK_PTP_REF_I>, 992 + <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 993 + <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 994 + clock-names = "stmmaceth", "pclk", "ptp_ref", 995 + "tx", "rx", "tx-180", "rx-180"; 996 + resets = <&cpg 0xb1>; 997 + power-domains = <&cpg>; 998 + snps,multicast-filter-bins = <256>; 999 + snps,perfect-filter-entries = <128>; 1000 + rx-fifo-depth = <8192>; 1001 + tx-fifo-depth = <8192>; 1002 + snps,fixed-burst; 1003 + snps,no-pbl-x8; 1004 + snps,force_thresh_dma_mode; 1005 + snps,axi-config = <&stmmac_axi_setup>; 1006 + snps,mtl-rx-config = <&mtl_rx_setup1>; 1007 + snps,mtl-tx-config = <&mtl_tx_setup1>; 1008 + snps,txpbl = <32>; 1009 + snps,rxpbl = <32>; 1010 + status = "disabled"; 1011 + 1012 + mdio1: mdio { 1013 + compatible = "snps,dwmac-mdio"; 1014 + #address-cells = <1>; 1015 + #size-cells = <0>; 1016 + }; 1017 + 1018 + mtl_rx_setup1: rx-queues-config { 1019 + snps,rx-queues-to-use = <4>; 1020 + snps,rx-sched-sp; 1021 + 1022 + queue0 { 1023 + snps,dcb-algorithm; 1024 + snps,priority = <0x1>; 1025 + snps,map-to-dma-channel = <0>; 1026 + }; 1027 + 1028 + queue1 { 1029 + snps,dcb-algorithm; 1030 + snps,priority = <0x2>; 1031 + snps,map-to-dma-channel = <1>; 1032 + }; 1033 + 1034 + queue2 { 1035 + snps,dcb-algorithm; 1036 + snps,priority = <0x4>; 1037 + snps,map-to-dma-channel = <2>; 1038 + }; 1039 + 1040 + queue3 { 1041 + snps,dcb-algorithm; 1042 + snps,priority = <0x8>; 1043 + snps,map-to-dma-channel = <3>; 1044 + }; 1045 + }; 1046 + 1047 + mtl_tx_setup1: tx-queues-config { 1048 + snps,tx-queues-to-use = <4>; 1049 + 1050 + queue0 { 1051 + snps,dcb-algorithm; 1052 + snps,priority = <0x1>; 1053 + }; 1054 + 1055 + queue1 { 1056 + snps,dcb-algorithm; 1057 + snps,priority = <0x2>; 1058 + }; 1059 + 1060 + queue2 { 1061 + snps,dcb-algorithm; 1062 + snps,priority = <0x4>; 1063 + }; 1064 + 1065 + queue3 { 1066 + snps,dcb-algorithm; 1067 + snps,priority = <0x8>; 1068 + }; 1069 + }; 1070 + }; 1071 + }; 1072 + 1073 + stmmac_axi_setup: stmmac-axi-config { 1074 + snps,lpi_en; 1075 + snps,wr_osr_lmt = <0xf>; 1076 + snps,rd_osr_lmt = <0xf>; 1077 + snps,blen = <16 8 4 0 0 0 0>; 982 1078 }; 983 1079 984 1080 timer {
+148 -2
arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
··· 16 16 compatible = "renesas,rzv2h-evk", "renesas,r9a09g057h44", "renesas,r9a09g057"; 17 17 18 18 aliases { 19 + ethernet0 = &eth0; 20 + ethernet1 = &eth1; 19 21 i2c0 = &i2c0; 20 22 i2c1 = &i2c1; 21 23 i2c2 = &i2c2; ··· 45 43 reg = <0x2 0x40000000 0x2 0x00000000>; 46 44 }; 47 45 48 - reg_0p8v: regulator0 { 46 + reg_0p8v: regulator-0p8v { 49 47 compatible = "regulator-fixed"; 50 48 51 49 regulator-name = "fixed-0.8V"; ··· 55 53 regulator-always-on; 56 54 }; 57 55 58 - reg_3p3v: regulator1 { 56 + reg_3p3v: regulator-3p3v { 59 57 compatible = "regulator-fixed"; 60 58 61 59 regulator-name = "fixed-3.3V"; ··· 74 72 gpios-states = <0>; 75 73 states = <3300000 0>, <1800000 1>; 76 74 }; 75 + 76 + /* 32.768kHz crystal */ 77 + x6: x6-clock { 78 + compatible = "fixed-clock"; 79 + #clock-cells = <0>; 80 + clock-frequency = <32768>; 81 + }; 77 82 }; 78 83 79 84 &audio_extal_clk { 80 85 clock-frequency = <22579200>; 81 86 }; 82 87 88 + &ehci0 { 89 + dr_mode = "otg"; 90 + status = "okay"; 91 + }; 92 + 93 + &ehci1 { 94 + status = "okay"; 95 + }; 96 + 97 + &eth0 { 98 + pinctrl-0 = <&eth0_pins>; 99 + pinctrl-names = "default"; 100 + phy-handle = <&phy0>; 101 + phy-mode = "rgmii-id"; 102 + status = "okay"; 103 + }; 104 + 105 + &eth1 { 106 + pinctrl-0 = <&eth1_pins>; 107 + pinctrl-names = "default"; 108 + phy-handle = <&phy1>; 109 + phy-mode = "rgmii-id"; 110 + status = "okay"; 111 + }; 112 + 83 113 &gpu { 84 114 status = "okay"; 85 115 mali-supply = <&reg_0p8v>; 116 + }; 117 + 118 + &hsusb { 119 + dr_mode = "otg"; 120 + status = "okay"; 86 121 }; 87 122 88 123 &i2c0 { ··· 176 137 clock-frequency = <400000>; 177 138 178 139 status = "okay"; 140 + 141 + raa215300: pmic@12 { 142 + compatible = "renesas,raa215300"; 143 + reg = <0x12>, <0x6f>; 144 + reg-names = "main", "rtc"; 145 + clocks = <&x6>; 146 + clock-names = "xin"; 147 + }; 148 + }; 149 + 150 + &mdio0 { 151 + phy0: ethernet-phy@0 { 152 + compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; 153 + reg = <0>; 154 + rxc-skew-psec = <0>; 155 + txc-skew-psec = <0>; 156 + rxdv-skew-psec = <0>; 157 + txdv-skew-psec = <0>; 158 + rxd0-skew-psec = <0>; 159 + rxd1-skew-psec = <0>; 160 + rxd2-skew-psec = <0>; 161 + rxd3-skew-psec = <0>; 162 + txd0-skew-psec = <0>; 163 + txd1-skew-psec = <0>; 164 + txd2-skew-psec = <0>; 165 + txd3-skew-psec = <0>; 166 + }; 167 + }; 168 + 169 + &mdio1 { 170 + phy1: ethernet-phy@1 { 171 + compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; 172 + reg = <0>; 173 + rxc-skew-psec = <0>; 174 + txc-skew-psec = <0>; 175 + rxdv-skew-psec = <0>; 176 + txdv-skew-psec = <0>; 177 + rxd0-skew-psec = <0>; 178 + rxd1-skew-psec = <0>; 179 + rxd2-skew-psec = <0>; 180 + rxd3-skew-psec = <0>; 181 + txd0-skew-psec = <0>; 182 + txd1-skew-psec = <0>; 183 + txd2-skew-psec = <0>; 184 + txd3-skew-psec = <0>; 185 + }; 186 + }; 187 + 188 + &ohci0 { 189 + dr_mode = "otg"; 190 + status = "okay"; 191 + }; 192 + 193 + &ohci1 { 194 + status = "okay"; 179 195 }; 180 196 181 197 &ostm0 { ··· 266 172 }; 267 173 268 174 &pinctrl { 175 + eth0_pins: eth0 { 176 + pins = "ET0_TXC_TXCLK"; 177 + output-enable; 178 + }; 179 + 180 + eth1_pins: eth0 { 181 + pins = "ET1_TXC_TXCLK"; 182 + output-enable; 183 + }; 184 + 269 185 i2c0_pins: i2c0 { 270 186 pinmux = <RZV2H_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */ 271 187 <RZV2H_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */ ··· 341 237 pinmux = <RZV2H_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */ 342 238 }; 343 239 }; 240 + 241 + usb20_pins: usb20 { 242 + ovc { 243 + pinmux = <RZV2H_PORT_PINMUX(9, 6, 14)>; /* OVC */ 244 + }; 245 + 246 + vbus { 247 + pinmux = <RZV2H_PORT_PINMUX(9, 5, 14)>; /* VBUS */ 248 + }; 249 + }; 250 + 251 + usb21_pins: usb21 { 252 + ovc { 253 + pinmux = <RZV2H_PORT_PINMUX(6, 7, 14)>; /* OVC */ 254 + }; 255 + 256 + vbus { 257 + pinmux = <RZV2H_PORT_PINMUX(6, 6, 14)>; /* VBUS */ 258 + }; 259 + }; 344 260 }; 345 261 346 262 &qextal_clk { ··· 387 263 bus-width = <4>; 388 264 sd-uhs-sdr50; 389 265 sd-uhs-sdr104; 266 + status = "okay"; 267 + }; 268 + 269 + &usb20phyrst { 270 + status = "okay"; 271 + }; 272 + 273 + &usb21phyrst { 274 + status = "okay"; 275 + }; 276 + 277 + &usb2_phy0 { 278 + pinctrl-0 = <&usb20_pins>; 279 + pinctrl-names = "default"; 280 + 281 + status = "okay"; 282 + }; 283 + 284 + &usb2_phy1 { 285 + pinctrl-0 = <&usb21_pins>; 286 + pinctrl-names = "default"; 287 + 390 288 status = "okay"; 391 289 }; 392 290
+6
arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
··· 35 35 }; 36 36 37 37 aliases { 38 + i2c0 = &i2c0; 38 39 serial3 = &scif0; 39 40 mmc1 = &sdhi1; 40 41 }; ··· 57 56 58 57 &canfd { 59 58 status = "okay"; 59 + }; 60 + 61 + &i2c0 { 62 + status = "okay"; 63 + clock-frequency = <400000>; 60 64 }; 61 65 62 66 &scif0 {
+46
arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
··· 182 182 pinmux = <RZG3E_PORT_PINMUX(K, 2, 1)>; /* SD2PWEN */ 183 183 }; 184 184 }; 185 + 186 + xspi_pins: xspi0 { 187 + pinmux = <RZG3E_PORT_PINMUX(M, 0, 0)>, /* XSPI0_IO0 */ 188 + <RZG3E_PORT_PINMUX(M, 1, 0)>, /* XSPI0_IO1 */ 189 + <RZG3E_PORT_PINMUX(M, 2, 0)>, /* XSPI0_IO2 */ 190 + <RZG3E_PORT_PINMUX(M, 3, 0)>, /* XSPI0_IO3 */ 191 + <RZG3E_PORT_PINMUX(L, 0, 0)>, /* XSPI0_CKP */ 192 + <RZG3E_PORT_PINMUX(L, 1, 0)>; /* XSPI0_CS0 */ 193 + }; 185 194 }; 186 195 187 196 &qextal_clk { ··· 253 244 254 245 &wdt1 { 255 246 status = "okay"; 247 + }; 248 + 249 + &xspi { 250 + pinctrl-0 = <&xspi_pins>; 251 + pinctrl-names = "default"; 252 + status = "okay"; 253 + 254 + flash@0 { 255 + compatible = "jedec,spi-nor"; 256 + reg = <0>; 257 + vcc-supply = <&reg_1p8v>; 258 + m25p,fast-read; 259 + spi-max-frequency = <50000000>; 260 + spi-tx-bus-width = <4>; 261 + spi-rx-bus-width = <4>; 262 + 263 + partitions { 264 + compatible = "fixed-partitions"; 265 + #address-cells = <1>; 266 + #size-cells = <1>; 267 + 268 + partition@0 { 269 + label = "bl2"; 270 + reg = <0x00000000 0x00060000>; 271 + }; 272 + 273 + partition@60000 { 274 + label = "fip"; 275 + reg = <0x00060000 0x007a0000>; 276 + }; 277 + 278 + partition@800000 { 279 + label = "user"; 280 + reg = <0x800000 0x800000>; 281 + }; 282 + }; 283 + }; 256 284 };
+2
arch/arm64/boot/dts/renesas/salvator-common.dtsi
··· 592 592 }; 593 593 594 594 &i2c_dvfs { 595 + bootph-all; 595 596 status = "okay"; 596 597 597 598 clock-frequency = <400000>; ··· 626 625 compatible = "rohm,br24t01", "atmel,24c01"; 627 626 reg = <0x50>; 628 627 pagesize = <8>; 628 + bootph-all; 629 629 }; 630 630 }; 631 631
+2
arch/arm64/boot/dts/renesas/ulcb.dtsi
··· 244 244 }; 245 245 246 246 &i2c_dvfs { 247 + bootph-all; 247 248 status = "okay"; 248 249 249 250 clock-frequency = <400000>; ··· 278 277 compatible = "rohm,br24t01", "atmel,24c01"; 279 278 reg = <0x50>; 280 279 pagesize = <8>; 280 + bootph-all; 281 281 }; 282 282 }; 283 283
+8
drivers/pci/pwrctrl/slot.c
··· 4 4 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 5 5 */ 6 6 7 + #include <linux/clk.h> 7 8 #include <linux/device.h> 8 9 #include <linux/mod_devicetable.h> 9 10 #include <linux/module.h> ··· 31 30 { 32 31 struct pci_pwrctrl_slot_data *slot; 33 32 struct device *dev = &pdev->dev; 33 + struct clk *clk; 34 34 int ret; 35 35 36 36 slot = devm_kzalloc(dev, sizeof(*slot), GFP_KERNEL); ··· 56 54 slot); 57 55 if (ret) 58 56 goto err_regulator_disable; 57 + 58 + clk = devm_clk_get_optional_enabled(dev, NULL); 59 + if (IS_ERR(clk)) { 60 + return dev_err_probe(dev, PTR_ERR(clk), 61 + "Failed to enable slot clock\n"); 62 + } 59 63 60 64 pci_pwrctrl_init(&slot->ctx, dev); 61 65