Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: RLC-G VF Register Access Interface
- Implement Gfx v12.1 VFi interface under SRIOV
- Redirect all RLCG interface access to new function after
Gfx v12.1
v2: squash in register updates
Signed-off-by: Bokun Zhang <Bokun.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Bokun Zhang
and committed by
Alex Deucher
0dd72af5
87046288
+194
-11
+9
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
+9
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
···
270
270
uint32_t grbm_cntl;
271
271
uint32_t grbm_idx;
272
272
uint32_t spare_int;
273
+
274
+
uint32_t vfi_cmd;
275
+
uint32_t vfi_stat;
276
+
uint32_t vfi_addr;
277
+
uint32_t vfi_data;
278
+
uint32_t vfi_grbm_cntl;
279
+
uint32_t vfi_grbm_idx;
280
+
uint32_t vfi_grbm_cntl_data;
281
+
uint32_t vfi_grbm_idx_data;
273
282
};
274
283
275
284
struct amdgpu_rlc {
+130
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+130
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
···
1338
1338
return ret;
1339
1339
}
1340
1340
1341
+
static u32 amdgpu_virt_rlcg_vfi_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id)
1342
+
{
1343
+
uint32_t timeout = 100;
1344
+
uint32_t i;
1345
+
1346
+
struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
1347
+
void *vfi_cmd;
1348
+
void *vfi_stat;
1349
+
void *vfi_addr;
1350
+
void *vfi_data;
1351
+
void *vfi_grbm_cntl;
1352
+
void *vfi_grbm_idx;
1353
+
uint32_t cmd;
1354
+
uint32_t stat;
1355
+
uint32_t addr = offset;
1356
+
uint32_t data;
1357
+
uint32_t grbm_cntl_data;
1358
+
uint32_t grbm_idx_data;
1359
+
1360
+
unsigned long flags;
1361
+
bool is_err = true;
1362
+
1363
+
if (!adev->gfx.rlc.rlcg_reg_access_supported) {
1364
+
dev_err(adev->dev, "VFi interface is not available\n");
1365
+
return 0;
1366
+
}
1367
+
1368
+
if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) {
1369
+
dev_err(adev->dev, "VFi invalid XCC, xcc_id=0x%x\n", xcc_id);
1370
+
return 0;
1371
+
}
1372
+
1373
+
if (amdgpu_device_skip_hw_access(adev))
1374
+
return 0;
1375
+
1376
+
reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id];
1377
+
vfi_cmd = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_cmd;
1378
+
vfi_stat = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_stat;
1379
+
vfi_addr = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_addr;
1380
+
vfi_data = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_data;
1381
+
vfi_grbm_cntl = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_grbm_cntl;
1382
+
vfi_grbm_idx = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_grbm_idx;
1383
+
grbm_cntl_data = reg_access_ctrl->vfi_grbm_cntl_data;
1384
+
grbm_idx_data = reg_access_ctrl->vfi_grbm_idx_data;
1385
+
1386
+
if (flag == AMDGPU_RLCG_GC_WRITE) {
1387
+
data = v;
1388
+
cmd = AMDGPU_RLCG_VFI_CMD__WR;
1389
+
1390
+
// the GRBM_GFX_CNTL and GRBM_GFX_INDEX are protected by mutex outside this call
1391
+
if (addr == reg_access_ctrl->grbm_cntl) {
1392
+
reg_access_ctrl->vfi_grbm_cntl_data = data;
1393
+
return 0;
1394
+
} else if (addr == reg_access_ctrl->grbm_idx) {
1395
+
reg_access_ctrl->vfi_grbm_idx_data = data;
1396
+
return 0;
1397
+
}
1398
+
1399
+
} else if (flag == AMDGPU_RLCG_GC_READ) {
1400
+
data = 0;
1401
+
cmd = AMDGPU_RLCG_VFI_CMD__RD;
1402
+
1403
+
// the GRBM_GFX_CNTL and GRBM_GFX_INDEX are protected by mutex outside this call
1404
+
if (addr == reg_access_ctrl->grbm_cntl)
1405
+
return grbm_cntl_data;
1406
+
else if (addr == reg_access_ctrl->grbm_idx)
1407
+
return grbm_idx_data;
1408
+
1409
+
} else {
1410
+
dev_err(adev->dev, "VFi invalid access, flag=0x%x\n", flag);
1411
+
return 0;
1412
+
}
1413
+
1414
+
spin_lock_irqsave(&adev->virt.rlcg_reg_lock, flags);
1415
+
1416
+
writel(addr, vfi_addr);
1417
+
writel(data, vfi_data);
1418
+
writel(grbm_cntl_data, vfi_grbm_cntl);
1419
+
writel(grbm_idx_data, vfi_grbm_idx);
1420
+
1421
+
writel(AMDGPU_RLCG_VFI_STAT__BUSY, vfi_stat);
1422
+
writel(cmd, vfi_cmd);
1423
+
1424
+
for (i = 0; i < timeout; i++) {
1425
+
stat = readl(vfi_stat);
1426
+
if (stat != AMDGPU_RLCG_VFI_STAT__BUSY)
1427
+
break;
1428
+
udelay(10);
1429
+
}
1430
+
1431
+
switch (stat) {
1432
+
case AMDGPU_RLCG_VFI_STAT__DONE:
1433
+
is_err = false;
1434
+
if (cmd == AMDGPU_RLCG_VFI_CMD__RD)
1435
+
data = readl(vfi_data);
1436
+
break;
1437
+
case AMDGPU_RLCG_VFI_STAT__BUSY:
1438
+
dev_err(adev->dev, "VFi access timeout\n");
1439
+
break;
1440
+
case AMDGPU_RLCG_VFI_STAT__INV_CMD:
1441
+
dev_err(adev->dev, "VFi invalid command\n");
1442
+
break;
1443
+
case AMDGPU_RLCG_VFI_STAT__INV_ADDR:
1444
+
dev_err(adev->dev, "VFi invalid address\n");
1445
+
break;
1446
+
case AMDGPU_RLCG_VFI_STAT__ERR:
1447
+
dev_err(adev->dev, "VFi unknown error\n");
1448
+
break;
1449
+
default:
1450
+
dev_err(adev->dev, "VFi unknown status code\n");
1451
+
break;
1452
+
}
1453
+
1454
+
spin_unlock_irqrestore(&adev->virt.rlcg_reg_lock, flags);
1455
+
1456
+
if (is_err)
1457
+
dev_err(adev->dev, "VFi: [grbm_cntl=0x%x grbm_idx=0x%x] addr=0x%x (byte addr 0x%x), data=0x%x, cmd=0x%x\n",
1458
+
grbm_cntl_data, grbm_idx_data,
1459
+
addr, addr * 4, data, cmd);
1460
+
else
1461
+
dev_dbg(adev->dev, "VFi: [grbm_cntl=0x%x grbm_idx=0x%x] addr=0x%x (byte addr 0x%x), data=0x%x, cmd=0x%x\n",
1462
+
grbm_cntl_data, grbm_idx_data,
1463
+
addr, addr * 4, data, cmd);
1464
+
1465
+
return data;
1466
+
}
1467
+
1341
1468
u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id)
1342
1469
{
1343
1470
struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
···
1477
1350
void *scratch_reg3;
1478
1351
void *spare_int;
1479
1352
unsigned long flags;
1353
+
1354
+
if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 1, 0))
1355
+
return amdgpu_virt_rlcg_vfi_reg_rw(adev, offset, v, flag, xcc_id);
1480
1356
1481
1357
if (!adev->gfx.rlc.rlcg_reg_access_supported) {
1482
1358
dev_err(adev->dev,
+9
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+9
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
···
47
47
#define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF
48
48
#define AMDGPU_RLCG_SCRATCH1_ERROR_MASK 0xF000000
49
49
50
+
#define AMDGPU_RLCG_VFI_CMD__WR 0x0
51
+
#define AMDGPU_RLCG_VFI_CMD__RD 0x1
52
+
53
+
#define AMDGPU_RLCG_VFI_STAT__BUSY 0x0
54
+
#define AMDGPU_RLCG_VFI_STAT__DONE 0x1
55
+
#define AMDGPU_RLCG_VFI_STAT__INV_CMD 0x2
56
+
#define AMDGPU_RLCG_VFI_STAT__INV_ADDR 0x3
57
+
#define AMDGPU_RLCG_VFI_STAT__ERR 0xFF
58
+
50
59
/* all asic after AI use this offset */
51
60
#define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
52
61
/* tonga/fiji use this offset */
+16
-10
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+16
-10
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
···
526
526
num_xcc = NUM_XCC(adev->gfx.xcc_mask);
527
527
for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
528
528
reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)];
529
-
reg_access_ctrl->scratch_reg0 =
530
-
SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0);
531
-
reg_access_ctrl->scratch_reg1 =
532
-
SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1);
533
-
reg_access_ctrl->scratch_reg2 =
534
-
SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2);
535
-
reg_access_ctrl->scratch_reg3 =
536
-
SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3);
529
+
537
530
reg_access_ctrl->grbm_cntl =
538
531
SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL);
539
532
reg_access_ctrl->grbm_idx =
540
533
SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX);
541
-
reg_access_ctrl->spare_int =
542
-
SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT_0);
534
+
535
+
reg_access_ctrl->vfi_cmd =
536
+
SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_CMD);
537
+
reg_access_ctrl->vfi_stat =
538
+
SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_STAT);
539
+
reg_access_ctrl->vfi_addr =
540
+
SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_ADDR);
541
+
reg_access_ctrl->vfi_data =
542
+
SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_DATA);
543
+
reg_access_ctrl->vfi_grbm_cntl =
544
+
SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_GRBM_GFX_CNTL);
545
+
reg_access_ctrl->vfi_grbm_idx =
546
+
SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_GRBM_GFX_INDEX);
547
+
reg_access_ctrl->vfi_grbm_cntl_data = 0;
548
+
reg_access_ctrl->vfi_grbm_idx_data = 0;
543
549
}
544
550
adev->gfx.rlc.rlcg_reg_access_supported = true;
545
551
}
+12
-1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h
+12
-1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h
···
6917
6917
#define regRLC_SPARE_INT_2_BASE_IDX 1
6918
6918
#define regRLC_RLCV_SPARE_INT_1 0x0992
6919
6919
#define regRLC_RLCV_SPARE_INT_1_BASE_IDX 1
6920
-
6920
+
#define regRLC_VFI_CMD 0x099a
6921
+
#define regRLC_VFI_CMD_BASE_IDX 1
6922
+
#define regRLC_VFI_STAT 0x099b
6923
+
#define regRLC_VFI_STAT_BASE_IDX 1
6924
+
#define regRLC_VFI_GRBM_GFX_INDEX 0x099c
6925
+
#define regRLC_VFI_GRBM_GFX_INDEX_BASE_IDX 1
6926
+
#define regRLC_VFI_GRBM_GFX_CNTL 0x099d
6927
+
#define regRLC_VFI_GRBM_GFX_CNTL_BASE_IDX 1
6928
+
#define regRLC_VFI_ADDR 0x099e
6929
+
#define regRLC_VFI_ADDR_BASE_IDX 1
6930
+
#define regRLC_VFI_DATA 0x099f
6931
+
#define regRLC_VFI_DATA_BASE_IDX 1
6921
6932
6922
6933
// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pwrdec
6923
6934
// base address: 0x3c000
+18
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h
+18
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h
···
21945
21945
#define RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT 0x1
21946
21946
#define RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK 0x00000001L
21947
21947
#define RLC_RLCV_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL
21948
+
//RLC_VFI_CMD
21949
+
#define RLC_VFI_CMD__VFI_CMD__SHIFT 0x0
21950
+
#define RLC_VFI_CMD__VFI_CMD_MASK 0xFFFFFFFFL
21951
+
//RLC_VFI_STAT
21952
+
#define RLC_VFI_STAT__VFI_STATUS__SHIFT 0x0
21953
+
#define RLC_VFI_STAT__VFI_STATUS_MASK 0xFFFFFFFFL
21954
+
//RLC_VFI_GRBM_GFX_INDEX
21955
+
#define RLC_VFI_GRBM_GFX_INDEX__VFI_GRBM_GFX_INDEX__SHIFT 0x0
21956
+
#define RLC_VFI_GRBM_GFX_INDEX__VFI_GRBM_GFX_INDEX_MASK 0xFFFFFFFFL
21957
+
//RLC_VFI_GRBM_GFX_CNTL
21958
+
#define RLC_VFI_GRBM_GFX_CNTL__VFI_GRBM_GFX_CNTL__SHIFT 0x0
21959
+
#define RLC_VFI_GRBM_GFX_CNTL__VFI_GRBM_GFX_CNTL_MASK 0xFFFFFFFFL
21960
+
//RLC_VFI_ADDR
21961
+
#define RLC_VFI_ADDR__VFI_ADDR__SHIFT 0x0
21962
+
#define RLC_VFI_ADDR__VFI_ADDR_MASK 0xFFFFFFFFL
21963
+
//RLC_VFI_DATA
21964
+
#define RLC_VFI_DATA__VFI_DATA__SHIFT 0x0
21965
+
#define RLC_VFI_DATA__VFI_DATA_MASK 0xFFFFFFFFL
21948
21966
21949
21967
21950
21968
// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pwrdec