tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

Merge branch 'add-support-for-icssg-pa_stats'

MD Danish Anwar says:

====================
Add support for ICSSG PA_STATS

This series adds support for PA_STATS. Previously this series was a
standalone patch adding documentation for PA_STATS in dt-bindings file
ti,pruss.yaml.

v1 https://lore.kernel.org/all/20240430121915.1561359-1-danishanwar@ti.com/
v2 https://lore.kernel.org/all/20240529115149.630273-1-danishanwar@ti.com/
v3 https://lore.kernel.org/all/20240625153319.795665-1-danishanwar@ti.com/
v4 https://lore.kernel.org/all/20240729113226.2905928-1-danishanwar@ti.com/
v5 https://lore.kernel.org/all/20240814092033.2984734-1-danishanwar@ti.com/
v6 https://lore.kernel.org/all/20240820091657.4068304-1-danishanwar@ti.com/
====================

Link: https://patch.msgid.link/20240822122652.1071801-1-danishanwar@ti.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski 0de45db8 f85cd6ae

+160 -83
+20
Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml
··· 278 278 279 279 additionalProperties: false 280 280 281 + ^pa-stats@[a-f0-9]+$: 282 + description: | 283 + PA-STATS sub-module represented as a SysCon. PA_STATS is a set of 284 + registers where different statistics related to ICSSG, are dumped by 285 + ICSSG firmware. This syscon sub-module will help the device to 286 + access/read/write those statistics. 287 + 288 + type: object 289 + 290 + additionalProperties: false 291 + 292 + properties: 293 + compatible: 294 + items: 295 + - const: ti,pruss-pa-st 296 + - const: syscon 297 + 298 + reg: 299 + maxItems: 1 300 + 281 301 interrupt-controller@[a-f0-9]+$: 282 302 description: | 283 303 PRUSS INTC Node. Each PRUSS has a single interrupt controller instance
+10 -9
drivers/net/ethernet/ti/icssg/icssg_ethtool.c
··· 83 83 84 84 switch (stringset) { 85 85 case ETH_SS_STATS: 86 - for (i = 0; i < ARRAY_SIZE(icssg_all_stats); i++) { 87 - if (!icssg_all_stats[i].standard_stats) { 88 - memcpy(p, icssg_all_stats[i].name, 89 - ETH_GSTRING_LEN); 90 - p += ETH_GSTRING_LEN; 91 - } 92 - } 86 + for (i = 0; i < ARRAY_SIZE(icssg_all_miig_stats); i++) 87 + if (!icssg_all_miig_stats[i].standard_stats) 88 + ethtool_puts(&p, icssg_all_miig_stats[i].name); 89 + for (i = 0; i < ARRAY_SIZE(icssg_all_pa_stats); i++) 90 + ethtool_puts(&p, icssg_all_pa_stats[i].name); 93 91 break; 94 92 default: 95 93 break; ··· 102 104 103 105 emac_update_hardware_stats(emac); 104 106 105 - for (i = 0; i < ARRAY_SIZE(icssg_all_stats); i++) 106 - if (!icssg_all_stats[i].standard_stats) 107 + for (i = 0; i < ARRAY_SIZE(icssg_all_miig_stats); i++) 108 + if (!icssg_all_miig_stats[i].standard_stats) 107 109 *(data++) = emac->stats[i]; 110 + 111 + for (i = 0; i < ARRAY_SIZE(icssg_all_pa_stats); i++) 112 + *(data++) = emac->pa_stats[i]; 108 113 } 109 114 110 115 static int emac_get_ts_info(struct net_device *ndev,
+6
drivers/net/ethernet/ti/icssg/icssg_prueth.c
··· 1182 1182 return -ENODEV; 1183 1183 } 1184 1184 1185 + prueth->pa_stats = syscon_regmap_lookup_by_phandle(np, "ti,pa-stats"); 1186 + if (IS_ERR(prueth->pa_stats)) { 1187 + dev_err(dev, "couldn't get ti,pa-stats syscon regmap\n"); 1188 + return -ENODEV; 1189 + } 1190 + 1185 1191 if (eth0_node) { 1186 1192 ret = prueth_get_cores(prueth, ICSS_SLICE0, false); 1187 1193 if (ret)
+7 -2
drivers/net/ethernet/ti/icssg/icssg_prueth.h
··· 50 50 51 51 #define ICSSG_MAX_RFLOWS 8 /* per slice */ 52 52 53 + #define ICSSG_NUM_PA_STATS 4 54 + #define ICSSG_NUM_MIIG_STATS 60 53 55 /* Number of ICSSG related stats */ 54 - #define ICSSG_NUM_STATS 60 56 + #define ICSSG_NUM_STATS (ICSSG_NUM_MIIG_STATS + ICSSG_NUM_PA_STATS) 55 57 #define ICSSG_NUM_STANDARD_STATS 31 56 58 #define ICSSG_NUM_ETHTOOL_STATS (ICSSG_NUM_STATS - ICSSG_NUM_STANDARD_STATS) 57 59 ··· 192 190 int port_vlan; 193 191 194 192 struct delayed_work stats_work; 195 - u64 stats[ICSSG_NUM_STATS]; 193 + u64 stats[ICSSG_NUM_MIIG_STATS]; 194 + u64 pa_stats[ICSSG_NUM_PA_STATS]; 196 195 197 196 /* RX IRQ Coalescing Related */ 198 197 struct hrtimer rx_hrtimer; ··· 233 230 * @registered_netdevs: list of registered netdevs 234 231 * @miig_rt: regmap to mii_g_rt block 235 232 * @mii_rt: regmap to mii_rt block 233 + * @pa_stats: regmap to pa_stats block 236 234 * @pru_id: ID for each of the PRUs 237 235 * @pdev: pointer to ICSSG platform device 238 236 * @pdata: pointer to platform data for ICSSG driver ··· 267 263 struct net_device *registered_netdevs[PRUETH_NUM_MACS]; 268 264 struct regmap *miig_rt; 269 265 struct regmap *mii_rt; 266 + struct regmap *pa_stats; 270 267 271 268 enum pruss_pru_id pru_id[PRUSS_NUM_PRUS]; 272 269 struct platform_device *pdev;
+22 -9
drivers/net/ethernet/ti/icssg/icssg_stats.c
··· 11 11 12 12 #define ICSSG_TX_PACKET_OFFSET 0xA0 13 13 #define ICSSG_TX_BYTE_OFFSET 0xEC 14 + #define ICSSG_FW_STATS_BASE 0x0248 14 15 15 16 static u32 stats_base[] = { 0x54c, /* Slice 0 stats start */ 16 17 0xb18, /* Slice 1 stats start */ ··· 23 22 int slice = prueth_emac_slice(emac); 24 23 u32 base = stats_base[slice]; 25 24 u32 tx_pkt_cnt = 0; 26 - u32 val; 25 + u32 val, reg; 27 26 int i; 28 27 29 - for (i = 0; i < ARRAY_SIZE(icssg_all_stats); i++) { 28 + for (i = 0; i < ARRAY_SIZE(icssg_all_miig_stats); i++) { 30 29 regmap_read(prueth->miig_rt, 31 - base + icssg_all_stats[i].offset, 30 + base + icssg_all_miig_stats[i].offset, 32 31 &val); 33 32 regmap_write(prueth->miig_rt, 34 - base + icssg_all_stats[i].offset, 33 + base + icssg_all_miig_stats[i].offset, 35 34 val); 36 35 37 - if (icssg_all_stats[i].offset == ICSSG_TX_PACKET_OFFSET) 36 + if (icssg_all_miig_stats[i].offset == ICSSG_TX_PACKET_OFFSET) 38 37 tx_pkt_cnt = val; 39 38 40 39 emac->stats[i] += val; 41 - if (icssg_all_stats[i].offset == ICSSG_TX_BYTE_OFFSET) 40 + if (icssg_all_miig_stats[i].offset == ICSSG_TX_BYTE_OFFSET) 42 41 emac->stats[i] -= tx_pkt_cnt * 8; 42 + } 43 + 44 + for (i = 0; i < ARRAY_SIZE(icssg_all_pa_stats); i++) { 45 + reg = ICSSG_FW_STATS_BASE + icssg_all_pa_stats[i].offset * 46 + PRUETH_NUM_MACS + slice * sizeof(u32); 47 + regmap_read(prueth->pa_stats, reg, &val); 48 + emac->pa_stats[i] += val; 43 49 } 44 50 } 45 51 ··· 65 57 { 66 58 int i; 67 59 68 - for (i = 0; i < ARRAY_SIZE(icssg_all_stats); i++) { 69 - if (!strcmp(icssg_all_stats[i].name, stat_name)) 70 - return emac->stats[icssg_all_stats[i].offset / sizeof(u32)]; 60 + for (i = 0; i < ARRAY_SIZE(icssg_all_miig_stats); i++) { 61 + if (!strcmp(icssg_all_miig_stats[i].name, stat_name)) 62 + return emac->stats[icssg_all_miig_stats[i].offset / sizeof(u32)]; 63 + } 64 + 65 + for (i = 0; i < ARRAY_SIZE(icssg_all_pa_stats); i++) { 66 + if (!strcmp(icssg_all_pa_stats[i].name, stat_name)) 67 + return emac->pa_stats[icssg_all_pa_stats[i].offset / sizeof(u32)]; 71 68 } 72 69 73 70 netdev_err(emac->ndev, "Invalid stats %s\n", stat_name);
+95 -63
drivers/net/ethernet/ti/icssg/icssg_stats.h
··· 77 77 u32 tx_bytes; 78 78 }; 79 79 80 - #define ICSSG_STATS(field, stats_type) \ 80 + #define ICSSG_MIIG_STATS(field, stats_type) \ 81 81 { \ 82 82 #field, \ 83 83 offsetof(struct miig_stats_regs, field), \ 84 84 stats_type \ 85 85 } 86 86 87 - struct icssg_stats { 87 + struct icssg_miig_stats { 88 88 char name[ETH_GSTRING_LEN]; 89 89 u32 offset; 90 90 bool standard_stats; 91 91 }; 92 92 93 - static const struct icssg_stats icssg_all_stats[] = { 93 + static const struct icssg_miig_stats icssg_all_miig_stats[] = { 94 94 /* Rx */ 95 - ICSSG_STATS(rx_packets, true), 96 - ICSSG_STATS(rx_broadcast_frames, false), 97 - ICSSG_STATS(rx_multicast_frames, true), 98 - ICSSG_STATS(rx_crc_errors, true), 99 - ICSSG_STATS(rx_mii_error_frames, false), 100 - ICSSG_STATS(rx_odd_nibble_frames, false), 101 - ICSSG_STATS(rx_frame_max_size, true), 102 - ICSSG_STATS(rx_max_size_error_frames, false), 103 - ICSSG_STATS(rx_frame_min_size, true), 104 - ICSSG_STATS(rx_min_size_error_frames, false), 105 - ICSSG_STATS(rx_over_errors, true), 106 - ICSSG_STATS(rx_class0_hits, false), 107 - ICSSG_STATS(rx_class1_hits, false), 108 - ICSSG_STATS(rx_class2_hits, false), 109 - ICSSG_STATS(rx_class3_hits, false), 110 - ICSSG_STATS(rx_class4_hits, false), 111 - ICSSG_STATS(rx_class5_hits, false), 112 - ICSSG_STATS(rx_class6_hits, false), 113 - ICSSG_STATS(rx_class7_hits, false), 114 - ICSSG_STATS(rx_class8_hits, false), 115 - ICSSG_STATS(rx_class9_hits, false), 116 - ICSSG_STATS(rx_class10_hits, false), 117 - ICSSG_STATS(rx_class11_hits, false), 118 - ICSSG_STATS(rx_class12_hits, false), 119 - ICSSG_STATS(rx_class13_hits, false), 120 - ICSSG_STATS(rx_class14_hits, false), 121 - ICSSG_STATS(rx_class15_hits, false), 122 - ICSSG_STATS(rx_smd_frags, false), 123 - ICSSG_STATS(rx_bucket1_size, true), 124 - ICSSG_STATS(rx_bucket2_size, true), 125 - ICSSG_STATS(rx_bucket3_size, true), 126 - ICSSG_STATS(rx_bucket4_size, true), 127 - ICSSG_STATS(rx_64B_frames, true), 128 - ICSSG_STATS(rx_bucket1_frames, true), 129 - ICSSG_STATS(rx_bucket2_frames, true), 130 - ICSSG_STATS(rx_bucket3_frames, true), 131 - ICSSG_STATS(rx_bucket4_frames, true), 132 - ICSSG_STATS(rx_bucket5_frames, true), 133 - ICSSG_STATS(rx_bytes, true), 134 - ICSSG_STATS(rx_tx_total_bytes, false), 95 + ICSSG_MIIG_STATS(rx_packets, true), 96 + ICSSG_MIIG_STATS(rx_broadcast_frames, false), 97 + ICSSG_MIIG_STATS(rx_multicast_frames, true), 98 + ICSSG_MIIG_STATS(rx_crc_errors, true), 99 + ICSSG_MIIG_STATS(rx_mii_error_frames, false), 100 + ICSSG_MIIG_STATS(rx_odd_nibble_frames, false), 101 + ICSSG_MIIG_STATS(rx_frame_max_size, true), 102 + ICSSG_MIIG_STATS(rx_max_size_error_frames, false), 103 + ICSSG_MIIG_STATS(rx_frame_min_size, true), 104 + ICSSG_MIIG_STATS(rx_min_size_error_frames, false), 105 + ICSSG_MIIG_STATS(rx_over_errors, true), 106 + ICSSG_MIIG_STATS(rx_class0_hits, false), 107 + ICSSG_MIIG_STATS(rx_class1_hits, false), 108 + ICSSG_MIIG_STATS(rx_class2_hits, false), 109 + ICSSG_MIIG_STATS(rx_class3_hits, false), 110 + ICSSG_MIIG_STATS(rx_class4_hits, false), 111 + ICSSG_MIIG_STATS(rx_class5_hits, false), 112 + ICSSG_MIIG_STATS(rx_class6_hits, false), 113 + ICSSG_MIIG_STATS(rx_class7_hits, false), 114 + ICSSG_MIIG_STATS(rx_class8_hits, false), 115 + ICSSG_MIIG_STATS(rx_class9_hits, false), 116 + ICSSG_MIIG_STATS(rx_class10_hits, false), 117 + ICSSG_MIIG_STATS(rx_class11_hits, false), 118 + ICSSG_MIIG_STATS(rx_class12_hits, false), 119 + ICSSG_MIIG_STATS(rx_class13_hits, false), 120 + ICSSG_MIIG_STATS(rx_class14_hits, false), 121 + ICSSG_MIIG_STATS(rx_class15_hits, false), 122 + ICSSG_MIIG_STATS(rx_smd_frags, false), 123 + ICSSG_MIIG_STATS(rx_bucket1_size, true), 124 + ICSSG_MIIG_STATS(rx_bucket2_size, true), 125 + ICSSG_MIIG_STATS(rx_bucket3_size, true), 126 + ICSSG_MIIG_STATS(rx_bucket4_size, true), 127 + ICSSG_MIIG_STATS(rx_64B_frames, true), 128 + ICSSG_MIIG_STATS(rx_bucket1_frames, true), 129 + ICSSG_MIIG_STATS(rx_bucket2_frames, true), 130 + ICSSG_MIIG_STATS(rx_bucket3_frames, true), 131 + ICSSG_MIIG_STATS(rx_bucket4_frames, true), 132 + ICSSG_MIIG_STATS(rx_bucket5_frames, true), 133 + ICSSG_MIIG_STATS(rx_bytes, true), 134 + ICSSG_MIIG_STATS(rx_tx_total_bytes, false), 135 135 /* Tx */ 136 - ICSSG_STATS(tx_packets, true), 137 - ICSSG_STATS(tx_broadcast_frames, false), 138 - ICSSG_STATS(tx_multicast_frames, false), 139 - ICSSG_STATS(tx_odd_nibble_frames, false), 140 - ICSSG_STATS(tx_underflow_errors, false), 141 - ICSSG_STATS(tx_frame_max_size, true), 142 - ICSSG_STATS(tx_max_size_error_frames, false), 143 - ICSSG_STATS(tx_frame_min_size, true), 144 - ICSSG_STATS(tx_min_size_error_frames, false), 145 - ICSSG_STATS(tx_bucket1_size, true), 146 - ICSSG_STATS(tx_bucket2_size, true), 147 - ICSSG_STATS(tx_bucket3_size, true), 148 - ICSSG_STATS(tx_bucket4_size, true), 149 - ICSSG_STATS(tx_64B_frames, true), 150 - ICSSG_STATS(tx_bucket1_frames, true), 151 - ICSSG_STATS(tx_bucket2_frames, true), 152 - ICSSG_STATS(tx_bucket3_frames, true), 153 - ICSSG_STATS(tx_bucket4_frames, true), 154 - ICSSG_STATS(tx_bucket5_frames, true), 155 - ICSSG_STATS(tx_bytes, true), 136 + ICSSG_MIIG_STATS(tx_packets, true), 137 + ICSSG_MIIG_STATS(tx_broadcast_frames, false), 138 + ICSSG_MIIG_STATS(tx_multicast_frames, false), 139 + ICSSG_MIIG_STATS(tx_odd_nibble_frames, false), 140 + ICSSG_MIIG_STATS(tx_underflow_errors, false), 141 + ICSSG_MIIG_STATS(tx_frame_max_size, true), 142 + ICSSG_MIIG_STATS(tx_max_size_error_frames, false), 143 + ICSSG_MIIG_STATS(tx_frame_min_size, true), 144 + ICSSG_MIIG_STATS(tx_min_size_error_frames, false), 145 + ICSSG_MIIG_STATS(tx_bucket1_size, true), 146 + ICSSG_MIIG_STATS(tx_bucket2_size, true), 147 + ICSSG_MIIG_STATS(tx_bucket3_size, true), 148 + ICSSG_MIIG_STATS(tx_bucket4_size, true), 149 + ICSSG_MIIG_STATS(tx_64B_frames, true), 150 + ICSSG_MIIG_STATS(tx_bucket1_frames, true), 151 + ICSSG_MIIG_STATS(tx_bucket2_frames, true), 152 + ICSSG_MIIG_STATS(tx_bucket3_frames, true), 153 + ICSSG_MIIG_STATS(tx_bucket4_frames, true), 154 + ICSSG_MIIG_STATS(tx_bucket5_frames, true), 155 + ICSSG_MIIG_STATS(tx_bytes, true), 156 + }; 157 + 158 + /** 159 + * struct pa_stats_regs - ICSSG Firmware maintained PA Stats register 160 + * @fw_rx_cnt: Number of valid packets sent by Rx PRU to Host on PSI 161 + * @fw_tx_cnt: Number of valid packets copied by RTU0 to Tx queues 162 + * @fw_tx_pre_overflow: Host Egress Q (Pre-emptible) Overflow Counter 163 + * @fw_tx_exp_overflow: Host Egress Q (Express) Overflow Counter 164 + */ 165 + struct pa_stats_regs { 166 + u32 fw_rx_cnt; 167 + u32 fw_tx_cnt; 168 + u32 fw_tx_pre_overflow; 169 + u32 fw_tx_exp_overflow; 170 + }; 171 + 172 + #define ICSSG_PA_STATS(field) \ 173 + { \ 174 + #field, \ 175 + offsetof(struct pa_stats_regs, field), \ 176 + } 177 + 178 + struct icssg_pa_stats { 179 + char name[ETH_GSTRING_LEN]; 180 + u32 offset; 181 + }; 182 + 183 + static const struct icssg_pa_stats icssg_all_pa_stats[] = { 184 + ICSSG_PA_STATS(fw_rx_cnt), 185 + ICSSG_PA_STATS(fw_tx_cnt), 186 + ICSSG_PA_STATS(fw_tx_pre_overflow), 187 + ICSSG_PA_STATS(fw_tx_exp_overflow), 156 188 }; 157 189 158 190 #endif /* __NET_TI_ICSSG_STATS_H */