Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie.
Small fixes for (mostly Nouveau, some radeon) regressions.
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/nouveau: use the correct fence implementation for nv50
drm/radeon: add new SI pci id
radeon: add AGPMode 1 quirk for RV250
drm/radeon: properly track the crtc not_enabled case evergreen_mc_stop()
drm/nouveau/bios: fix DCB v1.5 parsing
drm/nouveau: add missing pll_calc calls
drm/nouveau: fix crash with noaccel=1
drm/nv40: allocate ctxprog with kmalloc
drm/nvc0/disp: fix thinko in vblank regression fix..
+70
-21
+12
-7
drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+12
-7
drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
···
49
49
if (chan->vblank.crtc != crtc)
50
50
continue;
51
51
52
-
if (nv_device(priv)->chipset == 0x50) {
53
-
nv_wr32(priv, 0x001704, chan->vblank.channel);
54
-
nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
55
-
bar->flush(bar);
56
-
nv_wr32(priv, 0x001570, chan->vblank.offset);
57
-
nv_wr32(priv, 0x001574, chan->vblank.value);
58
-
} else {
52
+
if (nv_device(priv)->chipset >= 0xc0) {
59
53
nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
60
54
bar->flush(bar);
61
55
nv_wr32(priv, 0x06000c,
···
57
63
nv_wr32(priv, 0x060010,
58
64
lower_32_bits(chan->vblank.offset));
59
65
nv_wr32(priv, 0x060014, chan->vblank.value);
66
+
} else {
67
+
nv_wr32(priv, 0x001704, chan->vblank.channel);
68
+
nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
69
+
bar->flush(bar);
70
+
if (nv_device(priv)->chipset == 0x50) {
71
+
nv_wr32(priv, 0x001570, chan->vblank.offset);
72
+
nv_wr32(priv, 0x001574, chan->vblank.value);
73
+
} else {
74
+
nv_wr32(priv, 0x060010, chan->vblank.offset);
75
+
nv_wr32(priv, 0x060014, chan->vblank.value);
76
+
}
60
77
}
61
78
62
79
list_del(&chan->vblank.head);
+9
-3
drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c
+9
-3
drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c
···
669
669
});
670
670
}
671
671
672
-
void
672
+
int
673
673
nv40_grctx_init(struct nouveau_device *device, u32 *size)
674
674
{
675
-
u32 ctxprog[256], i;
675
+
u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i;
676
676
struct nouveau_grctx ctx = {
677
677
.device = device,
678
678
.mode = NOUVEAU_GRCTX_PROG,
679
679
.data = ctxprog,
680
-
.ctxprog_max = ARRAY_SIZE(ctxprog)
680
+
.ctxprog_max = 256,
681
681
};
682
+
683
+
if (!ctxprog)
684
+
return -ENOMEM;
682
685
683
686
nv40_grctx_generate(&ctx);
684
687
···
689
686
for (i = 0; i < ctx.ctxprog_len; i++)
690
687
nv_wr32(device, 0x400328, ctxprog[i]);
691
688
*size = ctx.ctxvals_pos * 4;
689
+
690
+
kfree(ctxprog);
691
+
return 0;
692
692
}
+3
-1
drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
+3
-1
drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
···
346
346
return ret;
347
347
348
348
/* generate and upload context program */
349
-
nv40_grctx_init(nv_device(priv), &priv->size);
349
+
ret = nv40_grctx_init(nv_device(priv), &priv->size);
350
+
if (ret)
351
+
return ret;
350
352
351
353
/* No context present currently */
352
354
nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
+1
-1
drivers/gpu/drm/nouveau/core/engine/graph/nv40.h
+1
-1
drivers/gpu/drm/nouveau/core/engine/graph/nv40.h
+9
-5
drivers/gpu/drm/nouveau/core/include/core/object.h
+9
-5
drivers/gpu/drm/nouveau/core/include/core/object.h
···
175
175
return temp;
176
176
}
177
177
178
-
static inline bool
179
-
nv_strncmp(void *obj, u32 addr, u32 len, const char *str)
178
+
static inline int
179
+
nv_memcmp(void *obj, u32 addr, const char *str, u32 len)
180
180
{
181
+
unsigned char c1, c2;
182
+
181
183
while (len--) {
182
-
if (nv_ro08(obj, addr++) != *(str++))
183
-
return false;
184
+
c1 = nv_ro08(obj, addr++);
185
+
c2 = *(str++);
186
+
if (c1 != c2)
187
+
return c1 - c2;
184
188
}
185
-
return true;
189
+
return 0;
186
190
}
187
191
188
192
#endif
+2
-1
drivers/gpu/drm/nouveau/core/include/subdev/clock.h
+2
-1
drivers/gpu/drm/nouveau/core/include/subdev/clock.h
+1
-1
drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c
+1
-1
drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c
+19
drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
+19
drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
···
66
66
return ret;
67
67
}
68
68
69
+
int
70
+
nva3_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info,
71
+
int clk, struct nouveau_pll_vals *pv)
72
+
{
73
+
int ret, N, M, P;
74
+
75
+
ret = nva3_pll_calc(clock, info, clk, &N, NULL, &M, &P);
76
+
77
+
if (ret > 0) {
78
+
pv->refclk = info->refclk;
79
+
pv->N1 = N;
80
+
pv->M1 = M;
81
+
pv->log2P = P;
82
+
}
83
+
return ret;
84
+
}
85
+
86
+
69
87
static int
70
88
nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
71
89
struct nouveau_oclass *oclass, void *data, u32 size,
···
98
80
return ret;
99
81
100
82
priv->base.pll_set = nva3_clock_pll_set;
83
+
priv->base.pll_calc = nva3_clock_pll_calc;
101
84
return 0;
102
85
}
103
86
+1
drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
+1
drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
+4
drivers/gpu/drm/nouveau/nouveau_abi16.c
+4
drivers/gpu/drm/nouveau/nouveau_abi16.c
+2
-1
drivers/gpu/drm/nouveau/nouveau_drm.c
+2
-1
drivers/gpu/drm/nouveau/nouveau_drm.c
···
129
129
130
130
/* initialise synchronisation routines */
131
131
if (device->card_type < NV_10) ret = nv04_fence_create(drm);
132
-
else if (device->chipset < 0x84) ret = nv10_fence_create(drm);
132
+
else if (device->card_type < NV_50) ret = nv10_fence_create(drm);
133
+
else if (device->chipset < 0x84) ret = nv50_fence_create(drm);
133
134
else if (device->card_type < NV_C0) ret = nv84_fence_create(drm);
134
135
else ret = nvc0_fence_create(drm);
135
136
if (ret) {
+2
drivers/gpu/drm/radeon/evergreen.c
+2
drivers/gpu/drm/radeon/evergreen.c
+4
-1
drivers/gpu/drm/radeon/radeon_agp.c
+4
-1
drivers/gpu/drm/radeon/radeon_agp.c
···
69
69
/* Intel 82830 830 Chipset Host Bridge / Mobility M6 LY Needs AGPMode 2 (fdo #17360)*/
70
70
{ PCI_VENDOR_ID_INTEL, 0x3575, PCI_VENDOR_ID_ATI, 0x4c59,
71
71
PCI_VENDOR_ID_DELL, 0x00e3, 2},
72
-
/* Intel 82852/82855 host bridge / Mobility FireGL 9000 R250 Needs AGPMode 1 (lp #296617) */
72
+
/* Intel 82852/82855 host bridge / Mobility FireGL 9000 RV250 Needs AGPMode 1 (lp #296617) */
73
73
{ PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4c66,
74
74
PCI_VENDOR_ID_DELL, 0x0149, 1},
75
+
/* Intel 82855PM host bridge / Mobility FireGL 9000 RV250 Needs AGPMode 1 for suspend/resume */
76
+
{ PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c66,
77
+
PCI_VENDOR_ID_IBM, 0x0531, 1},
75
78
/* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (deb #467460) */
76
79
{ PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50,
77
80
0x1025, 0x0061, 1},
+1
include/drm/drm_pciids.h
+1
include/drm/drm_pciids.h
···
210
210
{0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
211
211
{0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
212
212
{0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
213
+
{0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
213
214
{0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
214
215
{0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
215
216
{0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \